JP6548065B2 - Normally-off type nitride semiconductor field effect transistor with improved ohmic characteristics - Google Patents

Description

  The present invention relates to a field effect transistor (FET), in particular to a normally-off type HEMT device.

When a nitride semiconductor field effect transistor is used for a power device, it is strongly demanded that it is a normally-off type from the viewpoint of safety and compatibility with conventional Si power devices. In nitride semiconductor field effect transistors, a recess gate structure in which the gate portion of a high electron mobility transistor (HEMT) structure is dug down with respect to other portions is known as one of methods for achieving normally-off. (See Non-Patent Document 1). In the case of a GaN / AlGaN heterostructure using this recess structure, it is necessary to control the film thickness of the AlGaN layer on the channel layer (GaN layer) which determines the threshold of the transistor, but until now, the plasma density used for etching Since the etching rate is determined by the gas density and the substrate surface temperature, it has been difficult to control the etching depth in the substrate plane. In particular, within the plane of a large-diameter wafer, control of the etching depth becomes even more difficult.

Conventionally, a method called selective dry etching has been proposed as a method of controlling the etching depth regardless of the nonuniformity of the conditions on the substrate surface. This is to use the difference in etching rate depending on the type of material to be etched to stop the etching at the interface where the materials are different. A GaN (substrate side) / AlGaN / GaN (surface side) structure is produced by crystal growth, and after etching GaN on the surface side by using a fluorine-based etching gas, Al fluoride is exposed in the exposed AlGaN layer Is used to stop the etching (see Non-Patent Document 2).

  However, a positive charge is induced on the GaN side of the AlGaN / GaN (surface side) interface and a negative charge is induced on the AlGaN side, so a large notch is generated in the conduction band and the source and drain electrodes are It is difficult to form a good ohmic electrode. In order to avoid this, the ohmic contact in Non-Patent Document 2 has a structure in which the electrode metal is in direct contact with the electron transit layer (channel layer), but the ohmic contact is formed at a point and the surface is on the semiconductor surface. There is a problem that the contact resistance is increased as compared with the case where the electrode is formed.

Wataru Saito et al. IEEE Trans. Electron Devices, p. 356-362, Vol. 53, No. 2, 2006 Lu Bin et al. IEEE Electron Device Letts., P. 369-371, Vol. 34, No. 3, 2013

  An object of the present invention is to improve the ohmic characteristics of the source electrode and the drain electrode which occur when the normally off is realized by the recess structure of the nitride semiconductor HEMT device.

  The present inventors offset the negative polarization charge induced on the AlGaN side of the AlGaN / GaN (surface side) interface in order to reduce the band notch generated at the AlGan / GaN (surface side) interface. Was drafted. Therefore, a highly doped n-type doped layer is provided in the vicinity of the interface between the GaN layer on the front surface side and the AlGan layer, and carriers (electrons) from this layer are diffused toward the device surface to localize near the interface. It has been proposed to form a region that is positively charged and to offset the negative polarization charge induced on the AlGaN side by this positive charge. That is, according to the present invention, the following field effect transistor is provided.

[1] A barrier in which at least a channel layer, a barrier layer, and an n-type impurity doped layer are sequentially stacked on a substrate, a source electrode and a drain electrode are formed on the n-type impurity doped layer, and the n-type impurity doped layer is removed A GaN-based field effect transistor having a gate electrode formed on a layer, wherein at least a part of the n-type impurity-doped layer in the film thickness direction has a portion having a higher impurity concentration than other portions. Field effect transistor.

[2] When the channel layer, the barrier layer, and the n-type impurity doped layer are represented as a laminated structure of channel layer / barrier layer / n-type impurity doped layer, the laminated structure is GaN / Al _x Ga ₁ -xN (X > 0) / n-type _{GaN, Al X Ga 1-X} n / Al Y Ga 1-Y n / n -type GaN (0 <X <Y) , or _{GaN / In X Al 1-X} n (X> 0) The GaN-based field effect transistor according to the above [1], which is any of / n-type GaN.

[3] In the above [1] or [2], the impurity concentration of the n-type impurity doped layer is low on the source electrode and drain electrode side and is high on the barrier layer side, and the concentration change is stepped or continuous. The GaN-type field effect transistor of description.

[4] The impurity concentration of the n-type impurity-doped layer is higher in the central portion than in the source electrode and drain electrode proximity portions and the barrier layer proximity portion, and the concentration change is stepped or continuous. Or the GaN-based field effect transistor according to [2].

[5] A region in which the n-type impurity-doped layer is a region doped with an n-type impurity at a surface density Ns2 of at least 10% of polarization charge in the barrier layer, and a surface density lower than the n-type impurity surface density of the region The GaN-based field effect transistor according to [4], having a region doped with n-type impurities.

[6] The GaN-based field effect transistor according to [5], wherein the surface density Ns2 is 10 ¹² cm ⁻² or more.

[7] The GaN-based field effect transistor according to [1] to [6], wherein the thickness of the barrier layer is 1 to 10 nm, and the thickness of the n-type impurity doped layer is 3 to 15 nm.

[8] The GaN-based field effect transistor according to [1] to [7], wherein the gate electrode is a Schottky type.

[9] The GaN-based field effect transistor according to [1] to [7], wherein the gate electrode is a metal-insulator-semiconductor MIS type.

It is a figure which shows the cross-section of the field effect transistor in 1st Embodiment of this invention. It is a figure which shows the cross-section of the field effect transistor in 2nd Embodiment of this invention. It is a figure which shows the cross-section of the conventional recess gate type | mold field effect transistor. It is a figure which shows the conduction band profile of the vertical direction directly under an ohmic electrode in the state which does not apply the bias of the field effect transistor in 1st Embodiment of this invention. It is a figure which shows the conduction band profile of the vertical direction directly under an ohmic electrode in the state which does not apply the bias of the field effect transistor in 2nd Embodiment of this invention. It is a figure which shows the conduction band profile of the vertical direction directly under an ohmic electrode in the state which does not apply the bias of the recess gate type | mold field effect transistor of a prior art example. It is a figure which shows the manufacturing process flow of Example 1 contained in 2nd Embodiment of this invention. It is a figure which shows Si distribution of the depth direction of the laminated structure Si-doped to the surface side n-type GaN layer. It is a figure which shows the manufacturing process flow of Example 2 contained in 2nd Embodiment of this invention. It is a figure which shows the manufacturing process flow of Example 3 contained in 2nd Embodiment of this invention. Is a diagram showing a Hall effect measurement of GaN _/ Al _{0.15 Ga 0.85} N _/ high concentration Si-doped n-type GaN becomes laminated structure. It is a figure which shows the drain IV measurement result in FET of the laminated structure of Example 3 of 2nd Embodiment of this invention. It is a figure which shows the Id-Vg measurement result in FET of the laminated structure of Example 3 of 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and changes, modifications, and improvements can be made without departing from the scope of the invention.

In the present invention, the substrate is appropriately selected according to the buffer layer (buffer layer), the channel layer, the barrier layer, the n-type impurity doped layer, or each layer formation method to be formed thereon. For example, as the substrate, silicon, germanium, sapphire, silicon carbide, oxides (ZnO, LiAlO ₂ , LiGaO ₂ , MgAl ₂ O ₄ , (LaSr) (AlTa) O ₃ , NdGaO ₃ , MgO, etc.), Si—Ge Alloys, Group 3-Group 5 compounds of the periodic table (GaAs, AlN, GaN, AlGaN, AlInN), borides (such as ZrB2), and the like can be used. However, the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. is preferably smaller than the thermal expansion coefficient of the film made of Al _x Ga _1-x N formed on the substrate, and in particular the quality and cost of the Si substrate Preferably, the thickness of the Si substrate is 0.42 to 1.00 mm.

The buffer layer is formed of a single layer or a plurality of layers of various Group III nitride semiconductors, depending on the composition and structure of the device layer to be formed thereon, or the formation method of each layer. In the present invention, the buffer layer is made of _{Al X Ga 1-X} N, consists of one or more layers of X ≧ 0.2, 30 to 500 nm are preferred as the thickness of the total, 50 to 150 nm is more preferable. The buffer layer is formed, for example, by a known film forming method such as the MOCVD method or the MBE method. It is preferable to form a film structure with as little strain and dislocation density as possible, and in order to affect the quality of a film to be formed later, it is preferable to form the dislocation density at 1 × 10 ¹¹ / cm ³ or less. The composition gradient layer or the superlattice layer may be formed between the buffer layer and the channel layer for further reduction of lattice strain. It is preferable that the composition graded layer is continuously reduced in the film growth direction or stepwise reduced every 10 nm to 100 nm in the film growth direction. When forming a superlattice layer, it is preferable that one composition is AlN, the other composition is Al _X3 Ga _1-X3 N, and X3 is 0 to 0.2. When the superlattice pair is AlN and Al _X3 Ga _1-X3 N, the film thickness ratio is preferably 1: 2 to 1: 4.

In the case of the field effect transistor (FET) of the present invention, particularly the HEMT device, a channel layer, a barrier layer, and an n-type impurity doped layer are formed subsequently to the buffer layer. Channel layer is preferably constituted by i-GaN, it is preferable that the _{i-Al X Ga 1-X} N (0.1 ≦ X ≦ 0.3) as the barrier layer. In order to improve the mobility of the two-dimensional electron gas, an AlN spacer layer having a thickness of 0.5 to 1.5 nm is appropriately formed between the channel layer and the barrier layer. Incidentally, with respect to i-GaN of the channel _{layer, i-In X Al 1-} X N (0.1 ≦ X ≦ 0.3) can also be used as a barrier layer. In the case where the channel layer, the barrier layer, and the n-type impurity doped layer are represented as a laminated structure of channel layer / barrier layer / n-type impurity doped layer, the laminated structure is GaN / Al _x Ga ₁ -xN (X> 0) / n-type _{GaN, Al X Ga 1-X} n / Al Y Ga 1-Y n / n -type GaN (0 <X <Y) , or _{GaN / In X Al 1-X} n (X> 0) / n -type GaN It is preferable that it is either.

The impurity concentration distribution of the n-type impurity doped layer is low on the source electrode and drain electrode side and high on the barrier layer side, and the concentration change is preferably stepwise or continuous (first embodiment). As another mode, it is preferable that the impurity concentration of the n-type impurity-doped layer is higher in the central portion than in the source electrode and drain electrode proximity portions and in the barrier layer proximity portion, and the concentration change is stepwise or continuous. (Second Embodiment). As a second embodiment, the n-type impurity-doped layer is a region in which n-type impurities are doped at an area density Ns2 of at least 10% of polarization charges in the barrier layer, and a plane lower than the n-type impurity area density of the regions It is particularly preferred to have a region doped with n-type impurities at a density. In this case, the surface density Ns2 is preferably 10 ¹² cm ⁻² or more. The thickness of the barrier layer is preferably 1 to 10 nm, and the thickness of the n-type impurity doped layer is preferably 3 to 15 nm. The gate electrode formed on the barrier layer is preferably a Schottky type or a metal-insulator-semiconductor MIS type.

In the structure of the present invention, for example, the first embodiment, the conduction band profile in the vertical direction immediately below the ohmic electrode (see FIG. 4) in the state where no bias is applied is the vertical direction just below the ohmic electrode in the high concentration uniformly doped n-type GaN layer. As compared with the conduction band profile of (see FIG. 6), the electron barrier becomes smaller, and good ohmic characteristics can be expected. Furthermore, in the structure of the second embodiment, the electron barrier of the conduction band profile in the vertical direction immediately below the ohmic electrode is smaller than that of the structure of the first embodiment, and better ohmic characteristics can be expected (see FIG. 5).

Hereinafter, Examples 1 to 3 included in the second embodiment will be described in detail.
(Example 1: Structure for forming a gate electrode recessed between ohmic electrodes)
GaN layer of 100 nm thick as a buffer layer, GaN layer of 1 μm thick as a channel layer, and Al _0.15 Ga _{0.85 of} 6 nm thick as a barrier layer on an 8 inch diameter, 525 μm thick (111) surface silicon (Si) substrate N layer, n-type GaN layer of 1 nm in film thickness with 1 × 10 ¹⁸ cm ^{−3 of} Si added, layer of 1 × 10 ¹³ cm ^{−2 of} Si in sheet form as surface density, 1 × 10 ¹⁸ cm ^{− of} Si An n-type GaN layer with a film thickness of 20 nm doped with ³ was formed in this order by the metalorganic vapor phase epitaxy (MOCVD method) (FIG. 7- (a)). The substrate was heated to 1030 ° C. when the buffer layer was formed, and to 1130 ° C. when the other layers were formed. Next, element separation was performed by etching from the semiconductor surface to the middle of the GaN layer which is the channel layer by reactive ion etching ion implantation using CF ₄ as the etching gas (FIG. 7-(b)). . By depositing Ti / Al on the surface of the n-type GaN layer and heating at 800 ° C. for 30 seconds, an ohmic electrode was formed on the n-type GaN layer (FIG. 7- (c)). Next, between the ohmic electrodes, reactive ion etching using SF ₆ as the etching gas at the portion forming the gate electrode, the surface-side n-type GaN layer, the sheet-like Si layer, and the lower n-type GaN layer The layer is selectively etched (FIG. 7- (d)). Furthermore, a HEMT device was fabricated by depositing and lifting off Ni / Au at the opening (FIG. 7-(e)). The Si doping distribution in the epitaxial structure fabricated based on this example was measured by a SIMS apparatus. As a result, it was confirmed that there is a peak of Si concentration on the n-type GaN layer side in the vicinity of the interface between the element surface-side n-type GaN layer and the Al _0.15 Ga _0.85 N layer (see FIG. 8). The volume density of the Si concentration peak was almost as targeted, and was 0.9 × 10 ²⁰ cm ⁻³ (design value: 1 × 10 ²⁰ cm ⁻³ ). Incidentally, there was diffusion of Si on the element surface side.

Example 2: A structure in which a part of the gate is protruded on the insulating film in the FP structure
N-type with a buffer layer, GaN layer 1 μm, Al _0.15 Ga _0.85 N layer 6 nm, Si 1 × 10 ¹⁸ cm ⁻³ added on a (111) plane Si substrate in the completely same process as Example 1 A GaN layer of 1 nm, a layer of 1 × 10 ¹³ cm ^{−2 of} Si as a sheet density, and an n-type GaN layer of 20 nm of 1 × 10 ¹⁸ cm ^{−3 of} Si are sequentially formed by MOCVD in this order. Interelement isolation is achieved by etching to the middle of the 1 μm GaN layer from the semiconductor surface by reactive ion etching ion implantation using ₄ as the etching gas, and Ti / Al is vapor deposited on the surface of the n-type GaN layer. Ohmic electrodes were formed on the n-GaN layer by heating at 800 ° C. for 30 seconds (FIG. 9- (a) to FIG. 9- (c)). Next, Al ₂ O ₃ was formed to a film thickness of 10 nm on the entire element surface by atomic layer order deposition (ALD) (FIG. 9 (d)). Next, after removing the Al ₂ O _{3 in the} portion where the gate electrode is to be formed between the ohmic electrodes (FIG. 9-(e)), reactive ion etching using SF ₆ as an etching gas is used for the opening mask. The surface-side n-type GaN layer, the sheet-like Si layer, and the lower n-GaN layer are selectively etched (FIG. 9- (f)). A gate electrode was formed by vapor deposition and lift-off of Ni / Au at the electrode opening, to fabricate a HEMT device (FIG. 9- (g)).

Example 3 MIS-FET Structure
Ohmic electrodes were formed on the n-type GaN layer by the same process and film configuration as in Example 1 and Example 2 (FIG. 10- (a) to FIG. 10- (c)). Next, between the ohmic electrodes, the portion forming the gate electrode is reactive ion etching using SF ₆ as an etching gas to form an element surface side n-type GaN layer, a sheet-like Si layer, and its lower layer. The n-type GaN layer was selectively etched (FIG. 10- (d)). Al ₂ O ₃ was deposited to a thickness of 10 nm by atomic layer deposition (ALD) over the entire device surface (FIG. 10- (e)). A HEMT device was manufactured by forming a gate electrode by vapor deposition and liftoff of Ni / Au at the electrode opening (FIG. 10- (f)).

The Hall effect measurement of the stacked structure of high concentration Si-doped GaN / Al _0.15 Ga _0.85 N / n-type GaN shown in FIG. 8 was performed. As a result, the electron mobility μ: 560 cm ² / Vs (Si doping amount to the surface-side n-type GaN layer: 1.5 × 10 ¹³ cm ⁻² ), and the n-type doped GaN layer is removed by etching. The mobility μ could not be measured. If electrons flow only in the surface-side n-type GaN layer, the electron mobility is too high, so in the vicinity of the interface between the GaN layer as the channel layer and Al _0.15 Ga _0.85 N as the barrier layer. It is considered that electrons flow and ohmic contact is taken (see FIG. 11). The ohmic contact can not be obtained in the case of the Si uniformly doped structure to the n-type GaN layer.

The drain I-V measurement result in the HEMT of the laminated structure of Example 3 of the second embodiment of the present invention is shown in FIG. The average value of 10 samples is shown. The saturated drain current at a gate voltage of 8 V was 75 mA, the threshold voltage was 2 to 3 V, and the on-state specific resistance was 17 Ωmm.

Next, FIG. 13 shows the transfer characteristics (Id-Vg characteristics, drain voltage 8 V) in the HEMT of the laminated structure of Example 3 of the second embodiment of the present invention. It was found that the normally-off drain current was 10 ⁷ or more at the time of conduction with respect to the non-conduction drain current. The broken line is a change in gate voltage Vg per drain current (one digit change) in a region where the drain current Id changes linearly with respect to the gate voltage Vg, and this value is preferably small. It was 130 mV / dec when it measured in fact.

The present invention is used for a field effect transistor (FET), particularly, a normally-off type HEMT device having a small contact resistance.

Claims (9)

At least a channel layer, a barrier layer, and an n-type Si doped layer are sequentially stacked on the substrate, a source electrode and a drain electrode are formed on the n-type Si doped layer, and the n-type Si doped layer is removed on the barrier layer. a InAlGaN-based field effect transistor whose gate electrode is formed, at least part of the thickness direction of the n-type Si-doped layer, Ri site there a high concentration of Si concentration other sites, the channel layer , barrier layers, in the case of representing the n-type Si-doped layer as a channel layer / barrier layer / n-type Si-doped layer made laminated structure, the laminated structure _{GaN / Al X Ga 1-X} n (X> 0) / n -type _{GaN, Al X Ga 1-X} n / Al Y Ga 1-Y n / n -type GaN (0 <X <Y) , or _{GaN / in X Al 1-X} n (X> 0) / n -type GaN Either The concentration of Si in the n-type Si-doped layer is higher in the central portion than in the vicinity of the source electrode and the drain electrode and in the vicinity of the barrier layer, and the concentration change is stepped or continuous. Includes a sheet-like Si layer, and the Si concentration of the n-type Si-doped layer is 2 nm or less from the interface between the n-type Si-doped layer and the barrier layer by measurement with a SIMS device A GaN-based electric field having a peak (Highly-doped layer) of the Si concentration, and a valley of a conduction band extending from the interface between the n-type Si-doped layer and the barrier layer to the n-type Si-doped layer of 10 nm or more Effect transistor. The GaN-based field effect transistor according to claim 1, wherein the central portion is a sheet-like Si layer. The laminated structure is GaN / Al _X Ga _1-X The GaN-based field effect transistor according to claim 1 or 2, which is N (X> 0) / n-type GaN. The GaN-based field effect transistor according to any one of claims 1 to 3, wherein the laminated structure further comprises a buffer layer between the substrate and the channel layer. The n-type Si- doped layer is a region doped with n-type Si at a surface density Ns2 of at least 10% of the polarization charge in the barrier layer, and n-type with a surface density lower than the n-type Si surface density of the region The GaN-based field effect transistor according to claim 4, having a region doped with Si . The GaN-based field effect transistor according to claim 5, wherein the sheet density of the sheet-like Si layer is 10 ¹² cm ^-2 or more. The GaN-based field effect transistor according to any one of claims 1 to 6, wherein the thickness of the barrier layer is 1 to 10 nm, and the thickness of the n-type Si doped layer is 3 to 15 nm. The GaN-based field effect transistor according to claim 1, wherein the gate electrode is a Schottky type. The GaN-based field effect transistor according to any one of claims 1 to 7, wherein the gate electrode is a metal-insulator-semiconductor MIS type.