JP5190923B2 - Nitride semiconductor transistor having GaN as channel layer and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic device using a nitride semiconductor material, and more particularly to a nitride semiconductor transistor having a cap layer and using GaN as a channel layer and a method for manufacturing the same.

  GaN, which is a nitride semiconductor material having a large band gap, has features such as a high breakdown voltage and a high saturation drift speed. Therefore, if a GaN material is used, the resistance can be reduced without sacrificing the withstand voltage characteristics as compared with a silicon-based electronic device. Further, since it is chemically stable and thus stable at a high temperature, it can be used as a material for an electronic device that requires high output.

  GaN used for electronic devices is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation. Therefore, if a heterojunction structure such as an AlGaN / GaN junction is formed in parallel to the c-plane, a positive space fixed charge can be generated at the heterojunction interface due to the piezoelectric effect. By utilizing this, a two-dimensional electron gas can be formed at the heterojunction interface.

  For this reason, in a transistor or the like, an AlGaN / GaN heterojunction or an InAlN / GaN heterojunction formed in parallel with the c-plane is used to form a channel portion in which carriers travel, that is, electrons travel.

  An electronic device using a channel formed in a heterojunction mainly produced at present is a nitride semiconductor transistor having AlGaN / GaN as a channel layer. This transistor is manufactured as follows. As a layer structure, about 2 to 3 μm of non-doped GaN is grown on a substrate, and an AlGaN barrier layer is grown on the substrate to a thickness of about 10 to 50 nm. The AlGaN barrier layer is n-type doped to reduce ohmic resistance. The source electrode and the drain electrode are formed on the AlGaN barrier layer using a metal such as Ti / Al / Au. A metal such as Ni / Au or Pt is used for the gate electrode.

  On the other hand, a surface level exists on the surface of the AlGaN layer forming the AlGaN / GaN heterojunction. Since the AlGaN layer is as thin as 10 to 50 nm, electrons in the channel formed in the AlGaN / GaN heterojunction easily pass through the AlGaN layer when accelerated by an electric field.

  The electrons that have passed through are trapped in the surface level of the surface of the AlGaN layer, but the trapped electrons cannot easily return because the energy of the surface level is at a position deeper than the conduction band edge. . Although it depends on the depth of the surface level, it takes several seconds to several minutes. As a result, the amount of current flowing in the channel is reduced. This is called current collapse.

  This becomes a big problem when an electronic device is put into practical use. Despite applying the same drain voltage to the transistor, the drain current decreases with time. Also, the higher the drain voltage, the larger the current collapse, which becomes a serious problem when using a nitride semiconductor transistor as a switching device.

  In order to reduce current collapse, there is a method of covering a semiconductor surface with a GaN cap (Non-patent Document 1). This prevents the effect of the surface level formed on the AlGaN surface, but the deep level is still left on the GaN cap layer, which is improved for devices with high required breakdown voltage such as switching devices. There is a need to.

  In addition, an element using a GaN cap has a structure in which the composition is continuously changed from the AlGaN barrier layer to the GaN cap layer on the semiconductor surface (Patent Document 2). This is said to reduce current collapse and prevent the formation of holes. However, there is a problem that the level on the GaN cap layer remains.

Furthermore, although a method of forming a field plate on the GaN layer or p-type GaN cap layer on the semiconductor surface side between the gate and drain is shown, it is easy to discharge holes generated by avalanche amplification in the depletion layer region. (Patent Document 1). This also has a problem of the surface level formed on the GaN cap layer. Also, an example using a p-type InGaN cap layer is shown in order to more effectively discharge holes, but this is for reducing the contact resistance and facilitating the discharge of holes through the field plate electrode.
JP 2004-34907 A US Patent Application No. 2005/0077541 Published Specification Applied PhysicsLetters, vol. 85, No. 23, pp. 5745, 2004

  Therefore, the problem to be solved by the present invention is that in a nitride semiconductor transistor using GaN as a channel layer, when electrons in a channel formed in a heterojunction structure are accelerated, they are not easily trapped in the surface state. Is to do. Also, the trapped electrons can be easily returned.

That is, in the present invention, the problem is solved by providing the following nitride semiconductor transistor having GaN as a channel layer and a manufacturing method thereof.
(1) A channel layer of GaN having a cap layer containing In and N and Al and / or Ga and having a lattice constant larger than that of a GaN crystal on a semiconductor surface between the drain and the gate or between the gate and the source Nitride semiconductor transistor.
(2) The nitride semiconductor transistor using GaN as a channel layer according to (1), wherein the cap layer is p-type doped.
(3) The nitride semiconductor transistor using GaN as a channel layer according to (1), wherein the cap layer is p-type doped except for an interface on the channel side.
(4) The nitride semiconductor transistor using GaN as a channel layer according to (2) or (3), wherein the dopant concentration of the p-type doping is 5 × 10 ¹⁸ cm ⁻³ or more.
(5) The nitride semiconductor transistor using GaN as a channel layer according to (1), wherein the cap layer is delta-doped with an n-type dopant at a channel side interface.
(6) The nitride semiconductor transistor using GaN as a channel layer according to (5), wherein the concentration of the n-type dopant is 1 × 10 ¹⁸ cm ⁻³ or less.
(7) The nitride semiconductor transistor using GaN as a channel layer according to (1), wherein the lattice constant of the cap layer changes in a stepwise manner toward the semiconductor surface.
(8) The nitride semiconductor transistor using GaN as a channel layer according to (1), wherein the lattice constant of the cap layer changes so as to increase continuously toward the semiconductor surface.
(9) The barrier layer having the effect of generating carriers has a structure in which only the gate portion is thin, and a flattened cap layer is formed on the entire surface of the semiconductor surface between the source and drain. The nitride semiconductor transistor which uses GaN as described in (1) as a channel layer.
(10) including a step of forming a cap layer by regrowth over the entire surface of the semiconductor surface between the source and drain after forming a recess structure in the gate portion of the barrier layer having an effect of generating carriers. A method for producing a nitride semiconductor transistor using GaN as a channel layer according to claim 1.

  According to the present invention, current collapse can be reduced in a nitride semiconductor transistor having GaN as a channel layer.

  The nitride semiconductor material that can be used in the present invention is a semiconductor containing nitrogen composed of a group III element and a group V element. The main crystal structure is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation.

  A crystal composed of two elements such as GaN is suitable for the channel portion where the carrier travels. This is because a mixed crystal of three elements such as AlGaN, InGaN, and InAlN, and further a mixed crystal of four elements has a large alloy scattering resulting from the nonuniform composition. However, since the effective mass of electrons can be reduced for In, in the case of InGaN and InAlN, improvement in mobility can be expected.

  The heterojunction channel that can be used is a single heterostructure such as an AlGaN / GaN heterojunction, an AlGaInN / GaN heterojunction, or an InAlN / GaN heterojunction. It can also be used for double heterostructures such as AlGaN / GaN / AlGaN and InAlN / GaN / InAlN. In the case of a double heterostructure, a well portion sandwiched between barriers is a channel.

Hereinafter, the present invention will be described in detail by exemplifying an example used for a nitride semiconductor transistor having AlGaN / GaN as a channel layer.
Example 1
FIG. 1 shows a structure of a nitride semiconductor transistor having an InGaN cap layer and an AlGaN / GaN channel layer according to the present invention.

  As the crystal substrate 1 for forming the semiconductor crystal structure of the transistor, a sapphire substrate, a SiC substrate, a silicon substrate, a GaN substrate, or the like is used. For crystal growth, MOCVD may be used. After forming a structure for improving crystallinity such as the low-temperature growth GaN buffer layer 2 from the substrate side, the high-resistance GaN layer 3 is grown.

  Thereafter, an AlGaN barrier layer 4 is grown. The channel is formed on the high resistance GaN layer 3 side of the heterojunction surface of the high resistance GaN layer 3 and the AlGaN barrier layer 4. The AlGaN barrier layer 4 is partly or wholly n-type doped as necessary.

  Thereafter, the InGaN layer 5 is grown. The effect was obtained even when the In composition was 4% and the InGaN layer thickness was 5 nm. When the In composition was 15%, a stronger effect was obtained.

  Next, a mesa structure is formed leaving only the heterojunction structure used as a channel for the transistor. That is, the heterojunction structure between elements is removed and electrically separated in order to prevent unnecessary electrical continuity with other elements through the two-dimensional electron gas formed in the heterojunction structure.

  For this purpose, a photoresist mesa pattern having a rectangular shape of 20 μm in the direction in which the source electrode 10, the gate electrode 11, and the drain electrode 12 are aligned and 50 μm in the gate width direction is formed using a photoresist. The width and length of the mesa may be changed as necessary. The width of the gate electrode 11 and the width of the mesa are the same.

  As a method for producing a photoresist pattern, an exposure method using a commonly used stepper may be used. Thereafter, the grown substrate surface is processed into a mesa pattern by dry etching using a photoresist in the shape of a mesa as a mask.

  The dry etching is performed using, for example, chlorine plasma using an electron cyclotron resonance (ECR) method. Dry etching has a direction of etching compared to the wet etching method, and the etching rate is easily controlled. The etching rate varies depending on the crystal quality of the epitaxial film, the pressure of chlorine plasma, acceleration energy (plasma extraction voltage), etc., but is 200 to 300 nm per hour. Etching is performed to about 100 nm to remove portions of the AlGaN layer 4 and the GaN layer 3 other than the mesa.

  By forming the mesa, the elements on the same substrate are separated from each other, so that no current flows between the elements. The element isolation can be performed not only by dry etching using a chlorine-based gas but also by ion implantation. By isolating nitrogen ions or the like at a high speed, the elements may be electrically isolated from each other.

  After the mesa etching, an insulating film is formed in a portion other than the mesa. As the insulating film, a silicon oxide film, a silicon nitride film, or the like can be used. For example, after an insulating film is formed on the entire wafer surface with a thickness of about 100 nm using plasma CVD or the like, portions other than the mesa are covered with a photoresist, and only the insulating film on the top of the mesa is removed by etching. Pay attention to the part where the gate electrode 11 is located at the edge of the mesa. This is because the gate leakage current increases when the gate electrode 11 is in contact with the channel of the AlGaN / GaN heterojunction at the mesa interface. Therefore, the mesa interface is also covered with the insulating film.

  Thereafter, the source electrode 10 and the drain electrode 12 are formed. As the electrode metal of the source electrode 10 and the drain electrode 12, a Ti / Al / Ni / Au (30/220/40/50 nm) structure or the like is used from the substrate surface side. A lift-off method may be used for forming the electrode pattern.

  Electrode metal is deposited by electron beam evaporation. After the electrode metal is deposited, the electrode metal other than the pattern of the source and drain portions is removed by a lift-off method. Acetone may be used as the lift-off solution. Thereafter, annealing is performed for alloying the electrode metal. Annealing is performed at 800 ° C. for 30 seconds using a high-speed lamp annealing method (RTA).

  Thereafter, the gate electrode 11 is formed. Similarly, the lift-off method may be used. At this time, photolithography is used for patterning the resist in the shape of the gate electrode 11, but when the gate length is short and a fine pattern is used, electron beam lithography is used. For example, when the gate length is 200 nm or less, the electron beam lithography method is used.

As the gate electrode metal, Ni / Au (50/200 nm) is used from the substrate surface side. A high vacuum electron beam evaporation method may be used to form the gate metal. In this case, the evaporation source is heated by an electron beam and thermally evaporated.
The InGaN layer 5 immediately below the gate portion may be removed as necessary. In that case, dry etching may be used. Since the etching rate is fast, etching can be performed almost selectively.

  In addition, a silicon nitride film or a silicon oxide film is formed on the element surface such as the surface between the source and the drain by plasma CVD or the like in order to improve the breakdown voltage.

  FIG. 2 shows the result of switching the element manufactured by the method of the present invention in Example 1 at intervals of about 1 second. The horizontal axis is time, and the vertical axis is gate voltage and drain current. The gate voltage is switched between -3V and 0V at intervals of about 1 second. The drain voltage is 30V. The drain current is normalized to the amount of current per mm.

The AlGaN barrier layer 4 of the wafer used for manufacturing the device whose measurement results are shown in FIG. 2 has an Al composition ratio of about 25% and a film thickness of about 15 nm. The InGaN cap layer 5 has an In composition of about 3 to 5% and a film thickness of about 5 nm. The channel resistance immediately after growth is about 800Ω. The distance between the source and the gate is 2 μm, and the gate length is 3 μm. Further, in order to examine the influence of collapse, the distance between the drain and the gate was as long as 50 μm.
As can be seen from FIG. 2, immediately after the gate voltage reaches 0 V, the drain current rises and a substantially pulsed drain current is obtained.

  FIG. 3 shows a measurement result of an element without an InGaN cap layer for comparison. The AlGaN barrier layer thickness of this element is 15 nm. The distance between the source and the drain is 9 μm, the distance between the source and the gate is 2 μm, and the gate length is 1 μm. The gate width is 50 μm. The drain voltage is measured under the condition of 10V. The gate voltage is switched between -15V and 0V at intervals of about 1 second. The drain current is normalized to the amount of current per mm.

In the case of FIG. 3, it can be seen that even when the gate voltage is set to 0 V, the drain current does not rise easily and the drain current decreases with switching. This is a current collapse, and electrons are trapped in a deep surface level on the surface of the AlGaN barrier layer. Recovery is expected to take several minutes.
As can be seen by comparing FIG. 2 and FIG. 3, it was found that current collapse can be reduced by using the present invention.

  Since the lattice constant of InGaN is large, negative space charges are generated between the InGaN layer and the AlGaN layer due to the piezoelectric effect. As a result, the negative space charge is thought to have blocked the electrons.

(Example 2)
Further, similarly to the InGaN cap layer 5 of FIG. 1, an AlGaInN layer or InAlN layer having a lattice constant larger than that of the GaN layer can be used. Instead of the InGaN cap layer 5, an AlGaInN layer or an InAlN layer may be grown using a crystal growth method such as MOCVD. Since the optimal growth temperature of the AlGaN layer, AlGaInN layer, and InAlN layer differs depending on the composition, the growth is interrupted if growth interruption or the like is necessary, and the AlGaInN layer or InAlN layer is grown after changing the growth temperature. The manufacturing method and the like of the element are the same as in Example 1.

  If the lattice constant of the AlGaInN layer is larger than that of the GaN layer, negative space charges are generated by the piezo effect as in the case where the InGaN layer is used as the cap layer. Therefore, also in this case, the current collapse can be reduced. Similarly, when the InAlN layer is used as the cap layer, the current collapse can be reduced.

(Example 3)
Further, when the p-type doping was performed on the cap layer in order to further enhance the negative space charge effect, the effect was further improved. At this time, since the interface of the cap layer on the substrate side has the largest lattice strain, if a high concentration of Mg or the like is doped there, lattice defects are generated and the lattice strain is relaxed. Therefore, when p-type doping was performed away from the vicinity of the interface of the cap layer on the substrate side, there was an effect in reducing current collapse.

In an actually fabricated device, an InGaN cap layer having an In composition of about 15% was formed on an AlGaN barrier layer having an Al composition of 25% and a thickness of 20 nm. The 5 nm portion on the substrate side of the InGaN layer was not doped with Mg, and only the surface side of the InGaN layer was doped with a dopant concentration of about 1 × 10 ¹⁹ cm ⁻³ . As a result, there was an effect of reducing current collapse without lattice relaxation. The activation rate of the Mg dopant is about several percent, but it was effective at a dopant concentration of about 5 × 10 ¹⁸ cm ⁻³ or more.

Example 4
Also, the growth was interrupted and the growth temperature was changed, and then the InGaN cap layer was grown, but Si was supplied during the growth interruption, and Si was segregated at the interface between the InGaN cap layer and the layer immediately on the substrate side. However, the flatness of the cap layer surface was improved. Si or the like which is an n-type dopant has an effect such as anti-surfactant. This is probably because some effect was obtained in the early stage of growth of the InGaN cap layer. The density of the dopant was about 1 × 10 ¹⁸ cm ⁻³ or less.

(Example 5)
Next, a method for changing the composition of the cap layer will be described. Since the cap layer has a large lattice constant, the lattice is distorted, and a negative space fixed charge is formed by the piezoelectric effect on the hetero interface side of the cap layer, that is, the interface on the substrate side, and the charge blocks electrons. it is conceivable that. However, on the other hand, since the lattice constant of the cap layer is different from the lattice constant of the barrier layer immediately below the cap layer, transition may occur at the interface of the cap layer on the substrate side, and the lattice may be relaxed.

  Therefore, without directly growing a cap layer having a high lattice constant with a high In composition, the cap layer is divided into several layers and gradually increased from the substrate side to the outermost surface, and the In composition of the InGaN layer is gradually increased. Increase the lattice constant. The difference in lattice constant (a-axis, relaxed value) between adjacent layers was changed to about 0.5% or less. As an example, an InGaN layer 5 nm with an In composition of 5%, an InGaN layer 5 nm with an In composition of 10%, and an InGaN 5 nm with an In composition of 15% were grown in this order, and stable results were obtained in suppressing the collapse. The above is a case of dividing into 5 nm increments, but it may be 10 nm increments or 15 nm increments.

  The same applies when an AlGaInN layer or an InAlN layer is used as the cap layer. What is necessary is just to make it a layer by changing the composition stepwise so that the lattice constant (a-axis, the value at the time of relaxation) changes by about 0.5% at a film thickness interval of 5 nm or more.

The above is a method in which the cap layer is divided into several layers and the composition is changed stepwise so that the change in the lattice constant does not become steep. .
When the film thickness was in the range of 10 nm and the ratio was such that the lattice constant changed by about 2%, stable results were obtained.

(Example 6)
Further, the composition of the barrier layer at the heterostructure interface to the composition of the outermost surface of the cap layer can be continuously changed so that the band gap does not become discontinuous. In this case, it is possible to eliminate potential discontinuity when electrons trapped on the surface return to the channel through the barrier again, and the current collapse recovery time can be shortened.

A method of changing the composition of the cap layer will be described with reference to the drawings. There are AlGaN / GaN junctions, InAlN / GaN junctions, AlGaInN / GaN junctions, and the like as the types of heterojunctions forming the channel of the transistor. In both cases, GaN is bonded to a semiconductor having a lattice constant smaller than that of GaN, and a two-dimensional electron gas is formed by the piezoelectric effect. Here, a case of an Al _0.2 Ga _0.8 N / GaN junction will be described as an example.

  FIG. 4 shows the relationship between the lattice constant and the band gap. In this figure, the lattice constant of AlN is 3.11Å in the a-axis direction, 4.98Å in the c-axis direction, and the band gap is 6.2 eV. The lattice constant of GaN is 3.19 あ る in the a-axis direction, 5.19Å in the c-axis direction, and the band gap is 3.4 eV. The lattice constant of InN is 3.55３．５ in the a-axis direction, 5.76Å in the c-axis direction, and the band gap is 0.8 eV.

The barrier near the channel is an Al _0.2 Ga _0.8 N layer. A certain thickness is required. When the thickness is 15 nm or less, the number of carriers decreases due to the influence of the cap layer on the surface, and the sheet resistance increases. Therefore, 15 nm or more is necessary.

The method of changing the composition of the cap layer formed on the Al _0.2 Ga _0.8 N barrier layer is such that the lattice constant increases as it goes to the surface of the semiconductor element. That is, in FIG. 4, the composition is changed so as to go in the right direction. In the case where In _0.15 Ga _0.85 N is the outermost surface, an example is shown. In FIG. 4, Al _0.2 Ga _0.8 N → GaN → In _0.15 Ga _0.85 N or Al _0.2 Ga _0.8 N → AlGaInN ( Eg = 3.7 eV, a = 3.2 Å) → In _0.15 Ga _0.85 N The composition may be changed.

Alternatively, in order to make InAlN (a = 3.23Å) the outermost surface, the composition of In and Al increases in the upper right direction in FIG. 4 so that Al _0.2 Ga _0.8 N → InAlN (a = 3.23Å). Just go. The same applies when the final layer is an AlGaInN layer (Eg = 4.4 eV, a = 3.23 Å).

(Example 7)
In the above, the method of reducing current collapse by using an InGaN, AlGaInN, or InAlN layer having a large lattice constant as a cap layer has been described. The case where it is used for a layer will be described.

  In a nitride semiconductor transistor, an AlGaN layer having a band gap larger than that of GaN and a lattice constant smaller than that of GaN is bonded to the GaN layer, and carriers are generated at the heterojunction interface using the piezoelectric effect. This is a barrier layer having an effect of generating carriers. In the recess structure used for normally-off, the barrier layer having the effect of generating carriers only in the gate portion is thinned, and the carrier density is lowered only in the gate portion.

  For example, when an AlGaN layer is used as a barrier layer having an effect of generating carriers, the thickness of the AlGaN layer is set to about 10 nm only at the gate portion, and the AlGaN layer is formed between other sources and gates or between the drain and gates. The thickness is about 30 nm. As a result, the carrier density is reduced only in the gate portion, and normally-off can be achieved.

  On the other hand, in Example 1, a method for reducing current collapse using an InGaN, AlGaInN, or InAlN layer having a large lattice constant as a cap layer has been described. However, these cap layers having a large lattice constant have a negative space fixed charge. In order to form, it has the function of depleting electrons in the channel. Therefore, if these InGaN cap layer, AlGaInN cap layer, and InAlN layer are used for the surface layer of the recess structure of the gate portion, it becomes easy to shift the threshold voltage to the positive side and achieve the normally-off.

For this purpose, an InGaN cap layer, an AlGaInN cap layer, or an InAlN layer is formed by regrowth after forming a recess structure in the gate portion of the barrier layer that has an effect of generating carriers.
At this time, if regrowth is also performed on the surface between the source and gate and between the drain and gate, a discontinuous crystal portion does not occur, so that the performance of the transistor is not deteriorated.

  FIG. 5 shows the structure. It consists of a heterojunction barrier 8 adjacent to the heterojunction and a regrowth layer 9. The heterojunction barrier 8 is a barrier layer having an effect of generating carriers in the channel, and an AlGaN layer, an AlGaInN layer, an InAlN layer, or the like can be used. In this structure, the barrier having the effect of generating carriers is thin only in the gate portion and thick in other portions.

  The regrowth layer is a cap layer such as an InGaN layer, an AlGaInN layer, or an InN layer formed by regrowth after forming a recess structure in the gate portion of the heterojunction barrier. As in Example 3, Example 4, Example 5, Example 6, and the like, doping or composition change may be performed.

  In addition, an InGaN cap layer, an AlGaInN cap layer, and an InGaN cap layer are formed by the first growth from the beginning, and then a recess structure is formed in the gate portion, and the InGaN cap layer, the AlGaInN cap layer, The InGaN cap layer may be duplicated and regrown.

  Since the InGaN cap layer, the AlGaInN cap layer, and the InGaN cap layer are grown over the entire surface including the recess structure by regrowth, deterioration of the recess structure due to stress can be suppressed.

  Further, by optimizing the growth conditions, the surface of the regrowth layer 9 is flattened so that the height of the surface of the gate portion is the same as the height between the drain and the gate or the surface between the source and the gate. It is possible to make it. Even in this case, since the band gap change type structure layer has a recess structure, it can be normally-off. On the other hand, since the surface of the gate portion is flat, it was advantageous in a process using a fine pattern of a short gate electrode.

  It can be used for inverters and converters for household power supplies. Since the lateral element can increase the breakdown voltage with low loss, for example, it can be integrated with other electronic components, and the AC-DC converter of a household DC power source can be downsized. In addition, high-speed operation is possible, which is effective for energy saving.

It is a schematic diagram of a nitride semiconductor transistor having an InGaN layer on an AlGaN heterostructure between a drain and a gate and between a source and a gate and using GaN as a channel layer. It is a measurement result of the change of the drain current when there is an InGaN cap layer. It is a measurement result of the change of the drain current when there is no InGaN cap layer. It is a relationship diagram of a lattice constant and band gap energy. It is a schematic diagram of a normally-off type nitride semiconductor transistor comprising a heterojunction barrier layer and a regrowth layer.

Explanation of symbols

1: Substrate 2: Buffer layer 3: GaN layer 4: Heterobarrier layer 5: InGaN cap layer 8: Heterojunction barrier 9: Regrown layer 10: Source electrode 11: Gate electrode 12: Drain electrode

Claims (4)

Nitriding using GaN as a channel layer having a cap layer containing In and N and Al and / or Ga and having a lattice constant larger than that of a GaN crystal on the semiconductor surface between the drain and the gate or between the gate and the source A semiconductor transistor ,
The lattice constant of the cap layer, nitride compound semiconductor transistor you characterized in that it varies so as to increase stepwise as it goes to the semiconductor surface. Nitriding using GaN as a channel layer having a cap layer containing In and N and Al and / or Ga and having a lattice constant larger than that of a GaN crystal on the semiconductor surface between the drain and the gate or between the gate and the source A semiconductor transistor ,
The lattice constant of the cap layer, nitride compound semiconductor transistor characterized in that it changes as increases continuously as it goes to the semiconductor surface. Nitriding using GaN as a channel layer having a cap layer containing In and N and Al and / or Ga and having a lattice constant larger than that of a GaN crystal on the semiconductor surface between the drain and the gate or between the gate and the source A semiconductor transistor ,
The thickness of the barrier layer that is effective for generating a carrier is thinner only the gate portion, it wherein the cap layer that is entirely the planarization of the semiconductor surface between the source and drain is formed nitride nitride semiconductor transistor. After forming the recess structure in the gate portion of the barrier layer that is effective for generating a carrier, over the entire surface of the semiconductor surface between the source and drain, characterized in that it comprises a step of forming a cap layer by regrowth, wherein the method for manufacturing a nitride compound semiconductor transistor according to claim 3.

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