JP6447142B2 - Receiving circuit, receiving apparatus and receiving method - Google Patents

Description

  The present invention relates to a receiving circuit, a receiving apparatus, and a receiving method.

  The receiving circuit (receiver) of the SERializer / DESerializer (SERDES) circuit that transmits high-speed data (Data) signals is equipped with a filter called an equalizer, and intersymbol interference (InterSymbol Interference after being transmitted on the transmission line) : Correct signal waveform distorted by ISI). The equalizer is realized by a linear equalizer (LE), a decision-feedback equalizer (DFE), or a combination of LE and DFE.

  On the other hand, the receiving circuit is equipped with a logic circuit called a clock data recovery (CDR) circuit for detecting the boundary phase corresponding to the changing edge of the received data signal and tracking the boundary. The intermediate phase between two adjacent boundaries almost matches the optimum capture position of the received data signal.

  When boundary data is generated in the DFE from the received data signal, the load capacity of the LE in the previous stage is increased, the band is limited, and transmission quality deteriorates. In order to avoid this problem, it is conceivable that DFE processing is not performed for the generation of boundary data.

  However, the boundary intermediate phase determined from the boundary data generated without the DFE processing does not match the phase of the optimal capture (capture) position of the reception data generated from the reception data signal in the DFE processing, and there is a phase shift. Arise.

  In order to solve this phase shift problem, it is conceivable to set the optimum phase by manual processing in the manufacturing process, but there is a problem that the number of work steps increases.

  Therefore, it is hoped that the boundary phase is determined based on the boundary data generated from the reception data signal not subjected to DFE processing, and the optimum data (Data) phase for taking in the reception data signal subjected to DFE processing can be automatically adjusted. It is rare.

JP 2012-170081 JP 2013-135423 A

  According to the embodiment, a wideband receiving circuit that automatically adjusts a received data signal so as to take in an optimum phase is realized.

  The receiving circuit according to the first aspect includes a decision feedback equalizer, a sample circuit, a clock data recovery circuit, a data phase detection circuit, and a phase shifter. The decision feedback equalizer performs a decision feedback equalization process on the received data signal captured in synchronization with the clock, and outputs equalized reception data and error data. The sample circuit captures the boundary data of the received data signal. The clock data recovery circuit detects the boundary phase from the equalized reception data and boundary data. The data phase detection circuit calculates the inter-symbol interference amount of the target bit 1 UI before the target bit for two different filter patterns in which the signal polarities 1 UI before and 1 UI of the target bit are inverted from the equalized reception data and error data. The amount of intersymbol interference after 1 UI of bits is detected, and the data phase is detected from the difference between the amount of intersymbol interference before 1 UI and the amount of intersymbol interference after 1 UI. The phase shifter generates a clock from the boundary phase and the data phase, and outputs the clock to the decision feedback equalizer.

  According to the embodiment, a receiving circuit that has a wide band and automatically adjusts a received data signal so as to take in an optimum phase is realized.

FIG. 1 is a diagram illustrating a configuration of a communication system using a SERDES circuit. FIG. 2 is a diagram illustrating a configuration of a general receiving circuit. FIG. 3 is a diagram illustrating a circuit example of LE. FIG. 4 is a diagram illustrating a DFE circuit example. FIG. 5 is a diagram for explaining error data. FIG. 6 is a diagram illustrating a configuration example of another receiving circuit in which the DFE processing is not performed for the generation of boundary data in the receiving circuit of FIG. 7A and 7B are diagrams showing examples of signal shape changes in the receiving circuit, where FIG. 7A shows a waveform during transmission, FIG. 7B shows a waveform at the input end of the receiving device, and FIG. The waveform after breaking is shown. FIG. 8 is a diagram illustrating a configuration of the receiving circuit according to the embodiment. FIG. 9 is a diagram illustrating data phase determination processing in the receiving circuit according to the embodiment. FIG. 10 is a diagram showing an example of a waveform when the difference between h ₋₁ and h ₁ is not zero, (A) shows a case where h ₋₁ is larger than h ₁ , and (B) shows h ₋₁ is h. Indicates a case of less than ₁ . FIG. 11 is a flowchart illustrating processing in the receiving circuit of the embodiment. FIG. 12 is a diagram for explaining a case where “011” and “110” are used as two filter patterns (FP) and the sign of the difference between h ₋₁ and h ₁ is detected by error data. . FIG. 13 is a diagram illustrating a circuit example of a data phase detector that performs processing of adding the ISI amounts in the above-described −1 UI and +1 UI. FIG. 14 is a flowchart showing processing in the data phase detector that performs pattern matching with two filter patterns (FP). FIG. 15 is a diagram illustrating simulation results of a boundary phase, a data (Data) phase, and a convergence process of received data in the receiving circuit of the embodiment. FIG. 16 is a table comparing the man-hours and transmission quality (bandwidth) of adjustment operations in the final manufacturing process for the receiving circuit of the embodiment and the receiving circuits of FIGS. 2 and 6.

  Before describing the receiving circuit of the embodiment, a general receiving circuit will be described.

  The receiving circuit (receiver) of the SERializer / DESerializer (SERDES) circuit that transmits high-speed data (Data) signals is equipped with a filter called an equalizer, and intersymbol interference (InterSymbol Interference after being transmitted on the transmission line) : Correct signal waveform distorted by ISI).

FIG. 1 is a diagram illustrating a configuration of a communication system using a SERDES circuit.
The communication system includes a transmission device (transmitter (TX)) 10, a transmission line (channel) 15, and a reception device (receiver (RX)) 20. The transmission apparatus 10 includes a transmission data processing circuit 11, a multiplexer (MUX) 12, and a driver 13. The transmission data processing circuit 11 generates transmission data (Data). The multiplexer 12 converts the parallel data output from the transmission data processing circuit 11 into serial data. The driver 13 outputs serial data to the channel 15. The reception device 20 includes an equalizer 21, a demultiplexer (DEMUX) 22, and a reception data processing circuit 23. As described above, the equalizer 21 corrects the waveform of the received data signal distorted by transmission on the transmission path. The demultiplexer 22 converts serial data output from the equalizer 21 into parallel data. The reception data processing circuit 23 processes reception data (Data) which is parallel data output from the demultiplexer 22.

  Further description of the configuration of the communication system of FIG. 1 is omitted.

  The equalizer is realized by a linear equalizer (LE), a decision-feedback equalizer (DFE), or a combination of LE and DFE. The DFE has a function of estimating and correcting waveform deterioration information from past data strings.

FIG. 2 is a diagram illustrating a configuration of a general receiving circuit.
The reception circuit includes a linear equalizer (LE) 31, a DFE 32, a DEMUX 33, a boundary phase detector 34, a phase shifter 35, and an adaptive logic circuit 36.

FIG. 3 is a diagram illustrating a first-order continuous-time linear equalizer (CTLE), which is a circuit example of the LE 31.
The LE 31 has a differential amplifier circuit, receives a differential reception data signal having a high frequency component attenuated by transmission through the channel 15 as a CTLE input, performs linear equalization processing to amplify the attenuated high frequency component, and outputs a CTLE. Output as. Since the linear equalizer is widely known, further explanation is omitted.

FIG. 4 is a diagram illustrating a circuit example of the DFE 32.
The DFE 32 includes an adder 41, a determination circuit 42, and a feedback filter 43. The adder 41 removes the influence of the past data string by adding the inverted signal of the influence caused by the past data string (up to several cycles before) to the linearly corrected received data signal from the LE 31. The determination circuit 42 is formed of, for example, a comparator that compares the output of the adder 41 with a reference level, and determines the value (0 or 1) of the received data signal from which the influence of the past data string has been removed in synchronization with the clock. Determine as value. The feedback filter 43 multiplies the coefficient corresponding to the influence of the past data string generated by the determination circuit 42 and outputs the result to the adder 41. With the above configuration, the DFE 32 estimates waveform deterioration information from the past data string, corrects the received data signal, generates binary received data, and outputs it as a DFE output. The DFE 32 further generates error (Error) data according to the difference between the corrected received data signal and the reference level of 0 or 1 as well as the received data, and generates the combined data as a DFE output. Since DFE is widely known, further explanation is omitted.

  The reception data signal received by the reception circuit 30 in FIG. 2 is a signal that changes in one cycle (1 UI) of the clock, and the change edge is referred to as a boundary phase. The received data signal is stable in the middle of the boundary, that is, the phase of the boundary phase + 0.5 UI, and the determination circuit in FIG. 4 determines the received data signal at this timing. On the other hand, the boundary phase detector 34 detects the changing edge of the received data signal (in the case of a differential received data signal, the timing at which the normal phase signal and the negative phase signal cross), and follows the boundary so as to follow the changing edge. (Boundary) phase is generated. The phase shifter 35 generates a data clock CLK by shifting the boundary phase by 0.5 UI, and supplies the data clock CLK to the determination circuit 42 of the DFE 32 as a clock.

  The DFE 32 includes a circuit shown in FIG. 4 as a boundary DFE in order to detect the progress or delay of the boundary phase. Although not shown, the DFE 32 has a boundary that changes in the boundary phase as a clock. Clock is supplied. The boundary DFE takes in the reception data signal at the boundary phase and outputs it as boundary data. The phase difference between the actual change edge of the received data signal and the supplied boundary clock can be obtained from the boundary data. Since the generation of boundary data in DFE is widely known, further explanation is omitted.

  As described above, the DFE 32 generates and outputs received data (Data), error (Error) data, and boundary data (Boundary) from the received data signal.

  Returning to FIG. 2, the DEMUX 33 converts the received data (Data), error (Error) data, and boundary data (Boundary), which are serial data output from the DFE 32, into parallel data and outputs the parallel data.

  As described above, the boundary phase detector 34 detects a changing edge of the received data signal and generates a boundary phase so as to follow the changing edge. The boundary phase detector 34 determines whether the boundary clock is advanced or delayed with respect to the change edge of the reception data signal from the reception data and boundary data that are parallel data output from the DEMUX 33. The boundary phase detector 34 changes the phase of the boundary clock so that the boundary clock follows the change edge of the received data signal, and outputs the boundary phase at that time to the phase shifter 35. Since these operations are operations for recovering the clock of the received data signal, the boundary phase detector 34 is called a clock data recovery (CDR) circuit.

  The adaptive logic circuit 36 generates LE coefficients and DFE coefficients that are fed back to the LE 31 and DFE 32 for equalization processing from the received data (Data), error data, and boundary data (Boundary) of the parallel data.

FIG. 5 is a diagram for explaining error data.
In FIG. 5, + Vref and −Vref are data signal amplitude values without intersymbol interference (ISI), + Vref corresponds to the data value “1”, and −Vref corresponds to the data value “0”. The receiving circuit determines that the data value is “1” when the level is equal to or higher than zero level, and is “0” when the level is lower than zero level. The horizontal axis is a time axis in units of UI (Unit Interval), and the data signal is assumed to change in the middle of the integer UI.

  The received data signal corresponds to the data of 10101010 and exceeds + Vref in 1 UI, and is determined to be “1”, and the difference between the level of received data in 1 UI and + Vref is error 1 (Error 1). The error data is positive when it is higher than + Vref when it is determined to be “1”, negative when it is lower than + Vref, and negative when it is lower than −Vref when it is determined as “0”. High is positive. Therefore, error 2 which is the difference between the received data level at 2UI and -Vref is a positive value, and error 3 which is the difference between the received data level at 3UI and + Vref is a negative value. Error 4 in 4UI is a negative value, error 5 in 5UI is a positive value, error 6 in 6UI is a negative value, and error 7 in 7UI is a negative value.

  Heretofore, a general receiving circuit that uses LE and DFE in combination as an equalizer has been described. The receiving circuit described here is an example, and various modifications have been proposed.

  The receiving circuit of FIG. 2 generates boundary data by the DFE 32, and it is necessary to provide a circuit for executing the DFE processing as shown in FIG. 4 on the boundary data generation path. The load capacity increases, and the bandwidth is limited. As a result, transmission quality deteriorates. In order to avoid this problem, it is conceivable that DFE processing is not performed for the generation of boundary data.

  FIG. 6 is a diagram illustrating a configuration example of another receiving circuit 30A in which the DFE processing is not performed for the generation of boundary data in the receiving circuit of FIG.

  The receiving circuit 30A is different from the DFE 32 in that a DFE 37 that generates reception data and error data from the output of the LE 31 and a sample circuit (Sampler) 38 that generates boundary data from the output of the LE 31 are provided. The DFE 37 is the same as the DFE 32 in FIG. 2 except that a part for generating boundary data is removed.

  The sample circuit 38 is formed of, for example, a comparator similarly to the determination circuit 42 in FIG. 4, and determines the comparison value as boundary data in synchronization with the boundary phase.

  7A and 7B are diagrams illustrating examples of changes in signal shape in the receiving circuit 30A, where FIG. 7A is a waveform at the time of transmission, FIG. 7B is a pulse response at the input end of the receiving device 20, and FIG. The pulse response after processing is shown.

As shown in FIG. 7A, the pulse signal output from the driver 13 of the transmission device 10 has a rectangular shape. The pulse signal output from the driver 13 attenuates the high frequency by passing through the transmission line 15, and becomes a blunt pulse as shown in FIG. 7B at the input end of the receiving device 20. Waveform correction (linear equalization processing) is performed on the blunt pulse shown in FIG. 7B by LE31 to obtain a waveform as shown in FIG. In FIG. 7B, h _n (n = −2 to 6) indicates the signal intensity at the center of each UI. Since the original signal is the pulse shown in FIG. 7A, h _n (n ≠ 0) is the amount of ISI (intersymbol interference) in each UI, and can be said to be an error amount.

  The sample circuit 38 samples the waveform shown in FIG. 7C and generates boundary data. The boundary phase detector (CDR) 34 performs phase adjustment so as to reduce the difference between the boundary phase indicated by the boundary data and the change edge of the received data signal. As shown in FIG. 7C, this processing is equivalent to searching for two points having a width of 1 UI in the waveform shown in FIG. 7C, and the boundary phase is 2 Will lock into one point.

  As described above, when the data (Data) phase is shifted by 0.5 UI from the boundary phase, the edge (phase) of the clock CLK is located between the two lock points in FIG. At that timing, the DFE 37 takes in the received data signal. As shown in FIG. 7C, the intermediate position of the two lock points is shifted from the position of 0 UI, and the position of 0 UI is between -0.5 UI and 0 UI on the left side of the middle of the two points. Exists.

  In the DFE 37, the received data signal is subjected to DFE equalization processing, and the peak of the received data signal is corrected so as to coincide with the position of 0 UI. Therefore, when the phase of the clock CLK is set as a position where the data (Data) phase is shifted by 0.5 UI from the boundary phase, the DFE 37 captures (captures) data at a position shifted from the peak of the waveform of the received data signal. Thus, the optimum phase is deviated. The optimum data (Data) phase in the DFE 37 exists at a position shifted from 0 UI to 0.5 UI phase from the boundary phase.

  As described above, when the boundary phase is determined based on the boundary data generated from the reception data signal not subjected to the DFE processing, and the reception data signal subjected to the DFE processing is captured with the clock phase shifted by 0.5 UI therefrom, The timing is off.

  In order to eliminate this timing shift problem, in the manufacturing process, the data (Data) phase in FIG. 6 is manually swept between 0 UI and 0.5 UI from the boundary phase, and the point where the transmission state is the best is manually set. It is determined by processing, and is set as a data (Data) phase.

  However, when searching for the data phase manually, it is necessary to make manual settings after manual adjustment with actual products by measurement, etc., in order to perform optimal settings, and an investigation period before product shipment is required. This leads to an increase in man-hours.

  Furthermore, when the optimum data (Data) phase is different in each lane (receiver circuit) due to process variations or the like, manual adjustment for each lane at the time of product shipment is difficult due to time constraints. Accordingly, a fixed value is given to all lanes (or for each group of lanes), and depending on the lane, the transmission margin is reduced because the lanes deviate from the optimum data (Data) phase.

  In the embodiment described below, the boundary phase is determined based on the boundary data generated from the received data signal that has not been subjected to DFE processing, and the data (Data) phase that is optimal for capturing the DFE-processed received data signal is determined. A receiver circuit having an automatic adjustment function is provided.

FIG. 8 is a diagram illustrating a configuration of the receiving circuit according to the embodiment.
The receiving circuit 50 of the embodiment is used for the receiving portion of the receiving device 20 shown in FIG.
The receiving circuit 50 of the embodiment includes a linear equalizer (LE) 31, a DEMUX 33, a boundary phase detector 34, a phase shifter 35, an adaptive logic circuit 36, a DFE 37, and a sample circuit 38. And a data phase detector 39.

  The receiving circuit 50 of the embodiment adds a data (Data) phase detector 39 for detecting a data (Data) phase from received data and error data, and generates a data (Data) phase generated by the data (Data) phase detector 39. Is different from the receiving circuit of FIG.

FIG. 9 is a diagram illustrating data phase determination processing in the receiving circuit according to the embodiment.
As described with reference to FIG. 7, the intermediate position of the boundary searched from the received data signal that has not been subjected to DFE processing deviates from the data center position of the received data signal that has undergone DFE processing. As shown in FIG. 9, since the received data obtained from the DFE-processed received data signal has a symmetric waveform with respect to 0 UI, the DFE-processed received data signal is 1 UI before (−1 UI) and 1 UI after If the data phase is determined so that h ₋₁ and h _1, which are (+1 UI) ISI, are equal, the edge of the clock coincides with the data center position.

In the embodiment, as shown in FIG. 9, the data phase detector 39 detects h ₋₁ and h ₁ from the received data and error data obtained from the DFE processed received data signal, and h ₋₁ and h _1. The data phase is determined so that. In other words, the data (Data) phase detector 39 locks the control so that the error data h ₋₁ and h _{1 at} positions separated by 2 UI are equal. The data phase is an intermediate point between h ₋₁ and h ₁ (in the middle of the two circles in FIG. 9), and the peak position of the pulse response of the received data is located between the two circles. The phase will be optimal and data will be captured at the peak.

FIG. 10 is a diagram showing an example of a waveform when the difference between h ₋₁ and h ₁ is not zero, (A) shows a case where h ₋₁ is larger than h ₁ , and (B) shows h ₋₁ is h. Indicates a case of less than ₁ .

In the case of FIG. 10A, since the data phase is delayed, by converging the data phase, convergence is made at a point where the difference between h ₋₁ and h ₁ becomes zero. In the case of FIG. 10B, since the data phase is advanced, the data phase is delayed to converge at a point where the difference between h ₋₁ and h ₁ becomes zero.

  The amount to change the data phase is Δt, and Δt is the minimum resolution of the phase shifter 35 (a value sufficiently smaller than 1 UI, for example, about 1/100 of 1 UI).

FIG. 11 is a flowchart illustrating processing in the receiving circuit 30A of the embodiment.
In step S11, two filter patterns (FP) suitable for detecting symmetry are set in the data phase detector 39. The two FPs are two different patterns in which the signal polarity before and after 1 UI of the target bit that is an error observation point is inverted.

In step S12, an error amount is detected (calculated) when the received data matches the pattern. At this time, when receiving the received data matching the two FPs, the data phase detector 39 determines whether or not to calculate the two FPs so that the number of calculations is equal. The calculation detects a pre-cursor ISI (h ₋₁ ) before ₁ UI and a post-cursor ISI (h ₁ ) after ₁ UI based on an error value.

In step S13, the data phase detector 39 detects (calculates) the difference between the pre-cursor ISI (h _-1 ) and the post-cursor ISI (h ₁ ).

The phase shifter 35 determines whether the difference (h ₋₁ −h ₁ ) is positive or negative. If the difference is positive, the process proceeds to step S15, and if negative, the process proceeds to step S16.

In step S15, the phase shifter 35 advances the data phase by Δt and returns to step S12.
In step S16, the phase shifter 35 delays the data phase by Δt and returns to step S12.

When the difference (h ₋₁ −h ₁ ) becomes sufficiently small, it is determined that the difference has converged, and the received data is validated and output as actual data.

  Next, the calculation process in the data phase detector 39 will be described in more detail using a specific example of the filter pattern (FP).

FIG. 12 is a diagram for explaining a case where “011” and “110” are used as two filter patterns (FP) and the sign of the difference between h ₋₁ and h ₁ is detected by error data. .

In this example, the sign of the difference between the ISI amounts (corresponding to h ₋₁ and h ₁ respectively) at −1 and +1 on the horizontal axis in FIG. 7B is detected, and data (Data ) Determines the phase adjustment direction. As shown in FIG. 5, the error amount here is the difference between the reference amplitude value and the actual data (Data) amplitude value, which is the data (Data) amplitude value in the absence of ISI. Amount. This error amount includes all ISI amounts exerted from other symbols on the time series, and two FPs for filtering the received data string are used to extract a specific ISI amount from the ISI amount. As shown in FIG. 12, a different 3-bit pattern of “011” and “110” is applied to each of the two FPs, and each error amount is “1” (position D4) of the second bit. Detect E ₄ and take the difference. As a result, all ISI terms other than h _-1 and h _{1 in} the equation of FIG. 12 are canceled, and the difference 2 × (h _-1 -h ₁ ) between h _-1 and h ₁ can be detected. It is said. If this value is 0 or more (sign positive) h _-1> h ₁ Since the phase has been delayed, adjusted in a direction to advance the phase, 0 or less if the (negative sign) h _-1 <h ₁ Therefore, the phase is advanced, and the phase is adjusted to be delayed.

FIG. 13 is a diagram illustrating a circuit example of a data phase detector that performs processing of adding the ISI amounts in the above-described −1 UI and +1 UI.
The data phase detector 39 includes an FP0 detector 51, an FP1 detector 52, a 1 × multiplier 53, a −1 × multiplier 54, a selector 55, an FP balancer 56, and an adder 57. Latch 58.

The FP0 detector 51 determines whether or not the received data (Data) string matches the FP0 pattern, and outputs an error amount +1 or −1 when matching, and outputs 0 when not matching. The amount of error when pattern matching with FP0 represents (h _-1 -h ₁ ). The FP1 detector 52 determines whether or not the received data (Data) string matches the FP1 pattern, and outputs an error amount +1 or −1 when matching, and outputs 0 when not matching. The amount of error when pattern matching with FP1 represents (h ₁ -h _-1 ).

  The multiplier 53 multiplies the error amount output from the FP0 detector 51 by 1, and the multiplier 54 multiplies the error amount output from the FP1 detector 52 by -1. The FP balancer 56 controls the selector 55 to alternately select the outputs of the multipliers 53 and 54 when the FP0 detector 51 and the FP1 detector 52 have a pattern match. Therefore, even if the FP0 pattern match occurs continuously, if the FP1 pattern match does not occur, the output of the multiplier 53 is ignored until the FP1 pattern match occurs.

The adder 57 and the latch 58 form an integrator, and integrates a difference obtained by subtracting the error amount in the case of the FP1 pattern match, which is output from the selector 55, from the error amount in the case of the FP1 pattern match. This is equivalent to detecting 2 × (h ₋₁ -h ₁ ).
The data phase detector 39 in FIG. 13 is realized by a DSP, for example.

  FIG. 14 is a flowchart showing processing in the data phase detector that performs pattern matching with two filter patterns (FP).

  In step S21, two filter patterns (FP) suitable for detecting symmetry are set in the data phase detector 39. This is the same as step S11 in FIG.

In step S22, the data phase detector 39 detects (calculates) an error amount when the received data pattern matches (matches) FP0. Specifically, the data phase detector 39 determines the pre-cursor ISI (h ₋₁ ) before ₁ UI and the post-cursor ISI ( ₁ ) after ₁ UI based on the error value. h ₁ ) The difference is detected.

In step S23, the data phase detector 39 determines whether or not the difference (h ₋₁ −h ₁ ) is positive. If it is positive, the process proceeds to step S24, and if not positive, the process proceeds to step S25.

  In step S24, the data phase detector 39 outputs the data phase for advancing the phase, and in response, the phase shifter 35 advances the data phase by Δt.

  In step S25, the data phase detector 39 outputs a data phase that delays the phase, and in response thereto, the phase shifter 35 delays the data phase by Δt.

In step S26, the data phase detector 39 detects (calculates) an error amount when the received data matches the pattern FP1. Specifically, the data phase detector 39 determines the pre-cursor ISI (h ₋₁ ) before ₁ UI and the post-cursor ISI ( ₁ ) after ₁ UI based on the error value. h ₁ ) The difference is detected.

In step S27, the data phase detector 39 determines whether or not the difference (h ₋₁ −h ₁ ) is positive. If it is positive, the process proceeds to step S84, and if not positive, the process proceeds to step S29.

  In step S28, the data phase detector 39 outputs a data phase for advancing the phase, and in response, the phase shifter 35 advances the data phase by Δt.

  In step S29, the data phase detector 39 outputs a data phase that delays the phase, and in response, the phase shifter 35 delays the data phase by Δt.

  FIG. 15 is a diagram illustrating simulation results of a boundary phase, a data (Data) phase, and a convergence process of received data in the receiving circuit of the embodiment.

  In FIG. 15, the solid line indicates the boundary phase, the broken line indicates the data (Data) phase, and the hatched range indicates the amplitude of the received data (Data). In this case, it can be seen that the data phase converges around 30 ° (in this simulation, 180 ° = 1 UI, so 30 ° = 0.17 UI).

  As shown in FIG. 15, when a data signal is received, data cannot be received correctly until the data (Data) phase converges. Therefore, a certain period of time until the data phase converges includes the data acquired as a training period. Invalid. Then, after the training period ends, the received data is validated. At this time, there is no difference in operation of the data (Data) phase detector before and after the training period, and the data phase is continuously adjusted even after the training period. As a result, even when the environmental conditions (temperature, power supply voltage, etc.) change and the optimal data phase changes, it is possible to quickly converge to the optimal data phase.

  FIG. 16 is a table comparing the man-hours and transmission quality (bandwidth) of adjustment operations in the final manufacturing process for the receiving circuit of the embodiment and the receiving circuits of FIGS. 2 and 6.

  Since the receiving circuit of the embodiment and the receiving circuit of FIG. 2 do not perform the adjustment operation and only need to confirm the operation, the number of work steps is small. On the other hand, as described above, the receiving circuit in FIG. 6 manually sweeps the data (Data) phase between 0 UI and 0.5 UI from the boundary phase, and the point where the transmission state is the best is obtained. Determined by manual processing. This setting requires manual setting after manual adjustment with an actual product or the like by measurement or the like, leading to an increase in man-hours. Here, this work man-hour is estimated to be about 20 times as compared with the case of only the operation confirmation.

  Further, since the receiving circuit of FIG. 2 uses the received data signal that has been subjected to the DFE process for detecting the boundary data, the load capacity of the LE 31 is 1.6 times. For this reason, the bandwidth is limited, and the bandwidth is reduced to about 60% compared to the case where boundary data is detected for a received data signal that is not subjected to DFE processing as in the receiving circuit of the embodiment and FIG. To do. Thus, it can be said that the receiving circuit of the embodiment has good characteristics in both work man-hours (manufacturing cost) and transmission quality.

  Although the receiving circuit of the embodiment has been described above, it goes without saying that various modifications are possible. For example, in the embodiment, the two filter patterns are “110” and “011”, but “001” and “100” may be used, or a pattern of 5 bits or more may be used.

  According to the embodiment, it is possible to automatically detect a data phase without applying DFE to boundary data. In SERDES, in order to automatically adjust the coefficients of equalizers such as LE and DFE, observation circuits for pre-cursor ISI amounts and post-cursor ISI amounts are often mounted. Usually, these observation circuits capture the information of the ISI amount, that is, the voltage direction, and apply feedback in the voltage direction in order to cancel them, and do not feed back the phase amount, that is, the offset in the time direction. The receiving circuit of the embodiment diverts the function, and the addition of hardware is also realized on a small scale. In addition, in the embodiment, since the data phase is automatically adjusted, the time required for manual adjustment in the manufacturing process can be saved, thereby reducing the man-hours until product shipment and the transmission quality by absorbing individual differences due to process variations. Improvement can be expected.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

20 Receiver 21 Equalizer 22 Demultiplexer (DEMUX)
23 Receive Data Processing Unit 31 LE
33 Demultiplexer (DEMUX)
34 Boundary phase detector 35 Phase shifter 36 Adaptive logic circuit 37 DFE
38 Sample circuit
39 Data phase detector

Claims (9)

A decision feedback equalizer that performs decision feedback equalization on the received data signal captured in synchronization with the clock and outputs equalized reception data and error data; and
A sample circuit for capturing boundary data of the received data signal;
A clock data recovery circuit for detecting a boundary phase from the equalized reception data and the boundary data;
From the equalized reception data and the error data, the inter-symbol interference amount before 1 UI of the target bit and the target bit of the target bit for two different filter patterns in which the signal polarity before 1 UI and after 1 UI of the target bit is inverted are obtained. A data phase detection circuit that detects an intersymbol interference amount after 1 UI and detects a data phase from a difference between the intersymbol interference amount before 1 UI and the intersymbol interference amount after 1 UI;
And a phase shifter that generates the clock from the boundary phase and the data phase and outputs the clock to the decision feedback equalizer.   The data phase detection circuit accumulates the difference between the intersymbol interference amount before 1 UI and the intersymbol interference amount after 1 UI for each filter pattern so that the two filter patterns have the same number of times. The receiving circuit according to claim 1, wherein the data phase is determined so that a difference between the two differences becomes zero. The data phase detection circuit detects, as the data phase, the phase change direction of the clock corresponding to the direction in which the difference between the accumulated two differences becomes zero,
The receiving circuit according to claim 2, wherein the phase shifter changes and converges the phase of the generated clock until the phase change direction indicated by the data phase changes.   The receiving circuit according to claim 2, wherein an actual operation mode for validating the equalized reception data is started after the phase of the clock converges.   The receiving circuit according to claim 4, wherein the data phase detection circuit and the phase shifter continue to operate even in the actual operation mode.   6. The receiving circuit according to claim 1, wherein data values of the two filter patterns are “011” and “110” or “001” and “100”. A linear equalizer that linearly equalizes the received data signal, and outputs the received data signal subjected to the linear equalization process to the decision feedback equalizer and the sample circuit;
A demultiplexer for converting the equalized reception data and error data, which are serial data output from the decision feedback equalizer, and parallel data output from the sample circuit into parallel data;
The LE coefficient for the linear equalization process and the decision feedback type equalization process are obtained from the equalized reception data, the error data, and the boundary data converted into parallel data output from the demultiplexer. An adaptive logic circuit for detecting a DFE coefficient of
The clock data recovery circuit detects the boundary phase from the equalized reception data and the boundary data which are parallel data output from the demultiplexer,
The reception according to any one of claims 1 to 6, wherein the data phase detection circuit detects the data phase from the equalized reception data and the error data which are parallel data output from the demultiplexer. circuit. An equalizer for equalizing the received data signal;
A demultiplexer that converts serial data output from the equalizer into parallel data;
A reception data processing circuit that processes the parallel data output from the demultiplexer as reception data,
The equalizer is
A decision feedback equalizer that performs decision feedback equalization on the received data signal captured in synchronization with the clock and outputs equalized reception data and error data; and
A sample circuit for capturing boundary data of the received data signal;
A clock data recovery circuit for detecting a boundary phase from the equalized reception data and the boundary data converted into parallel data by the demultiplexer;
From the equalized reception data converted to parallel data by the demultiplexer and the error data, 1 UI before the target bit with respect to two different filter patterns in which the signal polarity before and after the UI of the target bit is inverted A data phase detection circuit that detects an intersymbol interference amount after 1 UI of the target bit and detects a data phase from a difference between the intersymbol interference amount before 1 UI and the intersymbol interference amount after 1 UI When,
A phase shifter that generates the clock from the boundary phase and the data phase and outputs the clock to the decision feedback equalizer. The received data signal is captured in synchronization with the clock, and the received data signal that has been captured is subjected to a decision feedback equalization process to generate equalized reception data and error data,
Capture boundary data of the received data signal,
A boundary phase is detected from the equalized reception data and the boundary data,
From the equalized reception data and the error data, the inter-symbol interference amount before 1 UI of the target bit and the target bit of the target bit for two different filter patterns in which the signal polarity before 1 UI and after 1 UI of the target bit is inverted are obtained. Detecting the amount of intersymbol interference after 1 UI, detecting the data phase from the difference between the amount of intersymbol interference before 1 UI and the amount of intersymbol interference after 1 UI,
The receiving method, wherein the clock is generated from the boundary phase and the data phase.

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