JP2015115850A - Data reception device and data transmission/reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the jitters due to inter-symbol interference by performing adaptive equalizing to reception data before binarization.SOLUTION: A data reception device includes: an equalizer 11 for correcting the frequency components of data RXDATA; an eye opening detection part 12 for detecting the opening of an eye by an eye diagram about correction data EQDATA; and an equalizer control part 13 for controlling the correction characteristics of the equalizer 11 on the basis of the detection result of the opening of the eye. The eye opening detection part 12 includes: a binarization part for binarizing the correction data EQDATA on the basis of a plurality of threshold voltages; and an over-sampling part for over-sampling the binary data. The data reception device also includes: threshold voltage setting means 15 and 16 for setting the plurality of threshold voltages in the binarization part in accordance with the voltage amplitude of the correction data EQDATA, and for outputting the plurality of threshold voltages to the binarization part.

Description

  The present invention relates to a data reception device and a data transmission / reception system.

  In recent years, many high-speed serial interface standards have been put into practical use in order to satisfy large capacity and high-speed data transmission. As such serial communication, USB (Universal Serial Bus) 3.0, PCI (Peripheral Component Interconnect) Express, etc. are known, and high-speed serial communication with a data rate of about several hundred Mbps (bits per second) to several Gbps. Has become the mainstream.

  Further, as one of 3R functions (waveform shaping (reshaping), timing reproduction (retiming), identification reproduction (regenerating)) in digital signal reception, a clock data recovery (CDR) technique is known. In clock data recovery, in digital communication, a signal on a transmission path in which a clock is superimposed on transmission data is received by a receiving device (data receiving device) (embedded clock method), the clock is extracted from the transmission data, and the clock is extracted. This is a function for restoring received data using.

  In the clock data recovery technique, an oversampling CDR using a PLL (Phase Locked Loop) circuit is known in order to cope with an increasing data rate. The oversampling CDR generates a multi-phase clock whose phase is shifted from the reference clock at equal intervals, and samples the input data at each phase (binarizes into 0 and 1) using the multi-phase clock. Oversampling data is obtained. Then, the logic inversion timing is detected from the bit string of the oversampling data, and the clock and the data are reproduced based on the detection result. With this configuration, it is possible to configure a circuit other than the multi-phase clock generation unit with a digital circuit, so that the circuit can be realized relatively easily.

  By the way, in serial communication, there is a problem that data cannot be received correctly due to deterioration of signal quality due to transmission path loss such as cable or microstrip line.

  Here, a variation (jitter) in data transition time is known as one of the elements for measuring signal quality. Intersymbol interference (ISI) is an example of jitter generated due to a transmission path. Intersymbol interference is caused by interference between adjacent data bits, and is affected by the frequency characteristics of the transmission path. In the case of high-speed transmission, it is difficult to flatten the frequency characteristics of the transmission path to the high frequency band, and generally the low-pass characteristics. Therefore, it is important to reduce the jitter component due to the intersymbol interference.

  Therefore, an equalizer is used to reduce intersymbol interference. By using an equalizer to implement a filter with an inverse frequency characteristic (for example, a high-pass characteristic when the frequency characteristic of the transmission line is a low-pass characteristic), the frequency characteristic of data transmission within the data band is flattened. Can be.

  In recent years, adaptive equalization techniques that adaptively adjust equalization amounts have been developed to cope with diversification of data rates and diversification of data transmission paths. In particular, a decision feedback equivalent circuit (DFE) is often used as an adaptive equalizer in a receiving circuit of a serial transmission system.

  As a technique for reducing intersymbol interference using an equalizer, for example, Patent Document 1 discloses a binarization unit that binarizes a received signal and a signal binarized by the binarization unit. A digital signal processing means for performing digital signal processing, and a re-binarization means for re-binarizing the output of the digital signal processing means, wherein the digital signal processing means equalizes the received signal. Is disclosed. In this signal processing apparatus, received data is binarized by an equalizing processing apparatus using an oversampling CDR circuit, the binarized data is subjected to digital signal processing, and re-binarization is performed using the signal processing result. In this way, adaptive equalizing is realized.

  As described above, a loss compensation method for reducing jitter due to intersymbol interference on the receiving side has been proposed. However, the conventional loss compensation method has a problem that it is difficult to perform adaptive equalization on the reception data before binarization in the oversampling CDR.

  That is, in the technique of Patent Document 1, jitter due to intersymbol interference included in binary data can be reduced by equalization using digital signal processing, but jitter due to intersymbol interference before binarization. There is a problem that it cannot be reduced. For example, when a large intersymbol interference that causes data bits to disappear occurs, the technique of Patent Document 1 cannot cope with it, and the jitter reduction capability is lost. It was difficult to perform adaptive equalization on received data before conversion.

  Accordingly, an object of the present invention is to provide a data receiving apparatus that enables adaptive equalization for serially received data before binarization.

  In order to achieve such an object, a data receiving apparatus according to the present invention includes an equilibration unit that corrects a frequency component of received data, and an eye opening by an eye diagram for the data corrected by the equilibration unit. Eye opening detecting means for detecting the eye opening, and balancing control means for controlling correction characteristics of the balancing means based on the detection result of the eye opening by the eye opening detecting means. The means includes: a binarization unit that binarizes the data corrected by the balancing unit based on a plurality of threshold voltages; and an oversampling unit that oversamples the binarized binarized data. And setting the plurality of threshold voltages in the binarization unit according to the voltage amplitude of the data corrected by the balancing means, the plurality of threshold voltages Those with a threshold voltage setting means for outputting to the binarization unit.

  According to the present invention, it is possible to suppress jitter due to intersymbol interference by performing adaptive equalization on received data before binarization.

It is a functional block diagram (1) of a data transmission / reception system in which a data reception device and a data transmission device are connected via a transmission line. It is a functional block and circuit block diagram which show the detail of the eye opening detection part in a data receiver. It is a schematic diagram which shows the example of an eye pattern when a sampling reference voltage is set appropriately. It is a schematic diagram of an eye opening sampling space, and is an example of (A) eye opening / large (E = 0) and (B) eye opening / small (E = 6). It is a flowchart which shows an example of the equalizer characteristic optimization process using eye opening determination. It is a flowchart which shows the detail of the equalization amount adjustment process in an equalizer control part. It is a functional block diagram (2) of the data transmission / reception system formed by connecting a data reception device and a data transmission device via a transmission line. It is explanatory drawing of the amplitude detection method which detects a signal amplitude in order to set a sampling reference voltage.

  Hereinafter, the configuration according to the present invention will be described in detail based on the embodiment shown in FIGS.

[First Embodiment]
The data receiving apparatus (data receiving apparatus 10) according to the present embodiment uses the balancing means (equalizer 11) for correcting the frequency component of the received data (RXDATA) and the data (EQDATA) corrected by the balancing means. The eye opening detecting means (eye opening detecting section 12) for detecting the eye opening by the eye diagram and the correction characteristic of the balancing means are controlled based on the detection result of the eye opening by the eye opening detecting means. And an eye opening detecting means based on a plurality of threshold voltages (sampling reference voltages VREF_S, VREF_H, VREF_L) for the data corrected by the balancing means. Binarization unit for binarization (binarization unit 21), and oversampling of binarized binarized data And a plurality of threshold voltages in the binarization unit are set in accordance with the voltage amplitude of the data corrected by the balancing means, and the plurality of threshold voltages are binarized. Threshold voltage setting means (eye height detection unit 15 and threshold voltage adjustment unit 16) for output to the unit. In addition, the code | symbol in embodiment and the example of application are shown in a parenthesis.

(System configuration overview)
FIG. 1 is a functional block diagram showing an embodiment of a data transmission / reception system in which a data reception device and a data transmission device according to this embodiment are connected via a transmission line. A data transmission / reception system 100 illustrated in FIG. 1 is a data transmission / reception system in which data transmitted from a data transmission device 50 via a transmission path 60 is received by the data reception device 10.

  The data transmission device 50 outputs serial data and an arbitrary test pattern to the data reception device 10. The transmission path 60 includes various interface cables, a PCB (Printed Circuit Board) connector, and other connectors.

  The data receiving apparatus 10 includes an equalizer 11 as balancing means, an eye opening detection section 12 as eye opening detection means, an equalizer control section 13 as balancing control means, and an oversampling clock data recovery means. An oversampling clock data recovery circuit (OVS CDR) 14, an eye height detection unit 15 as an amplitude detection unit, and a threshold voltage adjustment unit 16 as a threshold voltage adjustment unit are provided. The eye height detection unit 15 and the threshold voltage adjustment unit 16 function as a threshold voltage setting unit.

  As will be described in detail below, the data reception device 10 uses the threshold voltage used by the eye opening detection unit 12 in accordance with the eye height detection result of the eye height detection unit 15 for the equalized serial reception data (equalization output signal) EQDATA. To improve the accuracy of the eye opening detection result. The eye height indicates the width in the voltage axis direction (vertical axis) of the eye opening of the eye pattern (FIG. 3, described later), and indicates that the larger the eye height, the better the loss characteristics.

  The equalizer 11 receives data RXDATA sent from the data transmission device 50 via the transmission line 60, generates data EQDATA in which the frequency component attenuated in the transmission line 60 is corrected, and outputs this data EQDATA. Further, the equalization amount is controlled by the equalizer characteristic control signal EQCNT input from the equalizer control unit 13, and the frequency characteristic changes.

  The eye opening detector 12 receives the data EQDATA from the equalizer 11 and detects the eye opening of the eye pattern for the data EQDATA. Here, the eye opening detection unit 12 functions as multi-value oversampling means, generates multi-value oversampling data OVS_S, OVS_H, and OVS_L and outputs them to the equalizer control unit 13.

  The eye height detection unit 15 detects the eye height of the eye pattern for the data EQDATA, and outputs an eye height control signal corresponding to the detected eye height to the threshold voltage adjustment unit 16.

  Based on the eye height control signal input from the eye height detection unit 15, the threshold voltage adjustment unit 16, as will be described later, is a sampling reference voltage (multi-level overvoltage) that is a threshold voltage set to satisfy a predetermined relationship with the eye height. Sampling reference voltages) VREF_S, VREF_H, and VREF_L are generated. The sampling reference voltages VREF_S, VREF_H, and VREF_L are input to the eye opening detection unit 12.

  The equalizer controller 13 receives multi-value oversampling data OVS_S, OVS_H, and OVS_L from the eye opening detector 12. Based on the multi-value oversampling data OVS_S, OVS_H, and OVS_L, the amount of change in the characteristic of the equalizer 11 is determined, and an equalizer characteristic control signal EQCNT is output to the equalizer 11.

  The OVS CDR 14 uses any one of the multi-value oversampling data OVS_S as input data, and restores the data CDRDATA and the clock CDRCLK.

(Eye opening detector)
FIG. 2 is a functional block and circuit configuration diagram showing details of the eye opening detection unit 12 in the data receiving apparatus 10 shown in FIG.

  The eye opening detection unit 12 includes a multi-phase clock generation circuit (MCKG) 20, a binarization circuit (Q_L, Q_H, Q_S) 21, an oversampling unit (F0 to F7) 22, And a parallelizing unit 23.

  The multiphase clock generator 20 receives the reference clock REFCK, and generates a multiphase sampling clock SCLK [7: 0] having the same phase interval using the reference clock REFCK. The reference clock REFCK is set to a frequency corresponding to the data rate.

  The multiphase clock generation unit 20 has a phase adjustment function, and can arbitrarily adjust the phase advance and delay in synchronization with the data EQDATA. Note that a multiphase clock used for the OVS CDR 14 may be used as the multiphase sampling clock SCLK.

  The three binarization units 21 receive three different sampling reference voltages VREF_S, VREF_H, and VREF_L that are variably set by the threshold voltage adjustment unit 16. Here, the sampling reference voltage VREF_S is an arbitrary reference voltage, the sampling reference voltage VREF_H is an arbitrary voltage higher than VREF_S, and the sampling reference voltage VREF_L is an arbitrary voltage lower than VREF_S. Setting of the sampling reference voltages VREF_S, VREF_H, and VREF_L will be described later.

  The binarization circuit 21 (Q_L, Q_H, Q_S) binarizes the equalized data EQDATA using the sampling reference voltages VREF_S, VREF_H, VREF_L as threshold values.

  The oversampling unit 22 includes eight flip-flop circuits F0 to F7. In the eight flip-flop circuits F0 to F7, the binarized data input from the binarization circuit 21 and the multiphase sampling clock SCLK [7: 0] input from the multiphase clock generation unit 20 Oversample (three values) the value data.

  The paralleling unit 23 outputs the ternary oversampling data oversampled by the oversampling unit 22 in synchronization with one of the multiphase sampling clocks SCLK [7: 0].

(Eye opening detection)
3 and 4 are explanatory diagrams for eye opening detection. FIG. 3 is a schematic diagram illustrating an example of an eye pattern when a sampling reference voltage is appropriately set, and FIG. 4 is a schematic diagram of an eye opening sampling space. 4A shows an example in which the eye opening is large (edge count E = 0), and FIG. 4B shows an example in which the eye opening is small (edge count E = 6).

  An eye pattern (eye diagram) is known as an index for evaluating the quality of digital signal transmission in serial communication. As shown in FIG. 3, the eye pattern 30 visually displays the variation in time transition by overwriting and displaying the signal waveform. The vertical axis represents voltage amplitude, and the horizontal axis represents time.

  In the eye pattern, when the vertical axis (voltage amplitude) varies, the lowermost and uppermost lines of the eye are displayed thick. Further, when the horizontal axis (time) varies, that is, when jitter exists, a line that transitions from top to bottom or from bottom to top is displayed thick.

  In addition, when there is little change and variation in signal transition with time, the portion where the signal occupying the unit time is large, and the opening portion (eye opening) 31 of the eye pattern 30 becomes large. On the other hand, when there is a large change and variation in the signal transition with time, the portion where the signal occupying the unit time is fixed becomes small, so the eye opening becomes small. As described above, there is a correlation between the signal quality and the eye opening, and the transmission quality can be evaluated using the eye pattern.

  The binarization circuit 21, the oversampling unit 22, and the paralleling unit 23 of the eye opening detection unit 12 use the multiphase sampling clock SCLK [7: 0] input from the multiphase clock generation unit 20 to sample the reference voltage. Sampling is performed for VREF_S, VREF_H, and VREF_L to determine whether or not the threshold value is exceeded.

  Here, 24 points in FIG. 3 to FIG. 4 indicate sampling points (h0 to h7, s0 to s7, 10 to 17). The equalizer control unit 13 detects the opening degree in the voltage direction and time direction of the eye opening of the equalized data EQDATA using the detected 24 sampling data, and generates the equalization control signal EQCNT based on the detection result. Output to the equalizer 11.

  The eye opening detection process by the eye opening detection unit 12 and the setting process of the equalization characteristic control signal EQCNT by the equalizer control unit 13 will be described below.

  First, in the detected 24 sampling data (h0 to h7, s0 to s7, 10 to 17), an exclusive OR (XOR) with data adjacent to the top, bottom, left and right is taken, and all of them are added as an edge. Let count e. When taking an exclusive OR (XOR), it is 1 when adjacent input data are different, and 0 when they are the same. Therefore, the edge count e indicates whether adjacent data match.

  Here, the data adjacent in the vertical direction is data sampled by a clock having the same phase as the multiphase sampling clock SCLK, that is, multi-value oversampling data at the same time constituting one symbol.

  The data adjacent in the left-right direction is data sampled by clocks of adjacent phases, that is, multi-value oversampling data that constitutes one symbol, is adjacent in the time direction, and is binarized with the same threshold value. It becomes.

For example, in the case shown in FIG. 4A, the edge count e (s1) of the data in the voltage direction (for example, s1) can be expressed by the following equation [1].
e (s1) = (s1 xor s0) + (s1 xor s2) + (s1 xor h1) + (s1 xor l1) (1)

The sum of the edge counts e of all data is the edge count E of one symbol. Therefore, the edge count E can be expressed by the following equation [2].
E = Σe = e (s0) + e (s1) + ... + e (s7) + e (h0) + e (h1) + ... + e (h7) + e (l0) + e (l1) + ... + e ( l7) ... [2]

  Here, when the opening height and opening width of the eye opening 31 of the eye pattern 30 are increased, the edge count E is decreased, and when the opening height and opening width of the eye opening 31 of the eye pattern 30 is decreased, the edge count E is increased. Tend. For example, the value of the edge count E in FIG. 4A is 0 (that is, the eye opening is large), and the value of the edge count E in FIG. 4B is 6 (that is, the eye opening is small).

  Then, by accumulating the edge count E over a plurality of symbols, instantaneous edge count fluctuations can be smoothed, and the height and opening width of the eye opening 31 of the average eye pattern 30 of the plurality of symbols can be detected. can do.

  At this time, a required value (eye opening threshold value) from the system is set in advance for the integrated value of the edge count E, and compared with the operated count value. If the measured value is larger than the preset required value, it is determined that the opening height and the opening width of the eye opening 31 of the eye pattern 30 of the equalized data EQDATA input to the eye opening detection unit 12 are small. Thus, the equalization characteristic control signal EQCNT output from the equalizer control unit 13 is set so as to increase the equalization amount by one step (increase the correction amount).

  Next, when the equalization amount is changed, the integrated value of the edge count E is compared with the required value again to determine whether the equalization amount is appropriate.

  At this time, if the integrated value of the measured edge count E is smaller than a preset required value, the opening height of the eye opening 31 of the eye pattern 30 of the equalized data EQDATA input to the eye opening detecting unit 12 Therefore, it is determined that the setting value of the equalizer is appropriate, and the equalization amount is determined.

  In the processing of the eye opening detection unit 12 described so far, setting of the sampling reference voltages VREF_S, VREF_H, and VREF_L input to the binarization circuit 21 is important. Hereinafter, detection of eye height in the eye height detection unit 15 and setting of the sampling reference voltage in the threshold voltage adjustment unit 16 will be described.

  For example, as shown in FIG. 3, the absolute value (| VREF_H−VREF_L |) of the difference between VREF_H (maximum value) and VREF_L (minimum value) of a plurality of sampling reference voltages is the minimum width (in the voltage direction of the eye opening 31). If it is set smaller than (eye height), the eye opening can be estimated in all three stages with respect to the amplitude for all data bits.

  However, when the absolute value (| VREF_H−VREF_L |) of the difference between VREF_H and VREF_L is larger than the minimum width of the eye opening 31 in the voltage direction, only VREF_S crosses the signal amplitude, and thus obtained by VREF_S. Only the sampling data is effective for eye opening determination. In this case, the equalizer control unit 13 cannot set the equalize amount appropriately.

  There is a problem that the data bits missed in this way may disappear before reaching the oversampling CDR 14 or disappear when binarized. Therefore, as shown in FIG. 3, the absolute value of the difference between VREF_H and VREF_L (| VREF_H−VREF_L |) is set smaller than the minimum width of the eye opening 31 in the voltage direction as the sampling reference voltage, and the eye opening determination result It is important not to eliminate the minimum bit after successive bits by adjusting the equalization amount using.

  If the eye pattern mask pattern (eye opening mask pattern) is determined, VREF_H and VREF_L may be set according to the mask pattern (mask test). This makes it possible to easily estimate the eye opening after equalization.

(Equalizer characteristic optimization flow)
FIG. 5 is a flowchart illustrating an example of equalizer characteristic optimization processing using eye opening determination performed by the data transmission / reception system 100. The equalizer characteristic optimization process will be described with reference to the flowchart of FIG.

  This equalizer characteristic optimization process is executed, for example, during training before starting data transmission / reception in the data transmission / reception system 100, and optimizes the equalizer characteristic of the data receiving apparatus 10 according to the processing flow shown in FIG.

  First, as a CDR lock test pattern, a 01 continuous pattern having the same data rate as the transmission data is transmitted from the data transmission device 50 over an arbitrary period to lock the OVS CDR 14 (S101: CDR lock test pattern transmission). As a result, the CDR clock CDRCLK is reproduced based on the equalized data EQDATA, and a multiphase sampling clock SCLK is generated.

  After locking the OVS CDR 14, the characteristic of the equalizer 11 is changed (S102: equalizer setting). Further, as described above, the characteristic of the equalizer 11 is also changed when the eye opening determination does not satisfy the predetermined standard (S107: NO).

  Next, an arbitrary test pattern or random pattern is transmitted from the data transmission device 50 as an equalizer setting test pattern (S103: Equalizer setting test pattern output).

  In general, data deteriorated due to transmission path characteristics has a property that when the minimum bit follows a continuous data bit, the minimum bit tends to disappear. For example, when the data rate is 4 Gbps (bits per second), 1 bit is 250 psec (picoseconds). However, when the data is arranged in the order of 5 bits, 1 bit, and 1 bit, 5 bits One bit immediately after that may cause the data bit to disappear due to a transition to the next data bit before the amplitude is fully increased or decreased. Therefore, in order not to miss such easily-erased data bits, it is necessary to optimize the equalizer 11 with a pattern (equalizer setting test pattern) different from the CDR lock test pattern.

  Next, it is determined whether or not the OVS CDR 14 is locked (S104: CDR LOCK determination). In this determination, the OVS CDR 14 is locked in S101. If the equalizer 11 is greatly deviated from an appropriate setting, the OVS type is changed when the CDR locking test pattern in S101 is changed to the equalizer setting test pattern in S103. This is performed because the CDR 14 may be unlocked. This is because if the OVS CDR 14 is unlocked, the multiphase sampling clock SCLK used in S105 is not generated.

  If the OVS CDR 14 is unlocked (S104: NO), the process returns to S101, the equalizer setting is changed again (S102), and the lock determination is performed again (S104).

  When the OVS CDR 14 is locked (S104: YES), the eye height detector 15 sets the amplitude (voltage amplitude) of the equalize output signal EQDATA in order to appropriately set the multi-level sampling reference voltages VREF_S, VREF_H, and VREF_L. ) Is detected (S105).

  Next, based on the minimum voltage direction width (eye height) of the eye opening detected by the eye height detection unit 15, the threshold voltage adjustment unit 16 appropriately sets the sampling reference voltages VREF_S, VREF_H, and VREF_L as described above. (S106: Multi-level sampling reference voltage setting).

  Thereafter, the eye opening detection unit 12 estimates the eye opening by oversampling with multiple values and compares it with an eye opening threshold or a mask pattern (S107: eye opening determination). As a result of the comparison, when the height and width of the eye opening satisfy the predetermined conditions (S107: YES), the control signal EQCNT for changing the equalizer characteristic is output from the equalizer control unit 13 to the equalizer 11, and the process is performed. finish. On the other hand, if the height and width of the eye opening do not satisfy the predetermined conditions (S107: NO), the process returns to S102 and the process is repeated.

(Equalization amount adjustment flow)
FIG. 6 is a flowchart showing details of equalization amount adjustment processing in the equalizer control unit 13. The flowchart shown in FIG. 6 is a flowchart relating to processing for determining the equalization characteristic control signal EQCNT of the equalizer 11 in the equalizer control unit 13.

  First, the equalizer control unit 13 initializes (E = 0) a count value (hereinafter, edge count) E of an edge counter included in the equalizer control unit 13 (S201).

Next, the edge count E is calculated using the multi-value oversampling data OVS_S, OVS_H, and OVS_L as described above (S202). Here, the edge count E is calculated continuously for N symbols of the received signal, and the edge count results are integrated. Therefore, the edge count E is obtained by the following equation (3).
E = E0 + E1 +... + EN-1 (3)

  It is determined whether or not the integrated value of the edge count E obtained by the above equation (3) exceeds an edge count threshold value (Val) (which is the above eye opening threshold value) set in the equalizer control unit 13 in advance ( S203).

  When E> Val (S203: YES), the equalizer control unit 13 increases the equalization amount of the equalizer 11 by one level (S204: equalization amount increment). Then, the control signal EQCNT for changing the equalizer characteristics is output from the equalizer control unit 13 to the equalizer 11, and the process returns to S201. On the other hand, if E ≦ Val (S203: NO), the equalization amount is not adjusted, and the process ends.

  In the data receiving apparatus 10 according to the present embodiment described above, the eye opening of the eye pattern of the equalized data EQDATA input to the eye opening detecting unit 12 at the end of the above processing is set in advance by the system. The equalization characteristic control signal EQCNT for performing equalization to be larger than that is output to the equalizer 11.

  Therefore, in a data receiving apparatus including an oversampling CDR circuit, adaptive equalization for serially received data before binarization is possible.

  Further, by averaging the edge count E of the multi-value sampling data of one symbol over a plurality of symbols, the influence of instantaneous edge count fluctuation can be removed, and the detection accuracy of the eye opening can be improved. .

  In other words, the data receiving apparatus 10 performs oversampling by changing the threshold voltage of the binarization circuit, and estimates margins in the voltage direction and time direction of the input signal before binarization from the multilevel oversampling data. The equalization processing is performed on the input signal before binarization in the oversampling CDR so that the margin is maximized. Further, by switching the threshold voltage of the binarization circuit according to the signal amplitude of the input signal before binarization, the margins in the voltage direction and time direction of the input signal before binarization are estimated with high accuracy.

[Second Embodiment]
Hereinafter, other embodiments of the data reception device and the data transmission / reception system according to the present invention will be described. In addition, the description about the same point as the said embodiment is abbreviate | omitted suitably.

  FIG. 7 is a functional block diagram of a data transmission / reception system in which a data reception device and a data transmission device according to the second embodiment are connected via a transmission path. A data transmission / reception system 100 illustrated in FIG. 7 is a data transmission / reception system in which data transmitted from the data transmission device 50 via the transmission path 60 is received by the data reception device 40.

  The data receiving apparatus 40 of the second embodiment includes an equalizer 11, an eye opening detection unit 12, an equalizer control unit 13, an oversampling clock data recovery circuit (OVS type CDR) 14, and an eye height detection unit 15. And an amplitude adjusting unit 17. The data receiving apparatus 40 includes an amplitude adjusting unit 17 as an amplitude adjusting unit instead of the threshold voltage adjusting unit 16 described above. The amplitude adjustment unit 17 amplifies the amplitude itself of the equalizer output signal EQDATA, and includes, for example, an amplifier (amplifier circuit).

  In this embodiment, the eye opening detection unit 12 does not use the sampling reference voltages VREF_S, VREF_H, and VREF_L, but modulates the amplitude of the equalizer output signal EQDATA in the amplitude adjustment unit 17 to detect the eye opening. The unit 12 enables multi-value oversampling across a preset threshold voltage. Other points are the same as the method described in the first embodiment.

[Third Embodiment]
The processing of the threshold voltage setting means (eye height detection unit 15 and threshold voltage adjustment unit 16) may be performed by the eye opening detection unit 12. ^

  FIG. 8 is an explanatory diagram of an amplitude detection method for detecting a signal amplitude in order to set the sampling reference voltages VREF_S, VREF_H, and VREF_L.

  In the example of FIG. 8, the equalizer output signal EQDATA (symbol 32 in the figure) is subjected to multilevel sampling with the sampling reference voltage ternary value (VREF_S, VREF_H, VREF_L), so that VREF_S = Vdd × 3/6 and VREF_H is set to Consider an example of selecting either Vdd × 4/5 or Vdd × 5/6 and selecting VREF_L as either Vdd × 1/5 or Vdd × 2/6.

  Further, FIG. 8 illustrates 4 UI (Unit Interval). Although it is arranged 1010 from the left, the second data bit from the left is shown as a data bit that is likely to disappear due to intersymbol interference.

  Here, if the equalizer output signal EQDATA is controlled so as to increase the equalization amount, it can be expected that Vdd × 4/6 is corrected in the 0V direction at the timing of SCLK4. Therefore, since it can be confirmed that there is a signal transition in the eye opening determination range at the multi-value oversampling reference voltage, an appropriate equalization amount can be set.

  Here, more voltages than the number of multi-value oversampling reference voltages to be used are prepared. The means for generating the sampling reference voltage is not particularly limited. For example, a plurality of resistors may be connected in series between the GND and the power supply voltage to divide the voltage. Further, the voltage may be adjusted by giving a DC offset to any of a plurality of voltages.

  In the example of FIG. 8, eye height is estimated using one SCLK4 of multiphase sampling clocks located near the middle of 1UI. Here, it is important to detect the amplitude near the center of 1 UI, and all or a part of the sampling clock SCLK [7: 0] may be used. The multiphase sampling clock SCLK is adjusted in phase relationship with the equalized data EQDATA in the multiphase clock generation unit 20.

  There are three types of sampling reference voltages, VREF_S, VREF_H, and VREF_L. In order not to increase the circuit scale more than necessary, sampling is performed in two steps with each reference voltage. For example, the first time VREF_L = Vdd × 1/6, VREF_S = Vdd × 2/6, VREF_H = Vdd × 3/6, and the second time VREF_L = Vdd × 3/6, VREF_S = Vdd × 4/6, Assume that VREF_H = Vdd × 5/6.

  In FIGS. 8A and 8B, the cases where the signal amplitude is higher than each reference voltage when determining whether the reference voltage is high or low using the five reference voltages Vdd / 1 × 5 to Vdd × 5/6 as threshold values. ●, low case is represented as ○. ● Since there is a signal between ● and ○, the number of inversions between ● and ○ that occur between each reference voltage can be integrated and stored for an arbitrary time by taking the exclusive OR (XOR) as described above. It is stored in a register as a unit.

  Here, as shown in FIG. 3, all the data are obtained by selecting the reference voltage that has the inversion of ● / ◯ and is closer to the amplitude center Vdd × 3/6 as the sampling reference voltages VREF_L and VREF_H. Bits can be sampled in three values.

  Further, when the sampling reference voltage is determined for 4 UI shown in FIG. 8, the sampling reference voltages VREF_L and VREF_H must be set on the VDD / GND side, so VREF_L = Vdd × 2/6, VREF_S = Vdd × 3 / 6, VREF_H = Vdd × * 4/6. Thus, the eye opening can be accurately estimated by appropriately setting VREF_L and VREF_H.

  By performing the amplitude detection of the equalizer output signal EQDATA by the eye opening detection unit 12 as in the present embodiment, the circuit area and the power consumption can be suppressed as compared with the case where the threshold voltage setting unit is separately provided. Is possible.

  The above-described embodiment is a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10,40 Data receiver 11 Equalizer 12 Eye opening detection part 13 Equalizer control part 14 OVS type CDR (oversampling type clock data recovery circuit)
15 Eye height detector 16 Threshold voltage adjuster 17 Amplitude adjuster 20 Multiphase clock generator (MCKG)
21 Binarization unit 22 Oversampling unit 23 Parallelization unit 30 Eye pattern 31 Eye opening 50 Data transmission device 60 Transmission path 100 Data transmission / reception system

Japanese Patent No. 4413664

Claims (9)

Balancing means for correcting the frequency component of the received data;
Eye opening detecting means for detecting an eye opening by an eye diagram for the data corrected by the balancing means;
An equilibration control means for controlling correction characteristics of the equilibration means based on the detection result of the eye opening by the eye opening detection means,
The eye opening detecting unit binarizes the data corrected by the balancing unit based on a plurality of threshold voltages, and oversamples the binarized binarized data. A sampling unit, and
Threshold voltage setting means for setting the plurality of threshold voltages in the binarization unit according to the voltage amplitude of the data corrected by the balancing means, and outputting the plurality of threshold voltages to the binarization unit; A data receiving apparatus comprising: The threshold voltage setting means includes
Amplitude detecting means for detecting the voltage amplitude of the data corrected by the balancing means;
The threshold voltage adjusting means for setting the plurality of threshold voltages used in the eye opening detecting means based on the voltage amplitude detected by the amplitude detecting means. Data receiving device. The amplitude detection means detects the eye height of the eye pattern of the data corrected by the balancing means,
3. The threshold voltage adjustment unit sets the plurality of threshold voltages so that the maximum value and the minimum value of the plurality of threshold voltages are within the eye height detected by the amplitude detection unit. Data receiver.   The balancing control unit compares the detection result of the eye opening by the eye opening detection unit with an eye opening threshold value or an eye opening mask pattern, and when the detection result does not satisfy a predetermined condition, 4. The data receiving apparatus according to claim 1, wherein control for increasing the correction amount of the balancing means is performed. The eye opening detection means includes a multiphase clock generation unit that generates a multiphase sampling clock having the same phase interval based on a reference clock,
5. The data receiving apparatus according to claim 1, wherein the oversampling unit oversamples the binarized data based on the multiphase sampling clock. 6.   The eye opening detection unit includes a parallel unit that outputs the oversampling data oversampled by the oversampling unit to the balancing control unit in synchronization with one of the multiphase sampling clocks. The data receiving device according to claim 5. Balancing means for correcting the frequency component of the received data;
Amplitude adjusting means for amplifying the voltage amplitude of the data corrected by the balancing means;
Amplitude detecting means for detecting voltage amplitude of output data from the amplitude adjusting means;
For the output data from the amplitude adjusting means, eye opening detecting means for detecting an eye opening by an eye diagram;
An equilibration control means for controlling correction characteristics of the equilibration means based on the detection result of the eye opening by the eye opening detection means,
The eye opening detection unit includes a binarization unit that binarizes the output data from the amplitude adjustment unit, and an oversampling unit that oversamples the binarized binarization data,
The amplitude adjusting unit amplifies the voltage amplitude based on the detection result of the voltage amplitude by the amplitude detecting unit.   8. The apparatus according to claim 1, further comprising oversampling type clock data recovery means for receiving a part of output data from the eye opening detection unit and restoring data and a clock. Data receiver. A data receiving device according to any one of claims 1 to 8,
A data transmission / reception system comprising: a data transmission device that transmits data to the data reception device via a transmission path.