JP6210742B2 - Data processing device and data transfer control device - Google Patents

Description

  The present invention relates to a data processing device and a data transfer control device.

  In many system LSIs such as a system LSI mounted on an image processing apparatus such as a still image camera, a moving image camera, a medical endoscope camera, or an industrial endoscope camera, a single connected DRAM (Dynamic) Random Access Memory) is shared by a plurality of built-in processing blocks. In such a system LSI, a plurality of built-in processing blocks are connected to a data bus inside the system LSI, and each processing block accesses the DRAM by DMA (Direct Memory Access). At this time, the bus arbiter controls access to the DRAM while appropriately arbitrating an access request (DMA request) to the DRAM issued from each processing block.

  In general DRAM access, a method called bank interleaving is used to secure the bus bandwidth of the entire data bus. Here, the bus bandwidth represents the amount of data on the data bus when each processing block accesses the DRAM. In bank interleaving, data transfer is controlled for each bank of the DRAM. When sequentially accessing different banks of the DRAM by bank interleaving, the address setting processing for the next bank to be accessed can be performed in parallel during the data transfer processing from the previously accessed bank. The efficiency of data access can be improved.

  However, the DRAM has a period during which access cannot be accepted when the same bank is continuously accessed. For this reason, if the same bank of the DRAM is continuously accessed by bank interleaving, a loss time due to a period in which the DRAM cannot accept access occurs, and the data access efficiency of the DRAM decreases. Therefore, in order to ensure high data access efficiency by performing the data transfer process and the address setting process in parallel, it is necessary to sequentially access different banks by bank interleaving.

  In arbitration of DRAM access requests in a general bus arbiter, for example, a processing block in which processing fails if access to the DRAM is inhibited for a certain period based on the priority of each processing block. A method of preferentially receiving an access request from a processing block with a high priority is known. Also, based on the information of the bank to be accessed, for example, by reducing the priority of continuous access to the same bank, and selecting the processing block that accepts the access request, the bus bandwidth of the entire data bus There are also known methods for securing the above.

  However, as the system becomes more complex, the number of processing blocks built into the system LSI increases. This complicates the setting of the priority for each processing block, and it becomes difficult to appropriately arbitrate access requests to the DRAM from each processing block using only the bus arbiter.

  In order to solve such problems, conventionally, while securing the bus bandwidth required by each processing block, the bus bandwidth of the entire data bus is improved by bank interleaving, that is, the DRAM data access efficiency is improved. A technique for ensuring performance as a system is disclosed.

  The technology disclosed in Patent Document 1 controls the timing when each processing block issues an access request to the DRAM (request generation timing) and the method of generating the address of the DRAM accessed by each processing block. This is a technique for controlling a processing block having a high priority so as to continuously access different banks of the DRAM. With the technique disclosed in Patent Document 1, it is possible to secure the bus bandwidth of the entire data bus, that is, to efficiently perform data transfer, while securing the priority of each processing block.

  In addition, the techniques disclosed in Patent Document 2 and Patent Document 3 are techniques for avoiding continuous access to the same bank of DRAM by changing the order of accessing each bank of the DRAM in the bus arbiter. . With the techniques disclosed in Patent Document 2 and Patent Document 3, it is possible to minimize the occurrence of loss time during which the DRAM cannot accept access.

JP 2011-3160 JP 2006-260472 A JP 2010-27006 A

  However, even when the technology disclosed in Patent Document 1 is adopted and processing blocks with high priority are controlled so as to continuously access different banks of DRAM, there are a plurality of processing blocks with high priority, In addition, if the order of accessing the DRAM banks is different for each processing block with a high priority, continuous access to the same bank of the DRAM may occur.

  For example, if there are two processing blocks with high priority, one processing block accesses in the order of bank A → bank B → bank C → bank D, and the other processing block accesses bank D → bank C → bank B. When accessing in the order of bank A, successive accesses to the same bank occur at the timing when the processing block accessing the DRAM is switched.

  In order to change the order of accessing the DRAM banks in the bus arbiter using the techniques disclosed in Patent Document 2 and Patent Document 3, the data transferred in the replaced order is returned to the original order. Therefore, a buffer for outputting to the processing block that requested access to the DRAM (requesting processing block) must be mounted in the bus arbiter. For this reason, there is a problem that the circuit scale of the bus arbiter increases. In particular, when a plurality of buffers corresponding to each processing block are provided in the bus arbiter, the circuit scale is further increased.

  As a countermeasure to the problem that the circuit scale of the bus arbiter increases, a configuration in which a buffer provided in the bus arbiter is shared by a plurality of processing blocks can be considered. In this case, the priority for each processing block is set. There arises a new problem that the effect of changing the access order to the DRAM bank within the bus arbiter cannot be obtained sufficiently, such as difficulty in finely managing.

  In order to sufficiently obtain the effect of changing the order of access to the DRAM bank, when various other functions are realized by the bus arbiter, the exchange (interface) between the processing block and the bus arbiter is complicated. turn into. Furthermore, each processing block requires a configuration for supporting various other functions implemented by the bus arbiter, and the complexity of the configuration of each processing block increases the cost of the entire system.

  The present invention has been made based on the above problem recognition, and a data processing apparatus and data transfer control capable of improving the efficiency of data access even when the order of banks accessed by each processing block is different The object is to provide a device.

In order to solve the above problems, a data processing device according to the present invention includes a plurality of processing blocks connected to a common bus, a memory including an address space having a plurality of banks, and the plurality of processing blocks output from the processing block. A common bus arbitration unit that arbitrates an access request to a memory and controls data transfer through the common bus between the processing block that has received the access request and the memory, and a plurality of Among the processing blocks, at least one processing block exchanges the order of accessing the banks in the memory when transferring the data to and from the memory via the common bus, and the processing block for performing interchanging the order of accessing the bank in the memory, on the basis of the order of the data a predetermined menu By controlling the order of the data to be passed to and from the re comprises data transfer control device that performs switching of order of accessing the bank, characterized in that.

  The data transfer control device according to the present invention includes a buffer unit that stores the data that is transferred to and from the memory, a buffer write control unit that stores the data in the buffer unit, and a buffer unit that stores the data. And a buffer read control unit for reading out the read data.

  In addition, the data transfer control device of the present invention includes an operation mode register that sets the order of the data that is transferred to and from the memory, and the buffer write control unit is set in the operation mode register The data is stored in a storage area corresponding to the bank in the buffer unit based on the order of the data.

  Further, the data transfer control device of the present invention comprises an operation mode register for setting the order of the data to be transferred to and from the memory, and the buffer read control unit is set in the operation mode register The data is read from a storage area corresponding to the bank in the buffer unit based on the order of the data.

  The data transfer control device according to the present invention is characterized in that the order of accessing the banks is reversed from the order of the banks in the memory.

  Further, the data in the data processing apparatus of the present invention is data composed of areas in the first direction and the second direction, and the data processing apparatus changes the order of accessing the banks in the memory. A plurality of the processing blocks are provided, and at least one processing block among the plurality of the processing blocks that perform switching of the order of accessing the banks in the memory is the bank in the memory in the first direction of the data. And at least one other processing block is transferred to the bank in the memory in the second direction of the data. It is characterized by access.

  The data in the data processing apparatus of the present invention is image data, the first direction is a horizontal direction of the image data, and the second direction is a vertical direction of the image data. It is characterized by that.

The data transfer control device according to the present invention includes a plurality of processing blocks connected to a common bus, a memory composed of an address space having a plurality of banks, and an access request to the memory output from the plurality of processing blocks. And a common bus arbitration unit that controls data transfer via the common bus between the processing block that has received the access request and the memory. Among the processing blocks, the processing block is provided in at least one processing block, and the processing block controls the order of the data to be transferred to and from the memory based on the predetermined order of the data. When transferring the data to and from the memory via the memory, the order of accessing the banks in the memory Performing replacement of, characterized in that.

  According to the present invention, it is possible to increase the efficiency of data access even when the order of banks accessed by the respective processing blocks is different.

1 is a block diagram illustrating a schematic configuration of an image processing apparatus to which a data transfer control device according to an embodiment of the present invention is applied. It is the figure which showed an example of the inversion process of the image in the image processing apparatus of this embodiment. It is the figure which showed typically an example of the access method to DRAM in the inversion process of the image in the image processing apparatus of this embodiment. It is the figure which showed typically an example of the loss time resulting from the bank access of DRAM in the processing block with which the image processing apparatus of this embodiment was equipped. It is the figure which showed typically an example which avoids the loss time resulting from the bank access of DRAM by the 1st replacement process by the processing block with which the image processing apparatus of this embodiment was equipped. It is a block diagram showing a schematic configuration of a data transfer control device provided in the image processing apparatus of the present embodiment. It is a figure explaining an example of the DMA operation | movement in the 1st replacement process of the data transfer control apparatus with which the image processing apparatus of this embodiment was equipped. It is the figure which showed typically an example of the transfer timing of the image data in DMA operation | movement of the 1st replacement process by the data transfer control apparatus with which the image processing apparatus of this embodiment was equipped. It is a figure explaining another example of the DMA operation | movement in the 1st replacement process of the data transfer control apparatus with which the image processing apparatus of this embodiment was equipped. It is the figure which showed typically an example of the transfer timing of the image data in another example of DMA operation | movement of the 1st replacement process by the data transfer control apparatus with which the image processing apparatus of this embodiment was equipped. It is a figure explaining DMA operation | movement in the data transfer control apparatus with which the image processing apparatus of this embodiment was equipped. It is the figure which showed typically an example of the transfer direction of image data and DRAM access in the image processing apparatus of this embodiment. FIG. 3 is a diagram schematically illustrating an example of DRAM access corresponding to a case where the transfer direction of image data is different in the image processing apparatus of the present embodiment. It is the figure which showed typically an example of the loss time resulting from the bank access of DRAM in the processing block with which the image processing apparatus of this embodiment was equipped. It is the figure which showed typically an example which avoids the loss time resulting from the bank access of DRAM by the 2nd replacement process by the processing block with which the image processing apparatus of this embodiment was equipped.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, for example, an example in which an image processing apparatus such as a still image camera is used as the data processing apparatus of the present invention, and the data transfer control apparatus of the present invention is applied to the data processing apparatus will be described. FIG. 1 is a block diagram illustrating a schematic configuration of an image processing apparatus to which the data transfer control apparatus according to the present embodiment is applied. In FIG. 1, the image processing apparatus 1 includes an image sensor 10, a preprocessing unit 20 including an image transfer unit 21 and an evaluation value generation unit 22, an image processing unit 30, a display processing unit 40, and a display device 41. A card interface unit 50, a recording medium 51, a CPU 60, a bus arbiter 70, a DRAM interface unit 71, and a DRAM 72.

  As shown in FIG. 1, the image transfer unit 21, the evaluation value generation unit 22, the image processing unit 30, the display processing unit 40, the card interface unit 50, and the CPU 60 in the image processing apparatus 1 are each of the present embodiment. The data transfer control device 100, the data transfer control device 200, or the data transfer control device 300 is connected to a data bus 80 that is a common bus. Each processing block connected to the data bus 80 outputs a DRAM access request such as a DMA request to the bus arbiter 70 via the data bus 80, and is controlled by the DRAM interface unit 71 connected to the bus arbiter 70. The data is read from the DRAM 72 and the data is written to the DRAM 72. The data bus 80 receives signals such as a DMA request signal, a DMA acceptance signal, a read / write control signal (RW control signal), an address, and data for each processing block to perform DMA with the DRAM 72. include.

  The image sensor 10 is a CCD (Charge Coupled Device) image sensor that photoelectrically converts an optical image of a subject formed by a lens (not shown), or a CMOS (Complementary Metal-Oxide Semiconductor: complementary metal oxide semiconductor). An image sensor represented by an image sensor. The image sensor 10 outputs an image signal corresponding to subject light (hereinafter referred to as “input image data”) to the preprocessing unit 20.

  The preprocessing unit 20 is a processing block that performs preprocessing such as flaw correction and shading correction on the input image data input from the image sensor 10. The image transfer unit 21 included in the preprocessing unit 20 transfers (writes) image data (hereinafter referred to as “preprocessed image data”) as a result of the preprocessing to the DRAM 72. Further, the evaluation value generation unit 22 included in the preprocessing unit 20 is based on the preprocessed preprocessed image data, and includes automatic exposure (Auto Exposure: AE), automatic focus (Auto Focus: AF), and auto white balance (Auto). An evaluation value for performing control such as White Balance (AWB) is generated, and the generated evaluation value is transferred (written) to the DRAM 72.

  The image transfer unit 21 and the evaluation value generation unit 22 output a DMA request signal to the DRAM 72 to the bus arbiter 70 when transferring the preprocessed image data or the evaluation value to the DRAM 72. Then, after the DMA request is received by the bus arbiter 70 and the DMA acceptance signal is input, the image transfer unit 21 and the evaluation value generation unit 22 send the preprocessed image data or the evaluation value via the bus arbiter 70 and the DRAM interface unit 71. Output to the DRAM 72.

  The image processing unit 30 acquires (reads out) preprocessed image data stored in the DRAM 72, performs various image processing such as noise removal, YC conversion processing, resizing processing, and JPEG compression processing to display an image for display. It is a processing block for generating data and image data for recording. The image processing unit 30 is also a processing block that transfers (writes) the generated display image data and recording image data to the DRAM 72 again.

  The image processing unit 30 outputs a DMA request signal for the DRAM 72 to the bus arbiter 70 when acquiring preprocessed image data from the DRAM 72. Then, after the DMA request is accepted by the bus arbiter 70 and the DMA acceptance signal is input, the image processing unit 30 reads the preprocessed image data from the DRAM 72 via the DRAM interface unit 71 and the bus arbiter 70.

  Further, the image processing unit 30 outputs a DMA request signal to the DRAM 72 to the bus arbiter 70 when transferring the display image data and the recording image data to the DRAM 72. Then, after the DMA request is received by the bus arbiter 70 and the DMA acceptance signal is input, the image processing unit 30 transmits the generated display image data and recording image data via the bus arbiter 70 and the DRAM interface unit 71. Output to the DRAM 72.

  The display processing unit 40 acquires (reads) display image data stored in the DRAM 72, and displays such as processing for superimposing OSD (On-Screen Display) display data on the acquired display image data. It is a processing block that performs processing and outputs it to the display device 41.

  When the display processing unit 40 acquires display image data from the DRAM 72, the display processing unit 40 outputs a DMA request signal to the DRAM 72 to the bus arbiter 70. Then, after the DMA request is received by the bus arbiter 70 and the DMA acceptance signal is input, the display processing unit 40 reads display image data from the DRAM 72 via the DRAM interface unit 71 and the bus arbiter 70. Then, after the display process is performed on the read display image data, the image data after the display process is output to the display device 41.

  The display device 41 is a display device such as a TFT (Thin Film Transistor) liquid crystal display (LCD) or an organic EL (Electro Luminescence) display, and after display processing output from the display processing unit 40. An image corresponding to the image data is displayed.

  The card interface unit 50 is a processing block that acquires (reads out) image data for recording stored in the DRAM 72 and records it on the recording medium 51. The card interface unit 50 is also a processing block that reads image data recorded on the recording medium 51 and transfers (writes) the read image data to the DRAM 72.

  The card interface unit 50 outputs a DMA request signal to the DRAM 72 to the bus arbiter 70 when acquiring image data for recording from the DRAM 72. Then, after the DMA request is accepted by the bus arbiter 70 and the DMA acceptance signal is input, the card interface unit 50 reads the image data for recording from the DRAM 72 via the DRAM interface unit 71 and the bus arbiter 70. Then, the read image data for recording is output to the recording medium 51 and recorded.

  The card interface unit 50 outputs a DMA request signal to the DRAM 72 to the bus arbiter 70 when transferring the image data read from the recording medium 51 to the DRAM 72. Then, after the DMA request is received by the bus arbiter 70 and the DMA acceptance signal is input, the card interface unit 50 outputs the image data read from the recording medium 51 to the DRAM 72 via the bus arbiter 70 and the DRAM interface unit 71. .

  The recording medium 51 is a recording medium such as a memory card, and records the recording image data output from the card interface unit 50. The image data recorded by the card interface unit 50 is read out. In FIG. 1, the recording medium 51 is also a component of the image processing apparatus 1, but the recording medium 51 is detachable from the image processing apparatus 1.

  The CPU 60 is a processing block that controls the components of the image processing apparatus 1, that is, the entire image processing apparatus 1. The DRAM 72 is also accessed when the CPU 60 controls each component of the image processing apparatus 1. However, the data that the CPU 60 acquires (reads) from the DRAM 72 and the data that is transferred (written) to the DRAM 72 set not only the image data in the processing block described above but also the operation of each component of the image processing apparatus 1. The parameter data is also included.

  When the CPU 60 acquires data from the DRAM 72 by DMA, it outputs a DMA request signal to the DRAM 72 to the bus arbiter 70. Then, after the DMA request is accepted by the bus arbiter 70 and the DMA acceptance signal is input, the CPU 60 reads the acquired data from the DRAM 72 via the DRAM interface unit 71 and the bus arbiter 70.

  Further, when the CPU 60 transfers data to the DRAM 72 by DMA, it outputs a DMA request signal to the DRAM 72 to the bus arbiter 70. Then, after the DMA request is accepted by the bus arbiter 70 and the DMA acceptance signal is input, the CPU 60 outputs the data to be transferred to the DRAM 72 via the bus arbiter 70 and the DRAM interface unit 71.

  The bus arbiter (common bus arbitration unit) 70 transfers (writes) data to the DRAM 72 and receives data from the DRAM 72 in response to DMA requests from a plurality of processing blocks in the image processing apparatus 1 connected to the data bus 80. Arbitrates data acquisition (reading).

  More specifically, the bus arbiter 70 arbitrates access to the DRAM 72 by each processing block based on bank interleaving and the priority of each processing block in accordance with the DMA request signal input from each processing block. The processing block that accepts the DMA request is determined. Then, a DMA acceptance signal is output to the determined processing block.

  Thereafter, when the determined processing block transfers data to the DRAM 72, the bus arbiter 70 receives the RW control signal indicating that data is written to the DRAM 72, the address of the DRAM 72 input from the processing block, and the data to be transferred to the DRAM 72. The data is output to the interface unit 71. Further, when the determined processing block acquires data from the DRAM 72, the bus arbiter 70 outputs to the DRAM interface unit 71 an RW control signal indicating that data is read from the DRAM 72 and the address of the DRAM 72 input from the processing block. To do. Thereafter, the data input from the DRAM interface unit 71, that is, the data acquired from the DRAM 72 is output to the determined processing block.

  The DRAM interface unit 71 controls writing of data to or reading of data from the DRAM 72 based on an RW control signal representing writing or reading of the DRAM 72 input from the bus arbiter 70 and an address of the DRAM 72. That is, data writing to the DRAM 72 or data reading from the DRAM 72 is executed in accordance with the DRAM access from the processing block determined by the bus arbiter 70.

  More specifically, the DRAM interface unit 71 outputs the data input from the bus arbiter 70 to the DRAM 72 when the RW control signal input from the bus arbiter 70 represents writing to the DRAM 72. When the RW control signal input from the bus arbiter 70 indicates reading of the DRAM 72, the data output from the DRAM 72 is output to the bus arbiter 70.

  The DRAM 72 is a memory that is access-controlled by the DRAM interface unit 71 and stores various data in the process of each processing block in the image processing apparatus 1.

  As described above, each processing block in the image processing apparatus 1 issues a DMA request to the bus arbiter 70 when each processing block accesses the DRAM 72. Then, after the DMA request is received by the bus arbiter 70, data is written to the DRAM 72 or data is read from the DRAM 72 via the data bus 80, the bus arbiter 70, and the DRAM interface unit 71.

<First replacement process>
Here, in order to describe a method of accessing the DRAM 72 in each processing block in the image processing apparatus 1, an example of the operation of the image processing apparatus 1 will be described with reference to FIGS. The image processing apparatus 1 may perform a process of inverting the current image (hereinafter referred to as “inversion process”) depending on functions of the image processing apparatus 1 and restrictions on designing and manufacturing the image processing apparatus 1. FIG. 2 is a diagram illustrating an example of an image inversion process in the image processing apparatus 1 of the present embodiment. FIG. 3 is a diagram schematically showing an example of an access method to the DRAM 72 in the image inversion processing in the image processing apparatus 1 of the present embodiment.

  For example, in some cases, the image sensor 10 may need to be disposed in a state where the image sensor 10 is rotated by 180 ° due to restrictions on the layout of the substrate on which the image sensor 10 is disposed. In this case, since the image is formed on the image sensor 10 in a state where the image is inverted vertically and horizontally, when the preprocessing unit 20 preprocesses the input image data input from the image sensor 10 and transfers it to the DRAM 72. The preprocessed image data is inverted and output in the vertical and horizontal directions (see FIG. 2D). For example, when a refractive optical system is used as an optical system such as a lens in the image processing apparatus 1, the direction of the optical image of the subject imaged on the image sensor 10 is reversed left and right by the arrangement of the reflection mirror. There may be various directions such as a state, a vertically inverted state, or a vertically and horizontally inverted state. Also in this case, when the preprocessing unit 20 preprocesses the input image data input from the image sensor 10 and transfers the input image data to the DRAM 72, the preprocessing image data is inverted in the horizontal direction, the vertical direction, or the vertical and horizontal directions. (See FIGS. 2B to 2D).

  For example, in some cases, the display device 41 may need to be disposed in a state rotated by 180 ° due to restrictions on the layout of the substrate on which the display device 41 is disposed in the image processing apparatus 1. In this case, since the image is displayed on the display device 41 in a state where the image is vertically and horizontally reversed, when the display processing unit 40 acquires (reads out) the display image data from the DRAM 72, the display image data is displayed vertically. Inversion processing is performed in the horizontal direction, and the image data for display subjected to the inversion processing is output to the display device 41 (see FIG. 2D). In addition, for example, when the movable display device 41 is mounted as a function in the image processing apparatus 1, the image displayed on the display device 41 is horizontally reversed depending on the state of the movable unit. There may be various directions such as an inverted state or an up / down / left / right inverted state. Also in this case, when the display processing unit 40 acquires (reads out) display image data from the DRAM 72, the display image data is displayed in the left-right direction, the up-down direction, or the up-down, left-right direction depending on the state of the movable unit. The display image data subjected to the inversion processing is output to the display device 41 (see FIGS. 2B to 2D).

  As described above, in the image processing apparatus 1, restrictions on the mounting direction of the image sensor 10, restrictions on the direction of the optical image of the subject imaged by an optical system such as a lens, restrictions on the mounting direction of the display device 41, and movable type The display device 41 needs to perform an inversion process on the image in accordance with the function of correctly displaying the image. For this reason, each processing block provided in the image processing apparatus 1 performs the inversion processing of the image data by controlling the address when accessing the DRAM 72.

  For example, consider the case where the current image is displayed in the display device 41 after being reversed in the left-right direction as shown in FIG. When the input image data is input from the image sensor 10 in the direction as shown in FIG. 3A, each of the preprocessing unit 20 and the image processing unit 30 is in order from the left side to the right side of the image. And the processed preprocessed image data and display image data are transferred (written) to the DRAM 72. FIG. 3A shows a state in which ascending addresses such as 0, 1, 2, 3,..., 99 are assigned in order from the left side of the image, and display image data is transferred to the DRAM 72. Show. After that, as shown in FIG. 3B, the display processing unit 40 displays the image reversed in the left-right direction on the display device 41, so that the image is stored in the DRAM 72 sequentially from the right side to the left side of the image. The display image data being displayed is acquired (read out). That is, as shown in FIG. 3B, the display image data stored in the descending order of 99, 98, 97, 96,..., For example, in order from the right side of the image. Is read. As described above, the display image data stored in the DRAM 72 is read out in the reverse order of the addresses, whereby the image can be reversed in the horizontal direction.

  At this time, if the addresses 0 to 99 in the above example are not addresses for the same bank of the DRAM 72 but addresses for different banks of the DRAM 72, successive accesses to the same bank of the DRAM 72 by bank interleaving occur. The access efficiency to the DRAM 72 may be reduced. FIG. 4 is a diagram schematically illustrating an example of loss time caused by bank access of the DRAM 72 in the processing block provided in the image processing apparatus 1 of the present embodiment. In FIG. 4, the image processing unit 30 that does not perform inversion processing designates the addresses of the DRAM 72 in ascending order and transfers display image data to the DRAM 72, and the display processing unit 40 that performs inversion processing sets the addresses of the DRAM 72 in descending order. In the access to the DRAM 72 that designates and obtains image data for display, the timing when each address is an address that designates a different bank is shown.

  As shown in FIG. 4, when the image processing unit 30 and the display processing unit 40 alternately access the DRAM 72, when the processing block accessing the DRAM 72 is switched, continuous access to the same bank of the DRAM 72 is performed. Will occur. More specifically, after the image processing unit 30 that does not perform inversion processing designates the addresses of the DRAM 72 in ascending order, and accesses the respective banks of the DRAM 72 in the order of bank A, bank B, bank C, and bank D. The display processing unit 40 that performs inversion processing designates the addresses of the DRAM 72 in descending order, thereby accessing the banks of the DRAM 72 in the order of the bank D, the bank C, the bank B, and the bank A. Thereby, the access to the bank D by the image processing unit 30 and the access to the bank D by the display processing unit 40 are continued. At this time, since the DRAM 72 cannot accept continuous access to the bank D, this period becomes a loss time, and the access efficiency to the DRAM 72 decreases.

  Therefore, the data transfer control device provided in each processing block avoids continuous access to the same bank of the DRAM 72 by changing the order of the banks when the corresponding processing block accesses the DRAM 72. FIG. 5 is a diagram schematically illustrating an example of avoiding the loss time due to the bank access of the DRAM 72 by the first replacement process by the processing block provided in the image processing apparatus 1 of the present embodiment. 5, similar to the bank access of the DRAM 72 shown in FIG. 4, the image processing unit 30 that does not perform the inversion process designates the addresses of the DRAM 72 in ascending order and transfers the image data for display to the DRAM 72. In the access to the DRAM 72 in which the display processing unit 40 that performs the above operation specifies the addresses of the DRAM 72 in descending order and acquires display image data, the timing when each address is an address that designates a different bank is shown.

  As shown in FIG. 5, when the image processing unit 30 and the display processing unit 40 alternately access the DRAM 72, the processing block for accessing the DRAM 72 is switched, similar to the bank access of the DRAM 72 shown in FIG. Sometimes, continuous access to the same bank of the DRAM 72 occurs. However, in the bank access of the DRAM 72 shown in FIG. 5, the data transfer control device 200 provided in the display processing unit 40 changes the order of access to each bank of the DRAM 72. Thereby, the display processing unit 40 can avoid continuous access to the same bank of the DRAM 72 by bank interleaving.

  More specifically, as in the bank access of the DRAM 72 shown in FIG. 4, the image processing unit 30 that does not perform the inversion process designates the addresses of the DRAM 72 in ascending order, so that the bank A, bank B, bank C, bank After accessing each bank of the DRAM 72 in the order of D, the display processing unit 40 that does not perform the inversion processing designates the addresses of the DRAM 72 in descending order, so that the DRAM 72 in the order of the bank D, bank C, bank B, and bank A. Access each bank. Accordingly, similarly to the bank access of the DRAM 72 shown in FIG. 4, the access to the bank D by the image processing unit 30 and the access to the bank D by the display processing unit 40 are continued. At this time, the data transfer control device 200 provided in the display processing unit 40 changes the order of accessing each bank of the DRAM 72 to the order of the bank A, the bank B, the bank C, and the bank D similar to the image processing unit 30. . Thereby, even when the image processing unit 30 that does not perform the inversion process and the display processing unit 40 that performs the inversion process alternately access the DRAM 72, it is possible to avoid continuous access to the same bank of the DRAM 72.

  As described above, the data transfer control device provided in each processing block in the image processing apparatus 1 determines the bank order when the corresponding processing block accesses the DRAM 72, and the bank when the other processing block accesses the DRAM 72. Swap so that they are in the same order as As a result, the bank order when each processing block accesses the DRAM 72 is the same for all processing blocks in the image processing apparatus 1. As a result, processing blocks that do not perform inversion processing and processing blocks that perform inversion processing coexist in the image processing apparatus 1, and even when a plurality of processing blocks access the DRAM 72, the same bank of the DRAM 72 by bank interleaving is used. Therefore, it is possible to suppress a decrease in access efficiency to the DRAM 72 due to a loss time.

  Next, a data transfer control device provided for each processing block in the image processing apparatus 1 will be described. The data transfer control device 100, the data transfer control device 200, and the data transfer control device 300 have different directions for inputting / outputting data, but the concept for inputting / outputting data is the same. Therefore, in the following description, the data transfer control device 100 provided in the image transfer unit 21, the evaluation value generation unit 22, and the image processing unit 30 in the image processing apparatus 1 will be described as a representative. In the following description, the preprocessed image data output from the image transfer unit 21, the evaluation value output from the evaluation value generation unit 22, the display image data and the recording image data output from the image processing unit 30 are described. Collectively, it is called “image data”.

  FIG. 6 is a block diagram showing a schematic configuration of the data transfer control device 100 provided in the image processing apparatus 1 of the present embodiment. As shown in FIG. 6, the data transfer control device 100 includes an operation mode register 101, a packing unit 110, a buffer write control unit 120, a data buffer 130, an address buffer 140, a buffer read control unit 150, A bus interface unit 160.

  The data transfer control device 100 outputs a DMA request signal for transferring (writing) image data to the DRAM 72 via the data bus 80 to the bus arbiter 70 via the data bus 80. At this time, the data transfer control device 100 outputs a DMA request signal to the bus arbiter 70 after collecting a plurality of image data to be transferred to the DRAM 72 so that the order of banks accessing the DRAM 72 is continuous in a predetermined order. To do. Then, after the DMA request is accepted by the bus arbiter 70 and the DMA acceptance signal is input, the data transfer control device 100 receives the collected image data via the data bus 80 so as to be continuous in a predetermined bank order. To the bus arbiter 70. As a result, the bus arbiter 70 and the DRAM interface unit 71 operate in accordance with the DMA from the data transfer control device 100, and the data transfer control device 100 is stored in the storage area corresponding to the address of the DRAM 72 designated by the data transfer control device 100. The image data output from is written.

  In the following description, the case where the address space of the DRAM 72 to which the data transfer control device 100 transfers image data is composed of four banks (bank A, bank B, bank C, and bank D) will be described. To do. In the following description, one DMA by the data transfer control device 100 performs access by bank interleaving for successively accessing each of the four banks of the DRAM 72, that is, four banks of the DRAM 72. A case will be described in which consecutive accesses to are used as one DMA transfer unit.

  In the operation mode register 101, information related to the operation when the data transfer control device 100 accesses the DRAM 72 by DMA, that is, information on the operation mode is set. The information on the operation mode includes, for example, information for changing the order of accessing the banks of the DRAM 72 and the order of the image data when the input image data is collected (packed) into a predetermined unit. And information for switching the address generation order of the DRAM 72 in the horizontal direction and the vertical direction. Then, the operation mode register 101 outputs information on the set operation mode to the packing unit 110. For example, information on operation modes in inversion processing such as no inversion, left-right inversion, up-down inversion, up-down, left-right inversion, and the like is output to the packing unit 110.

  For example, the CPU 60 sets the operation mode information in the operation mode register 101 in advance before the data transfer control device 100 starts the transfer of image data by DMA. For example, when the inversion process of “no inversion” is set as the operation mode, the order of packing the image data is set in ascending order, and the address generation order of the DRAM 72 is set in the ascending order in the horizontal direction and the ascending order in the vertical direction. In this operation mode, the order of accessing the banks is ascending. Further, for example, when “reversal of left and right” is set as the operation mode, the order of packing the image data is set in descending order, and the address generation order of the DRAM 72 is set in the horizontal direction in descending order and in the ascending order in the vertical direction. In this operation mode, the bank access order is descending. For example, when “inverted up / down” is set as the operation mode, the packing order of the image data is set in ascending order, and the address generation order of the DRAM 72 is set in the ascending order in the horizontal direction and the descending order in the vertical direction. In this operation mode, the order of accessing the banks is ascending. Further, for example, when the inversion processing of “up / down / left / right inversion” is set as the operation mode, the packing order of the image data is set in descending order, and the address generation order of the DRAM 72 is set in the descending order in the horizontal direction and the descending order in the vertical direction. . In this operation mode, the bank access order is descending.

  Based on the operation mode information input from the operation mode register 101, the packing unit 110 collects (packages) sequentially input image data into units that match the bus width of the data bus 80, and performs buffer write control. To the unit 120. For example, when the image data is 8 bits and the bus width of the data bus 80 is 32 bits, the sequentially input four image data are packed into 32-bit image data, and the packed 32-bit image data is The data is output to the buffer write control unit 120. At this time, when the information of the operation mode input from the operation mode register 101 is “no inversion”, the order of packing the image data is ascending order. The lower bits are packed into 32-bit image data. When the operation mode information input from the operation mode register 101 is “inverted horizontally”, the order of packing the image data is in descending order. From the bits on the side, it is converted into 32-bit image data.

  The packing unit 110 generates an address of the DRAM 72 to which the packed image data is transferred based on the operation mode information input from the operation mode register 101, and outputs the generated address to the buffer write control unit 120. For example, when the operation mode information input from the operation mode register 101 is “no inversion”, the bank access order is ascending order, and the address generation order of the DRAM 72 is ascending order in the horizontal direction and ascending order in the vertical direction. Therefore, the bank for transferring the packed 32-bit image data is designated in ascending order, and an address for designating the storage area of the DRAM 72 in the ascending order in the horizontal direction and the ascending order in the vertical direction is generated. Further, for example, when the information of the operation mode input from the operation mode register 101 is “left-right inversion”, the order of accessing the bank is descending order, and the address generation order of the DRAM 72 is the descending order in the horizontal direction and the vertical direction. Therefore, the bank for transferring the packed 32-bit image data is designated in descending order, and an address for designating the storage area of the DRAM 72 in the descending order in the horizontal direction and the ascending order in the vertical direction is generated.

  The buffer write control unit 120 sequentially stores the packed image data input from the packing unit 110 in the data buffer 130 and the address input from the packing unit 110 in the address buffer 140 sequentially. When the buffer write control unit 120 completes storing the image data and the address to be transferred to the DRAM 72 by one DMA in the data buffer 130 and the address buffer 140, the buffer write control unit 120 transfers the data to the data buffer 130 and the address buffer 140. A write completion notification indicating that the storage of the image data and address is completed, that is, that one DMA is ready is output to the buffer read control unit 150. In the following description, image data and addresses transferred by one DMA are collectively referred to as “one transfer unit data”.

  When the buffer write control unit 120 receives from the buffer read control unit 150 a read completion notification indicating that reading of one transfer unit of data stored in each of the data buffer 130 and the address buffer 140 has been completed, It is determined that the storage areas of the buffer 130 and the address buffer 140 are empty, and the storage of data for the next one transfer unit is started.

  The data buffer (buffer unit) 130 temporarily stores (saves) a plurality of packed image data sequentially input from the buffer write control unit 120 in accordance with control from the buffer write control unit 120, for example, SRAM (Static). Random Access Memory). The data buffer 130 has storage areas 1301 for storing a plurality of image data to be transferred to the corresponding banks of the DRAM 72, as many as the number of banks of the DRAM 72. For example, a storage area 1301 having a storage capacity for storing 16 packed 32-bit image data input from the buffer write control unit 120, that is, a 64-byte storage area 1301, is provided for the four banks of the DRAM 72. . The data buffer 130 sequentially outputs the image data stored in each storage area 1301 to the buffer read control unit 150 in accordance with the control from the buffer read control unit 150.

  The configuration of the data transfer control device 100 shown in FIG. 6 shows a configuration including four storage area groups 1304 each including four storage areas 1301. In the data transfer control device 100, transfer of all the image data stored in the storage area group 1304 is set as one transfer unit of DMA. With this configuration, the data transfer control device 100 performs DMA four times for performing burst transfer for continuously transferring 16 32-bit image data to each bank of the DRAM 72 for four banks. be able to. Here, the reference numerals written in the respective storage areas 1301 represent the banks of the DRAM 72 to which the respective storage areas 1301 correspond.

  In the present embodiment, the timing for writing image data to the data buffer 130 and the timing for reading image data from the data buffer 130 are not limited at all. Therefore, the data buffer 130 may be an SRAM that can control the data write timing and the data read timing at different timings. That is, when the operation clock of the buffer write control unit 120 and the operation clock of the buffer read control unit 150 are different, the write clock that is the timing to write image data to the data buffer 130 and the timing to read the image data from the data buffer 130 The read clock may be a different clock.

  The address buffer (buffer unit) 140 is a memory having the same configuration as the data buffer 130 for temporarily storing (saving) the address of the DRAM 72 input from the buffer write control unit 120 in accordance with the control from the buffer write control unit 120. Part. That is, the address buffer 140 is a storage unit that stores an address for designating a bank of the DRAM 72 to which image data stored in the data buffer 130 is transferred (written). The address buffer 140 has the same number of storage areas 1401 as the data buffer 130 corresponding to each of the storage areas 1301 in the data buffer 130. However, the storage capacity of the storage area 1401 is not necessarily the same as the storage capacity of the storage area 1301 in the data buffer 130, and is necessary for storing the address specified when transferring the image data stored in the storage area 1301 to the DRAM 72. Storage capacity. The address buffer 140 outputs the address stored in each storage area 1401 to the buffer read control unit 150 in accordance with the control from the buffer read control unit 150.

  In the configuration of the data transfer control device 100 illustrated in FIG. 6, similarly to the data buffer 130, a configuration in which four storage area groups 1404 each including four storage areas 1401 is provided is illustrated. Here again, the reference numerals written in the respective storage areas 1401 represent the banks of the DRAM 72 to which the respective storage areas 1401 correspond.

  In the present embodiment, the timing for writing image data to the address buffer 140 and the timing for reading image data from the address buffer 140 are not limited at all. Further, the data buffer 130 and the address buffer 140 do not necessarily have to be configured by individual buffers, and are configured to provide a data buffer area and an address buffer area in different storage areas on the same SRAM. Also good.

  When a write completion notification is input from the buffer write control unit 120, the buffer read control unit 150 determines that the storage of one transfer unit of data has been completed in the storage areas of the data buffer 130 and the address buffer 140, and the data buffer 130 Sequentially read the packed image data stored in the address and the address stored in the address buffer 140. Then, the buffer read control unit 150 outputs the read image data and address to the bus interface unit 160.

  Further, when the reading of the image data and the address to be transferred to the DRAM 72 by one DMA from the data buffer 130 and the address buffer 140 is completed, the buffer read control unit 150 receives the data from the data buffer 130 and the address buffer 140. A read completion notification indicating that the reading of the image data and address, that is, reading of one transfer unit of data has been completed, is output to the buffer write control unit 120. As a result, the buffer read control unit 150 notifies the buffer write control unit 120 that the storage areas of the data buffer 130 and the address buffer 140 are free.

  The bus interface unit 160 exchanges (interfaces) the image data and the address input from the buffer read control unit 150 with the bus arbiter 70 based on the DMA protocol in the image processing apparatus 1. More specifically, the bus interface unit 160 outputs a DMA request signal for accessing the DRAM 72 to the bus arbiter 70 via the data bus 80. Then, after the DMA request is received by the bus arbiter 70 and the DMA reception signal is input via the data bus 80, the bus interface unit 160 receives the image data and the address input from the buffer read control unit 150 as the data bus. The data is output to the bus arbiter 70 via 80.

  In the configuration of the data transfer control device 100 shown in FIG. 6, the data buffer 130 and the address buffer 140 have a storage area capable of performing DMA four times, so that the bus arbiter 70 DMA can be performed in between.

  Next, a DMA operation performed between the data transfer control device 100 and the bus arbiter 70 will be described. FIG. 7 is a diagram illustrating an example of a DMA operation in the first replacement process of the data transfer control device 100 provided in the image processing apparatus 1 of the present embodiment. FIG. 7 sequentially shows the operation in which the data transfer control device 100 outputs image data by DMA when the inversion processing of “no inversion” is set as the operation mode when outputting image data. Data paths in each operation are shown. In FIG. 7, only the components related to the output of the image data among the components of the data transfer control device 100 are shown for ease of explanation. In the following description, the data transfer control device 100 provided in the image transfer unit 21 in the image processing apparatus 1 will be described. Therefore, “image data” in the following description is preprocessed image data output by the image transfer unit 21.

  First, in the path C11 shown in FIG. 7A, the CPU 60 sets the inversion process of “no inversion” in the operation mode register 101 as an operation mode. Subsequently, when image data (preprocessed image data) to be transferred by the image transfer unit 21 to each bank of the DRAM 72 is input, the image data is packed by the packing unit 110 along the path C12 illustrated in FIG. Thereafter, the image data is stored in the corresponding storage area 1301 of the data buffer 130. FIG. 7A shows a state where the image data of bank A to which address = 0 is assigned is stored in the corresponding storage area 1301 of the data buffer 130. Note that the address generated by the packing unit 110 at this time is stored in the corresponding storage area 1401 of the address buffer 140.

  Similarly, when image data (preprocessed image data) to be transferred by the image transfer unit 21 to each bank of the DRAM 72 is input, the image data is packed by the packing unit 110 along a path C13 illustrated in FIG. Each of the image data after that is stored in the corresponding storage area 1301 of the data buffer 130. FIG. 7B shows a state in which the image data of bank B to bank D to which address = 1 to address = 3 is assigned is stored in the corresponding storage area 1301 of the data buffer 130. At this time, the respective addresses generated by the packing unit 110 are stored in the corresponding storage areas 1401 of the address buffer 140.

  Subsequently, the image data (preprocessed image data) to be transferred to each bank of the DRAM 72 corresponds to four corresponding storage areas 1301 in the data buffer 130, that is, one transfer unit of data corresponds to the corresponding storage area in the data buffer 130. When stored in the group 1304, the buffer write control unit 120 sends a write completion notification indicating that one DMA is ready on the route C14 shown in FIG. 7B to the buffer read control unit. 150.

  Subsequently, when a write completion notification is input from the buffer write control unit 120, the buffer read control unit 150 cooperates with the bus interface unit 160 in the path C 15 shown in FIG. The data of one transfer unit stored in 130 and the address buffer 140 is output to the bus arbiter 70 via the data bus 80.

  More specifically, first, the buffer read control unit 150 requests the bus interface unit 160 to output a DMA request signal in response to a write completion notification input from the buffer write control unit 120. As a result, the bus interface unit 160 outputs a DMA request signal for accessing the DRAM 72 to the bus arbiter 70 via the data bus 80. Thereafter, when the DMA request is received by the bus arbiter 70 and a DMA acceptance signal is input to the bus interface unit 160 via the data bus 80, the bus interface unit 160 starts reading each of the data buffer 130 and the address buffer 140. Is output to the buffer read control unit 150. As a result, the buffer read control unit 150 sequentially reads the data of one transfer unit stored in the data buffer 130 and the address buffer 140 and outputs the data to the bus interface unit 160. Then, the bus interface unit 160 sequentially outputs the data for one transfer unit sequentially input from the buffer read control unit 150 to the bus arbiter 70 via the data bus 80. As a result, data for one transfer unit is written in the storage area corresponding to the designated address of the DRAM 72. FIG. 7C shows a state in which the image data of bank A to bank D to which address = 0 to address = 3 are assigned is sequentially output to the data bus 80.

  After that, when the reading of the data for one transfer unit stored in the data buffer 130 and the address buffer 140 is completed, the buffer read control unit 150 performs the data for one transfer unit through the path C16 shown in FIG. A read completion notification indicating that the reading is completed is output to the buffer write control unit 120.

  In the data transfer control device 100, as described above, each of the data buffer 130 and the address buffer 140 is configured to perform four DMAs. Therefore, in the data transfer control device 100, the buffer read control unit 150 and the bus interface unit 160 cooperate to transfer the image data of the banks A to D to which the address = 0 to the address = 3 are allocated by DMA. In the meantime, data of one transfer unit transferred by the next DMA can be stored in each of the data buffer 130 and the address buffer 140.

  More specifically, during the transfer by DMA, the next image data (pre-processing) that the image transfer unit 21 transfers to each bank of the DRAM 72 through the path C17 shown in FIG. Even when (image data) is input, each image data after being packed by the packing unit 110 can be stored in the corresponding storage area 1301 of the data buffer 130. In FIG. 7D, image data of bank A to bank D (image data transferred by the second DMA) to which address = 4 to address = 7 is assigned, and address = 8 to address = 11 are assigned. The image data of bank A to bank D (image data transferred by the third DMA) is stored in the corresponding storage area 1301 of the data buffer 130. At this time, the respective addresses generated by the packing unit 110 are stored in the corresponding storage areas 1401 of the address buffer 140.

  The buffer write control unit 120 stores the path shown in FIG. 7D every time one transfer unit of data to be transferred to each bank of the DRAM 72 is stored in the corresponding storage area group 1304 in the data buffer 130. A write completion notification is output to the buffer read control unit 150 via the path C18. Thereby, the data transfer control device 100 continues the buffer read control unit 150 and the bus interface unit 160 after the transfer of the image data of the banks A to D to which the address = 0 to the address = 3 is assigned by the DMA. And the second DMA transfer and the third DMA transfer can be sequentially performed.

  FIG. 8 is a diagram schematically showing an example of image data transfer timing in the DMA operation of the first replacement processing by the data transfer control device 100 provided in the image processing apparatus 1 of the present embodiment. FIG. 8 shows the timing of the image data stored in the data buffer 130 and the image data output to the data bus 80 in the DMA operation shown in FIG.

  As described above, the data transfer control device 100 performs bank interleaved access for successively accessing each of the four banks of the DRAM 72 once in each DMA transfer. In the DMA operation shown in FIG. 7, the inversion process is not performed. Therefore, the image data of each bank to which the addresses of the DRAM 72 are assigned in ascending order is stored in the data buffer 130 of the data transfer control device 100 without performing inversion processing. Then, the buffer read control unit 150 and the bus interface unit 160 of the data transfer control device 100, each time the image data to be transferred to the bank A to the bank D of the DRAM 72 is prepared, the bank A and bank B to which the addresses of the DRAM 72 are assigned in ascending order. The image data stored in the data buffer 130 is output to the data bus 80 in the order of bank C and bank D.

  More specifically, as illustrated in FIG. 8, the data transfer control device 100 stores the image data of the banks A to D to which the addresses = 0 to 0 = 3 are assigned in ascending order in the data buffer 130, The image data of bank A to bank D to which this address = 0 to address = 3 is assigned is sequentially output to the data bus 80. Thereafter, as shown in FIG. 8, the data transfer control device 100 stores the image data of the banks A to D to which the addresses = 4 to addresses = 7 are assigned in ascending order in the data buffer 130, and then the address = 4 The image data of bank A to bank D to which address = 7 is assigned are sequentially output to the data bus 80. Thereafter, as shown in FIG. 8, the data transfer control device 100 stores the image data of the banks A to D to which the addresses = 8 to addresses = 11 are assigned in ascending order in the data buffer 130, and then stores the addresses. The image data of bank A to bank D to which = 8 to address = 11 are assigned is sequentially output to the data bus 80.

  Next, another DMA operation performed by the data transfer control device 100 with the bus arbiter 70 will be described. FIG. 9 is a diagram illustrating another example of the DMA operation in the first replacement process of the data transfer control device 100 provided in the image processing apparatus 1 of the present embodiment. FIG. 9 shows in sequence the operation in which the data transfer control device 100 outputs image data by DMA when the inversion processing of “horizontal inversion” is set as the operation mode when outputting image data. Data paths in each operation are shown. 9 shows only the components related to the output of the image data among the components of the data transfer control device 100 for ease of explanation, as in the DMA operation shown in FIG. . In the following description, the data transfer control device 100 provided in the image transfer unit 21 in the image processing apparatus 1 will be described in the same manner as the DMA operation shown in FIG.

  First, in the path C21 shown in FIG. 9A, the CPU 60 sets the inversion process of “horizontal inversion” in the operation mode register 101 as an operation mode. Subsequently, when image data (preprocessed image data) to be transferred by the image transfer unit 21 to each bank of the DRAM 72 is input, the image data is packed by the packing unit 110 along a path C22 illustrated in FIG. Thereafter, the image data is stored in the corresponding storage area 1301 of the data buffer 130. FIG. 9A shows a state in which the image data of the bank D to which the address = 11 is assigned is stored in the corresponding storage area 1301 of the data buffer 130. Note that the address generated by the packing unit 110 at this time is stored in the corresponding storage area 1401 of the address buffer 140.

  Similarly, when image data (preprocessed image data) transferred by the image transfer unit 21 to each bank of the DRAM 72 is input, the image data is packed by the packing unit 110 along the path C23 shown in FIG. 9B. Each of the image data after that is stored in the corresponding storage area 1301 of the data buffer 130. FIG. 9B shows a state where the image data of bank C to bank A to which address = 10 to address = 8 is assigned is stored in the corresponding storage area 1301 of the data buffer 130. At this time, the respective addresses generated by the packing unit 110 are stored in the corresponding storage areas 1401 of the address buffer 140.

  Subsequently, the image data (preprocessed image data) to be transferred to each bank of the DRAM 72 corresponds to four corresponding storage areas 1301 in the data buffer 130, that is, one transfer unit of data corresponds to the corresponding storage area in the data buffer 130. When stored in the group 1304, the buffer write control unit 120 sends a write completion notification to the buffer read control unit 150 through the path C24 illustrated in FIG. 9B, similarly to the DMA operation illustrated in FIG. Output.

  Subsequently, when a write completion notification is input from the buffer write control unit 120, the buffer read control unit 150 cooperates with the bus interface unit 160 in a manner similar to the DMA operation illustrated in FIG. The data of one transfer unit stored in the data buffer 130 and the address buffer 140 is output to the bus arbiter 70 via the data bus 80 through the path C25 shown in FIG.

  More specifically, first, the buffer read control unit 150 requests the bus interface unit 160 to output a DMA request signal in response to the write completion notification input from the buffer write control unit 120, and the bus interface unit 160 A DMA request signal for accessing the DRAM 72 is output to the bus arbiter 70 via the data bus 80. Thereafter, when the DMA request is received by the bus arbiter 70 and a DMA acceptance signal is input, the bus interface unit 160 outputs a signal indicating the start of reading of data for one transfer unit to the buffer read control unit 150, and buffer read The control unit 150 sequentially reads data for one transfer unit stored in the data buffer 130 and the address buffer 140 and outputs the data to the bus interface unit 160. Then, the bus interface unit 160 sequentially outputs the data for one transfer unit sequentially input from the buffer read control unit 150 to the bus arbiter 70 via the data bus 80. As a result, data for one transfer unit is written in the storage area corresponding to the designated address of the DRAM 72. FIG. 9C shows a state in which the image data of bank A to bank D to which address = 8 to address = 11 are assigned is sequentially output to the data bus 80.

  Here, as can be seen from FIG. 9, the image data stored in the data buffer 130 along the path C22 shown in FIG. 9A and the path C23 shown in FIG. Are assigned in descending order, that is, image data of bank D to bank A assigned in the order of address = 11, address = 10, address = 9, address = 8. Then, the buffer read control unit 150 processes the image data stored in the data buffer 130 in ascending order, that is, address = 8, address = 9, address = 10, in the path C25 illustrated in FIG. The data are sequentially read in the order of address = 11 and output to the bus interface unit 160. As described above, the data transfer control device 100 performs the inversion processing of the image data by reversing the order of storing the image data in the data buffer 130 and the order of reading the image data from the data buffer 130.

  Thereafter, when the reading of data for one transfer unit stored in the data buffer 130 and the address buffer 140 is completed, the buffer read control unit 150, as shown in FIG. 9C, is similar to the DMA operation shown in FIG. A read completion notification is output to the buffer write control unit 120 through the path C26.

  In the data transfer control device 100, similarly to the DMA operation shown in FIG. 7, the buffer read control unit 150 and the bus interface unit 160 cooperate with each other in the banks A to B to which addresses = 8 to address = 11 are assigned. Even while the D image data is being transferred by DMA, the data for one transfer unit transferred by the next DMA can be stored in each of the data buffer 130 and the address buffer 140.

  More specifically, the next image data (pre-processing) that the image transfer unit 21 transfers to each bank of the DRAM 72 through the path C27 shown in FIG. Even when (image data) is input, each image data after being packed by the packing unit 110 can be stored in the corresponding storage area 1301 of the data buffer 130. In FIG. 9D, the image data of bank D to bank A (image data transferred by the second DMA) to which address = 7 to address = 4 is assigned, and address = 3 to address = 0 are assigned. The image data of the banks D to A (image data transferred by the third DMA) is stored in the corresponding storage area 1301 of the data buffer 130. At this time, the respective addresses generated by the packing unit 110 are stored in the corresponding storage areas 1401 of the address buffer 140.

  Similarly to the DMA operation shown in FIG. 7, the buffer write control unit 120 stores the data of one transfer unit to be transferred to each bank of the DRAM 72 in the corresponding storage area group 1304 in the data buffer 130. In addition, a write completion notification is output to the buffer read control unit 150 via the route C28 shown in FIG. Thereby, the data transfer control device 100 continues the buffer read control unit 150 and the bus interface unit 160 after the transfer of the image data of the banks A to D to which the address = 8 to the address = 11 is assigned by the DMA. And the second DMA transfer and the third DMA transfer can be sequentially performed.

  FIG. 10 is a diagram schematically illustrating an example of image data transfer timing in another example of the DMA operation of the first replacement processing by the data transfer control device 100 included in the image processing apparatus 1 of the present embodiment. . FIG. 10 shows the timing of the image data stored in the data buffer 130 and the image data output to the data bus 80 in another operation of the DMA shown in FIG.

  Similar to the DMA operation shown in FIG. 7, the data transfer control device 100 performs bank interleaved access for successively accessing each of the four banks of the DRAM 72 in one DMA transfer. In another operation of the DMA shown in FIG. 9, the left / right inversion processing is performed. Therefore, the image data of each bank to which the addresses of the DRAM 72 are assigned in descending order is stored in the data buffer 130 of the data transfer control device 100 in the reverse order of the DMA operation shown in FIG. Then, the buffer read control unit 150 and the bus interface unit 160 of the data transfer control device 100 each time the image data to be transferred to the banks A to D of the DRAM 72 is prepared, as in the DMA operation shown in FIG. The image data stored in the data buffer 130 is output to the data bus 80 in the order of bank A, bank B, bank C, and bank D assigned addresses in ascending order.

  More specifically, as illustrated in FIG. 10, the data transfer control device 100 stores the image data of the banks D to A, to which the addresses = 11 to addresses = 8 are assigned in descending order, in the data buffer 130. The image data of the banks A to D to which the address = 8 to address = 11 are assigned are read out in descending order and sequentially output to the data bus 80. Thereafter, as shown in FIG. 10, the data transfer control device 100 stores the image data of the banks D to A, to which addresses = 7 to addresses = 4 are assigned in descending order, in the data buffer 130, and then this address = 4. The image data of bank A to bank D to which address = 7 is assigned are read in descending order and sequentially output to the data bus 80. After that, as shown in FIG. 10, the data transfer control device 100 stores the image data of the banks D to A to which the addresses = 4 to 0 are assigned in descending order in the data buffer 130, and then stores the addresses. The image data of bank A to bank D assigned with = 0 to address = 3 are read in descending order and sequentially output to the data bus 80.

  As described above, in the data transfer control device 100, when the image data is stored in the data buffer 130, the image data is stored in the reverse order, and the image data is read from the data buffer 130 in the same order regardless of whether the inversion process is performed. Thus, the inversion processing of the image data is performed.

  As described above, the data transfer control device 100 changes the order in which the image data is stored in the data buffer 130 according to the operation mode information set in the operation mode register 101, so that the DMA The order of image data to be output to the bus arbiter 70 via the data bus 80 is changed in the transfer, and an inversion process is performed on the image. Thereby, the order of the banks when the respective processing blocks provided in the image processing apparatus 1 access the DRAM 72 can be made the same in all the processing blocks in the image processing apparatus 1. As a result, processing blocks that do not perform inversion processing and processing blocks that perform inversion processing coexist in the image processing apparatus 1, and even when a plurality of processing blocks access the DRAM 72, the same in the DRAM 72 by bank interleaving. A continuous access to the bank can be avoided, and a decrease in access efficiency to the DRAM 72 due to a loss time can be suppressed.

  In the example of the DMA operation in the data transfer control device 100 shown in FIGS. 7 to 10, as shown in FIG. 11A, each storage area 1301 in the data buffer 130 and each address in the address buffer 140. When the bank of the DRAM 72 corresponding to the storage area 1401 is determined in advance, that is, the corresponding bank is fixed, and the image data and address of each bank are stored in the corresponding storage area 1301 and storage area 1401 Explained. As described above, by determining in advance the banks of the DRAM 72 to which the respective storage areas 1301 in the data buffer 130 and the respective storage areas 1401 in the address buffer 140 correspond, the order in which the image data of the respective banks is arranged. In this case, the stored image data can be output to the DRAM 72 in the same bank order.

  More specifically, in the example of the DMA operation in the data transfer control device 100 shown in FIGS. 7 and 8, for example, as shown in FIG. 11B, bank A, bank B, bank C, bank D In the above description, the image data input in this order is output to the DRAM 72 in the order of bank A, bank B, bank C, and bank D without changing the order. Further, in the example of the DMA operation in the data transfer control device 100 shown in FIGS. 9 and 10, for example, as shown in FIG. 11C, input is performed in the order of bank D, bank C, bank B, and bank A. The case has been described in which the image data is exchanged so that the order is reversed and output to the DRAM 72 in the order of bank A, bank B, bank C, and bank D. However, even if image data is input in an order other than the reverse order by predetermining the banks of the DRAM 72 to which the respective storage areas 1301 in the data buffer 130 and the respective storage areas 1401 in the address buffer 140 correspond. Can be output to the DRAM 72 in the same order. For example, as shown in FIG. 11D, even when image data is input to the data transfer control device 100 in the order of bank D, bank B, bank C, and bank A, each image data is stored in the corresponding memory. By saving the image data in the areas 1301 and reading the saved image data so that the order is the same, the data can be output to the DRAM 72 in the order of bank A, bank B, bank C, and bank D.

  In the example of the DMA operation in the data transfer control device 100 shown in FIGS. 7 to 10, the image data corresponding to each of the bank A, bank B, bank C, and bank D is always included in the data of one transfer unit. The case where one is included has been described. However, the image data input to the data transfer control device 100 does not necessarily include one image data corresponding to each of bank A, bank B, bank C, and bank D. In this case, the storage area 1301 in the data buffer 130 and the storage area 1401 in the address buffer 140 change the banks corresponding to the storage area 1301 and the storage area 1401 as appropriate, such as storing image data corresponding to different banks. You can also For example, consider a case where image data input in the order of bank A, bank B, bank A, and bank B is stored in the same storage area group 1304 in the data buffer 130. In this case, the image data of the first bank A is stored in the storage area 1301 corresponding to the bank A, and the image data of the first bank B is stored in the storage area 1301 corresponding to the bank B. The image data of A can be changed to be stored in the storage area 1301 corresponding to the bank C, and the image data of the second bank B can be stored in the storage area 1301 corresponding to the bank D.

<Second replacement process>
Next, in order to describe another method of accessing the DRAM 72 in each processing block in the image processing apparatus 1, an example of another operation of the image processing apparatus 1 will be described with reference to FIGS. FIG. 12 is a diagram schematically showing an example of image data transfer direction and DRAM 72 access in the image processing apparatus 1 of the present embodiment. FIG. 13 is a diagram schematically showing an example of access to the DRAM 72 corresponding to a case where the image data transfer direction is different in the image processing apparatus 1 of the present embodiment.

  In the image processing apparatus 1, the direction in which the image sensor 10 captures an image may be different from the direction in which the image processing unit 30 performs image processing. For example, as shown in FIG. 12A, the pre-processing unit 20 corresponds to the image sensor 10 raster-scanning pixels and sequentially outputting input image data in the horizontal direction (lateral direction) with respect to the image. The preprocessed image data is transferred (written) to the DRAM 72 in the horizontal direction (lateral direction) with respect to the image. Then, the image processing unit 30 may divide the image into blocks of a predetermined size, and acquire (read) preprocessed image data from the DRAM 72 in the vertical direction (vertical direction) in each block.

  At this time, it is conceivable that each preprocessed image data is stored in the DRAM 72, for example, as shown in FIG. In FIG. 12B, pre-processed image data in which ascending addresses are assigned in order from the left side in each line of the image, and ascending addresses are assigned in order from the upper side of the image, respectively. The state stored in the storage area of the bank is shown.

  In this case, as shown in FIG. 12C, the data transfer control device 100 provided in the image transfer unit 21 in the image processing device 1 continuously accesses different banks of the DRAM 72 to perform preprocessing. Although the image data is transferred to the DRAM 72, the data transfer control device 200 provided in the image processing unit 30 needs to continuously access the same bank of the DRAM 72 and acquire the preprocessed image data from the DRAM 72. become. For this reason, a lot of loss time occurs in successive accesses to the same bank of the DRAM 72 by the data transfer control device 200 for the reasons described above (see FIG. 12C).

  Therefore, as shown in FIG. 13A, an invalid image data area (invalid area) is added to the right side of the valid image data (effective image) area, and the horizontal direction (lateral direction) of the image is considered. A method is conceivable in which the width is controlled to be larger than the horizontal (lateral) image width of the effective image. With this method, the width of the address assigned in each line of the image, i.e., the difference between the first address and the last address in each line is made larger than the width of the address assigned in each line of the effective image. Can think.

  Then, by adjusting the setting of the size of the invalid area, that is, the address width of the invalid area, the data transfer control device 200 provided in the image processing unit 30 converts the preprocessed image data in the vertical direction (vertical direction). The banks of the DRAM 72 that are continuously accessed for acquisition can be different banks. FIG. 13B shows a preprocessed image at the same position in the vertical direction (vertical direction) in the effective image when the horizontal size (horizontal direction) of the invalid area is set to the same size as the bank of the DRAM 72. A state in which data is stored in different banks of the DRAM 72 is shown.

  In this case, as shown in FIG. 13C, the data transfer control device 100 provided in the image transfer unit 21 in the image processing device 1 continuously accesses different banks of the DRAM 72 to perform preprocessing. The image data is transferred to the DRAM 72 and the data transfer control device 200 provided in the image processing unit 30 can also continuously access different banks of the DRAM 72 and acquire the preprocessed image data from the DRAM 72. In this way, by adding the invalid area to the right side of the valid image area, continuous access to the same bank of the DRAM 72 can be avoided (see FIG. 13C).

  However, even by adding an invalid area to the right side of the valid image area, it is not always possible to avoid all consecutive accesses to the same bank of the DRAM 72. For example, in the image processing apparatus 1, transfer (writing) of preprocessed image data by the data transfer control device 100 provided in the image transfer unit 21 in the image processing apparatus 1 and data transfer provided in the image processing unit 30 are described above. In parallel with the acquisition (reading) of the preprocessed image data by the control device 200, the image transfer control device 200 provided in the display processing unit 40 may also acquire (read) the display image data.

  FIG. 14 is a diagram schematically illustrating an example of loss time due to DRAM bank access in the processing block provided in the image processing apparatus 1 of the present embodiment. In FIG. 14, when the data transfer control device 200 provided in the display processing unit 40 acquires display image data from the DRAM 72, the data transfer control device 100 provided in the image transfer unit 21 performs pre-processing image data. The timing in the case of transferring to the DRAM 72 is shown.

  As shown in FIG. 14, when the image transfer unit 21 and the display processing unit 40 alternately access the DRAM 72, when the processing block for accessing the DRAM 72 is switched, continuous access to the same bank of the DRAM 72 is performed. Will occur. More specifically, the data transfer control device 200 provided in the display processing unit 40 accesses the respective banks of the DRAM 72 in the order of bank A, bank B, bank C, and bank D to acquire image data for display. After that, the data transfer control device 100 provided in the image transfer unit 21 accesses the respective banks of the DRAM 72 in the order of bank D, bank A, bank B, and bank C and transfers the preprocessed image data on the fourth line. To do. Accordingly, the access to the bank D by the data transfer control device 200 provided in the display processing unit 40 and the access to the bank D by the data transfer control device 100 provided in the image transfer unit 21 are continued. At this time, since the DRAM 72 cannot accept continuous access to the bank D, this period becomes a loss time, and the access efficiency to the DRAM 72 decreases.

  Therefore, the data transfer control device provided in each processing block avoids continuous access to the same bank of the DRAM 72 by changing the order of the banks when the corresponding processing block accesses the DRAM 72. FIG. 15 is a diagram schematically illustrating an example of avoiding the loss time due to the bank access of the DRAM 72 by the second replacement process by the processing block provided in the image processing apparatus 1 of the present embodiment. FIG. 15 shows the image transfer unit 21 when the data transfer control device 200 provided in the display processing unit 40 acquires image data for display from the DRAM 72 as in the bank access of the DRAM 72 shown in FIG. 4 shows the timing when the data transfer control device 100 provided in FIG. 1 transfers the preprocessed image data to the DRAM 72.

  As shown in FIG. 15, when the image transfer unit 21 and the display processing unit 40 alternately access the DRAM 72, the processing block for accessing the DRAM 72 is switched, similar to the bank access of the DRAM 72 shown in FIG. Sometimes, continuous access to the same bank of the DRAM 72 occurs. However, in the bank access of the DRAM 72 shown in FIG. 15, the data transfer control device 100 provided in the image transfer unit 21 changes the order of access to each bank of the DRAM 72. As a result, the image transfer unit 21 can avoid continuous access to the same bank of the DRAM 72 by bank interleaving.

  More specifically, similar to the bank access of the DRAM 72 shown in FIG. 14, the data transfer control device 200 provided in the display processing unit 40 operates in the order of the bank A, the bank B, the bank C, and the bank D. After the image data for display is obtained by accessing the banks, the data transfer control device 100 provided in the image transfer unit 21 stores the data in the DRAM 72 in the order of bank D, bank A, bank B, and bank C. Access and transfer the preprocessed image data of the fourth line. As a result, similarly to the bank access of the DRAM 72 shown in FIG. 14, the access to the bank D by the data transfer control device 200 provided in the display processing unit 40 and the bank by the data transfer control device 100 provided in the image transfer unit 21 are performed. Access to D continues. At this time, the data transfer control device 100 provided in the image transfer unit 21 determines the order of accessing each bank of the DRAM 72 in the same bank A, bank B, and bank as the data transfer control device 200 provided in the display processing unit 40. The order is changed in the order of C and bank D. Thereby, even when the image transfer unit 21 and the display processing unit 40 alternately access the DRAM 72, continuous access to the same bank of the DRAM 72 can be avoided.

  Note that the operation mode information set in the operation mode register 101 of the data transfer control device 100 provided in the image transfer unit 21 at this time is information different from the inversion processing setting described in the first replacement processing. . More specifically, in the first replacement process, the bank access order, the image data packing order, and the horizontal and vertical address generation order of the DRAM 72 are set in ascending or descending order. However, in the second replacement process, the setting for switching the bank access order from the order of bank D, bank A, bank B, and bank C to the order of bank A, bank B, bank C, and bank D is performed. Do.

  As described above, the data transfer control device provided in each processing block in the image processing apparatus 1 determines the bank order when the corresponding processing block accesses the DRAM 72, and the other processing block accesses the DRAM 72. Swap them so that they are in the same order as the banks. As a result, the bank order when each processing block accesses the DRAM 72 is the same for all processing blocks in the image processing apparatus 1. Thereby, even when a plurality of processing blocks accessing the bank of the DRAM 72 in a different order are mixed in the image processing apparatus 1 and each processing block accesses the DRAM 72 in parallel, the same bank of the DRAM 72 by bank interleaving is used. Therefore, it is possible to suppress a decrease in access efficiency to the DRAM 72 due to a loss time.

  Note that the order of the banks when accessing the DRAM 72 is changed, as described above, by previously determining the banks of the DRAM 72 to which the respective storage areas 1301 in the data buffer 130 and the respective storage areas 1401 in the address buffer 140 correspond. By keeping (fixing), the order of the banks can be easily changed regardless of the order in which the image data of each bank is input to the data transfer control device. However, even when each storage area 1301 in the data buffer 130 and each storage area 1401 in the address buffer 140 correspond to a bank of the DRAM 72 that is not predetermined (not fixed), for example, buffer write control It is considered that the bank order can be changed by the cooperation of the unit 120 and the buffer read control unit 150.

  As described above, according to the mode for carrying out the present invention, the data transfer control device is provided in each processing block in the image processing device 1. The data transfer control device changes the order of data stored in each of the data buffer and the address buffer provided in the data transfer control device itself according to the operation mode information set in the operation mode register, The order of the DRAM banks accessed by one DMA transfer is made the same as the order of the DRAM banks accessed by other processing blocks by DMA transfer. As a result, in the image processing apparatus according to the embodiment for carrying out the present invention, the bank order when each processing block to which the data transfer control apparatus of the present embodiment is applied accesses the DRAM is all set in the image processing apparatus. The same processing block can be used. As a result, a plurality of processing blocks to which the data transfer control device of this embodiment for accessing the bank of DRAMs is accessed in a different order are mixed in the image processing device of the embodiment for carrying out the present invention. Even when the DRAM is accessed in parallel, continuous access to the same bank does not occur in accessing the DRAM by bank interleaving. As a result, it is possible to suppress a decrease in access efficiency to the DRAM due to a loss time caused by successive accesses to the same bank of the DRAM.

  In the present embodiment, the configuration in which all the processing blocks in the image processing apparatus 1 are provided with the data transfer control device has been described. However, the processing block having the data transfer control device has the configuration shown in the present embodiment. For example, the data transfer control device may be provided only in some processing blocks of the image processing device 1. For example, the data transfer control device may be provided only in the image transfer unit 21 and the display processing unit 40 which change the order of the DRAM banks accessed by DMA transfer. As described above, even if the data transfer control device is provided only in a part of the processing blocks of the image processing device 1, it is not necessary to change the exchange (interface) between the processing block and the bus arbiter. This is because the interface between the processing block and the bus arbiter is complicated by changing the order of accessing the DRAM bank in the bus arbiter, and all processing including the processing block that does not change the order of accessing the DRAM bank is performed. It may be advantageous over conventional configurations that require a block to accommodate complex interfaces.

  In the present embodiment, the configuration in which the data buffer 130 and the address buffer 140 are dedicated buffers provided in the data transfer control device 100 for changing the order of banks accessing the DRAM 72 has been described. However, the configuration of the data buffer 130 and the address buffer 140 is not limited to the configuration shown in the present embodiment. For example, in a general processing block that outputs data by DMA transfer, a configuration for reliably transferring data when the data bus is free even when data transfer is awaited due to data bus congestion It is considered that a buffer for temporarily storing (saving) data is provided. In addition, for example, in a general processing block that outputs data by DMA transfer, when the internal clock for processing data is different from the clock in the data bus, a configuration for transferring these clocks is used. It is considered that a buffer for temporarily storing (saving) data is provided. Therefore, when the concept of the present invention is applied to a processing block having the same configuration as the data buffer 130 and the address buffer 140 in the data transfer control device 100 of the present embodiment, the buffer already provided is It can also be used as the data buffer 130 and the address buffer 140 in the data transfer control device 100 of this embodiment. In this case, the access efficiency to the DRAM can be improved without increasing the circuit scale of the processing block. This is considered to be more advantageous than the conventional configuration in which a buffer for changing the order of accessing DRAM banks in the bus arbiter is installed in the bus arbiter.

  In the present embodiment, the storage area 1301 of the data buffer 130 and the storage area of the address buffer 140 that store data and addresses output by DMA transfer according to the operation mode information set in the operation mode register 101. The configuration for changing 1401 has been described. That is, the configuration in which the order of the banks accessing the DRAM 72 is switched when data and addresses are stored in the data buffer 130 and the address buffer 140 provided in the data transfer control device 100 has been described. However, the configuration for changing the order of banks accessing the DRAM 72 is not limited to the configuration shown in the present embodiment. For example, in accordance with the operation mode information set in the operation mode register 101, the storage area 1301 of the data buffer 130 and the storage area 1401 of the address buffer 140 for reading data and addresses output by DMA transfer are changed. You can also That is, in the data transfer control device 100, when the data and addresses stored in the data buffer 130 and the address buffer 140 are read and output by the DMA, the order of banks accessing the DRAM 72 can be changed. In this case, the operation mode information output from the operation mode register 101 is input to the buffer read control unit 150, for example, and the buffer read control unit 150 stores the information in the data buffer 130 according to the input operation mode information. A configuration in which reading of the read data and the address stored in the address buffer 140 is controlled is conceivable.

  In the present embodiment, the configuration in which the packing unit 110 included in the data transfer control device 100 packs input image data and generates the address of the DRAM 72 that transfers the packed image data has been described. However, the configuration for generating the address of the DRAM 72 is not limited to the configuration shown in the present embodiment. For example, the buffer read control unit 150 or the bus interface unit 160 may be configured to generate the address of the DRAM 72 in accordance with the operation mode information set in the operation mode register 101. In this case, the data transfer control device 100 may be configured not to include the address buffer 140.

  Further, in the present embodiment, the case where the DRAM 72 to which the data transfer control device 100 transfers image data is configured with four banks (bank A, bank B, bank C, and bank D) has been described. However, the configuration of the bank in the DRAM is not limited to the configuration shown in the present embodiment. For example, even a DRAM composed of eight banks can be considered similarly.

  In the present embodiment, one DMA by the data transfer control device 100 performs access by bank interleaving for sequentially accessing each of the four banks of the DRAM 72, that is, four banks of the DRAM 72. In the above description, the continuous access to the data is defined as one DMA transfer unit. However, the number of banks accessed by one DMA is not limited to the configuration shown in the present embodiment. For example, an access to one bank in one DMA can be used as a transfer unit for one DMA.

  In the present embodiment, the case has been described in which an image processing apparatus such as a still image camera is used as the data processing apparatus of the present invention, and the data transfer control apparatus of the present invention is applied to this image processing apparatus. However, the system of the data processing apparatus to which the data transfer control apparatus of this embodiment can be applied is not limited to the form for carrying out the present invention, and a plurality of processing blocks connected to the data bus are included. The data transfer control device can be similarly applied to any system as long as it is a data processing device system that sequentially accesses different banks of one DRAM shared by bank interleaving.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

1. Image processing device (data processing device)
10: Image sensor 20: Pre-processing unit (processing block)
21... Image transfer unit (processing block)
22... Evaluation value generator (processing block)
30 ... Image processing unit (processing block)
40: Display processing unit (processing block)
41: Display device 50: Card interface unit (processing block)
51... Recording medium 60... CPU (processing block)
70 ... Bus Arbiter (Common Bus Arbitration Department)
71 ... DRAM interface part (common bus arbitration part)
72 ... DRAM (memory)
80: Data bus (common bus)
100, 200, 300 ... data transfer control device 101 ... operation mode register (data transfer control device, operation mode register)
110... Packing unit (data transfer control device, buffer write control unit)
120: Buffer write control unit (data transfer control device, buffer write control unit)
130... Data buffer (data transfer control device, buffer unit)
140: Address buffer (data transfer control device, buffer unit)
150: Buffer read control unit (data transfer control device, buffer read control unit)
160: Bus interface unit (data transfer control device, buffer read control unit)

Claims (8)

A plurality of processing blocks connected to a common bus;
A memory composed of an address space having a plurality of banks;
A common bus that arbitrates access requests to the memory output from the plurality of processing blocks, and controls data transfer through the common bus between the processing blocks that have received the access requests and the memory The mediation department;
Comprising
Among the plurality of processing blocks, at least one processing block exchanges the order of accessing the banks in the memory when transferring the data to and from the memory via the common bus. ,
The processing block for changing the order of accessing the banks in the memory is:
A data transfer control device for switching the order of accessing the banks by controlling the order of the data to be transferred to and from the memory based on a predetermined order of the data;
Comprising
A data processing apparatus. The data transfer control device includes:
A buffer unit for storing the data to be transferred to and from the memory;
A buffer write control unit for storing the data in the buffer unit;
A buffer read control unit for reading out the data stored in the buffer unit;
Comprising
The data processing apparatus according to claim 1. The data transfer control device includes:
An operation mode register for setting the order of the data to be transferred to and from the memory;
With
The buffer write control unit
Based on the order of the data set in the operation mode register, the data is stored in a storage area corresponding to the bank in the buffer unit,
The data processing apparatus according to claim 2. The data transfer control device includes:
An operation mode register for setting the order of the data to be transferred to and from the memory;
With
The buffer read controller
Based on the order of the data set in the operation mode register, the data is read from the storage area corresponding to the bank in the buffer unit.
The data processing apparatus according to claim 2. The data transfer control device includes:
The order of accessing the banks is reversed to the order of the banks in the memory.
The data processing apparatus according to any one of claims 1 to 4, wherein the data processing apparatus is configured as described above. The data is
Data consisting of areas in a first direction and a second direction;
The data processing device
Comprising a plurality of the processing blocks for changing the order of accessing the banks in the memory;
At least one processing block of the plurality of processing blocks that perform a change in order of accessing the banks in the memory accesses the bank in the memory in the first direction of the data,
At least one other processing block out of the plurality of processing blocks performing a change of the order of accessing the banks in the memory accesses the banks in the memory in the second direction of the data.
The data processing apparatus according to claim 1, wherein the data processing apparatus is a data processing apparatus. The data is
Image data,
The first direction is:
The horizontal direction of the image data,
The second direction is
A vertical direction of the image data;
The data processing apparatus according to claim 6. A plurality of processing blocks connected to a common bus, a memory composed of an address space having a plurality of banks, and arbitrating access requests to the memory output from the plurality of processing blocks, and accepting the access request In a data processing apparatus comprising: a common bus arbitration unit that controls data transfer between the processing block and the memory via the common bus;
The processing block is provided in at least one processing block among the plurality of processing blocks, and controls the order of the data to be transferred to and from the memory based on the predetermined order of the data. When transferring the data to and from the memory via the common bus, the order of accessing the banks in the memory is changed.
A data transfer control device.

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