JP2005011029A - Memory access control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the bus bandwidth and the read latency of a memory device and to reduce the number of access to the memory device. <P>SOLUTION: When an access request adjusted by an access distribution device 111 is a write access request, a buffering device 113 writes corresponding data into a data table 132. When the data written are selected for transfer to the memory device 103, the write access request is entered into an FIFO memory 131. When the access request adjusted is a read access request and when the data requested to be read exist in the data table 132, the buffering device 113 sends the data to the access distribution device 111 as read data. When the relevant data do not exist, the read access request is entered into the FIFO memory 131. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access control device.
[0002]
[Prior art]
As a memory device that can be highly integrated, there is an SDRAM (Synchronous DRAM) having the same basic configuration as a general-purpose DRAM. SDRAM employs a pipeline architecture that uses a command system for burst access, and is attracting attention as a high-speed data access memory device.
[0003]
The SDRAM allows high-speed data access for accessing memory cells in the same bank and the same row. However, since latency occurs in each access, a method of accepting memory access contents as a command is adopted as a reduction method, and the command control is devised.
[0004]
As an SDRAM control method, for example, those disclosed in Patent Documents 1 and 2 are known. The outline will be described below with reference to FIG. FIG. 6 is a control system diagram for explaining a conventional SDRAM control method.
[0005]
As shown in FIG. 6, the conventional SDRAM control method employs a method in which a plurality of bus masters (bus master 0 to bus master 3) 601 access the memory controller 603 via the arbiter 602, and the memory controller 603 accesses the SDRAM 605. Has been.
[0006]
Specifically, when a plurality of bus masters 601 access the SDRAM 605, the access request is received by the arbiter 602, and then the access contents of the bus master are queued in the FIFO memory 604 in the memory controller 603. The memory controller 603 issues a command to the SDRAM 605 with reference to the access contents of the bus master queued in the FIFO memory 604, and determines which bank is to be accessed with reference to the burst length and address.
[0007]
[Patent Document 1]
JP 2001-125826 A
[Patent Document 2]
JP 11-345165 A
[0008]
[Problems to be solved by the invention]
However, in the conventional SDRAM control method, it is possible to achieve the maximum bus bandwidth by switching the command order in the FIFO memory, but it cannot contribute to improving the read data latency. .
[0009]
In addition, since SDRAM increases the power consumption as the number of accesses increases, it is necessary to reduce the number of accesses.
[0010]
The present invention has been made in view of such a point, and when accessing a memory device shared by a plurality of bus masters, the memory device is improved in bus bandwidth, read latency, and memory device. An object of the present invention is to provide a memory access control device that can suppress the number of accesses.
[0011]
[Means for Solving the Problems]
A memory access control device according to the present invention is a memory access control device that controls access to a memory device shared by a plurality of bus masters, arbitrates an access request from the plurality of bus masters, and receives one bus master. When the access request is a write access request, a completion notification is issued to the one bus master after issuing a write registration request, while the access request is a read access request. When issuing a read registration request, the access distribution device relays and transfers the read data sent in accordance with the issued read registration request to the one bus master, and receives the write registration request from the access distribution device. Write the corresponding data to the storage area prepared in advance and An address is registered, and a write request is issued when the written data is to be transferred to the memory device. On the other hand, when the read registration request is received from the access distribution device, the read request is received on the memory device. And the address on the memory device registered in advance is searched for the presence or absence of the corresponding data. If the corresponding data exists, the data is sent to the access distribution device as the read data. On the other hand, if the corresponding data does not exist, the address is registered and a read request is issued, and the read data sent in accordance with the issued read request is registered with the already registered address as well as the read data. A buffering device for sending to the access distribution device, and a buffering device from the buffering device In response to a write request, the memory device generates a signal for accessing the memory device and transfers write data sent from the buffering device to the memory device, while receiving the read request from the buffering device, the memory device And a scheduling device that generates a signal for accessing the data and transfers read data and an address from the memory device to the buffering device.
[0012]
According to this configuration, when a plurality of bus masters access data on the memory device, it may not be necessary to perform memory access to the memory device, so it is possible to speed up the memory operation of the bus master. It becomes. In addition, since the number of memory accesses can be reduced, it is possible to save power.
[0013]
In the memory access control device according to the present invention, in the above invention, the buffering device manages a content to access the memory device based on an access registration request from the access distribution device as an access request job, According to the present invention, the memory device includes an address on the memory device, data to be written to and read from the memory device according to an access request job managed by the FIFO memory, and a data table for managing the address.
[0014]
According to this configuration, data transfer between the memory access control device and the memory device can be realized by changing the order of the access request jobs in the FIFO memory.
[0015]
In the memory access control device according to the present invention, in the above invention, the FIFO memory has a read / write identifier indicating whether the operation content of the access request job is read or write for each access request job. A storage area, a storage area of a table address used in the access request job among the table addresses of the data table, and a storage area of a reuse identifier indicating whether or not data accessing the memory device has reusability The structure which comprises is taken.
[0016]
According to this configuration, in combination with the information in the data table, the contents accessed by a plurality of bus masters are accepted, and memory access can be performed instead of the bus master, so that the access request and the actual access can be separated. Therefore, each operation can be made highly efficient.
[0017]
In the memory access control device according to the present invention, in the above invention, the data table includes an area for storing a physical address of the memory device for each address of a table address that is an address of the data table, and the physical address. An area for storing associated data, a storage area for an access identifier indicating an access status of the data stored in the data storage area to the memory device, and the stored data in the memory device A storage area for a consistency identifier indicating whether consistency with data is maintained, an area for storing an ID for identifying a bus master accessing the memory device, a burst length, and a wraparound address issuance Burst access that accompanies burst access or increment address issuance A configuration that includes a storage area for information that indicates whether it is a.
[0018]
According to this configuration, data transfer between the memory access control device and the memory device can be performed without impairing the consistency and validity of the data held in the memory access control device and the data in the memory device. realizable.
[0019]
In the memory access control device according to the present invention, in the above invention, the buffering device calculates the number of additionally recordable data, which is the number of occupied lines in the data table, based on the access identifier and the consistency identifier in the data table. Means for notifying that the number of additionally recordable data is less than or equal to a threshold value, and generating an access request job for writing the data stored in the data table in the memory device based on the notification information in the FIFO memory The means and the structure to comprise are taken.
[0020]
According to this configuration, the amount of data that can be additionally recorded in the memory access control device can be avoided in advance, and the efficiency of memory access can be improved.
[0021]
In the memory access control device according to the present invention, in the above invention, the buffering device is configured such that the data executed by the access request job is reusable based on the type of the bus master and the address of the memory device accessed by the bus master. Means for determining whether or not the data is the data, and setting the determination result in the reuse identifier in the FIFO memory; and access to the memory device when the setting content of the reuse identifier is not reusable And a means for deleting the corresponding data from the data table after completion.
[0022]
According to this configuration, it is possible to avoid unnecessary data from being stored in the memory access control device, and to improve the efficiency of memory access.
[0023]
The memory access control device according to the present invention is the memory access control device according to the above invention, wherein the buffering device stores means for notifying that there is no access request job in the FIFO memory, and stores in the data table when there is the notification. Means for selecting data that does not match the data in the memory device among the data being generated, and generating an access request job in the FIFO memory for transferring the selected data from the data table to the memory device; The structure which comprises is taken.
[0024]
According to this configuration, it becomes possible to transfer the data in the buffering device that is not consistent with the memory device to the memory device when the memory access is stopped, and can be used immediately in the buffering device. The area can be increased.
[0025]
The memory access control device according to the present invention is the memory access control device according to the above invention, wherein the buffering device adds a priority to the type of read access and write access to the memory device, and the read / write identifier in the FIFO memory. And a means for determining the type of read access and write access to the memory device and controlling the execution order of the access request job in the FIFO memory based on the priority.
[0026]
According to this configuration, read access can be preferentially performed, and the data reception time at the time of read access by the bus master can be shortened.
[0027]
In the memory access control device according to the present invention, in the above invention, the scheduling device adds a priority to an access request from the buffering device, and accesses the memory device based on the priority. And a means for generating a signal that generates the above.
[0028]
According to this configuration, it is possible to devise the order of accepting access request jobs managed in the FIFO memory, and to perform control that increases the data transfer efficiency between the memory access control device and the memory device. Is possible.
[0029]
A memory access control device according to the present invention comprises: an access distribution device according to the invention that interfaces with a plurality of bus masters; a scheduling device according to the invention that interfaces with a memory device having a plurality of banks; and the access distribution device; If the number of buffering devices is m and the number of the memory devices is n, the buffering device according to the invention is interposed between the scheduling device and m. As for the relationship of n, if an arbitrary p is used, m = p × n or n = p × m holds, and each buffering device handles data for an address space obtained by dividing the address space of the memory device into m equal parts. The buffering devices are configured not to handle overlapping address spaces.
[0030]
According to this configuration, high-efficiency transfer control between the memory device and the buffering device can be performed by considering the order of processing access registration requests from the access distribution device while maintaining coherency. It becomes possible.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
The essence of the present invention is that a memory device having a relatively large latency as a memory device shared by a plurality of processors including the DSP and the DMA controller, for example, a memory without accessing the performance of the processor or the DMA controller when accessing the SDRAM. It is to improve the bandwidth and realize efficient and power-saving memory access. The memory access control device of the present invention can also be used in combination with a control unit of a memory device such as a built-in SRAM that does not have a large latency during access.
[0032]
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0033]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a memory access control apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a specific configuration example of the buffering apparatus shown in FIG.
[0034]
1, a memory access control device 101 according to the first embodiment includes an access distribution device 111 that interfaces with a plurality of bus masters (bus master 0 to bus master 4) 102, and a memory device 103 that is shared by the plurality of bus masters 102. And a buffering device 113 interposed between the access distribution device 111 and the scheduling device 112.
[0035]
The buffering device 113 is a FIFO memory 131 that manages the contents of access to the memory device 103 based on an access request from the access distribution device 111 as an access request job, and an address on the memory device 103 and an access request managed by the FIFO memory 131. A data table 132 that manages data to be written to and read from the memory device 103 according to the job is provided.
[0036]
Specifically, the buffering device 113 is configured as shown in FIG. 2, for example. As shown in FIG. 2, the FIFO memory 131 and the data table 132 are provided with areas for storing various parameters. The buffering device 113 is provided with various peripheral devices in addition to the FIFO memory 131 and the data table 132.
[0037]
The specific configuration (FIG. 2) and detailed operation (FIGS. 3 and 4) of the buffering device 113 will be described later, and the overall operation will be described.
[0038]
In the above configuration, the access distribution device 111 arbitrates access requests (read access requests, write access requests) from a plurality of bus masters 102, and receives an access request from one bus master 102, the received bus master 102 To notify that it has been accepted.
[0039]
If the arbitrated access request is a write access request, the access distribution device 111 issues a write registration request to the buffering device 113 and then notifies the bus master 102 that has received the access request of the end of the write. On the other hand, when the arbitrated access request is a read access request, the access distribution device 111 issues a read registration request to the buffering device 113 and is sent from the buffering device 113 according to the issued read registration request. The incoming read data is relayed to the bus master 102 that has received it.
[0040]
The buffering device 113 receives a write registration request from the access distribution device 111, writes the corresponding data if there is an area for writing the write data in the data table 132, and registers the address on the memory device 103. When the data written in the data table 132 is selected to be transferred to the memory device 103, the buffering device 113 enters a write access request to the memory device 103 in the FIFO memory 131 as an access request job. . As a result, the scheduling device 112 selects the access request job, the write access request is converted into an access signal of the memory device 103, and data is written.
[0041]
Also, the buffering device 113 receives a read registration request from the access distribution device 111, compares the address on the memory device that is the read request destination with the address on the memory device registered in the data table 132, and the corresponding data. If the corresponding data exists, the data is sent to the access distribution device 111 as the read data.
[0042]
On the other hand, if the corresponding data does not exist as a result of the search, the buffering device 113 enters a read access request to the memory device 103 in the FIFO memory 131 as an access request job. As a result, the scheduling device 112 selects the access request job, converts it into an access signal for the memory device 103, and performs reading. The buffering device 113 registers the read data and address sent from the scheduling device 112 in the corresponding storage area of the data table 132 and sends the read data to the access distribution device 111.
[0043]
Next, a specific configuration of the buffering device 113 will be described. In FIG. 2, the FIFO memory 131 includes an execution order management device 252 that stores an access request job. For each access request job, storage areas of a read / write identifier 200, a reuse identifier 201, and a table address 202 are provided and managed.
[0044]
The read / write identifier 200 indicates whether the operation of the access request job has a read attribute (reading from the memory device 103) or a write attribute (writing to the memory device 103). The read / write identifier 200 is used for control to change the operation order of an access request job having a read attribute and a write attribute.
[0045]
That is, the read / write switching control register 251 enables or disables the switching control of the operation order of the access request job having the read attribute and the write attribute displayed by the read / write identifier 200 from the bus master 102. Is set.
[0046]
The read / write identifying device 250 refers to the read / write identifier 200 to identify the position of the access request job having the read attribute and the write attribute, and the setting of the read / write switching control register 251 is “the switching control is valid”. At some point, the execution order management device 252 is made to change the execution order so that read is processed preferentially.
[0047]
The next reuse identifier 201 indicates whether the data handled in the access request job is re-referenced (yes) after accessing the memory device 103 (not). This reuse identifier 201 is set by the reuse identification device 231.
[0048]
That is, the reuse identification device 231 determines whether or not the access request job generated by the FIFO memory 131 is an access to a specific area set in the specific area register 232. Further, the reuse identification device 231 compares the access request job generated in the FIFO memory 131 with the bus master ID 208 in the data table 132 as to whether or not the access request job is an access from the bus master set in the specific master register 233. to decide.
[0049]
As a result, the reuse identifying device 231 is set in the specific master register 233 when the access request job generated in the FIFO memory 131 is an access to a specific area set in the specific area register 232. When the access is from the bus master, valid (yes) is displayed in the reuse identifier 201, and invalid (not) is displayed when it is neither. The specific area register 232 and the specific master register 233 can be arbitrarily set from the bus master 102.
[0050]
The next table address 202 stores the table address 203 in the data table 132. That is, the table address 203 stores the table address 203 in the data table 132 that is actually used for transfer to and from the memory device 103 when executing an access job when an access request is received from the access distribution device 111.
[0051]
Further, the IDLE observation device 241 identifies whether or not there is an access request job generated in the FIFO memory 131, and when it is IDLE (idle), that is, when it does not exist, notifies the exit selection device 224 to that effect. It is like that.
[0052]
Next, the data table 132 is associated with the modify identifier 204, the access identifier 205, the physical address 206 on the memory device 103, and the physical address 206 for each address of the table address 203 that is the address of the data table 132. An area for storing the received data 207, a bus master ID 208 for identifying a bus master accessing the memory device 103, and a burst type 209 is provided and managed.
[0053]
The modify identifier 204 is valid (Yes) because the data 207 in the data table 132 does not match the data on the memory device 103 corresponding to the address 206, because the data 207 is used as transfer data to the memory device 103. If they match, the data 207 is not used because it is not used as transfer data to the memory device 103, and thus becomes invalid.
[0054]
The access identifier 205 is information indicating the access status of the data 207 to the memory device 103, and displays an access end “finished”, an initial state of no access “no access”, and an access “access”. Specifically, at the time of write access, “access” being accessed is displayed until the data 207 is written in the memory device 103 by accepting the write access to the address existing in the table address 203. Further, at the time of read access, when data is read from the memory device 103 by accepting the read access corresponding to the address existing in the table address 203, “access” is displayed during access, and when the access is completed, the access is terminated “finished” Is displayed.
[0055]
The burst type 209 stores a burst length and a flag indicating whether the access is a burst access with a wrap around address issuance or a burst access with an increment address issuance. .
[0056]
Next, the valid line calculation device 223 calculates the number of additionally recordable data that is the number of occupied lines in the data table 132 with reference to the valid flag of the modify identifier 204 and the valid flag of the access identifier 205. Specifically, the sum of the number of lines in the table with the access identifier 205 “no access” and the number of lines in the table with the access identifier 205 “finished” and the modify identifier 204 “not” is stored in the data table. The number of lines subtracted from the total number of lines is the number of data lines that can be additionally written. Then, the calculation result in the effective line calculation device 223 and the threshold value set in the threshold value register 221 are compared by the comparator 222, and the comparison result is given to the exit selection device 224.
[0057]
When the comparison result of the comparator 222 indicates that the number of occupied lines is smaller than the threshold set in the threshold register 221, it indicates that the modify identifier 204 has many invalid flags (that is, additional writing is possible), and vice versa. Indicates that the modify identifier 204 has many valid flags (that is, additional writing is not possible).
[0058]
The exit selection device 224 determines the flag status of the modify identifier 204 from the comparison result in the comparator 222. If the modify identifier 204 is invalid, overwriting is possible (that is, additional writing is possible), and nothing is done. On the other hand, in order to transfer to the memory device 103 if the modify identifier 204 is valid, the leaving selection device 224 selects a line that is not consistent with the data 207 in the memory device 103, and sends it to the memory device 103. An access request job having a write attribute is generated in the FIFO memory 131. Then, after receiving the idle notification from the IDLE observation device 241, the line of the selected data table is invalidated. Further, the exit selection device 224 updates the modify identifier 204 when data is written to the memory device 103.
[0059]
Next, the operation of the buffering device 113 configured as described above will be described with reference to FIGS. FIG. 3 is a flowchart for explaining the operation when a write access request is generated in the buffering device 113 shown in FIG. FIG. 4 is a flowchart for explaining the operation when a read access request is generated in the buffering device 113 shown in FIG.
[0060]
In FIG. 3, when a write access request is input from the access distribution device 111 (step ST301), it is searched whether or not the write destination address exists in the data table 132 (step ST302). As a result, when the write destination address exists in the data table 132 (step ST303: Yes), the data 207 is stored in the corresponding data area in the data table 132 (step ST304), and the process proceeds to step ST308.
[0061]
On the other hand, when the write destination address does not exist in the data table 132 (step ST303: No), it is determined whether or not the data table 132 can be additionally written (step ST305). As a result, if additional writing is not possible (step ST305: No), the data selection process is performed by the data selection unit 224 to secure a write area (step ST306), and an address and data are registered in the secured area (step ST306). ST307), the process proceeds to step ST308. If the data table 132 can be additionally recorded (step ST305: Yes), the address and data are registered in the additionally recordable area (step ST307), and the process proceeds to step ST308.
[0062]
In step ST308, it is determined with reference to the reuse identifier 201 whether the written data is reused. As a result of the determination, if the data is to be reused (step ST308: Yes), this processing ends, but if the data is not to be reused (step ST308: No), it is registered as write access in the FIFO memory 131, After writing data to the memory device 103 for access, the target data area of the data table 132 is released as an empty area (step ST309), and then this process is terminated.
[0063]
Next, in FIG. 4, when a read access request is input from the access distribution device 111 (step ST401), it is searched whether or not the read destination address exists in the data table 132 (step ST402). As a result, when the read destination address exists in the data table 132 (step ST403: Yes), it is determined whether or not the data 207 associated with the physical address 206 is valid (step ST404). If the corresponding data 207 is valid (step ST404: Yes), the process directly proceeds to step ST408.
[0064]
On the other hand, when the read destination address does not exist in the data table 132 (step ST403: No) or when the corresponding data 207 is not valid (step ST404: No), it is determined whether or not the data table 132 can be additionally written. (Step ST405). As a result, if additional writing is not possible (step ST405: No), the data selection process is performed by the data selection unit 224 to secure a write area (step ST406), and the data read from the memory device 103 in the secured area The address is registered (step ST407), and the process proceeds to step ST408.
[0065]
Further, even when the read destination address does not exist in the data table 132 (step ST403: No), or even when the corresponding data 207 is not valid (step ST404: No), the data table 132 can be additionally written (step ST405: Yes), the process proceeds directly to step ST408.
[0066]
In step ST408, the data 207 in the data table 132 is read by the bus master 102 that has requested read access. In parallel, it is determined with reference to the reuse identifier 201 whether the written data is reused (step ST409). As a result of the determination, if the data is to be reused (step ST409: Yes), this processing ends, but if the data is not to be reused (step ST409: No), the target data area of the data table 132 is set as an empty area. It is opened (step ST410), and then this process is terminated.
[0067]
As described above, according to the first embodiment, when a plurality of bus masters access data on a memory device, it may not be necessary to access the memory device. It is possible to increase the speed, and it is possible to save power by reducing the number of memory accesses.
[0068]
Here, the buffering device 113 manages the contents of accessing the memory device 103 based on the access request from the access distribution device 111 as an access request job, and manages the address on the memory device 103 and the FIFO memory 131. And the data table 132 for managing the data to be written to and read from the memory device 103 in accordance with the access request job to be executed, the order of the access request jobs in the FIFO memory 131 is changed, and the memory access control device 101 and the memory device 103 are changed. It is possible to realize data transfer between the two.
[0069]
The FIFO memory 131 also includes a read / write identifier 200 indicating whether the operation content of the access request job is read or write for each access request job managed by the execution order management device 252, and a table of the data table 132. Since the table address 202 used in the access request job in the address 203 and the reuse identifier 201 indicating whether or not the data accessing the memory device 103 has reusability are stored and managed, respectively. In combination with the information in the data table 132, memory access is possible instead of the plurality of bus masters 102. Therefore, the access request and the actual access can be separated, and the operation in each can be made highly efficient.
[0070]
The data table 132 includes a physical address 206 of the memory device 103, data 207 associated with the physical address 206, and stored data 207 for each address of the table address 203 that is the address of the data table. An access identifier 05 indicating an access status to the memory device 103, a modify identifier 204 which is a consistency identifier indicating whether or not the stored data 207 is consistent with the data in the memory device 103, and access A bus master ID 208 for identifying the received bus master 102, and a burst type and a burst type 209 which is information indicating whether the burst access is a burst access accompanied by a wraparound address issue or a burst access accompanied by an increment address issue It Since the data 207 held in the data table 132 and the data in the memory device 103 are not lost, the memory access control device 101, the memory device 103, and Data transfer between the two can be realized.
[0071]
In addition, the buffering device 113 includes the effective line calculation device 223 that is a means for calculating the number of additionally recordable data that is the number of occupied lines in the data table 132 based on the access identifier 205 and the modify identifier 204 in the data table 132, and the additional writing is possible A threshold register 221 and a comparator 222 that are means for notifying that the number of data is equal to or less than a threshold, and an access request for writing the stored data 207 of the data table 132 to the memory device 103 based on the notification information from the comparator 222. Since the exit selection device 224, which is a means for generating a job in the FIFO memory 131, is provided, it is possible to avoid in advance that the amount of data that can be additionally recorded in the memory access control device 101 becomes zero, and to improve the efficiency of memory access And can That.
[0072]
In addition, the buffering device 113 uses the type of the bus master 102 (specific master register 233) and the address of the memory device 103 accessed by the bus master 102 (specific region register 232) to make the data executed by the access request job reusable. It is determined whether or not the data is certain, and the determination result is set to the reuse identifier 201 in the FIFO memory 131, and the setting contents of the reuse identifier 201 are not reusable. Since there is an exit selection device 224 that is means for deleting the corresponding data from the data table 132 after the access to the memory device 103 is completed, it is possible to avoid storing unnecessary data in the memory access control device 101. This makes it possible to improve the efficiency of memory access.
[0073]
In addition, the buffering device 113 receives an IDLE observation device 241 as a means for notifying that an access request job does not exist (that is, idle) in the FIFO memory 131, and when the IDLE observation device 241 notifies the idle. An access request job for selecting the data 207 that does not match the data in the memory device from the data 207 stored in the data table 132 and transferring the selected data 207 from the data table 132 to the memory device 103. Since the egress selection device 224 that is a means for generating the FIFO memory 131 is provided, the memory device 103 stores data 207 that is not consistent with the memory device 103 existing in the buffering device 113 when the memory access is idle. Can be transferred to , It is possible to increase the space available immediately at the buffering device 113.
[0074]
Further, the buffering device 113 is a memory based on the read / write switching control register 252 which is a means for adding priority to the types of read access and write access to the memory device 103 and the read / write identifier 200 in the FIFO memory 131. A read / write identifying device 250 that is a means for determining the type of read access and write access to the device 103 and controlling the execution order of the access request job in the FIFO memory 131 based on the priority. Read access can be preferentially performed, and data reception time at the time of read access by the bus master 102 can be shortened.
[0075]
In addition, the scheduling device 112 includes means for adding a priority to an access request from the buffering device 113 and means for generating a signal that causes access to the memory device 103 based on the priority. Can be. According to this, it becomes possible to devise the order in which the access request jobs managed in the FIFO memory 131 are received, and the efficiency of data transfer between the memory access control device 101 and the memory device 103 is improved. Control can be performed.
[0076]
(Embodiment 2)
FIG. 5 is a block diagram showing the configuration of the memory access control apparatus according to the second embodiment of the present invention. As illustrated in FIG. 5, the memory access control device 301 according to the second embodiment has a case where a memory device 302 accessed by a plurality of bus masters (bus master 0 to bus master 4) 102 has a plurality of banks 321.
[0077]
In FIG. 5, a memory access control device 301 is a scheduling device that interfaces with an access distribution device 311 that interfaces with a plurality of bus masters (bus master 0 to bus master 4) 102 and a memory device 302 that is shared by the plurality of bus masters 102. 312, and a plurality of buffering devices 313 interposed between the access distribution device 311 and the scheduling device 312.
[0078]
Since the plurality of buffering devices 313 are mounted, the access distribution device 311 distributes the access registration request to the plurality of buffering devices 313 after the access arbitration of the bus master 102. This distribution criterion is based on a specific address area.
[0079]
The access distribution device 311 has a function of sending the read data sent from the buffering device 313 to the bus master 102 in the order requested by the bus master 102 in response to the read access registration request distributed to each buffering device 313. is doing.
[0080]
Each of the plurality of buffering devices 313 has the same configuration as the buffering device 113 described in the first embodiment, and includes a data table 331 and a FIFO memory 332 having the same configuration.
[0081]
The scheduling device 312 selects the head access request job in the FIFO memory 332 in the plurality of buffering devices 313, converts it into an access signal to the memory device 302, and transmits data between the buffering device 313 and the memory device 302. Perform the transfer.
[0082]
At this time, if the memory device 302 is an SDRAM in which accesses to the same bank 321 and read / write accesses occur alternately, the bandwidth decreases. For this reason, the scheduling apparatus 312 implements a measure for avoiding this point to the maximum, and realizes highly efficient memory access.
[0083]
Here, if the number of buffering devices 313 is m and the memory device 302 has a bank configuration of n, the relationship between m and n is m = p × n or n = Since p × m holds, each buffering device 313 handles data for an address space obtained by equally dividing the address space of the memory device 302 into m, and does not handle an overlapping address space among a plurality of buffering devices 313. It has become.
[0084]
With this configuration, it is possible to perform highly efficient transfer control between the memory device 302 and the buffering device 313 by considering the order of processing access registration requests from the access distribution device 311 while maintaining coherency. It becomes possible.
[0085]
In each embodiment, the SDRAM has been described as a memory device. However, the present invention is not limited to this, and can be applied to other high-speed access memories. Needless to say, there is no limit to the number.
[0086]
【The invention's effect】
As described above, according to the present invention, when a memory device shared by a plurality of bus masters is accessed, the bus bandwidth of the memory device is improved, the read latency is improved, and the number of accesses to the memory device is increased. Can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a memory access control apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a specific configuration example of the buffering device shown in FIG.
FIG. 3 is a flowchart for explaining the operation when a write access request is generated in the buffering device shown in FIG. 1;
4 is a flowchart for explaining the operation when a read access request is generated in the buffering device shown in FIG.
FIG. 5 is a block diagram showing a configuration of a memory access control apparatus according to a second embodiment of the present invention.
FIG. 6 is a control system diagram for explaining a conventional SDRAM control method;
[Explanation of symbols]
101, 301 Memory access control device
102 Bus master
103,302 memory device
111,311 access distribution device
112, 312 scheduling device
113,313 Buffering device
131,332 FIFO memory
132,331 data table
200 Read / write identifier
201 Reuse identifier
202, 203 Table address
204 modify identifier
205 Access identifier
206 Physical address
207 data
208 Bus master ID
221 Threshold register
222 Comparator
223 Effective line calculation device
224 Exit selection device
231 Reuse identification device
232 Specific area register
233 Specific master register
241 IDLE observation device
250 read / write identification device
251 read / write exchange control register
252 Execution order management device
321 Bank

Claims (10)

A memory access control device for controlling access to a memory device shared by a plurality of bus masters,
Arbitrates access requests from the plurality of bus masters, issues an acceptance notification to the accepted one bus master, and if the access request is a write access request, issues a write registration request to the one bus master. When the access request is a read access request, it issues a read registration request and relays the read data sent in accordance with the issued read registration request to the one bus master. An access distribution device,
When the write registration request from the access distribution device is received and the corresponding data is written in a storage area prepared in advance and the address on the memory device is registered, and the written data is to be transferred to the memory device. While issuing the write request, the presence or absence of the corresponding data by comparing the address on the memory device of the read request destination with the address on the pre-registered memory device in response to the read registration request from the access distribution device If the corresponding data exists, the data is sent as the read data to the access distribution device. On the other hand, if the corresponding data does not exist, an address is registered and a read request is issued. Register the read data sent according to the issued read request with the already registered address. Buffering device for both sending the read data to the access distribution device,
In response to the write request from the buffering device, generates a signal for accessing the memory device and transfers write data sent from the buffering device to the memory device, while reading from the buffering device. A scheduling device for receiving a request and generating a signal for accessing the memory device and transferring read data and an address from the memory device to the buffering device;
A memory access control device comprising: The buffering device includes a FIFO memory that manages, as an access request job, contents to access the memory device based on an access registration request from the access distribution device, an address on the memory device, and an access request managed by the FIFO memory. 2. The memory access control device according to claim 1, further comprising: a data table for managing data to be written to and read from the memory device according to a job, and data addresses thereof. The FIFO memory includes, for each access request job, a storage area of a read / write identifier indicating whether the operation content of the access request job is read or write, and the access request among the table addresses of the data table 3. The memory according to claim 2, further comprising: a storage area for a table address used in a job; and a storage area for a reuse identifier indicating whether or not data accessing the memory device has reusability. Access control device. The data table includes an area for storing a physical address of the memory device, an area for storing data associated with the physical address, and a data storage area for each address of a table address that is an address of the data table. The storage area of the access identifier indicating the access status of the data stored in the memory device and the consistency indicating whether the stored data is consistent with the data in the memory device An identifier storage area, an area for storing an ID for identifying a bus master accessing the memory device, burst access with burst length and wraparound address issuance, or burst access with increment address issuance A storage area for information indicating whether or not Memory access control device according to claim 2, wherein. The buffering device calculates a number of additionally recordable data that is the number of occupied lines in the data table based on the access identifier and the consistency identifier in the data table, and the number of additionally recordable data is equal to or less than a threshold value. And a means for causing the FIFO memory to generate an access request job for writing data stored in the data table to the memory device based on the notification information. Memory access control device. The buffering device determines whether the data executed by the access request job is reusable data based on the type of the bus master or the address of the memory device accessed by the bus master, and the determination result Means for setting the reuse identifier in the FIFO memory, and means for deleting the relevant data from the data table after the access to the memory device is completed when the setting content of the reuse identifier is not reusable. 3. The memory access control device according to claim 2, further comprising: The buffering device is configured to notify that there is no access request job in the FIFO memory, and when the notification is received, the buffering device matches the data in the memory device among the data stored in the data table. 3. A memory access according to claim 2, further comprising: means for generating, in the FIFO memory, an access request job for selecting non-existing data and transferring the selected data from the data table to the memory device. Control device. The buffering device discriminates the type of read access and write access to the memory device based on the means for adding priority to the type of read access and write access to the memory device and the read / write identifier in the FIFO memory 3. The memory access control apparatus according to claim 2, further comprising means for controlling an execution order of access request jobs in the FIFO memory based on the priority. The scheduling device comprises means for adding a priority to an access request from the buffering device, and means for generating a signal for causing access to a memory device based on the priority. The memory access control device according to claim 1, wherein: 10. The access distribution device according to claim 1, which interfaces with a plurality of bus masters, and a memory device with a plurality of banks. And a plurality of buffering devices according to any one of claims 1 to 9 interposed between the access distribution device and the scheduling device. Assuming that the memory device has a configuration of n banks, the relationship between m and n is m = p × n or n = p × m when an arbitrary p is used, and each buffering device Handles data for an address space obtained by dividing the address space of the memory device into m equal parts. A memory access control device characterized by not being handled.

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