JP6199147B2 - Field effect type compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect compound semiconductor device and a method for manufacturing the same, and relates to, for example, improvement of a drain breakdown voltage in a GaN-based HEMT.

  With the rapid development of the network society in recent years, it is expected that the number of wireless communication systems and the accompanying demand for radio waves will further increase, and the allocated frequency will be tightened. Also, since radar can measure an object more accurately as the frequency becomes higher, radar using 10 GHz band has already been adopted in aircraft, but it is expected that it will shift to a higher frequency in the future.

  In order to cope with such high-frequency operation, development of a semiconductor device capable of high-speed operation is urgent. Nitride semiconductor devices such as GaNHEMT have features such as a high saturation electron velocity and a wide band gap, and therefore are actively developed as semiconductor devices with a high breakdown voltage and a high output.

  As nitride semiconductor devices, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). In particular, AlGaN / GaN HEMTs using GaN as an electron transit layer and AlGaN as an electron supply layer are attracting attention.

  In the AlGaN / GaN.HEMT, strain due to the lattice constant difference between GaN and AlGaN is generated on the AlGaN side. Due to the piezo polarization generated and the spontaneous polarization of AlGaN, a high-concentration two-dimensional electron gas (2DEG) is formed at the interface between GaN and AlGaN.

At this time, it is generally known that current collapse can be suppressed by using a Si ₃ N ₄ film as a protective film on the GaN surface protective layer (see, for example, Non-Patent Document 1). The Si ₃ N ₄ film can be formed by a plasma CVD method. Another protective film is an AlN film which is also a nitride insulating film.

However, since the AlN film is formed by ALD (Atomic Layer Deposition), the productivity of the AlN film is poor because it takes more time to form the film than Si ₃ N ₄ . Therefore, a Si ₃ N ₄ film is often used on the GaN surface protective layer.

In order to increase the insulation between the GaN surface protective layer and the wiring electrode or decrease the capacitance, a SiO ₂ film is laminated on the surface of Si ₃ N ₄ to keep a distance between the GaN surface protective layer and the wiring electrode. . In this case, the stacked interface between the SiO ₂ film and the Si ₃ N ₄ film is exposed on the sidewall of the drain contact hole.

Here, a conventional GaN-based HEMT will be described with reference to FIG. FIG. 14 is a schematic sectional view of a conventional GaN-based HEMT. An i-type GaN electron transit layer 54, an n-type AlGaN electron supply layer 55, and an i-type are provided on a silicon substrate 51 via an AlN buffer layer 52 and an AlGaN layer 53. A GaN surface protective layer 56 is grown. Then, _{the Si} 3 _{N 4} film 57 provided as a surface protective film, to remove _{the Si} 3 _{N 4} film 57 of the gate-forming region, to form a _Si 3 _{N 4} film 58 as a gate insulating film.

Next, after forming the gate electrode 59, the SiO ₂ film 60 is deposited on the entire surface. Next, after forming contact holes for forming the source / drain electrodes, an Al film is formed, and the Al film is etched to form the source electrode 61 and the drain electrode 62, thereby forming the basic structure of the GaN-based HEMT. Is completed.

In this case, although a high voltage is applied to the drain electrode, since the band gap of Si ₃ N ₄ is smaller than that of SiO ₂ , the lateral breakdown voltage of the Si ₃ N ₄ films 57 and 58 is weakened. In addition, since the charges indicated by ◯ in the figure are likely to accumulate at the interface between the insulating films, the Si ₃ N ₄ films 57 and 58 having a relatively small band gap are likely to break down.

  Therefore, attempts have been made to relax the electric field by increasing the distance between the drain electrode 62 and the gate electrode 59. FIG. 15 is a schematic cross-sectional view of a conventional improved GaN-based HEMT, but the configuration is the same as that of the GaN-based MEMT in FIG. 14 except that the interval between the drain electrode 62 and the gate electrode 59 is widened.

JP 2010-238982 A

Y. Ando et al., 10-W / mm AlGaN GaN HFET With a Field Modulating Plate, IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 5, p289, MAY 2003

  However, the improved GaN-based HEMT has a problem that the distance between the drain and the source becomes long, so that there is a problem that the on-resistance is increased, and there is a problem that the chip area is increased and the chip cost is increased.

  Accordingly, it is an object of the field effect compound semiconductor device and the manufacturing method thereof to improve the drain breakdown voltage without expanding the gate-drain space.

  From one aspect to be disclosed, a gallium nitride-based carrier traveling layer, a gallium nitride-based carrier supply layer, a gallium nitride-based surface protective layer, a silicon nitride film and a silicon oxide sequentially stacked on the gallium nitride-based surface protective layer And a wide forbidden band width insulating film having a wider band gap than silicon nitride covering the side walls of the contact holes for the source electrode and the drain electrode provided in the silicon oxide film and the silicon nitride film. A field effect type compound semiconductor device is provided.

  Further, from another viewpoint to be disclosed, a step of sequentially laminating a gallium nitride-based carrier traveling layer, a gallium nitride-based carrier supply layer, and a gallium nitride-based surface protective layer on a substrate, and on the gallium nitride-based surface protective layer A step of forming a first silicon nitride film, a step of selectively removing the first silicon nitride film in the gate electrode formation portion, and a second silicon nitride film to be a gate insulating film are formed on the entire surface. A step of forming a gate electrode in the gate electrode formation portion, a step of forming a silicon oxide film on the entire surface, and a source electrode and drain electrode formation portion, and the silicon oxide film and the second silicon nitride film. And a step of selectively removing the first silicon nitride film to form a contact hole; and a side wall surface of the contact hole from a silicon nitride band gap. And a step of forming a source electrode and a drain electrode in contact with the wide forbidden band width insulating film in the contact hole. A method for manufacturing a semiconductor device is provided.

  According to the disclosed field effect type compound semiconductor device and the method for manufacturing the same, it is possible to improve the drain breakdown voltage without expanding between the gate and the drain.

1 is a schematic cross-sectional view of a field effect compound semiconductor device according to an embodiment of the present invention. It is explanatory drawing of the electric field strength distribution of the field effect type compound semiconductor device of embodiment of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing after FIG. 6 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 8 of the manufacturing process of GaN-type HEMT of Example 2 of this invention. It is explanatory drawing after FIG. 9 of the manufacturing process of GaN-type HEMT of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 11 of the manufacturing process of GaN-type HEMT of Example 3 of this invention. It is explanatory drawing after FIG. 12 of the manufacturing process of GaN-type HEMT of Example 3 of this invention. It is a schematic sectional view of a conventional GaN-based HEMT. It is a schematic sectional view of a conventional improved GaN-based HEMT.

Here, with reference to FIG.1 and FIG.2, the field effect type compound semiconductor device of embodiment of this invention is demonstrated. FIG. 1 is a schematic cross-sectional view of a field effect compound semiconductor device according to an embodiment of the present invention. A GaN-based carrier running layer 4, a GaN-based carrier supply layer 5, and a GaN-based surface protective layer 6 are sequentially stacked on the substrate 1 via the buffer layer 2 and the AlGaN layer 3. Then, _{the Si} 3 _{N 4} film 7 provided on the GaN-based surface protective layer, to remove _{the Si} 3 _{N 4} film 7 of the gate-forming region, to form a _Si 3 _{N 4} film 8 serving as a gate insulating film. Next, after forming the gate electrode 9, a SiO ₂ film 10 is deposited on the entire surface. Next, contact holes for forming the source electrode 12 and the drain electrode 13 are formed. Note that the Si ₃ N ₄ film 8 is not essential, and the Si ₃ N ₄ film 8 is not provided when the gate electrode 9 is a Schottky electrode.

Next, the wide forbidden band width insulating film 11 having a wider band gap than Si ₃ N _{4 at the} interface of the laminated film composed of the Si ₃ N ₄ film 7 / Si ₃ N ₄ film 8 / SiO ₂ film 10 exposed on the side wall surface of the contact hole. Cover with. In this case, the wide forbidden band insulating film 11 may be anything as long as it has a wider band gap and higher insulation than Si ₃ N ₄ , but typically, either a SiO ₂ film or an AlN film is used.

In the case of using the SiO ₂ film, it may be deposited on the entire surface and then left in a sidewall shape by anisotropic etching. In the case of using AlN, the AlN film may be deposited thinly and the contact portion may be removed by etching, or the AlN film may be deposited with a lift-off pattern provided in advance on the bottom surface of the contact hole.

  As the substrate 1, a silicon substrate, a sapphire substrate, a SiC substrate, or a GaN substrate can be used, and the buffer layer 2 may be appropriately selected according to the type of the substrate 1. For example, when a silicon substrate is used, an AlN layer may be used, and when a sapphire substrate is used, a GaN low-temperature buffer layer may be used.

  The GaN-based carrier running layer 4 is typically an i-type GaN layer, but an i-type InGaN layer may be used. The GaN-based carrier supply layer 5 is typically an n-type AlGaN layer, but when an i-type InGaN layer is used as a carrier travel layer, the n-type GaN layer may be used as a carrier supply layer. Further, an i-type semiconductor layer having the same composition as the GaN-based carrier supply layer may be interposed between the GaN-based carrier running layer 4 and the GaN-based carrier supply layer 5.

  The GaN-based surface protective layer 6 is typically an i-type GaN layer, but an n-type GaN layer may be used, or a laminated film of an i-type GaN layer and an n-type GaN layer may be used. The carrier is typically an electron, but a hole may be a carrier. In that case, the n-type semiconductor may be replaced with a p-type semiconductor.

FIG. 2 is an explanatory diagram of the electric field intensity distribution of the field effect compound semiconductor device of the present invention, and shows the results obtained by electric field simulation. The solid line shows the case where only the periphery of the drain electrode is made of an SiO ₂ film as in the field effect type compound semiconductor device of the present invention, and the broken line shows the case where the whole is made of an Si ₃ N ₄ film. As shown in the figure, it was confirmed that when only the periphery of the drain electrode is an SiO ₂ film, the electric field strength in the Si ₃ N ₄ film in the vicinity thereof is lowered.

As described above, in the embodiment of the present invention, the laminated interface of the laminated insulating film including the Si ₃ N ₄ film exposed on the side wall surface of the contact hole for the drain electrode has a wider band gap than Si ₃ N _4. Since it is covered with the forbidden band insulating film, the drain breakdown voltage can be increased. As a result, since it is not necessary to increase the gate-drain interval, an increase in on-resistance and an increase in chip area can be avoided.

Next, a GaN-based HEMT according to Example 1 of the present invention will be described with reference to FIGS. As shown in FIG. 3A, first, an AlN buffer layer 22 having a thickness of 100 nm and an AlGaN layer 23 having a thickness of 1 μm are formed on a silicon substrate 21 by MOCVD (metal organic chemical vapor deposition). Grow. Subsequently, an i-type GaN electron transit layer 24 having a thickness of 3 μm, an n-type AlGaN electron supply layer 25 having a thickness of 25 nm and an Si doping concentration of 2 × 10 ¹⁸ cm ⁻³ , and an i-type having a thickness of 5 nm. A GaN surface protective layer 26 is sequentially deposited. The composition of each AlGaN layer is Al _0.25 Ga _0.75 N.

Next, as shown in FIG. 3B, a Si ₃ N ₄ film 27 having a thickness of 100 nm is deposited on the entire surface by plasma CVD. Next, as shown in FIG. 3C, the Si ₃ N ₄ film 27 in the gate formation region is selectively removed to form an opening 28 to expose the i-type GaN surface protective layer 26.

Next, as shown in FIG. 4D, a Si ₃ N ₄ film 29 having a thickness of 50 nm is deposited again using a plasma CVD method as a gate insulating film. Next, as shown in FIG. 4E, after a TiN film is provided on the entire surface by reactive sputtering, a gate electrode 30 having a shape covering the opening 28 is formed by dry etching. TiN may be replaced with another refractory metal such as TaN. Next, as shown in FIG. 4F, a SiO ₂ film 31 is deposited on the entire surface by plasma CVD.

Next, as shown in FIG. 5G, the contact hole 32 is formed by etching the SiO ₂ film 31 to the Si ₃ N ₄ film 27. In this case, dry etching may be used, or wet etching with hydrogen fluoride or phosphoric acid may be used. Here, all of the exposed i-type GaN surface protective layer 26 is removed and a part of the n-type AlGaN layer electron supply layer 25 is also removed.

Next, as shown in FIG. 5H, the SiO ₂ film 33 is again deposited on the entire surface by using the plasma CVD method. Next, as shown in FIG. 6 (i), etching back is performed by anisotropic dry etching to leave the SiO ₂ film 33 on the side wall surface of the contact hole 32 to form the side wall 34.

  Next, as shown in FIG. 6J, after depositing an Al film on the entire surface by sputtering, the source electrode 35 and the drain electrode 36 are formed by dry etching using the resist pattern as a mask. Next, annealing is performed to make the source electrode 35 and the drain electrode 36 ohmic contact.

Next, as shown in FIG. 7 (k), the basic structure of the GaN-based HEMT according to the first embodiment of the present invention is completed by depositing the SiO ₂ film using the plasma CVD method to form the passivation film 37. In the case of integration, etching may be performed to the depth of the i-type GaN electron transit layer 24 for element isolation, or by ion implantation to the depth of the i-type GaN electron transit layer 24, Crystals may be destroyed.

As described above, in Example 1 of the present invention, the laminated interface of the Si ₃ N ₄ film / SiO ₂ film exposed on the side wall surface of the contact hole is covered with the SiO ₂ film having a wider band gap than Si ₃ N ₄ . Therefore, the drain breakdown voltage is improved. As a result, there is no need to expand the space between the gate electrode and the drain electrode, so that an increase in element size can be avoided.

  Next, the manufacturing process of the GaN-based HEMT according to the second embodiment of the present invention will be described with reference to FIGS. 8 to 10. However, the process until the contact hole is formed is the same as the first embodiment. The illustration up to the step of forming the contact hole is omitted.

Similar to the first embodiment, first, an AlN buffer layer 22 having a thickness of 100 nm and an AlGaN layer 23 having a thickness of 1 μm are grown on the silicon substrate 21 by MOCVD. Subsequently, an i-type GaN electron transit layer 24 having a thickness of 3 μm, an n-type AlGaN electron supply layer 25 having a thickness of 25 nm and an Si doping concentration of 2 × 10 ¹⁸ cm ⁻³ , and an i-type having a thickness of 5 nm. A GaN surface protective layer 26 is sequentially deposited. The composition of each AlGaN layer is Al _0.25 Ga _0.75 N.

Next, a Si ₃ N ₄ film 27 having a thickness of 100 nm is deposited on the entire surface by plasma CVD. Next, the Si ₃ N ₄ film 27 in the gate formation region is selectively removed to form an opening, and the i-type GaN surface protective layer 26 is exposed. Next, a Si ₃ N ₄ film 29 having a thickness of 50 nm is deposited again using a plasma CVD method as a gate insulating film.

Next, after a TiN film is provided on the entire surface by reactive sputtering, a gate electrode 30 having a shape covering the opening is formed by dry etching. Next, a SiO ₂ film 31 is deposited on the entire surface by plasma CVD. Next, the contact hole 32 is formed by etching the SiO ₂ film 31 to the Si ₃ N ₄ film 27, thereby obtaining the configuration of FIG.

  Next, as shown in FIG. 8B, an AlN insulating film 38 having a thickness of 50 nm is formed on the entire surface by using the ALD method. Next, as shown in FIG. 9C, the AlN insulating film 38 is selectively etched to expose the bottom of the contact hole 32. At this time, dry etching may be used, or wet etching with a sulfuric acid / hydrogen peroxide mixture may be used.

Next, as shown in FIG. 9D, after depositing an Al film on the entire surface by sputtering, the source electrode 35 and the drain electrode 36 are formed by dry etching using the resist pattern as a mask. Next, as shown in FIG. 10E, the basic structure of the GaN-based HEMT according to the second embodiment of the present invention is completed by depositing the SiO ₂ film using the plasma CVD method to form the passivation film 37.

  As described above, in Example 2 of the present invention, the side wall surface of the contact hole is covered with the same nitride insulating film, so that the withstand voltage can be reliably improved. In order to use AlN, the ALD method is necessary. However, since the film covering the side wall surface of the contact hole may be a thin film, the film formation rate is not a problem.

  Next, the manufacturing process of the GaN-based HEMT according to the third embodiment of the present invention will be described with reference to FIGS. 11 to 13. However, the process up to the step of forming the contact hole is the same as the first embodiment. The illustration up to the step of forming the contact hole is omitted.

Similar to the first embodiment, first, an AlN buffer layer 22 having a thickness of 100 nm and an AlGaN layer 23 having a thickness of 1 μm are grown on the silicon substrate 21 by MOCVD. Subsequently, an i-type GaN electron transit layer 24 having a thickness of 3 μm, an n-type AlGaN electron supply layer 25 having a thickness of 25 nm and an Si doping concentration of 2 × 10 ¹⁸ cm ⁻³ , and an i-type having a thickness of 5 nm. A GaN surface protective layer 26 is sequentially deposited. The composition of each AlGaN layer is Al _0.25 Ga _0.75 N.

Next, a Si ₃ N ₄ film 27 having a thickness of 100 nm is deposited on the entire surface by plasma CVD. Next, the Si ₃ N ₄ film 27 in the gate formation region is selectively removed to form an opening, and the i-type GaN surface protective layer 26 is exposed. Next, a Si ₃ N ₄ film 29 having a thickness of 50 nm is deposited again using a plasma CVD method as a gate insulating film.

Next, after a TiN film is provided on the entire surface by reactive sputtering, a gate electrode 30 having a shape covering the opening is formed by dry etching. Next, a SiO ₂ film 31 is deposited on the entire surface by plasma CVD. Next, the contact hole 32 is formed by etching the SiO ₂ film 31 to the Si ₃ N ₄ film 27, whereby the configuration of FIG. 11A is obtained.

  Next, as shown in FIG. 11B, a photoresist is applied to the entire surface, then exposed so as to remain only in the central portion of the bottom surface of the contact hole 32, and developed to form a resist pattern 39. .

  Next, as shown in FIG. 12C, an AlN insulating film 38 having a thickness of 50 nm is formed on the entire surface by using the ALD method. Next, as shown in FIG. 12D, by removing the resist pattern 39, the AlN insulating film 38 deposited thereon is lifted off, and the bottom of the contact hole 32 is exposed.

Next, as shown in FIG. 13E, after depositing an Al film on the entire surface by sputtering, the source electrode 35 and the drain electrode 36 are formed by dry etching using the resist pattern as a mask. Next, as shown in FIG. 13F, the basic structure of the GaN-based HEMT according to the third embodiment of the present invention is completed by depositing a SiO ₂ film using the plasma CVD method to form the passivation film 37.

  As described above, in the third embodiment of the present invention, the bottom surface of the contact hole is exposed using the lift-off method, and the etching process of the AlN insulating film is not required, so that the exposed portion of the contact hole is controlled with good reproducibility. can do. In this case, the ALD method is necessary to use AlN. However, since the film covering the side wall surface of the contact hole may be a thin film, the slow deposition rate is not a problem.

Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 3.
(Supplementary Note 1) A gallium nitride carrier running layer, a gallium nitride carrier supply layer, a gallium nitride surface protective layer, and a silicon nitride film and a silicon oxide film sequentially stacked on the gallium nitride surface protective layer And a wide forbidden band width insulating film having a wider band gap than silicon nitride covering the side wall surfaces of the contact holes for the source electrode and the drain electrode provided in the silicon nitride film and the silicon oxide film, Field effect type compound semiconductor device.
(Supplementary note 2) The field effect type compound semiconductor device according to supplementary note 1, wherein the wide forbidden band width insulating film is either a silicon oxide film or an aluminum nitride film.
(Additional remark 3) The silicon nitride film laminated | stacked in order on the said gallium nitride type surface protective layer is the 1st silicon nitride film from which the gate electrode formation part was missing, and the 2nd silicon nitride film used as a gate insulating film The field effect type compound semiconductor device according to appendix 1 or appendix 2, wherein
(Supplementary note 4) The field-effect compound semiconductor according to any one of supplementary notes 1 to 3, wherein an interval between the gate electrode and the source electrode is equal to an interval between the gate electrode and the drain electrode. apparatus.
(Supplementary note 5) The field effect compound semiconductor device according to any one of supplementary notes 1 to 4, wherein the silicon nitride film is a Si ₃ N ₄ film and the silicon oxide film is a SiO ₂ film. .
(Appendix 6) A step of sequentially laminating a gallium nitride based carrier running layer, a gallium nitride based carrier supply layer and a gallium nitride based surface protective layer on a substrate, and a first silicon nitride film on the gallium nitride based surface protective layer A step of selectively removing the first silicon nitride film in the gate electrode formation portion, a step of forming a second silicon nitride film to be a gate insulating film on the entire surface, and the gate electrode A step of forming a gate electrode in the formation portion, a step of forming a silicon oxide film on the entire surface, and a source electrode and drain electrode formation portion, the silicon oxide film, the second silicon nitride film, and the first nitride A step of selectively removing the silicon film to form a contact hole; and a side band of the contact hole having a wider band gap than silicon nitride. A step of coating with a film, in the contact hole, a method of manufacturing a field effect type compound semiconductor device, characterized by a step of forming a source electrode and a drain electrode so as to contact with the wide bandgap insulating film.
(Supplementary note 7) The step of covering the side wall surface of the contact hole with a wide forbidden band width insulating film having a wider band gap than silicon nitride, the step of forming a silicon oxide film on the entire surface, and the anisotropy of the silicon oxide film The method of manufacturing a field effect type compound semiconductor device according to appendix 6, further comprising a step of remaining on at least a side wall surface of the contact hole by etching.
(Appendix 8) The step of coating the sidewall surface of the contact hole with a wide forbidden band width insulating film having a wider band gap than silicon nitride includes depositing an aluminum nitride film over the entire surface using an atomic layer deposition method, The method for manufacturing a field effect compound semiconductor device according to appendix 6, further comprising: etching away at least a part of the aluminum nitride film deposited on the bottom surface of the contact hole.
(Supplementary Note 9) The step of covering the side wall surface of the contact hole with a wide forbidden band width insulating film having a wider band gap than silicon nitride does not cover the side wall surface of the contact hole on at least a part of the bottom surface of the contact hole. The method of claim 6, further comprising: providing a lift-off mask on the substrate; depositing an aluminum nitride film over the entire surface using an atomic layer deposition method; and removing the lift-off mask. Manufacturing method of effect type compound semiconductor device.
(Appendix 10) The appendix 6 to appendix 9, wherein the first and second silicon nitride films are Si ₃ N ₄ films, and the silicon oxide film is a SiO ₂ film. Manufacturing method of field effect type compound semiconductor device.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 AlGaN layer 4 GaN-based carrier running layer 5 GaN-based carrier supply layer 6 GaN-based surface protective layer 7, 8 Si ₃ N ₄ film 9 Gate electrode 10 SiO ₂ film 11 Wide forbidden band width insulating film 12 Source Electrode 13 Drain electrode 21 Silicon substrate 22 AlN buffer layer 23 AlGaN layer 24 i-type GaN electron transit layer 25 n-type AlGaN electron supply layer 26 i-type GaN surface protective layer 27, 29 Si ₃ N ₄ film 28 Opening 30 Gate electrode 31 SiO ₂ film 32 Contact hole 33 SiO ₂ film 34 Side wall 35 Source electrode 36 Drain electrode 37 Passivation film 38 AlN insulating film 39 Resist pattern 51 Silicon substrate 52 AlN buffer layer 53 AlGaN layer 54 i-type GaN electron transit layer 55 n-type AlGaN Electron supply layer 56 i-type G N surface protective layer 57, 58 _Si 3 _{N 4} film 59 gate electrode 60 SiO ₂ film 61 source electrode 62 drain electrode

Claims (3)

A step of sequentially laminating a gallium nitride based carrier running layer, a gallium nitride based carrier supply layer, and a gallium nitride based surface protection layer on a substrate;
Forming a first silicon nitride film on the gallium nitride-based surface protective layer;
Selectively removing the first silicon nitride film in a gate electrode formation portion;
Forming a second silicon nitride film to be a gate insulating film on the entire surface;
Forming a gate electrode in the gate electrode formation portion;
Forming a silicon oxide film on the entire surface;
Forming a contact hole by selectively removing the silicon oxide film, the second silicon nitride film, and the first silicon nitride film in a source electrode and drain electrode formation portion;
Coating the side wall surface of the contact hole with a wide band gap insulating film having a wider band gap than silicon nitride;
Forming a source electrode and a drain electrode so as to be in contact with the wide forbidden band width insulating film in the contact hole. The step of coating the side wall surface of the contact hole with a wide band gap insulating film having a wider band gap than silicon nitride,
Forming a silicon oxide film on the entire surface;
The method of manufacturing a field effect compound semiconductor device according to claim 1 , further comprising a step of leaving the silicon oxide film at least on a side wall surface of the contact hole by anisotropic etching. The step of coating the side wall surface of the contact hole with a wide band gap insulating film having a wider band gap than silicon nitride,
Depositing an aluminum nitride film over the entire surface using an atomic layer deposition method;
The method of manufacturing a field effect type compound semiconductor device according to claim 1 , further comprising: etching away at least a part of the aluminum nitride film deposited on the bottom surface of the contact hole.

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