JP6198461B2 - Power supply device, control circuit, and control method - Google Patents

Description

  The present invention relates to a power supply device, a control circuit, and a control method.

  Electronic devices such as personal computers and mobile phones have a built-in switching power supply circuit (DC-DC converter) that supplies a drive voltage to an internal circuit that performs signal processing. The switching power supply circuit converts a DC voltage supplied from, for example, an AC adapter or a battery into a driving voltage suitable for the operation of the internal circuit. For example, the switching power supply circuit controls on / off of the main switch to boost and step down the DC input voltage to generate a DC output voltage, and feed back the DC output voltage supplied to the load to a constant target voltage. Control is in progress.

  Incidentally, in recent years, with the widespread use of portable electronic devices such as notebook personal computers and mobile phones, there is an increasing demand for miniaturization of the switching power supply circuit. Therefore, in order to meet such a demand, a single inductor multiple output (SIMO) DC-DC converter capable of obtaining a plurality of outputs with one inductor (coil) has been proposed (for example, , See Patent Document 1). For example, in a power supply that requires a power supply for the back gate of a MOS transistor to reduce leakage current, a single inductor multi-output type DC-DC converter that can obtain a step-down output and an inverted output with one coil is used. To be considered. If this type of DC-DC converter can be used, since a single coil is shared by a plurality of outputs, an increase in the number of parts and an increase in circuit area due to an increase in the number of outputs can be suppressed.

FIG. 10 shows an example of an output unit of a single inductor multi-output DC-DC converter 100 that can obtain a step-down output and an inverted output with one coil.
The switch circuit SW11 has a first terminal connected to the input terminal Pi to which the input voltage Vin is supplied, and a second terminal connected to the first terminal of the coil L11. A cathode of a diode D11 is connected to a node N11 to which the switch circuit SW11 and the coil L11 are connected. The anode of the diode D11 is connected to an output terminal Po12 that generates an output voltage Vout2 obtained by inverting the input voltage Vin. The node N11 is connected to the cathode of a diode D12, and the anode of the diode D12 is connected to the first terminal of the switch circuit SW12. A second terminal of the switch circuit SW12 is connected to the ground GND. On the other hand, the first terminal of the switch circuit SW13 is connected to the second terminal of the coil L11, and the second terminal of the switch circuit SW13 is connected to the ground GND. The anode of the diode D13 is connected to the second terminal of the coil L11. The cathode of the diode D13 is connected to an output terminal Po11 that generates an output voltage Vout1 lower than the input voltage Vin. Then, an output voltage Vout1 and an output current Iout1 that are voltages across the capacitor C11 are supplied from the output terminal Po11 to the load 2A. Further, an output voltage Vout2 and an output current Iout2 that are voltages across the capacitor C12 are supplied from the output terminal Po12 to the load 3A.

  Such a DC-DC converter 100 operates as a step-up / step-down converter by switching on / off the switch circuits SW11 and SW13 when the switch circuit SW12 for switching between the step-up / step-down mode and the inversion mode is in an on state. On the other hand, the DC-DC converter 100 operates as an inverting converter when the switch circuits SW11 and SW13 are controlled on and off when the switch circuit SW12 is in the off state.

JP 2003-319647 A

  However, in the DC-DC converter 100, a loss occurs due to the on-resistance of the switch circuit SW13 connected to the second terminal (output side terminal) of the coil L11 and the diode D13, so that the power conversion efficiency deteriorates.

  According to one aspect of the present invention, a coil having a first terminal and a second terminal connected to a first output terminal that outputs a first output voltage lower than the input voltage, and the first terminal of the coil And a first switch circuit provided between the input terminal to which the input voltage is supplied, a first switch circuit provided between the first terminal of the coil and a power supply line having a potential lower than the input voltage. A second switch circuit, a third switch circuit provided between a first terminal of the coil and a second output terminal from which a second output voltage obtained by inverting the input voltage is output; and the first output voltage A control unit that generates a first control signal based on the second output voltage and generates a second control signal based on the second output voltage, and the control unit includes the first control signal and the second control signal. Based on the first switch circuit, the second switch circuit, and the third switch circuit. Tsu to control on and off the switch circuit.

  According to one aspect of the present invention, there is an effect that power conversion efficiency can be improved.

The circuit diagram which shows the DC-DC converter of 1st Embodiment. The wave form diagram which shows the operation | movement of the DC-DC converter of 1st Embodiment. (A)-(c) is explanatory drawing which shows operation | movement of the DC-DC converter of 1st Embodiment. (A), (b) is a wave form diagram which shows operation | movement of the DC-DC converter of 1st Embodiment. The block circuit diagram which shows the DC-DC converter of 2nd Embodiment. The circuit diagram which shows the example of an internal structure of a detection circuit. Explanatory drawing which shows operation | movement of the DC-DC converter of 2nd Embodiment. Explanatory drawing which shows operation | movement of the DC-DC converter of 2nd Embodiment. The wave form diagram which shows the operation | movement of a detection circuit. The block circuit diagram which shows the output part of the conventional DC-DC converter.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the DC-DC converter 1 is a single inductor multi-output type DC-DC converter that generates a large number of output voltages Vo1, Vo2 with one inductor (coil) L1. The DC-DC converter 1 generates an output voltage Vo1 lower than the input voltage Vin and an output voltage Vo2 that is an inverted voltage of the input voltage Vin based on the input voltage Vin supplied to the input terminal Pi. It is a DC-DC converter. That is, the output voltage Vo1 is a step-down output, and the output voltage Vo2 is an inverted output. The output voltage Vo1 is supplied to the load 2 connected to the output terminal Po1, and the output voltage Vo2 is supplied to the load 3 connected to the output terminal Po2. The loads 2 and 3 are connected to a power supply line (here, ground GND) having a potential lower than the input voltage Vin. Here, examples of the loads 2 and 3 are built in an internal circuit of a portable electronic device (personal computer, mobile phone, game device, digital camera, etc.) and other electronic devices, or a notebook personal computer. Examples include rechargeable batteries such as lithium batteries. The magnitude relationship among the input voltage Vin, the ground GND potential, and the output voltages Vo1 and Vo2 in this example is Vo2 <GND <Vo1 <Vin.

The DC-DC converter 1 includes an output unit including a switch circuit group 10, a coil L1, a capacitor C1, and a capacitor C2, and a control unit 11 that controls the output unit.
The switch circuit group 10 includes three switch circuits SW1, SW2, and SW3. For example, the switch circuit SW1 is a P-channel MOS transistor, and the switch circuits SW2 and SW3 are N-channel MOS transistors.

  A first terminal (for example, a source terminal) of the switch circuit SW1 is connected to an input terminal Pi to which an input voltage Vin is supplied. The second terminal (for example, drain terminal) of the switch circuit SW1 is connected to the first terminal (for example, drain terminal) of the switch circuit SW2, and the second terminal (for example, source terminal) of the switch circuit SW2 is connected to the ground GND. Has been.

  A node N1 between the switch circuit SW1 and the switch circuit SW2 is connected to a first terminal (for example, a drain terminal) of the switch circuit SW3. A second terminal (for example, a source terminal) of the switch circuit SW3 is connected to the output terminal Po2. The output terminal Po2 is connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is connected to the ground GND. Then, an output voltage Vo2 that is a voltage across the capacitor C2 is supplied to the load 3 from the output terminal Po2. The capacitor C2 is included in a smoothing circuit that smoothes the output voltage Vo2.

  The node N1 to which the second terminal of the switch circuit SW1 and the first terminals of the switch circuits SW2 and SW3 are connected is connected to the first terminal of the coil L1. The second terminal of the coil L1 is connected to the output terminal Po1. The output terminal Po1 is connected to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is connected to the ground GND. Then, an output voltage Vo1 that is a voltage across the capacitor C1 is supplied to the load 2 from the output terminal Po1. The capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo1.

  A control signal SG1 is supplied from the control unit 11 to a control terminal (for example, a gate terminal) of the switch circuit SW1. A control signal SG2 is supplied from the control unit 11 to a control terminal (for example, a gate terminal) of the switch circuit SW2. A control signal SG3 is supplied from the control unit 11 to a control terminal (for example, a gate terminal) of the switch circuit SW3. The switch circuits SW1, SW2, SW3 are turned on / off in response to the control signals SG1, SG2, SG3, respectively. Then, the output voltage Vo1 and the output current Io1 are output from the output terminal Po1 via the switch circuit SW1 or the switch circuit SW2 and the coil L1, and the output voltage Vo2 and the output current Io2 are output from the output terminal Po2 via the switch circuit SW3. The These output terminals Po1 and Po2 are connected to the control unit 11.

The control unit 11 includes a first control unit 20, a second control unit 30, an oscillator 40, a logic circuit 50, and a drive circuit 60.
The first control unit 20 is connected to an output terminal Po1, and is supplied with an output voltage Vo1 generated at the output terminal Po1. The first control unit 20 generates the PWM signal S2 based on the output voltage Vo1. The first control unit 20 generates a PWM signal S2 that performs on / off control of the switch circuits SW1 to SW3 so that the output voltage Vo1 approaches the target value. For example, the first control unit 20 adjusts the ON time of the switch circuit SW1 so that desired power is supplied to the load 2 based on the output voltage Vo1. Specifically, the first control unit 20 generates a PWM signal S <b> 2 having a constant frequency (period) and a pulse width that varies according to the power supplied to the load 2.

The first control unit 20 includes a feedback voltage generation circuit 21, an error amplification circuit 22, and a PWM comparison circuit 23.
The feedback voltage generation circuit 21 generates a feedback voltage VFB1 corresponding to the output voltage Vo1. The feedback voltage generation circuit 21 has resistors R1 and R2. Specifically, the output terminal Po1 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R1 is connected to the first terminal of the resistor R2. The second terminal of the resistor R2 is connected to the ground GND. A node N2 between the resistors R1 and R2 is connected to the inverting input terminal of the error amplifier circuit 22. Here, the resistors R1 and R2 generate a feedback voltage VFB1 obtained by dividing the output voltage Vo1 at the node N2 according to the respective resistance values. The value of the feedback voltage VFB1 corresponds to the ratio of the resistance values of the resistors R1 and R2 and the potential difference between the output voltage Vo1 and the ground GND. Therefore, the resistors R1 and R2 generate a feedback voltage VFB1 that is proportional to the output voltage Vo1. The feedback voltage VFB1 is supplied to the inverting input terminal of the error amplifier circuit 22.

  A reference voltage Vr generated by the reference power supply E1 is supplied to the non-inverting input terminal of the error amplifier circuit 22. The error amplifier circuit 22 compares the feedback voltage VFB1 with the reference voltage Vr, and outputs an error signal S1 obtained by amplifying the difference voltage between the two voltages to the PWM comparator circuit 23.

  The error signal S <b> 1 is supplied from the error amplifier circuit 22 to the non-inverting input terminal of the PWM comparison circuit 23. A periodic signal CK having a predetermined period T (first period) is supplied from the oscillator 40 to the inverting input terminal of the PWM comparison circuit 23. The periodic signal CK is, for example, a sawtooth wave signal (a sawtooth waveform signal that rises from a reference value with a predetermined rising characteristic and rapidly drops to a reference value upon reset).

  The PWM comparison circuit 23 compares the error signal S1 with the periodic signal CK. When the level of the periodic signal CK is higher than that of the error signal S1, the PWM comparison circuit 23 generates the PWM signal S2 of L level (for example, the ground GND level), and the level of the periodic signal CK is higher than that of the error signal S1. When it becomes low, a PWM signal S2 of H level (for example, input voltage Vin level) is generated. The PWM signal S2 has the same cycle as the cycle T. Then, the PWM signal S <b> 2 is supplied to the logic circuit 50.

  An output terminal Po2 is connected to the second control unit 30, and an output voltage Vo2 generated at the output terminal Po2 is supplied. The second control unit 30 generates the PWM signal S4 based on the output voltage Vo2. The second control unit 30 generates a PWM signal S4 that performs on / off control of the switch circuits SW1 to SW3 so that the output voltage Vo2 approaches the target value. For example, the second control unit 30 adjusts the ON time of the switch circuit SW3 so that desired power is supplied to the load 3 based on the output voltage Vo2. Specifically, the second control unit 30 generates a PWM signal S4 having a constant frequency (period) and a pulse width that varies according to the power supplied to the load 3.

The second control unit 30 includes a feedback voltage generation circuit 31, an error amplification circuit 32, and a PWM comparison circuit 33.
The feedback voltage generation circuit 31 generates a feedback voltage VFB2 corresponding to the output voltage Vo2. The feedback voltage generation circuit 31 has resistors R3 and R4. Specifically, the output terminal Po2 is connected to the first terminal of the resistor R3, and the second terminal of the resistor R3 is connected to the first terminal of the resistor R4. The second terminal of the resistor R4 is connected to the plus side terminal of the reference power supply E1. A node N3 between the resistors R3 and R4 is connected to the inverting input terminal of the error amplifier circuit 32. Here, the resistors R3 and R4 generate a feedback voltage VFB2 obtained by dividing the output voltage Vo2 at the node N3 according to the respective resistance values. The value of the feedback voltage VFB2 corresponds to the ratio between the resistance values of the resistors R3 and R4 and the potential difference between the output voltage Vo2 and the reference voltage Vr generated by the reference power supply E1. The feedback voltage VFB2 is supplied to the non-inverting input terminal of the error amplifier circuit 22.

  The ground GND is connected to the non-inverting input terminal of the error amplifier circuit 32. The error amplification circuit 32 compares the feedback voltage VFB2 with the ground potential, and outputs an error signal S3 obtained by amplifying the difference voltage between the two voltages to the PWM comparison circuit 33.

  The error signal S3 is supplied from the error amplification circuit 32 to the non-inverting input terminal of the PWM comparison circuit 33. The periodic signal CK is supplied from the oscillator 40 to the inverting input terminal of the PWM comparison circuit 33.

  The PWM comparison circuit 33 compares the error signal S3 with the periodic signal CK. The PWM comparison circuit 33 generates an L level PWM signal S4 when the level of the periodic signal CK is higher than the error signal S3, and when the level of the periodic signal CK is lower than the error signal S3, A signal S4 is generated. The PWM signal S4 has the same cycle (frequency) as the PWM signal S2. That is, the PWM signal S4 has the same cycle as the cycle T. Furthermore, the PWM signal S4 is a signal synchronized with the PWM signal S2. Then, the PWM signal S4 is supplied to the logic circuit 50.

  The logic circuit 50 includes inverter circuits 51 and 52 and NOR circuits 53 and 54. The drive circuit 60 includes an OR circuit 61, inverter circuits 62 and 63, AND circuits 64 and 65, and driver circuits 66 to 68. The OR circuit 61, the inverter circuits 62 and 63, and the AND circuits 64 and 65 function as an anti-shoot-through circuit (AST).

  The PWM signal S2 is supplied to the inverter circuit 51 and the NOR circuits 53 and 54. The inverter circuit 51 outputs an output signal S5 obtained by logically inverting the PWM signal S2 to the OR circuit 61 in the drive circuit 60. The NOR circuit 53 outputs an output signal S6 having a result obtained by performing a NOR operation on the PWM signal S2 and the PWM signal S4 to the AND circuit 64 in the drive circuit 60.

  The inverter circuit 52 outputs an output signal obtained by logically inverting the PWM signal S4 to the NOR circuit 54. The NOR circuit 54 outputs to the AND circuit 65 in the drive circuit 60 an output signal S7 having a result obtained by performing a negative OR operation on the PWM signal S2 and the output signal of the inverter circuit 52.

  In such a logic circuit 50, L level output signals S5 to S7 are generated in response to the H level PWM signal S2, regardless of the signal level of the PWM signal S4. Further, in the logic circuit 50, when an L level PWM signal S2 is input, an H level output signal S5 is generated in response to the PWM signal S2, and an output signal S6 which is an inverted level of the PWM signal S4. Is generated, and an output signal S7 having a signal level equivalent to that of the PWM signal S4 is generated. For example, in the logic circuit 50 to which the L level PWM signal S2 is input, the L level output signal S6 and the H level output signal S7 are generated in response to the H level PWM signal S4, and the L level PWM signal S4 is generated. In response to this, an H level output signal S6 and an L level output signal S7 are generated.

  The driver circuits 66, 67, 68 in the drive circuit 60 output control signals SG1, SG2, SG3, respectively. The OR circuit 61 is supplied with the output signal S5 of the inverter circuit 51, the control signal SG2, and the control signal SG3. The OR circuit 61 outputs to the driver circuit 66 an output signal S8 having a result obtained by performing an OR operation on the output signal S5, the control signal SG2, and the control signal SG3.

  The output terminal of the driver circuit 66 is connected to the control terminal of the switch circuit SW1. For example, the driver circuit 66 outputs a control signal SG1 of H level (for example, input voltage Vin level) to the switch circuit SW1 in response to the output signal S8 of H level (for example, input voltage Vin level). The driver circuit 66 outputs a control signal SG1 of L level (for example, ground GND level) to the switch circuit SW1 in response to the output signal S8 of L level (for example, ground GND level). The switch circuit SW1 is turned on in response to the L level control signal SG1, and turned off in response to the H level control signal SG1.

  The AND circuit 64 is supplied with the output signal S6 of the NOR circuit 53 and the control signal SG1, and is also supplied with the control signal SG3 via the inverter circuit 62. The AND circuit 64 outputs to the driver circuit 67 an output signal S9 having a result obtained by ANDing the output signal S6, the control signal SG1, and the output signal of the inverter circuit 62 (inverted signal of the control signal SG1).

  The output terminal of the driver circuit 67 is connected to the control terminal of the switch circuit SW2. For example, the driver circuit 67 outputs a control signal SG2 of H level (for example, input voltage Vin level) to the switch circuit SW2 in response to the output signal S9 of H level (for example, input voltage Vin level). In addition, the driver circuit 67 outputs an L level (for example, ground GND level) control signal SG2 to the switch circuit SW2 in response to an L level (for example, ground GND level) output signal S9. The switch circuit SW2 is turned on in response to the H level control signal SG2, and turned off in response to the L level control signal SG2.

  The AND circuit 65 is supplied with the output signal S7 of the NOR circuit 54 and the control signal SG1, and also supplied with the control signal SG2 via the inverter circuit 63. The AND circuit 65 outputs to the driver circuit 68 an output signal S10 having a result obtained by ANDing the output signal S7, the control signal SG1, and the output signal of the inverter circuit 63 (inverted signal of the control signal SG2).

  The output terminal of the driver circuit 68 is connected to the control terminal of the switch circuit SW3. For example, the driver circuit 68 outputs a control signal SG3 of H level (for example, input voltage Vin level) to the switch circuit SW3 in response to an output signal S10 of H level (for example, input voltage Vin level). Further, the driver circuit 68 outputs an L level (for example, ground GND level) control signal SG3 to the switch circuit SW3 in response to an L level (for example, ground GND level) output signal S10. The switch circuit SW3 is turned on in response to the H level control signal SG3 and turned off in response to the L level control signal SG3.

  In such a drive circuit 60, an L level control signal SG1 for turning on the switch circuit SW1 is generated in response to the L level output signal S5, and the switch circuit SW1 is turned off in response to the H level output signal S5. An H level control signal SG1 is generated. The drive circuit 60 generates an H level control signal SG2 that turns on the switch circuit SW2 in response to the H level output signal S6, and turns off the switch circuit SW2 in response to the L level output signal S6. A level control signal SG2 is generated. In the drive circuit 60, an H level control signal SG3 for turning on the switch circuit SW3 is generated in response to the H level output signal S7, and an L level for turning off the switch circuit SW3 in response to the L level output signal S7. A level control signal SG3 is generated. However, when either one of the control signals SG2 and SG3 is at the H level, that is, when one of the switch circuits SW2 and SW3 is in the ON state, the drive circuit 60 has the output signal S5 at the L level. However, the control signal SG1 at H level for turning off the switch circuit SW1 is generated. Further, when the control signal SG1 is at the L level or the control signal SG3 is at the H level, that is, when one of the switch circuits SW1 and SW3 is in the ON state, the drive circuit 60 has the output signal S6 at the H level. Even if it exists, the L level control signal SG2 for turning off the switch circuit SW2 is generated. Further, when the control signal SG1 is at the L level or the control signal SG2 is at the H level, that is, when one of the switch circuits SW1 and SW2 is in the ON state, the drive circuit 60 has the output signal S7 at the H level. Even if it exists, the L-level control signal SG3 for turning off the switch circuit SW3 is generated. As described above, the drive circuit 60 generates the control signals SG1 to SG3 so that two or more of the switch circuits SW1 to SW3 are not turned on at the same time.

  In this embodiment, the DC-DC converter 1 is an example of a power supply device and a power supply, the control unit 11 is an example of a control unit and a control circuit, the switch circuit SW1 is an example of a first switch circuit, and the switch circuit SW2 is a second switch. An example of the circuit, the switch circuit SW3, is an example of the third switch circuit. The output terminal Po1 is an example of the first output terminal, the output terminal Po2 is an example of the second output terminal, the ground GND is an example of the power supply line, the PWM signal S2 is an example of the first control signal, and the PWM signal S4 is the second control signal. For example, the output voltage Vo1 is an example of a first output voltage, and the output voltage Vo2 is an example of a second output voltage.

  Next, the operation of the DC-DC converter 1 will be described with reference to FIGS. 2 and 4, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  When the periodic signal CK is reset to the reference value at a constant period T at time t1 shown in FIG. 2, the level of the periodic signal CK becomes lower than the error signals S1 and S3. Then, the PWM comparison circuit 23 outputs an H level PWM signal S2, and the PWM comparison circuit 33 outputs an H level PWM signal S4. In response to the H level PWM signal S2, L level output signals S5 to S7 are generated, and L level control signals SG1 to SG3 are generated. In response to these L level control signals SG1 to SG3, the switch circuit SW1 is turned on and the switch circuits SW2 and SW3 are turned off.

  Then, as shown in FIG. 3A, the first terminal of the coil L1 is connected to the input terminal Pi through the switch circuit SW1, and the second terminal of the coil L1 is connected to the output terminal Po1. That is, the input terminal Pi and the output terminal Po1 are connected via the coil L1. For this reason, a current path from the input terminal Pi to the output terminal Po1 through the coil L1 is formed. During this connection state, specifically, in the first period P1 from time t1 to time t2 in FIG. 2, the coil current IL corresponding to the potential difference between the input voltage Vin and the output voltage Vo1 flows to the coil L1, and the coil Energy is stored in L1. In the first period P1, the coil current IL increases with a predetermined slope as time passes. Specifically, the increasing slope m1 of the coil current IL in the first period P1 is that the voltage values of the input voltage Vin and the output voltage Vo1 are Vin and Vo1, respectively, and the inductance value of the coil L1 is L1.

It becomes. That is, the coil current IL in the first period P1 increases in proportion to the potential difference between the input voltage Vin and the output voltage Vo1.

  Next, when the level of the periodic signal CK that gradually increases with a predetermined rising characteristic from time t1 becomes higher than the error signal S1 (see time t2), the PWM signal S2 output from the PWM comparison circuit 23 changes from H level to L. Transition to level. In response to the L level PWM signal S2 and the H level PWM signal S4, an H level output signal S5, an L level output signal S6, and an H level output signal S7 are generated. In response to these output signals S5 to S7, an H level control signal SG1, an L level control signal SG2, and an H level control signal SG3 are generated. Then, the switch circuits SW1 and SW2 are turned off in response to the H level control signal SG1 and the L level control signal SG2, respectively, and the switch circuit SW3 is turned on in response to the H level control signal SG3.

  Then, as shown in FIG. 3B, the first terminal of the coil L1 is connected to the output terminal Po2 through the switch circuit SW3, and the second terminal of the coil L1 is connected to the output terminal Po1. That is, the output terminal Po2 and the output terminal Po1 are connected via the coil L1. For this reason, a current path from the output terminal Po2 to the output terminal Po1 through the coil L1 is formed. During this connection state, specifically, in the second period P2 from time t2 to time t3 in FIG. 2, the coil current IL corresponding to the potential difference between the output voltage Vo1 and the output voltage Vo2 is applied to the two output terminals Po1, Supplied to Po2. At this time, since the coil current IL flows from the capacitor C2 toward the capacitor C1, the output voltage Vo2 becomes a negative power source. In the second period P2, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decrease slope m2 of the coil current IL in the second period P2 is expressed as follows when the voltage value of the output voltage Vo2 is Vo2.

It becomes. That is, the coil current IL in the second period P2 decreases in proportion to the potential difference between the output voltage Vo1 and the output voltage Vo2.

  Subsequently, when the level of the periodic signal CK becomes higher than the error signal S3 (see time t3), the PWM signal S4 output from the PWM comparison circuit 33 changes from the H level to the L level. In response to the L level PWM signal S4 and the L level PWM signal S2, an H level output signal S5, an H level output signal S6, and an L level output signal S7 are generated. In response to these output signals S5 to S7, an H level control signal SG1, an H level control signal SG2, and an L level control signal SG3 are generated. The switch circuits SW1 and SW3 are turned off in response to the H level control signal SG1 and the L level control signal SG3, respectively, and the switch circuit SW2 is turned on in response to the H level control signal SG2.

  Then, as shown in FIG. 3C, the first terminal of the coil L1 is connected to the ground GND through the switch circuit SW2, and the second terminal of the coil L1 is connected to the output terminal Po1. That is, the ground GND and the output terminal Po1 are connected via the coil L1. For this reason, a current path from the ground GND to the output terminal Po1 through the coil L1 is formed. During this connection state, specifically, in the third period P3 from time t3 to time t4 in FIG. 2, the energy stored in the coil L1 in the first period P1 is released toward the output terminal Po1. An induced current flows through the coil L1. In the third period P3, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decreasing slope m3 of the coil current IL in the third period P3 is

It becomes. That is, the coil current IL in the third period P3 decreases in proportion to the output voltage Vo1.

  Thereafter, when the periodic signal CK is reset to the reference value again at a constant period T (see time t4), the switch circuit SW1 is turned on and the switch circuits SW2 and SW3 are turned off. Thereby, the next period T is started, and in the period T, the first period P1, the second period P2, and the third period P3 are executed in this order.

  Here, the average value of the coil current IL in each cycle T (the first period P1 to the third period P3) is the output current Io1 supplied to the load 2. Further, an average value obtained by averaging the total amount of the coil current IL in the period T during which the switch circuit SW3 is on (second period P2) is the output current Io2 supplied to the load 3.

Next, feedback control by the first control unit 20 and the second control unit 30 will be described in detail. First, feedback control by the first control unit 20 will be described.
In the series of operations in each cycle T described above, when the output voltage Vo1 becomes higher than the target voltage, that is, when the feedback voltage VFB1 becomes higher than the reference voltage Vr, the error signal S1 output from the error amplifier circuit 22 decreases. Then, the H-level pulse width of the PWM signal S2 is shortened, and the L-level pulse width of the control signal SG1 is shortened. For this reason, the ON time of the switch circuit SW1, that is, the time width of the first period P1 in which energy is stored in the coil L1 is shortened. As a result, the amount of coil current IL flowing through the coil L1 in the first period P1 decreases, and the energy accumulated in the coil L1 decreases. Accordingly, the energy released from the coil L1 toward the output terminal Po1 in the second period P2 and the third period P3 decreases. Therefore, the amount of coil current IL supplied to the capacitor C1 decreases, and the output voltage Vo1 becomes low.

  On the other hand, when the output voltage Vo1 becomes lower than the target voltage, that is, when the feedback voltage VFB1 becomes lower than the reference voltage Vr, the error signal S1 output from the error amplifier circuit 22 increases. Then, the H-level pulse width of the PWM signal S2 becomes longer, and the time width of the first period P1 in which energy is stored in the coil L1 becomes longer. As a result, the amount of coil current IL flowing through the coil L1 in the first period P1 increases, and the energy accumulated in the coil L1 increases. Along with this, energy released from the coil L1 toward the output terminal Po1 in the second period P2 and the third period P3 increases. Therefore, since the amount of coil current IL supplied to the capacitor C1 increases, the output voltage Vo1 increases. By such an operation, the output voltage Vo1 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R1 and R2.

  As described above, in the first control unit 20, the ON time of the switch circuit SW1 is controlled based on the output voltage Vo1 so that the output voltage Vo1 approaches the target voltage based on the reference voltage Vr and the resistors R1 and R2. In other words, in the first control unit 20, each cycle T is set so that a desired current supplied to the load 2 in the second period P2 and the third period P3, that is, the output current Io1, flows based on the output voltage Vo1. The total amount of coil current IL at is controlled.

Next, feedback control by the second control unit 30 will be described.
In a series of operations in each cycle T, when the output voltage Vo2 becomes lower than the target voltage, that is, when the feedback voltage VFB2 becomes lower than the ground GND potential, the error signal S3 output from the error amplifier circuit 32 decreases. Then, the H-level pulse width of the PWM signal S4 is shortened, and the H-level pulse width of the control signal SG3 is shortened. Therefore, the time during which the switch circuit SW3 is turned on (the time width of the second period P2) is shortened. That is, the output terminal Po2 (capacitor C2) is connected to the output terminal Po1 (capacitor C1) through the coil L1, and the time during which the coil current IL is supplied from the output terminal Po2 (capacitor C2) to the output terminal Po1 is shortened. In other words, the time for discharging the charge from the capacitor C2 is shortened. As a result, the output voltage Vo2 (voltage lower than the ground GND), which is an inverted voltage of the input voltage Vin, increases.

  On the contrary, when the output voltage Vo2 becomes higher than the target voltage, that is, when the feedback voltage VFB2 becomes higher than the ground GND potential, the error signal S3 output from the error amplifier circuit 32 increases. Then, the H-level pulse width of the PWM signal S4 becomes longer, and the H-level pulse width of the control signal SG3 becomes longer. Therefore, the time for which the switch circuit SW3 is turned on becomes longer. That is, the output terminals Po2 and Po1 (capacitors C2 and C1) are connected via the coil L1, and the time during which the coil current IL is supplied from the capacitor C2 to the capacitor C1 becomes longer. In other words, it takes a long time for the electric charge to be discharged from the capacitor C2. As a result, the output voltage Vo2 that is the inverted voltage of the input voltage Vin is lowered. By such an operation, the output voltage Vo2 is maintained at a target voltage (a constant value) based on the ground GND potential and the resistors R3 and R4.

  Thus, in the second control unit 30, the ON time of the switch circuit SW3 is controlled based on the output voltage Vo2 so that the output voltage Vo2 approaches the target voltage based on the ground GND potential and the resistors R3 and R4. In other words, the second control unit 30 supplies the coil current IL to the capacitor C2 so that a desired current to be supplied to the load 3 in the second period P2, that is, the output current Io2, flows based on the output voltage Vo2. The time width required for this is controlled.

  As described above, in the DC-DC converter 1, the first period P1, the second period P2, and the third period P3 are controlled by the PWM signals S2 and S4 having the same frequency. Specifically, the PWM signal S2 controls (determines) the time width of the first period P1 and the total time width of the second period P2 and the third period P3. More specifically, the PWM signal S2 determines the time for storing energy in the coil L1 (the time width of the first period P1). The remaining time obtained by removing the time width of the first period P1 determined from the period T is a time for releasing the energy accumulated in the coil L1 toward the output terminal Po1 (the second period P2 and the second period P1). 3 period P3). Further, the remaining time, that is, a part of the time for supplying the coil current IL to the capacitor C1, is also used as the time for supplying the coil current IL to the capacitor C2 (that is, the time for extracting the charge from the capacitor C2). The time width for extracting charges from the capacitor C2 is controlled (determined) by the PWM signal S4. As a result, the time widths of the second period P2 and the third period P3 in which the coil current IL is supplied to the capacitor C1 by the PWM signal S2 are determined, and the second period P2 in which charges are extracted from the capacitor C2 by the PWM signal S4. A time span is determined.

  Therefore, as shown in FIG. 4A, when the weights of the loads 2 and 3 are greatly different, for example, when the output current Io1 is larger than the output current Io2, the time of the second period P2 in the remaining time. The width is adjusted to be short, and the output voltages Vo1 and Vo2 are stably generated. 4B, when the weights of the loads 2 and 3 are substantially equal, that is, when the output currents Io1 and Io2 are substantially equal, the time width of the second period P2 in the remaining time is long. Thus, the output voltages Vo1 and Vo2 are stably generated. Thus, the time width of the second period P2 in the remaining time is automatically adjusted according to the weight of the loads 2 and 3, and the output voltages Vo1 and Vo2 are stably generated.

  The switch circuits SW1 to SW3 are controlled to be turned on / off by PWM signals S2 and S4 having the same cycle (same frequency) as the cycle T of the periodic signal CK. Therefore, the switch circuits SW1 to SW3 are turned on / off at the same frequency as the PWM signals S2 and S4 (periodic signal CK). Thereby, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the difference between the frequency of the PWM signals S2 and S4 and the switching frequency fsw of the switch circuits SW1 to SW3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with the case where a frequency component appears in the coil current IL, loss can be reduced and conversion efficiency can be improved.

  Further, since the control signals SG1 to SG3 for controlling on / off of the switch circuits SW1 to SW3 are all signals having the same period (same frequency), the switch circuits SW1 to SW3 are all turned on / off at the same switching frequency fsw. . As a result, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the different frequencies of the control signals SG1 to SG3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with the case where a frequency component appears in the coil current IL, loss can be reduced and conversion efficiency can be improved.

  Further, since the switch circuits SW1 to SW3 are all turned on / off at the same switching frequency fsw as described above, the DC-DC in the current continuous mode (CCM) in which the coil current IL continuously changes in each cycle T. Even when the converter 1 is operated, the output voltages Vo1 and Vo2 can be stably generated. That is, since it is possible to prevent the occurrence of a problem that low frequency components appear in the output voltages Vo1 and Vo2 due to the different frequencies of the control signals SG1 to SG3, the DC-DC converter 1 is controlled in the CCM region. Even in the case of operation, the output voltages Vo1 and Vo2 can be stably generated.

  From another viewpoint, when the output voltages Vo1 and Vo2 are in a steady state, the coil current IL at the start time of each cycle T (see time t1) is controlled by feedback control by the first control unit 20 and the second control unit 30. And the current value of the coil current IL at the end time of each cycle T (see time t4) are controlled. More specifically, the increase in the coil current IL in the first period P1 is controlled to be equal to the decrease in the coil current IL in the second period P2 and the third period P3. The relationship between the increase and decrease of the coil current IL is as follows. When the times of the first to third periods P1, P2, and P3 are P1, P2, and P3, respectively,

It becomes. Further, the relationship between the period T and the times of the first to third periods P1, P2, and P3 is as follows:

It becomes. And the time width of the 1st-3rd period P1-P3 is controlled by feedback control by the control part 11 so that the relationship of these Formula 4 and Formula 5 may be satisfy | filled. That is, the time width of the first period P1 is controlled by the feedback control by the first control unit 20 so that the relationship of Expression 4 and Expression 5 is satisfied. Further, the time widths of the second period P2 and the third period P3 are controlled by the feedback control by the second control unit 30 so that the relations of Expression 4 and Expression 5 are satisfied.

According to this embodiment described above, the following effects can be obtained.
(1) The switch circuit SW1 is provided between the first terminal of the coil L1 and the input terminal Pi, the switch circuit SW2 is provided between the first terminal of the coil L1 and the ground GND, and the first terminal of the coil L1 and the output The switch circuit SW3 is provided between the terminal Po2. Then, on / off control of the switch circuits SW1 to SW3 is performed based on the PWM signal S2 generated based on the output voltage Vo1 and the PWM signal S4 generated based on the output voltage Vo2. Accordingly, it is possible to omit providing the diode D13 and the switch circuit SW13 (see FIG. 10) as in the conventional technique at the second terminal (output side terminal) of the coil L1, and therefore the diode D13 and the switch circuit SW13. Loss caused by the on-resistance can be eliminated. For this reason, power conversion efficiency can be improved compared with a prior art.

  (2) A first period P1 in which the input terminal Pi and the output terminal Po1 are connected via the coil L1, a second period P2 in which the output terminals Po1 and Po2 are connected via the coil L1, and a coil L1. Thus, the third period P3 for connecting the output terminal Po1 and the ground GND is continuously controlled within one period of the periodic signal CK based on the PWM signals S2 and S4. As a result, the output voltage Vo1 which is a step-down output and the output which is an inverted output can be provided without providing the diode D13 and the switch circuit SW13 (see FIG. 10) as in the prior art at the second terminal (output side terminal) of the coil L1. The voltage Vo2 can be suitably generated. Therefore, it is possible to eliminate the loss caused by the on-resistance of the diode D13 and the switch circuit SW13. For this reason, it is possible to further improve the power conversion efficiency as compared with the prior art.

  (3) The connection state of the coil L1 and the like is changed in the order of the first period P1, the second period P2, and the third period P3. Thereby, for example, the ripple of the coil current IL can be reduced as compared with the case where the connection state of the coil L1 or the like is changed in the order of the first period P1 → the third period P3 → the second period P2. As a result, the loss can be reduced and the power conversion efficiency can be improved as compared with the case where the connection state of the coil L1 and the like is changed in the order of the first period P1 → the third period P3 → the second period P2. Can be made.

  More specifically, an average value obtained by averaging the total amount of the coil current IL in the second period P2 in which the output terminals Po1 and Po2 are connected via the coil L1 in the period T is the output current Io2. Further, the coil current IL gradually decreases after the energy accumulated in the coil L1 starts to be released. For this reason, when the second period P2 is executed prior to the third period P3 in the energy release period, the second period P2 is compared to the case where the second period P2 is executed after the third period P3. Can be shortened. Here, the decrease slope m2 of the coil current IL in the second period P2 is − (Vo1−Vo2) / L (see Equation 2 above), and the decrease slope m3 of the coil current IL in the third period P3 is −Vo1. / L (see Equation 3 above). For this reason, the degree of decrease in the coil current IL in the second period P2 is greater than the degree of decrease in the coil current IL in the third period P3. Therefore, when the second period P2 is executed before the third period P3 in the energy release period, the coil in the energy release period is compared to the case where the second period P2 is executed after the third period P3. The amount of decrease in current IL can be reduced. Here, as described above, when it is considered that the coil current IL at the start and end of each cycle T coincides, the amount of decrease (amplitude) of the coil current IL in the second period P2 and the third period P3 is the coil current. This corresponds to the ripple ΔIL of IL. Therefore, by executing the second period P2 prior to the third period P3 in the energy release period, the coil current IL is reduced as compared with the case where the second period P2 is executed after the third period P3. The ripple ΔIL can be reduced. As a result, power conversion efficiency can be improved.

  (4) The switch circuits SW1 to SW3 are controlled to be turned on / off by PWM signals S2 and S4 (control signals SG1 to SG3) having the same period (same frequency) as the period T of the periodic signal CK. Therefore, the switch circuits SW1 to SW3 are turned on / off at the same frequency as the PWM signals S2 and S4 (periodic signal CK). Thereby, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the difference between the frequency of the PWM signals S2 and S4 and the switching frequency fsw of the switch circuits SW1 to SW3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with a prior art, a loss can be reduced and conversion efficiency can be improved.

  (5) Since the switch circuits SW1 to SW3 are all turned on / off at the same switching frequency fsw, the DC-DC converter 1 is operated in the current continuous mode in which the coil current IL continuously changes in each cycle T. Even so, the output voltages Vo1 and Vo2 can be stably generated. That is, since it is possible to prevent the occurrence of a problem that low frequency components appear in the output voltages Vo1 and Vo2 due to the different frequencies of the control signals SG1 to SG3, the DC-DC converter 1 is controlled in the CCM region. Even in the case of operation, the output voltages Vo1 and Vo2 can be stably generated.

(Second Embodiment)
Hereinafter, a second embodiment will be described. The DC-DC converter 1A of this embodiment is different from the first embodiment in that a detection circuit 70, a switch circuit SW4, and the like are added. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 5, the switch circuit group 10A includes four switch circuits SW1, SW2, SW3, SW4. For example, the switch circuit SW1 is a P-channel MOS transistor, and the switch circuits SW2 to SW4 are N-channel MOS transistors.

  A first terminal (for example, a source terminal) of the switch circuit SW1 is connected to the input terminal Pi. The second terminal (for example, drain terminal) of the switch circuit SW1 is connected to the first terminal (for example, drain terminal) of the switch circuit SW4. The back gate of the switch circuit SW1 is connected to the first terminal (source terminal) of the switch circuit SW1. Such a connection forms a body diode D1 in which the direction from the drain terminal of the switch circuit SW1 to the source terminal (from the coil L1 to the input terminal Pi) is the forward direction. That is, the body diode D1 has an anode connected to the first terminal of the coil L1 and a cathode connected to the input terminal Pi.

  A second terminal (for example, a source terminal) of the switch circuit SW4 is connected to a first terminal (for example, a drain terminal) of the switch circuit SW2. The back gate of the switch circuit SW4 is connected to the first terminal (drain terminal) of the switch circuit SW4. Such a connection forms a body diode D4 in which the direction from the drain terminal of the switch circuit SW4 to the source terminal (from the coil L1 to the switch circuit SW2) is the forward direction. That is, the body diode D4 has an anode connected to the first terminal of the coil L1 and a cathode connected to the first terminal of the switch circuit SW2.

  A second terminal (for example, a source terminal) of the switch circuit SW2 is connected to the ground GND. The back gate of the switch circuit SW2 is connected to the second terminal (source terminal) of the switch circuit SW2. Such a connection forms a body diode D2 in which the direction from the source terminal to the drain terminal (from ground GND to the switch circuit SW4) of the switch circuit SW2 is the forward direction. That is, the body diode D2 has an anode connected to the ground GND and a cathode connected to the second terminal of the switch circuit SW4.

  A node N1 between the switch circuit SW1 and the switch circuit SW4 is connected to a first terminal (for example, a drain terminal) of the switch circuit SW3. A second terminal (for example, a source terminal) of the switch circuit SW3 is connected to the output terminal Po2. The back gate of the switch circuit SW3 is connected to the second terminal of the switch circuit SW3. By such connection, a body diode D3 is formed in which the direction from the source terminal of the switch circuit SW4 to the drain terminal (from the output terminal Po2 to the coil L1) is the forward direction. That is, the body diode D3 has an anode connected to the output terminal Po2 and a cathode connected to the first terminal of the coil L1.

  By the way, when the switch circuit SW4 is not provided as shown in FIG. 8, when the absolute value of the output voltage Vo2 that is the inverted output becomes higher than the forward voltage Vf of the body diode D2 of the switch circuit SW2, The following problem occurs during the period P2. That is, in the second period P2 in which the switch circuits SW1 and SW2 are turned off and the switch circuit SW3 is turned on, if | Vo2 |> Vf, the output terminal from the ground GND through the body diode D2 and the turned on switch circuit SW2 Leakage current flows toward Po2.

  On the other hand, as shown in FIG. 7, in the DC-DC converter 1A of the present embodiment, the direction from the coil L1 to the switch circuit SW2 is the forward direction between the coil L1 and the switch circuit SW2, as described above. The body diode D4 (that is, the body diode D4 connected in the opposite direction to the body diode D2) is formed. Even if the absolute value of the output voltage Vo2 becomes higher than the forward voltage Vf of the switch circuit SW2 due to the body diode D4, leakage occurs from the ground GND toward the output terminal Po2 in the second period P2. It can suppress suitably that an electric current flows.

  The control unit 11 includes a first control unit 20, a second control unit 30, an oscillator 40, a logic circuit 50, a drive circuit 60, a detection circuit 70, an OR circuit 81, and a driver circuit 82. ing.

  The detection circuit 70 is supplied with the output signal S5 from the inverter circuit 51 in the logic circuit 50 and the output signal S7 from the NOR circuit 54 in the logic circuit 50. Based on the output signals S5 and S7, the detection circuit 70 detects whether or not the time width of the second period P2 is 0 s. The detection circuit 70 generates a detection signal VS1 having a signal level corresponding to the detection result. For example, when the detection circuit 70 detects that the time width of the second period P2 is 0 s, the detection circuit 70 generates the detection signal VS1 at the H level. Here, when the time width of the second period P2 is 0 s, only the first period P1 and the third period P3 are executed within one period T, and the switch circuit SW3 is always turned off within one period T. It is in a state of being. Therefore, when the detection circuit 70 detects that the switch circuit SW3 is not turned on within one cycle of the output signals S5 and S7 (one cycle of the PWM signals S2 and S4 and the control signals SG1 and SG2), It can be said that the detection signal VS1 is generated.

  The detection signal VS1 is supplied to the OR circuit 81. The OR circuit 81 is supplied with the output signal S9 from the AND circuit 64 in the drive circuit 60 together with the detection signal VS1. The OR circuit 81 outputs to the driver circuit 82 an output signal S11 having a result obtained by performing a logical OR operation on the detection signal VS1 and the output signal S9. For example, the OR circuit 81 generates an H level output signal S11 in response to the H level detection signal VS1, regardless of the signal level of the output signal S9. The OR circuit 81 generates an output signal S11 having a signal level equivalent to that of the output signal S9 in response to the L level detection signal VS1.

  The output terminal of the driver circuit 82 is connected to the control terminal of the switch circuit SW4. For example, the driver circuit 82 outputs a control signal SG4 of H level (for example, input voltage Vin level) to the switch circuit SW4 in response to the output signal S11 of H level (for example, input voltage Vin level). The driver circuit 82 outputs a control signal SG4 of L level (for example, ground GND level) to the switch circuit SW4 in response to the output signal S11 of L level (for example, ground GND level). The switch circuit SW4 is turned on in response to the H level control signal SG4 and turned off in response to the L level control signal SG4.

Next, an example of the internal configuration of the detection circuit 70 will be described.
As shown in FIG. 6, the detection circuit 70 includes inverter circuits 71 and 72 and D-flip flop circuits (D-FF circuits) 73 and 74.

  The inverter circuit 71 supplies a signal obtained by logically inverting the output signal S5 to the clock terminals of the D-FF circuits 73 and 74. The inverter circuit 72 supplies a signal obtained by logically inverting the output signal S7 to the reset terminals R of the D-FF circuits 73 and 74.

  A high potential power supply voltage VDD generated by a power supply circuit (not shown) is supplied to the input terminal D of the D-FF circuit 73. The output signal Q1 is output from the output terminal Q of the D-FF circuit 73 to the input terminal D of the D-FF circuit 74 at the next stage. The detection signal VS1 is output from the output terminal Q of the D-FF circuit 74.

Next, the operation of the detection circuit 70 will be described.
In the period Ta shown in FIG. 9, the H level output signal S7 is generated within one period T of the PWM signals S2 and S4. Specifically, in the period Ta, the H-level output signal S7 is generated between the falling edge of the output signal S5 and the falling edge of the next output signal S5. In this case, the D-FF circuits 73 and 74 are reset by the H level output signal S7. Thereby, since the output signal Q1 becomes L level, the detection signal VS1 output from the D-FF circuit 74 is maintained at L level. In response to the L level detection signal VS1, a control signal SG4 having a signal level equivalent to that of the output signal S6 is supplied to the switch circuit SW4. For this reason, the switch circuit SW4 is turned on / off in conjunction with the switch circuit SW2.

  On the other hand, when the period during which the output signal S7 is at the H level does not occur within one cycle T of the PWM signals S2 and S4 as in the period Tb, that is, when the time width of the second period P2 becomes 0 s. In the period T, the D-FF circuits 73 and 74 are not reset. More specifically, the output signal Q1 of the D-FF circuit 73 becomes H level in response to the falling edge of the output signal S5 (see time t11). After that, since the output signal S7 does not transit to the H level, the output signal Q1 that has become the H level does not transit to the L level, and the H level output signal Q1 is input to the D-FF circuit 74 in the next cycle T. Supplied to terminal D. Subsequently, in response to the falling edge of the output signal S5 of the next period T, the D-FF circuit 74 outputs the H level detection signal VS1 (see time t12). In response to the H level detection signal VS1, a control signal SG4 having a fixed H level is supplied to the switch circuit SW4. As a result, the switch circuit SW4 is maintained in the on state.

  In this manner, the switch circuit SW4 is controlled to be turned on / off in conjunction with the switch circuit SW2 when the time width of the second period P2 is not 0 s. That is, the switch circuit SW4 when the time width of the second period P2 is not 0 s is turned off together with the switch circuit SW2 in the first period P1 and the second period P2, and is turned on together with the switch circuit SW3 in the third period P3. Is done. Further, the switch circuit SW4 is maintained in the ON state when the time width of the second period P2 is 0 s.

  By the way, in the DC-DC converter 1A, a period in which the switch circuits SW1 to SW3 are simultaneously turned off is generated by the control by the OR circuit 61, the inverter circuits 62 and 63, and the AND circuits 64 and 65 (AST circuit) in the drive circuit 60. . At this time, when the switch circuit SW4 is always on / off controlled in conjunction with the switch circuit SW2, the following problem occurs when the load 3 is unloaded. More specifically, when all the switch circuits SW1 to SW4 are simultaneously turned off when the load 3 is unloaded, a current path from the output terminal Po2 to the output terminal Po1 through the body diode D3 and the coil L1 is formed ( That is, the second period P2 is reached). As a result, the coil current IL is supplied to the output terminal Po2 (capacitor C2), so that the output voltage Vo2 deviates from the target voltage.

  On the other hand, in the DC-DC converter 1A of the present embodiment, when the detection circuit 70 detects that the time width of the second period P2 is 0 s, that is, when the load 3 is unloaded, The circuit SW4 is kept on. Thereby, even when the switch circuit SW1 to SW3 is simultaneously turned off when the load 3 is unloaded, the current from the ground GND to the output terminal Po1 through the body diode D2, the turned on switch circuit SW4, and the coil L1. A path is formed (that is, the third period P3). For this reason, it can suppress suitably that coil current IL is supplied to output terminal Po2 (capacitor C2), and can generate output voltage Vo1, Vo2 stably.

According to the embodiment described above, the following effects can be obtained in addition to the effects (1) to (5) of the first embodiment.
(6) Between the coil L1 and the switch circuit SW2, the body diode D4 is connected in the direction opposite to the body diode D2 from the coil L1 to the switch circuit SW2 ground GND to the switch circuit SW4. Body diode D4). Even if the absolute value of the output voltage Vo2 becomes higher than the forward voltage Vf of the switch circuit SW2 due to the body diode D4, leakage occurs from the ground GND toward the output terminal Po2 in the second period P2. It can suppress suitably that an electric current flows.

  (7) When the detection circuit 70 detects that the time width of the second period P2 is 0 s, that is, when the load 3 is unloaded, the switch circuit SW4 is maintained in the on state. Thereby, even when the load 3 becomes no load, the output voltages Vo1 and Vo2 can be stably generated.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, in each cycle T, the connection state of the coil L1 and the like is changed in the order of the first period P1, the second period P2, and the third period P3. For example, in each cycle T, the connection state of the coil L1 and the like may be changed in the order of the first period P1, the third period P3, and the second period P2.

  In place of the body diodes D1 to D4 in the second embodiment, diodes corresponding to the body diodes may be connected in parallel to the switch circuits SW1 to SW4.

  In each of the above embodiments, a P-channel MOS transistor is disclosed as an example of the switch circuit SW1, but an N-channel MOS transistor may be used. Further, a bipolar transistor may be used as the switch circuit SW1. Alternatively, a switch circuit including a plurality of transistors may be used as the switch circuit SW1.

  In each of the above embodiments, an N-channel MOS transistor is disclosed as an example of the switch circuits SW2, SW3, SW4, but a P-channel MOS transistor may be used. Bipolar transistors may be used as the switch circuits SW2, SW3, SW4. Alternatively, a switch circuit including a plurality of transistors may be used as the switch circuits SW2, SW3, SW4.

-The internal structure of the control part 11 (1st control part 20, the 2nd control part 30, the logic circuit 50, and the drive circuit 60) in each said embodiment is not specifically limited.
The oscillator 40 in each of the above embodiments generates the periodic signal CK that is a sawtooth wave signal. Not limited to this, the oscillator 40 may generate a triangular wave signal.

In each of the above embodiments, the voltage control mode DC-DC converter is embodied. However, the current control mode DC-DC converter may be embodied.
In each of the above embodiments and each of the modifications, the PWM control type DC-DC converter is embodied. However, a PFM (Pulse Frequency Modulation) control type DC-DC converter or a PSM (Pulse Skipping Modulation) control type DC is used. -It may be embodied in a DC converter. However, even in this case, it is preferable that all the control signals for on / off control of the switch circuits SW1 to SW3 are signals having the same frequency.

1, 1A DC-DC converter 10, 10A Switch circuit group 11 Control unit (control circuit)
20 First Control Unit 30 Second Control Unit 40 Oscillator 50 Logic Circuit 60 Drive Circuit 70 Detection Circuit L1 Coil SW1 Switch Circuit (First Switch Circuit)
SW2 switch circuit (second switch circuit)
SW3 switch circuit (third switch circuit)
SW4 Switch circuit (MOS transistor)
D4 Body diode (diode)
IL coil current S2 PWM signal S4 PWM signal SG1 to SG4 control signal VS1 detection signal CK periodic signal P1 first period P2 second period P3 third period

Claims (8)

A coil having a first terminal and a second terminal connected to a first output terminal from which a first output voltage lower than the input voltage is output;
A first switch circuit provided between a first terminal of the coil and an input terminal to which the input voltage is supplied;
A second switch circuit provided between a first terminal of the coil and a power supply line having a potential lower than the input voltage;
A third switch circuit provided between a first terminal of the coil and a second output terminal from which a second output voltage obtained by inverting the input voltage is output;
A control unit that generates a first control signal based on the first output voltage and generates a second control signal based on the second output voltage;
The control unit performs on / off control of the first switch circuit, the second switch circuit, and the third switch circuit at the same frequency based on the first control signal and the second control signal. Power supply. The controller is
An oscillator that generates a periodic signal having a first period;
A first period in which the first switch circuit is turned on and the second switch circuit and the third switch circuit are turned off; and the third switch circuit is turned on and the first switch circuit and the second switch circuit are turned off. Based on the first control signal and the second control signal, a second period and a third period in which the second switch circuit is turned on and the first switch circuit and the third switch circuit are turned off, The power supply apparatus according to claim 1, wherein continuous control is performed within one period of the periodic signal.   The control unit is configured to change the connection period of the coil in the order of the first period, the second period, and the third period, the first switch circuit, the second switch circuit, and the The power supply device according to claim 2, wherein the third switch circuit is on / off controlled.   A diode having an anode connected to a first terminal of the coil and a cathode connected to the second switch circuit is formed between the coil and the second switch circuit. Item 4. The power supply device according to any one of Items 1 to 3. A MOS transistor is provided between the coil and the second switch circuit,
The power supply device according to claim 4, wherein the diode is a parasitic diode of the MOS transistor.   6. The detection circuit according to claim 5, further comprising a detection circuit that generates a detection signal for turning on the MOS transistor when it is detected that the third switch circuit is not turned on within one cycle of the first control signal. Power supply. A coil having a first terminal and a second terminal connected to a first output terminal from which a first output voltage lower than the input voltage is output; a first terminal of the coil; and an input to which the input voltage is supplied A first switch circuit provided between the first terminal of the coil, a second switch circuit provided between a first terminal of the coil and a power supply line having a potential lower than the input voltage, and a first of the coil A control circuit for controlling a power supply, comprising: a third switch circuit provided between the terminal and a second output terminal from which a second output voltage obtained by inverting the input voltage is output;
A first control signal is generated based on the first output voltage, a second control signal is generated based on the second output voltage, and the first control signal is generated based on the first control signal and the second control signal. A control circuit that performs on / off control of the switch circuit, the second switch circuit, and the third switch circuit at the same frequency . A coil having a first terminal and a second terminal connected to a first output terminal from which a first output voltage lower than the input voltage is output; a first terminal of the coil; and an input to which the input voltage is supplied A first switch circuit provided between the first terminal of the coil, a second switch circuit provided between a first terminal of the coil and a power supply line having a potential lower than the input voltage, and a first of the coil A third switching circuit provided between a terminal and a second output terminal from which a second output voltage obtained by inverting the input voltage is output.
Generating a first control signal based on the first output voltage;
Generating a second control signal based on the second output voltage;
A control method comprising: turning on / off the first switch circuit, the second switch circuit, and the third switch circuit at the same frequency based on the first control signal and the second control signal.