JP6177057B2 - IC for wireless communication - Google Patents

Description

  The present invention relates to an IC for radio communication, and more particularly to an IC for radio communication having a radio transmission function of a polar modulation scheme or an out-fading modulation scheme.

  Many mobile communication terminal apparatuses have a wireless data communication function using Wi-Fi technology, which is one of the wireless LAN standards. In the Wi-Fi technology, typically, an OFDM (Orthogonal Frequency-Division Multiplexing) method or the like that can realize a high transmission rate is adopted. Therefore, in addition to the phase modulation function, the internal wireless transmission circuit includes: It is necessary to implement the amplitude modulation function.

  Such a mobile communication terminal device is desired to have as long a drive time as possible as long as it is mounted on a battery. In order to make the battery driving time as long as possible, it is desirable that the current consumption in the internal IC is as small as possible. For this reason, the nonlinear power amplifier has a relatively high power efficiency (ratio of transmission power to power consumption). Employing this is extremely advantageous from the viewpoint of low power consumption. To date, as a radio transmission technique using a nonlinear power amplifier, a polar modulation method and an outphasing modulation method are known.

(A) Polar modulation scheme The polar modulation scheme is a modulation scheme that compensates for distortion of the polar (that is, phase and amplitude) of a radio signal (RF signal) transmitted from an antenna. That is, for example, as shown in FIG. 17, a wireless transmission circuit that realizes a polar modulation system includes a phase modulator and an amplitude modulator using an amplitude variable power amplifier. The polar modulation method is also described in detail in Non-Patent Document 1. With such a polar modulation method, it is possible to amplitude-modulate a signal while saturating the power amplifier, so that it is not necessary to require high linearity in the power amplifier itself, resulting in reduced component costs and reduced power consumption. Reduction can be expected.

(B) Out-fading modulation method On the other hand, the out-fading modulation method includes a phase modulator, an amplitude modulator, and an amplitude-phase data converter as shown in FIG. 18, for example. Each of the amplitude modulators includes two rotation amount variable phase rotators, a fixed amplitude power amplifier, and an adder. In the figure, if a signal phase-modulated according to the phase modulation signal PH is cos (2πF ₀ t + PH), this signal is input to the rotation amount variable phase rotator # 1 and the rotation amount variable phase rotator # 2, respectively. Further, the phase rotation of + φ and −φ is received and input to power amplifier # 1 and power amplifier # 2, respectively. Here, F ₀ is the RF channel center frequency, and t is the time. Then, the signals output from each of the power amplifier # 1 and the power amplifier # 2 are subjected to amplitude modulation corresponding to φ as shown in the following equation 1 by being added by the power combiner. Here, A is the output amplitude of each power amplifier.
<Formula 1>
Acos (2πF ₀ t + PH + φ) + Acos (2πF ₀ t + PH−φ) = 2Acosφcos (2πF ₀ t + PH)
The out fading modulation method is described in detail in Non-Patent Document 2, for example. With such an out-fading modulation method, the signal can be amplitude-modulated while operating the power amplifier in a saturated manner, and it can be expected to reduce the component cost and power consumption.

(C) Modulation method in phase modulator Typically, the phase modulator described above typically uses a closed-loop phase modulation method (Non-Patent Document 3) and an open-loop phase modulation method (non-patent document 3). Patent Document 4). As described in detail below, Non-Patent Document 3 discloses a closed-loop phase modulation system configured to input a phase modulation signal to two nodes in a loop including a PLL (Phase Locked Loop) circuit and an analog output oscillator. Is disclosed. Non-Patent Document 4 discloses an open loop phase modulation system configured to input a phase modulation signal to an analog phase interpolator together with a sine wave signal having two or more different phases output from an analog output oscillator. Disclose.

(A) Closed-loop phase modulation method The closed-loop phase modulation method is a method in which a phase-modulated signal is given to one or more nodes in a loop configured using a PLL circuit and an analog output oscillator. The analog output oscillator here is typically a VCO (Voltage Controlled Oscillator) or a DCO (Digitally Controlled Oscillator), both of which output an analog sine wave. In this method, a variable frequency divider is provided in the loop, and a frequency synthesizer is configured by dynamically switching the frequency dividing number of the variable frequency divider, thereby realizing RF channel selection.

FIG. 19 is a block diagram showing an example of a conventional phase modulator using a closed loop phase modulation method. As shown in the figure, in this system, the PLL circuit compares the frequencies of the reference clock and the output clock from the variable frequency divider, and adjusts the frequency of the output sine wave from the analog output oscillator to a desired frequency. The frequency control signal is output to the analog output oscillator. Here, when the frequency of the reference clock is F _ref and the frequency _dividing number of the variable frequency divider is N and constant, the frequency of the sine wave signal output from the analog output oscillator is N · F _ref [Hz]. . In order to perform RF channel selection and to apply phase modulation to a sine wave signal by an analog output oscillator, typically, a phase divider signal is input to a variable frequency divider. A sine wave signal subjected to desired phase modulation can be obtained by dynamically switching the frequency dividing number of the variable frequency divider between N and N + 1. In this case, in order to match the dimensions of the two inputs of the PLL circuit, the phase modulation signal is time-differentiated once by the time differentiating circuit and further multiplied by the period 1 / F _ref of the reference clock. In addition, when the PLL circuit compares the phases of the two inputs, it is typically performed by comparing the time difference between the rising edges, so that the analog output oscillator is not _{synchronized with} the reference clock period 1 / F _ref. If a continuous control signal is given, the frequency of the sine wave output will rise and fall rapidly at a period of 1 / F _ref . In order to mitigate this effect, the PLL circuit usually includes a low-pass filter called a loop filter, through which the control signal is smoothed and input to the analog output oscillator. However, as a result, a sudden change that is originally desired in the phase-modulated sinusoidal signal is also simultaneously smoothed and input to the analog output oscillator, thereby reducing the signal quality. In order to eliminate such a contradiction, for example, a two-point modulation technique is used in which a phase modulation signal is input to two nodes in a loop including a PLL circuit and an analog output oscillator (Non-Patent Document 3). As shown in the same document, typically, the second node for inputting the phase modulation signal is the second input of the VCO or DCO. It is known that the closed-loop response characteristic of the phase modulation signal input to the second input of the VCO or DCO has a high-pass characteristic having the same cutoff frequency as the cutoff frequency indicated by the low-pass characteristic of the loop filter. At this time, the phase-modulated signal is differentiated once in the time differentiating circuit, then multiplied by the inverse 1 / K _vco of the gain of the VCO or DCO, and input to the second node, whereby the variable frequency period that is the first node is obtained. Therefore, the phase modulation signal applied to the output sine wave of the analog output oscillator has an ideal all-pass characteristic as a whole. That is, if the two-point modulation technique is ideally achieved, a desired phase modulator can be configured.

(B) Open-loop phase modulation method Unlike the above-described closed-loop phase modulation method, the open-loop phase modulation method does not apply a phase-modulated signal to a loop composed of a PLL circuit, an analog output oscillator, etc. Is a method applied to an analog phase interpolator that receives a sine wave signal having two or more different phases output from an analog output oscillator.

  FIG. 20 is a block diagram showing an example of a conventional phase modulator using an open loop phase modulation method. Referring to the figure, in this system, two or more sine wave signals out of phase output from the analog output oscillator are used, and after the weights of the two or more sine wave signals are separately weighted, They are fed to an analog phase interpolator having a summing function together with a phase modulation signal. The analog output oscillator referred to here is a VCO or a DCO as described above, and both output an analog sine wave signal. The loop configuration of the PLL circuit and the analog output oscillator is the same as described above.

  FIG. 21 is a block diagram showing an example of a conventional differential analog phase interpolator. The analog phase interpolator shown in the figure is manufactured using, for example, a CMOS manufacturing process. The differential sine wave signal output from the analog output oscillator is frequency-divided by a frequency divider to become a sine wave signal having two or more different phases. Referring to the figure, the currents of the two branches of the grounded-source stage to which the first differential sine wave signal (0 degree) and the second differential sine wave signal (90 degrees) are input by the phase modulation signal. The magnitude ratio is controlled, and the polarity of the switches of the cross switch # 1 and the cross switch # 2 is controlled, and the phase of the final phase-modulated differential sine wave signal is variable from 0 degree to 360 degrees Become. In the figure, the sign function is a function for discriminating between positive and negative, and | * | means an absolute value. In the case of the open loop phase modulation system, the frequency characteristic of the phase modulation signal has an ideal all-pass characteristic with a fundamentally uniform gain.

  In addition, a wireless communication circuit that handles digital wireless communication requires a digital-analog converter (hereinafter referred to as “DAC” or “DA converter”) for converting a digital signal into an analog signal. According to the Nyquist sampling theorem, in order to retain the information that the transmission signal has, it is necessary to sample at a sampling frequency Fs that is at least twice the bandwidth (BW) occupied by the signal. Must operate at this sampling frequency Fs.

The Nyquist DAC converts a digital signal into an analog signal in synchronization with a sampling clock. A feature of the Nyquist DAC is that quantization noise generated by the quantizer is output as white noise together with a transmission signal. In this case, the maximum value that can be taken by the SQNR (Signal to Quantization Noise Ratio), which is an index by which quantization noise degrades the signal quality, is the bandwidth for the Nyquist frequency (that is, ½ of the sampling frequency Fs). Sampling Ratio) is expressed by the following formula 2. However, it is assumed that the input signal is a sine wave signal. B represents the number of DAC bits.
<Formula 2>
SQNR [dB] = 6.02B + 1.76 + 10 log (OSR)

  Therefore, as the number of DAC bits increases, the SQNR increases and the signal quality improves. For example, if the DAC is a current output design, the number of current cells representing 1 LSB increases by a power of 2. This increases the current consumption. Also, the SQNR increases and the signal quality is improved by increasing the OSR, but if the bandwidth is constant, it is necessary to increase the sampling frequency Fs, which also causes an increase in current consumption. become.

The ΔΣ DAC converts the digital signal into an analog signal after applying the ΔΣ modulation to the signal to be transmitted by the digital ΔΣ modulator, and low power consumption can be expected. ΔΣ modulation has noise shaping characteristics, and the quantization noise is colored noise unlike the Nyquist DAC, and is output together with the transmission signal. Utilizing such characteristics, the power of quantization noise can be driven to a band other than the frequency band of the transmission signal, and the SQNR can be effectively increased. The maximum value that the SQNR can take in this case is expressed by <Equation 3>. However, the input signal is assumed to be a sine wave. B represents the number of bits of the DAC, and k represents the order of the digital ΔΣ modulator.
<Formula 3>
SQNR [dB] = 10 log (3 (2k + 1) 2 ^2B-1 / π ^2k−2 ) +10 (2k + 1) log (OSR)

  As with the Nyquist DAC, to improve the SQNR, it is necessary to increase B or OSR. Here, when the formula 2 and the formula 3 are compared, there is a difference in the effect of improving the SQNR due to the increase in OSR. That is, when the OSR is doubled, for example, the Nyquist DAC can only improve 10 log2 = 3 [dB], whereas the ΔΣ DAC can be expected to improve 10 (2k + 1) log2. By using this characteristic, the bit number B of ΔΣDAC can be kept low to achieve the same SQNR, instead of taking the OSR sufficiently high.

To achieve the desired SQNR and to set the number of bits B for reasonable current consumption, a sampling frequency Fs of several hundred MHz to several GHz is usually required. In the current semiconductor manufacturing process using CMOS technology or the like, it is extremely difficult to realize a component corresponding to such a high frequency at present, and even if it can be realized, a large current consumption is required.

  Non-Patent Document 5 proposes a method of parallelizing a digital ΔΣ modulator and processing transmission signals input thereto in parallel. This makes it possible to design a digital ΔΣ modulator composed of standard primitive cells using a logic synthesis method of an RTL (Register Transfer Level) hardware description language. Note that FIG. 4 shows a block diagram of an error feedback type parallelized low-pass ΔΣ modulator.

J.F.Bercher, and C.Berland, "Envelope and phase delays correction in an EER radio architecture", Analog Integrated Circuits and Signal Processing, vol. 55, pp. 21.35, April 2008. M.E.Heidari, M.Lee, and A.A.Abidi, "All-Digital Outphasing Modulator for a Software-Defined Transmitter", IEEE Journal of Solid-State Circuits, vol.44, no.4, pp. 1260-1270, April 2009. S. Lee, J. Lee, H. Park, KYLee, and S. Nam, "Self-Calibrated Two-Point Delta. Sigma Modulation Technique for RF Transmitters", IEEE Transactions, Microwave Theory and Technique, vol. 58, no 7, pp. 1748-1757, July2010. P.E.Su, and S. Pamarti, "A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation", IEEE Journal of Solid-State Circuits, vol.46, no.3, pp. 615-626, March 2011. J. Pham, and AC Carusone, "A Time-Interleaved delta-sigma-DAC Architecture Clocked at the Nyquist Rate", IEEE Transactions, Circuit and Systems: Express Briefs, vol.55, no.9, pp. 858-862, September 2008

  In a conventional polar modulation type radio transmission circuit, data to be transmitted is separated into an amplitude modulation signal and a phase modulation signal in advance, and is combined again by a power amplifier and output as a radio transmission signal. However, at this time, a path (phase modulation path) from the phase modulation signal input of the wireless transmission circuit to the power amplifier as a phase-modulated sine wave signal via the phase modulator and the amplitude modulation signal input of the wireless transmission circuit to the power amplifier If there is a delay value mismatch between the path to reach (amplitude modulation path), the problem is that ACPR (Adjacent Channel Power Ratio) and EVM (Error Vector Magnitude), which are indicators of the quality of wireless transmission data, deteriorate. Yes (see FIG. 2 and FIG. 3 of Non-Patent Document 1).

  In particular, since the phase modulation signal and the amplitude modulation signal have different analog delay values (non-constant group delay) in the respective paths, the mismatch of the delay values becomes extremely complicated. Further, this delay value mismatch varies depending on the radio transmission circuit due to manufacturing variations, power supply voltage variations, and ambient temperature variations (generally referred to as “PVT variations” in combination with the three types of variations) in the semiconductor manufacturing process. Not only that, it will change over time in one wireless transmission circuit. Therefore, in order to satisfy the values specified by ACPR and EVM in the target wireless communication standard, it is necessary to provide a calibration mechanism for delay mismatch around the wireless transmission circuit, and estimate and correct this delay mismatch. It is said. This is obviously disadvantageous from the viewpoint of hardware mounting area and current consumption. Also, when viewed as a whole wireless communication apparatus, a calibration time must be provided immediately before transmission by the wireless transmission circuit, and there is a problem that the time required for starting the apparatus is further increased.

In addition, in the conventional closed-loop phase modulation type phase modulator, there is a problem in the mismatch between the delay value and gain of each phase modulation signal applied to two nodes in the loop composed of a PLL circuit, an analog output oscillator, and the like. . In addition, since the phase modulation signal input to the phase modulator has different analog delay values (non-constant group delay) before reaching the two nodes, the mismatch of the delay values becomes extremely complicated. . In addition, due to PVT fluctuations, this delay value mismatch is not only different for each wireless transmission circuit, but also changes over time in one wireless transmission circuit. Further, as shown in FIG. 19, the second application node is typically an analog output oscillator, and the gain of the second application node varies due to the PVT variation of K _vco . Due to the delay value mismatch and the gain mismatch, the phase modulation signal cannot have an ideal all-pass characteristic when output from the phase modulator as a phase-modulated sine wave signal.

  In the above-mentioned Non-Patent Document 3, FIG. As shown in FIG. 4, in addition to the actual two application paths B1-path and B2-path, by providing A1-path and A2-path simulating these two paths, delay value mismatch and gain mismatch It has been proposed to correct both mismatches by estimating the estimation result and feeding back the estimation result to B2-path. In any case, however, in order to satisfy the specified values of ACPR and EVM, it is necessary to provide a calibration mechanism for mismatch, which is disadvantageous from the viewpoint of hardware mounting area and current consumption. Also, when viewed as a whole wireless communication apparatus, a calibration time must be provided immediately before transmission by the wireless transmission circuit, and there is a problem that the time required for starting the apparatus is further increased.

  On the other hand, in the case of the conventional open loop phase modulation method, the loop configuration by the PLL circuit and the analog output oscillator and the analog phase interpolator to which the phase modulation signal is input are independent. The problem will not occur. However, for the analog phase interpolator itself and the path from the output of the phase modulator to the input to the analog phase interpolator, the linearity with respect to phase rotation may be impaired due to manufacturing variations in the semiconductor manufacturing process. That is, the phase of the sine wave signal does not monotonously increase from 0 degrees to 360 degrees due to the phase modulation signal. In the example of the conventional analog phase interpolator shown in FIG. 21, manufacturing variations between the current sources IB1 and IB2, manufacturing variations between the transistors M1P, M1N, M2P, and M2N, load resistances RP and RN And the phase variation from the ideal 90 degree between the differential sine wave signal (0 degree) and the differential sine wave signal (90 degree) cause the loss of linearity. Although linearity can be improved to some extent by increasing the size of each device constituting the analog phase interpolator and increasing the current value of the current source, from the viewpoint of hardware mounting area and current consumption It is not valid.

  Further, in any of the phase modulation methods described above, the frequency of the sine wave output by the analog output oscillator varies depending on the phase modulation and the RF channel selection. A wireless transmission circuit including such an analog output oscillator is mixed with a digital circuit for baseband signal processing that is expected to operate at a constant clock frequency as a SoC (System-on-a-Chip). Even so, the sine wave output by the analog output oscillator could not be used as a clock for operating the digital circuit. Therefore, after all, in order to obtain a constant clock frequency, another clock generation unit may be required.

  Furthermore, the low-pass ΔΣ DAC disclosed in Non-Patent Document 5 is premised on digital-to-analog conversion of a baseband signal before frequency conversion to the RF transmission band. That is, this document relates to a technique for handling a transmission signal having its spectrum in the vicinity of DC. Therefore, no consideration was given to quantization noise in the vicinity of the RF transmission band. In the same document, FIG. As shown in FIG. 2, the parallel output of the ΔΣ modulator is converted again into serial data and input to the Nyquist DAC. Therefore, for a transmission signal having the spectrum near the RF transmission band, the serial data is at least several GHz. Realization of a DAC corresponding to such a high frequency is extremely difficult at present, and even if it can be realized, a large current consumption is required.

  As described above, in the wireless communication technology field represented by Wi-Fi or the like employed in mobile communication terminal devices, it is an important issue to make the battery driving time as long as possible. Therefore, the use of a nonlinear power amplifier in the wireless communication circuit inside the communication terminal device is effective for reducing the power consumption of the device. However, the nonlinear power amplifier is an analog circuit, and the manufacturing cost and design freedom are reduced. From a viewpoint of degree, it was not necessarily advantageous.

  On the other hand, a digital circuit manufactured by CMOS technology or the like is advantageous from the viewpoint of manufacturing cost and design freedom. However, conventionally, there has been no attempt to apply such a digital circuit to a wireless communication circuit. Even if it was done, it was very difficult to design a digital circuit on the premise that it would be mixed with an analog circuit that handles high frequencies, and it was not easy to implement.

  Accordingly, the present invention provides a wireless communication circuit that realizes low power consumption in a mobile wireless communication device, and that can be mixed with a digital circuit manufactured by CMOS technology or the like, and is advantageous in terms of manufacturing cost. For the purpose.

  More specifically, one of the objects of the present invention is to reduce the power consumption of a wireless communication circuit (IC) built in a mobile wireless communication device and to make the battery driving time of the device as long as possible. .

  Another object of the present invention is to solve the above-described problems in the conventional polar modulation type radio communication circuit while realizing low power consumption.

  Furthermore, one of the objects of the present invention is to solve the above-mentioned problems in the conventional radio communication circuit of the out-fading modulation system while realizing low power consumption.

  Furthermore, one of the objects of the present invention is a new wireless transmission circuit that meets the design concept of a mixed IC of an analog front end unit and a baseband signal processing unit, that is, a SoC (System-On-a-Chip). An analog front-end unit architecture is provided, which in turn reduces the manufacturing cost per wireless communication terminal device.

  The present invention according to a certain aspect for solving the above-described problem is a wireless communication IC including a polar modulation type wireless transmission circuit, and includes a clock generation circuit that generates a clock having a constant frequency, and the clock generation circuit. A digital signal that uses a generated clock to phase-modulate a predetermined digital sine wave signal according to an RF channel selection signal based on a phase modulation signal based on a signal to be transmitted, and output the phase-modulated digital sine wave signal A phase modulator, a DA converter that converts the phase-modulated digital sine wave signal into an analog sine wave signal using the clock generated by the clock generation circuit, and a signal to be transmitted from the analog sine wave signal And a power amplifier that amplifies using an amplitude modulation signal based on the digital phase modulator. A parallelized digital phase modulator including a predetermined number of subphase modulators configured to each of the subphase modulators, wherein each of the subphase modulators phase-modulates a parallelized digital sine wave signal based on the phase modulated signal, The DA converter is a parallelized DA converter including a predetermined number of sub DA converters configured in parallel, and the parallelized DA converter performs analog conversion on the modulated parallelized digital sine wave signal, This is an IC for wireless communication that outputs an analog sine wave signal.

  Each of the sub-phase modulators is configured to include a numerically controlled oscillator that generates the parallel digital sine wave signal so that each of the parallel digital sine wave signals is temporally complementary to each other. Is done.

  Here, each numerically controlled oscillator of the sub-phase modulator has a first numerically controlled oscillator that generates a first parallelized digital sine wave signal and a phase with respect to the first parallelized digital sine wave. And a second numerically controlled oscillator that generates a second parallelized digital sine wave signal shifted by 90 degrees. Each of the sub-phase modulators further outputs a predetermined weighting coefficient for each of the first parallelized digital sine wave signal and the second parallelized digital sine wave signal based on the phase modulation signal. A phase-amplitude converter; and a logic operation circuit that performs a logic operation based on the first parallelized digital sine wave signal, the second parallelized digital sine wave signal, and the predetermined weighting factor. Composed.

  The parallel DA converter further includes a digital filter that performs a predetermined filtering operation on the modulated parallel digital sine wave signal, and each of the sub DA converters performs the predetermined filtering operation. A corresponding signal among the output signals is configured to perform analog conversion.

Here, when the input signal is x [n] and the output signal is y [n], the digital filter has the following equation regarding the input / output transfer function:
y [n] = x [n] -x [n-1] + y [n-4]
(Where n represents the overall signal consisting of a parallel digital sine wave signal)
The circuit is configured to satisfy the relationship.

  Further, the parallel DA converter is configured to further include a band-pass ΔΣ modulator disposed in the preceding stage of the digital filter.

Here, the band-pass ΔΣ modulator has the modulated parallel digital sine wave signal as w [n], the output signal to the digital filter as x [n], and the quantization noise as e [n]. And the following formula for the input / output transfer function:
x [n] = w [n] + (1 / (1+ (2cos 2θ) * z ⁻² + z ⁻⁴ )) * e [n]
(Where n represents the overall signal consisting of a parallel digital sine wave signal)
The circuit is configured to satisfy the relationship.

  The wireless communication IC may further include a reception analog front end unit including an orthogonal mixer.

  The wireless communication IC is preferably a digital / analog mixed SoC.

  According to another aspect of the present invention, there is provided a wireless communication IC including an out-fading wireless transmission circuit, a clock generation circuit for generating a clock having a constant frequency, and a clock generated by the clock generation circuit. In accordance with the RF channel selection signal, a pair of digital sine wave signals whose phases are shifted from each other by a predetermined rotation amount are respectively modulated based on the phase modulation signal and the amplitude modulation signal based on the signal to be transmitted, and the modulation is performed. Using the digital phase modulation / phase rotator that outputs a pair of digital sine wave signals and the clock generated by the clock generation circuit, the pair of modulated digital sine wave signals are converted into analog sine wave signals, respectively. A pair of DA converters, wherein the digital phase modulation / phase rotator is configured in parallel. A parallelized digital phase modulation / phase rotator including a number of subphase modulation / phase rotators, each of the subphase modulation / phase rotators being paired in parallel based on the phase modulation signal and the amplitude modulation signal The DA converter is a parallel DA converter that includes a predetermined number of sub DA converters configured in parallel, and the pair of parallel DA converters includes the pair of parallel parallel DA converters. This is a wireless communication IC that performs analog conversion on a digital sine wave signal and outputs an analog sine wave signal.

  Each of the sub-phase modulation / phase rotators includes a numerically controlled oscillator that generates the parallelized digital sine wave signal such that each of the parallelized digital sine wave signals is complementary in time to each other. Configured as follows.

  Each of the numerically controlled oscillators of the sub-phase modulation / phase rotator has a first numerically controlled oscillator that generates a first parallelized digital sine wave signal, and a first parallelized digital sine wave. And a second numerically controlled oscillator that generates a second parallel digital sine wave signal that is 90 degrees out of phase. Each of the sub phase modulation / phase rotators further includes the first parallel digital sine wave signal and the second parallel digital sine wave signal based on the phase modulation signal and the amplitude modulation signal, respectively. A phase-amplitude converter that outputs a pair of predetermined weighting coefficients for the first and second parallelized digital sine wave signals, the second parallelized digital sine wave signal, and the pair of predetermined weighting coefficients. And a logic operation circuit that performs an operation.

  According to the present invention, a wireless communication circuit realizing low power consumption in a mobile wireless communication device can be obtained. Further, such a wireless communication circuit is suitable for mixed mounting with a digital circuit manufactured by CMOS technology or the like, and therefore can be superior in terms of manufacturing cost.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a block diagram which shows an example of IC for radio | wireless communication in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the digital phase modulator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating the parallel sine wave output by the numerical control oscillator of the digital phase modulator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the sub phase modulator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the parallel DAC in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows the other example of the parallel DAC in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating the noise shaping characteristic of the quantization noise in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the delta-sigma modulator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the delta-sigma modulator which has a parallel structure in IC for radio | wireless communication of the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram explaining an example of IC for radio | wireless communication in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the digital phase modulation / phase rotator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the sub phase modulation / phase rotator which comprises the digital phase modulation / phase rotator in the radio | wireless communication apparatus which concerns on one Embodiment of this invention. It is a figure which shows the spectrum of the transmission signal by the numerical calculation simulation about IC for radio | wireless communication based on this invention which employ | adopted the polar modulation system. It is a figure which shows the spectrum of the transmission signal by the numerical calculation simulation about IC for radio | wireless communication based on this invention which employ | adopted the polar modulation system. It is a figure which shows the spectrum of the transmission signal by the numerical calculation simulation about IC for radio | wireless communication based on this invention which employ | adopted the out fading modulation system. It is a figure which shows the spectrum of the transmission signal by the numerical calculation simulation about IC for radio | wireless communication based on this invention which employ | adopted the out fading modulation system. It is a block diagram which shows an example of the conventional radio | wireless transmission circuit using a polar modulation system. It is a block diagram which shows an example of the conventional radio | wireless transmission circuit using an out fading modulation system. It is a block diagram which shows an example of the conventional phase modulator using a closed loop phase modulation system. It is a block diagram which shows an example of the conventional phase modulator using an open loop phase modulation system. It is a block diagram which shows an example of the conventional differential type | mold analog phase interpolator.

  Next, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
The present embodiment discloses a digital communication mixed type wireless communication IC including a wireless transmission circuit using a polar modulation method.

  FIG. 1 is a block diagram illustrating an example of a wireless communication IC in a wireless communication apparatus according to an embodiment of the present invention. More specifically, the wireless communication IC 100 shown in the figure is a SoC in which a polar modulation type wireless transmission circuit and a logic synthesis circuit including a digital signal processing unit are mixedly mounted.

  As shown in the figure, the wireless communication IC 100 includes, for example, a clock generation unit 110, a logic synthesis unit 120, a transmission analog front end unit 130, and a reception analog front end unit 140.

  The clock generation unit 110 is a circuit for generating a clock having a certain frequency and supplying it to each component in the wireless communication IC 100. In this example, the clock generated by the clock generation unit 110 is supplied to the logic synthesis unit 120 and the transmission analog front end unit 130, respectively. The clock generation unit 110 includes, for example, a PLL circuit and an analog output oscillator, but is not limited thereto. For example, the clock generation unit 110 may be a clock by an external crystal oscillator or the like. It should be noted here that the clock generation unit 110 is independent of functions related to RF channel selection.

  The logic synthesis unit 120 is a digital circuit including a digital signal processing unit 121 including a baseband signal processing circuit, a modem circuit, and the like, and a digital phase modulator 122, for example. The digital signal processing unit 121 outputs the RF channel selection signal and the phase modulation signal to the digital phase modulator 122 during the transmission mode, and outputs the amplitude modulation signal to the digital-analog converter (DAC) of the analog front end unit 130 for transmission. To 131a. The digital phase modulator 122 determines the RF channel center frequency based on the RF channel selection signal, phase-modulates the digital sine wave signal according to the phase modulation signal, and transmits the phase-modulated sine wave signal to the analog front end unit 130 for transmission. To the DAC 131b.

  On the other hand, during the reception mode, the digital signal processing unit 121 supplies the RF channel selection signal to the digital phase modulator 122 while stopping the phase modulation function of the digital phase modulator 122. As a result, the digital phase modulator 122 outputs two digital sine wave signals having a frequency corresponding to the RF channel selection signal and having a phase shifted by 90 degrees to the DAC 131b and the DAC 131c, respectively. As will be described later, the two digital sine wave signals are analog-converted by the DAC 131b and the DAC 131c, and are supplied as a local sine wave signal LO to an orthogonal mixer (not shown) of the reception analog front end 140.

  The transmission analog front end unit 130 is an analog circuit including DACs 131a to 131c, a power amplifier 132, and switches 133a and 133b, for example. The transmission analog front end unit 130 operates by switching between the transmission mode and the reception mode by the switches 133a and 133b controlled by the logic synthesis unit 120. That is, when the switch 133a is in the open state and the switch 133b is in the closed state, the transmission analog front end unit 130 operates in the transmission mode, and when the switch 133a is in the closed state and the switch 133b is in the open state, the wireless communication IC 100 Operates in receive mode.

  The DACs 131a to 131c are circuits that convert input digital signals into analog signals and output the analog signals. The DAC 131 a converts the digital amplitude modulation signal output from the digital signal processing unit 121 into an analog signal and outputs the analog signal to the power amplifier 132. In the transmission mode, the DAC 131 b converts the digital phase modulation signal input from the digital phase modulator 122 into an analog signal and outputs the analog signal to the power amplifier 132. The power amplifier 132 generates and outputs an RF transmission signal based on the input analog amplitude modulation signal and analog phase modulated signal. Although not shown, the wireless communication IC 100 outputs from the digital signal processing unit 121 the latency until the amplitude modulation signal output from the digital signal processing unit 121 is input to the DAC 131a. It is configured to be the same as the latency until it is input to the DAC 131b via 122. That is, for example, a delay element is inserted in the path of the amplitude modulation signal so as to have the same delay as the digital phase modulator 122. Thereby, since the delay processing is performed digitally, an analog delay (non-constant group delay) can be avoided. In this example, the DAC 131c is used only during the reception mode. In this case, the DAC 131b and the DAC 131c convert the two digital sine wave signals output from the digital phase modulator 122 and having a phase shift of 90 degrees into analog sine wave signals. Therefore, it is preferable that the DACs 131b and 131c have the same configuration in consideration of circuit characteristics and the like.

  Although not shown, the transmission analog front-end unit 130 may include a reconstruction filter disposed on the output path of the DACs 131a to 131c.

  As the reception analog front end unit 140, a known one can be adopted, and although not shown, for example, a low noise amplifier (LNA), a quadrature mixer, a variable gain amplifier (VGA), and an analog digital converter (ADC).

  In this embodiment, as will be described later, at least the DACs 131b and 131c are configured to include a plurality of DACs configured in parallel. Therefore, the digital phase modulator 122 is also configured to include a plurality of digital phase modulators configured in parallel so that the DACs configured in parallel function effectively. Hereinafter, such DACs 131b and 131c may be referred to as “parallelized DACs”. The DAC 131a is also preferably parallelized in order to match the operation with the DAC 131b.

  FIG. 2 is a block diagram showing an example of a digital phase modulator in the wireless communication apparatus according to the embodiment of the present invention. As shown in the figure, the digital phase modulator 122 includes, for example, four sub-phase modulators 122 (0) to 122 (3). In the figure, for the sake of convenience, a parallel DAC 131 (ie, corresponding to the DAC 131b) connected to the digital phase modulator 122 is also shown. The parallel DAC 131 in this example is a Nyquist DAC (parallel Nyquist DAC). The configuration shown in the figure is sometimes called a digital phase interpolator. Details of the parallel Nyquist DAC will be described with reference to FIG.

  The sub-phase modulators 122 (0) to 122 (3) are each configured to operate with a clock having a frequency that is ¼ of the original sampling frequency Fs, and generate parallel phase-modulated sinusoidal signals. ,Output. The sub-phase modulators 122 (0) to (3) may have the same configuration. In this specification, the sub-phase modulators 122 (0) to (3) are referred to as the sub-phase modulators 122 (i) unless particularly distinguished. Each of the parallel sine wave signals is generated so that their amplitude values complement each other in time with respect to each other, for example, as shown in FIG. In order to generate such a parallel sine wave signal, each of the sub-phase modulators 122 (0) to 122 (3) oscillates a digital sine wave signal whose phases are shifted from each other by 90 degrees. A numerically controlled oscillator) (see FIG. 4).

  In this example, the digital phase modulator 122 is composed of four sub-phase modulators 122 (0) to 122 (3). However, the present invention is not limited to this, and for example, two digital phase modulators 122 There may be eight or more sub-phase modulators.

  FIG. 4 is a block diagram showing an example of a sub-phase modulator constituting the digital phase modulator in the wireless communication apparatus according to the embodiment of the present invention. As shown in the figure, the sub-phase modulator 122 (i) of this embodiment includes, for example, a first numerically controlled oscillator 1221a and a second numerically controlled oscillator 1221b, a phase amplitude converter 1222, and a digital multiplier. 1223a and 1223b, a digital adder 1224, and a multiplexer 1225 are included.

  The first numerically controlled oscillator 1221a and the second numerically controlled oscillator 1221b have a frequency according to the RF channel selection signal output from the digital signal processing unit 121. When viewed in relation to each other, 0 degrees and 90 degrees, respectively. Outputs a digital sine wave with a phase of degrees. The first numerically controlled oscillator 1221a and the second numerically controlled oscillator 1221b are configured to include, for example, a look-up table based on element values of a sine wave, and output a digital sine wave by sequentially reading the element values according to a clock. To do. Alternatively, it may be based on the CORDIC algorithm.

  For example, the numerically controlled oscillators 1221a and 1221b are set so that the output control circulates (updates) in N clocks, and further, a sine wave signal is generated 4M + 1 times in the N clocks according to the RF channel selection signal M (however, M Is a positive integer). With such a configuration, a sine wave signal is output M + 1/4 times at the N / 4 clock. That is, regardless of the value of the RF channel selection signal M, a value shifted by ¼ period from the original sine wave signal is output at the N / 4 clock. Accordingly, if the second numerically controlled oscillator 1221b is configured to oscillate with a shift of N / 4 clocks relative to the first numerically controlled oscillator 1221a, these outputs have two phases that are 90 degrees out of phase with each other. Sine wave signal.

  As described above, since the sub-phase modulators 122 (0) to 122 (3) are configured in parallel, a corresponding sine wave signal is also generated between the sub-phase modulators 122 (0) to 122 (3). The phase is shifted by 90 degrees, that is, the amplitude values of the corresponding sine wave signals complement each other in time with the other amplitude values. That is, when viewed between the first numerically controlled oscillators 1221a and the second numerically controlled oscillators 1221b in the sub-phase modulator 122 (i), sine wave signals whose phases are shifted by 90 degrees are output. .

The phase / amplitude converter 1222 performs a predetermined phase / amplitude conversion on the phase modulation signal output from the digital signal processing unit 121, and outputs weighting coefficients a1 [n] and a2 [n]. The predetermined phase / amplitude conversion is defined by, for example, Expression 4 where the phase modulation signal is PH [n].
<Formula 4>
a1 [n] = cos (PH [n])
a2 [n] = sin (PH [n])

  The weighting coefficients a1 [n] and a2 [n] obtained by the phase / amplitude converter 1222 are output to the digital multipliers 1223a and 1223b, respectively. The digital multiplier 1223a multiplies the weighting coefficient a1 [n] by the digital sine wave signal having a phase of 0 degree, and outputs the weighted first digital sine wave signal to the digital adder 1224, while the digital multiplier 1223b. Multiplies the weighting coefficient a2 [n] by the digital sine wave signal having a phase of 90 degrees, and outputs the weighted second digital sine wave signal to the digital adder 1224. The digital adder 1224 adds the multiplied sine wave signals and outputs the result to the multiplexer 1225 as a phase-modulated sine wave signal. The multiplexer 1225 outputs the phase-modulated sine wave signal to the DAC 131b of the transmission analog front end unit 130 during the transmission mode, while it is not phase-modulated during the reception mode, that is, pure digital. A sine wave signal is output to the DAC 131b. That is, during the reception mode, two digital sine wave signals shifted by 90 degrees and output from the first numerically controlled oscillator 1221a and the second numerically controlled oscillator 1221b are output as they are. As described above, the two digital sine wave signals are output as local sine wave signals LO to the quadrature mixer of the reception analog front end unit 140.

  The phase / amplitude converter 1222 is not limited to the above configuration, and may be realized by other configurations as long as the above Expression 4 is satisfied. For example, the phase amplitude converter 1222 may also be configured to read out the weighting factors a1 [n] and a2 [n] corresponding to the phase modulation signal PH [n] using a lookup table.

  FIG. 5 is a block diagram showing an example of a parallel DAC in the wireless communication apparatus according to the embodiment of the present invention. Specifically, this figure shows an example in which the DAC 131b of the transmission analog front end unit 130 is configured as a Nyquist parallelized DAC.

  That is, the parallelized Nyquist DAC 500 shown in the figure includes a digital filter 510, a plurality of sub DACs 520 (0) to 520 (3) configured in parallel, and an analog adder 530. The digital filter 510 performs a predetermined filtering calculation process on the input digital signal x [n] (that is, a phase-modulated sine wave signal), and outputs an output signal y [n]. The output signal y [n] is input to the sub DACs 520 (0) to 520 (3). Note that the argument “n” indicates a serial number of the entire digital data string, and “m” in the figure indicates a serial number of a data string of four data, for example, when parallel data processing is performed.

Specifically, the digital filter 510 of the present embodiment is a circuit designed to satisfy the following formula 5. In the figure, an element represented by z ₄ ⁻¹ represents one clock delay with respect to a clock having a frequency that is ¼ of the original sampling frequency Fs.
<Formula 5>
y [n] = x [n] -x [n-1] + y [n-4]

In addition, the said Formula 5 is derived as follows. That is, the relationship between the input signal x [n] and the output signal y [n] can be expressed by Equation 6 below.
<Formula 6>
x [n] = y [n] + y [n-1] + y [n-2] + y [n-3]

Further, when the rank of n is lowered by 1 with respect to Equation 6, the following Equation 7 is obtained.
<Formula 7>
x [n-1] = y [n-1] + y [n-2] + y [n-3] + y [n-4]

  Therefore, by subtracting Expression 7 from Expression 6, the above Expression 5 is obtained.

  In this embodiment, the signal y [n] arithmetically processed by the digital filter 510 is subjected to digital-analog conversion in each of the four sub DACs 520 in this embodiment. In this case, the sampling frequency of each of the sub DACs 520 (0) to 520 (3) may be ¼ of the original sampling frequency Fs. Further, each of the sub DACs 520 (0) to 520 (3) samples with clocks whose phases are shifted by 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. Here, each output by the sub DACs 520 (0) to 520 (3) keeps the output of the same value for a period four times the original sampling period 1 / Fs, and therefore the input signal x [n ] Cannot be used to obtain desired analog data. However, the desired result can be obtained by using the output signal y [n] processed by the digital filter 510 as described above.

  As is clear from Equation 5 above, the total value from y [n−3] to y [n] is a value represented by x [n]. There is a risk of divergence over time. For this reason, the digital filter 510 is not shown in the figure, but after repeating the calculation process of Equation 7, any one of the absolute values from y [n] to y [n-3] has a predetermined upper limit value, for example. A circuit that redistributes as a small absolute value from y [n−3] to y [n] according to the value of x [n] may be included. Such a circuit is disposed, for example, before the sub DACs 520 (0) to 520 (3).

  Thus, in the present embodiment, the DAC 131b is configured as the parallel Nyquist DAC 500, so that a practical analog / digital mixed SoC can be realized. That is, considering the RF transmission band used by a general wireless communication apparatus, the sampling frequency Fs of the RF signal is at least several GHz. Therefore, the corresponding DAC is difficult to manufacture and very expensive. It becomes. However, in this embodiment, since the plurality of sub-DACs are configured in parallel, each sub-DAC only needs to operate at a low sampling frequency corresponding to the number of parallels, so that the mounting can be facilitated. Become.

  In the present embodiment, the digital filter 510 is configured as a part of the parallel DAC 131. However, the present invention is not limited to this. For example, the digital filter 510 is configured as a part of the digital phase modulator 122. May be. Alternatively, the digital filter 510 may be arranged between the digital phase modulator 122 and the parallel DAC 131 as an independent component.

(Modification)
Next, a modified example of the above-described embodiment will be described. In this modification, in order to further reduce the power consumption of the wireless communication IC 100, a DAC 131 (parallelized DAC) configured as a bandpass ΔΣ DAC is disclosed.

  FIG. 6 is a block diagram showing an example of a bandpass ΣΔDAC in the wireless communication apparatus according to one embodiment of the present invention. As shown in the figure, the band-pass ΔΣ DAC 600 includes a band-pass ΔΣ modulator 610 disposed in front of the Nyquist DAC 500 shown in FIG. The band pass ΔΣ DAC 600 can be applied to the parallel DAC 131 shown in FIG. In this example, for convenience of explanation, the output signal (phase-modulated sine wave signal) from the digital phase modulator 122 is replaced with x [4m] to x [4m-3], and w [4m] to w [4m−]. 3] and the output signal of the bandpass ΔΣ modulator 610 is expressed as x [4m] to x [4m−3]. In the band pass ΔΣ DAC 600 shown in the figure, each sub DAC operates with a clock having a frequency that is ¼ of the original sampling frequency Fs, by a 4-parallel configuration.

  The bandpass ΔΣ modulator 610 of this example has a function of passing only digital signals in the RF transmission band. This means that the DACs 131b and 131c need to directly digital-analog convert signals having the frequency spectrum in the RF transmission band, and therefore the effect of noise shaping characteristics of quantization noise by the bandpass ΔΣ modulator is maximized. This is so that you can receive a limit.

  Here, the noise shaping characteristic of the quantization noise by the bandpass ΔΣ modulator will be described.

The input data to the bandpass ΔΣ modulator, the output data from the bandpass ΔΣ modulator, and the quantization noise generated by the quantizer in the bandpass ΔΣ modulator are respectively w [n], x [n], and e [ n], the input / output transfer function of the first fourth-order bandpass filter is expressed by the following Expression 8.
<Formula 8>
x [n] = w [n] + (1 / (1 + 2 * z ⁻² + z ⁻⁴ )) * e [n]
Here, z ⁻¹ represents a delay of one clock with respect to the original sampling frequency Fs in the bandpass ΔΣ modulator.

  FIG. 7A schematically shows the frequency characteristics of the transfer function for e [n] in the above equation 8. At this time, e [n] indicates not the white noise characteristic but the colored noise characteristic as illustrated. Since this colored noise becomes 0 in the vicinity of the ¼ frequency band of the entire sampling frequency Fs of the bandpass ΔΣ modulator, a desired signal is transmitted using this frequency band as an RF transmission band. In addition, noise having a large power in a frequency band other than the RF transmission band is removed by using an analog bandpass filter in the analog region of the transmission analog front end unit 130.

FIG. 7B shows the pole arrangement in the Z plane of the transfer function for e [n] in the above equation 8. As shown in FIG. 5B, this transfer function has a double pole at each of the positions of π / 2 and −π / 2 on the unit circle, and has a total of four poles. However, when the poles are arranged in this way, even if a large power noise in a frequency band other than the RF transmission band as shown in FIG. There are still cases where the spectrum mask regulations stipulated by the Radio Law etc. are not satisfied. Alternatively, an expensive analog bandpass filter having high noise removal performance that satisfies this spectrum mask specification may be required. Therefore, in this embodiment, the ΔΣ modulator 610 in which the input / output transfer function shown in the above equation 8 is corrected as shown in the following equation 9 which is the input / output transfer function of the second fourth-order bandpass ΔΣ modulator. By using, noise shaping of quantization noise is more effectively realized.
<Formula 9>
x [n] = w [n] + (1 / (1+ (2cos 2θ) * z ⁻² + z ⁻⁴ )) * e [n]

  At this time, the frequency characteristic of the transfer function for e [n] in the above equation 9 is corrected as shown in FIG. 9C, and as shown in FIG. They are arranged at π / 2 ± θ and −π / 2 ± θ. As shown in FIG. 5C, part of the noise power leaks to the RF transmission band, while the noise power in the frequency band other than the RF transmission band is reduced. Therefore, by using such a bandpass ΔΣ modulator, it becomes possible to satisfy the spectrum mask rule defined by the Radio Law or the like without using an expensive analog bandpass filter.

  In view of the above, FIG. 8 shows an error feedback type bandpass ΔΣ modulator in which Equation 9 is implemented as a digital circuit. As shown in the figure, the bandpass ΔΣ modulator 610 includes adders 801a to 801c, a quantizer 802, delay circuits 803a to 803d, a multiplier 804, and the like. In the figure, a phase-modulated sine wave signal w [n] as an input signal is added with feedback delay data including a quantization error by an adder 801a. The quantizer 802 is a multi-bit quantizer.

  In consideration of the fact that the RF transmission band is in the vicinity of the frequency Fs / 4, the sampling frequency Fs of the clock for operating the bandpass ΔΣ modulator having such a circuit configuration is at least several GHz. It is difficult to use a semiconductor manufacturing process such as CMOS technology. Therefore, in this modification, a bandpass ΔΣ modulator 610 having a parallel configuration having an input / output relationship equivalent to the circuit shown in FIG. 8 is proposed.

  FIG. 9 is a block diagram illustrating an example of a bandpass ΔΣ modulator having a parallel configuration in a wireless communication IC of a wireless communication apparatus according to an embodiment of the present invention. As shown in the figure, the bandpass ΔΣ modulator 610 processes the phase-modulated sinusoidal signals w [4m−3] to w [4m], which are four consecutive input signals, in parallel, and generates a signal x [ 4m-3] to x [4m] are output. Since the band-pass ΔΣ modulator 610 includes four sub-modulators configured in parallel, if each sub-modulator operates with a clock having a frequency ¼ of the original sampling frequency Fs. It ’s enough. When θ = 0 is set, 2 cos 2θ = 2 is established, and the bandpass ΔΣ modulator 610 satisfies the relational expression of Expression 8 above. In other words, the bandpass ΔΣ modulator 610 shown in FIG. 9 is a circuit that includes not only the above formula 9 but also the implementation of the above formula 8.

  As described above, according to the present embodiment, in the polar modulation type radio communication IC 100, the phase modulation signal and the amplitude modulation signal are designed to have the same digital delay value in each path. , Delay value mismatch does not occur, and therefore there is no need to provide a calibration mechanism. Further, in the wireless communication IC 100, since the RF channel selection is performed in the digital phase adjuster 122 instead of the RF channel selection in the loop including the analog output oscillator and the PLL circuit, the conventional wireless communication IC 100 is provided. The frequency synthesizer that is essential in the communication apparatus is no longer necessary, and only the clock generation unit 110 that generates a clock having a constant frequency is required. As a result, the entire wireless communication IC 100 can be easily mounted, the circuit area can be reduced, and power consumption can be reduced. Furthermore, since the clock generation unit 110 only generates a clock with a constant frequency, it is irrelevant to satisfying the specified values of ACPR and EVM in the target wireless communication standard, and the startup time can be shortened. Therefore, power consumption can be reduced.

  Also, the digital phase modulator 122 of this embodiment uses the weighting coefficients a1 [n] and a2 [n] for the amplitudes of two digitally generated sinusoidal signals having different phases (0 degrees and 90 degrees). After the digital multiplication, the two are further added, so that the problem of deterioration of linearity with respect to the phase rotation as seen in the conventional analog phase interpolator does not occur. Further, the digital phase modulator 122 can easily increase the resolution as necessary by increasing the number of bits of the multiplier. That is, this increase in resolution means that any phase from 0 degrees to 360 degrees can be easily selected. Therefore, if there is a possibility that distortion due to nonlinearity of a circuit inherent in the wireless communication IC 100 does not satisfy the specified value of ACPR or EVM of the target wireless communication standard, the resolution of the quantizer is increased, or By taking measures such as increasing the resolution of the input modulated digital sine wave signal w [n], the performance of the wireless communication IC 100 can be easily optimized.

  Further, the sub-phase converter 122 (i) constituting the digital phase modulator 122 digitally generates two sine waves with a shift of N / 4 clocks when the two numerically controlled oscillators 1221 have N clocks / cycle. Therefore, an ideal sine wave having phases shifted from each other by 90 degrees can be obtained without being affected by the PVT fluctuation.

  Further, according to the present embodiment, the Nyquist DAC 500 is configured to include the sub DACs 520 configured in parallel. Therefore, it is sufficient that each sub DAC 520 operates at a frequency that is 1/4 of the sampling frequency Fs. As a result, the mounting can be facilitated.

  Furthermore, according to the present embodiment, since the bandpass ΔΣDAC 600 includes the parallelized bandpass ΔΣ modulator 610, the noise shaping characteristics of the quantization noise can be used effectively, and the subsequent stage By reducing the clock frequency for each of the sub DACs 520, power consumption can be reduced.

  Further, according to the present embodiment, since the digital phase modulator 122 and the DAC 131 are parallelized in the wireless communication IC 100, it is possible to mount a circuit composed of standard primitive cells using the RTL logic synthesis method.

[Second Embodiment]
This embodiment discloses a digital communication mixed type wireless communication IC including a wireless transmission circuit using an out-fading modulation method.

  FIG. 10 is a block diagram illustrating an example of a wireless communication IC in the wireless communication apparatus according to the embodiment of the present invention. More specifically, the wireless communication IC 200 shown in the figure is an SoC in which an out-fading modulation type wireless transmission circuit and a logic synthesis circuit including a digital signal processing unit are mixedly mounted.

  As shown in the figure, the wireless communication IC 200 includes, for example, a clock generation unit 210, a logic synthesis unit 220, a transmission analog front end unit 230, and a reception analog front end unit 240.

  The logic synthesis unit 220 is a digital circuit including a digital signal processing unit 221 including a baseband signal processing circuit, a modem circuit, and the like, and a digital phase modulation / phase rotator 222, for example.

  The clock generation unit 210 is a circuit for generating a clock having a certain frequency and supplying it to each component in the wireless communication IC 200. For example, the clock generation unit 210 can be configured by the same as the clock generation unit 110 described above. Also in this embodiment, the clock generation unit 210 is independent of the RF channel selection function.

  The digital signal processing unit 221 outputs the RF channel selection signal, the phase modulation signal, and the amplitude modulation signal to the digital phase modulation / phase rotator 222 during the transmission mode. The digital phase modulation / phase rotator 222 determines the RF channel center frequency based on the RF channel selection signal, modulates the digital sine wave by the phase modulation signal and the amplitude modulation signal, and transmits the modulated digital sine wave signal. The data is output to the DAC 231a and the DAC 231b of the analog front end unit 230.

  On the other hand, during the reception mode, the digital signal processing unit 221 supplies the RF channel selection signal to the digital phase modulation / phase rotator 222, while stopping both the phase modulation and phase rotation functions of the digital phase modulation / phase rotator 222. Let In this case, the digital phase modulation / phase rotator 222 outputs, to the DAC 231a and the DAC 231b, two digital sine wave signals having a frequency corresponding to the RF channel selection signal and having a phase shifted by 90 degrees. The two digital sine wave signals are converted into analog signals and supplied to a quadrature mixer (not shown) of the reception analog front end 240 as a local sine wave signal LO.

  The transmission analog front end unit 230 is an analog circuit including a pair of DACs 231a and 231b, a pair of power amplifiers 232a and 232b, a power combiner 233, and switches 234a and 234b, for example. The transmission analog front end unit 230 operates by switching between a transmission mode and a reception mode by switches 234a and 234b controlled by the logic synthesis unit 220. That is, when the switch 234a is in the open state and the switch 234b is in the closed state, the transmission analog front end unit 230 operates in the transmission mode, and when the switch 234a is in the closed state and the switch 234b is in the open state, the wireless communication IC 200 Operates in receive mode.

  The DACs 231a and 231b are circuits that convert an input digital signal into an analog signal and output the analog signal. The DACs 231a and 231b convert the digital sine wave signal input from the digital phase modulation / phase rotator 222 into an analog signal and output the analog signal to the power amplifiers 232a and 232b, respectively.

  The power amplifiers 232a and 232b amplify the input analog signals and output them to the power combiner 233. The power combiner 233 adds the amplified analog signals and outputs the result as an RF transmission signal.

  Although not shown, the transmission analog front end unit 230 may include a reconstruction filter arranged on the output paths of the DACs 231a and 231b.

  As the reception analog front end unit 240, a known one can be adopted. Although not shown, for example, a low noise amplifier (LNA), a quadrature mixer, a variable gain amplifier (VGA), and an analog / digital converter are used. (ADC).

  FIG. 11 is a block diagram showing an example of a digital phase modulation / phase rotator in the wireless communication apparatus according to the embodiment of the present invention. As shown in the figure, the digital phase modulation / phase rotator 222 includes, for example, four sub-phase modulation / phase rotators 222 (0) to 222 (3). In the figure, for convenience, two parallelized DACs 231 (that is, DACs 231a and 231b) connected to the digital phase modulation / phase rotator 222 are also shown. As the parallel DAC, for example, the one shown in FIG. 5 or 6 can be applied. Note that the notations w [4m-3], w [4m-2], w [4m-1], and w [4m] shown in FIG. 6 are w1 [4m-3] and w1 [4m-] in FIG. 2], w1 [4m-1], w1 [4m] and w2 [4m-3], w2 [4m-2], w2 [4m-1], w2 [4m].

  The sub-phase modulation / phase rotators 222 (0) to 222 (3) are each configured to operate with a clock having a frequency that is ¼ of the original sampling frequency Fs. Each of the sub-phase modulation / phase rotators 222 (0) to 222 (3) generates a pair of digital signals whose phases are shifted by 90 degrees, and outputs each of the pair of digital signals to the pair of parallel DACs 231. . That is, each of the pair of parallel DACs 231 receives a pair of digital signals w1 [n] and w2 [n] generated by each of the sub-phase modulation / phase rotators 222 (0) to 222 (3). Composed.

  The sub-phase modulation / phase rotators 222 (0) to 222 (3) may have the same configuration, and are referred to as the sub-phase modulation / phase rotator 222 (i) when it is not necessary to distinguish between them. . Each of the parallel digital sine wave signals is generated such that, for example, as shown in FIG. 3, the amplitude values complement each other in time with other amplitude values. In order to generate such a parallel digital sine wave signal, each of the sub-phase modulation / phase rotators 222 (0) to 222 (3) performs numerical control to oscillate a digital sine wave whose phase is shifted by 90 degrees. Consists of an oscillator.

  In this example, the digital phase modulation / phase rotator 222 is composed of four sub-phase modulation / phase rotators 222 (0) to 222 (3). However, the present invention is not limited to this. For example, the number may be two, or may be composed of eight or more sub-phase modulation / phase rotators.

  FIG. 12 is a block diagram showing an example of a sub-phase modulation / phase rotator constituting the digital phase modulation / phase rotator in the wireless communication apparatus according to the embodiment of the present invention. As shown in the figure, the sub-phase modulator 222 (i) of this embodiment includes, for example, a first numerically controlled oscillator 2221a and a second numerically controlled oscillator 2221b, a phase amplitude converter 2222, and a digital multiplier. 2223a to 2223d, digital adders 2224a and 2224b, and multiplexers 2225a and 2225b.

  The first numerically controlled oscillator 2221a and the second numerically controlled oscillator 2221b have frequencies according to the RF channel selection signal output from the digital signal processing unit 221, and are 0 ° and 90 °, respectively, when viewed in relation to each other. A digital sine wave signal having a phase of degree is output. The digital sine wave signal output from the first numerically controlled oscillator 2221a is branched and input to the corresponding multipliers 2223a and 2223c, while the digital sine wave signal output from the second numerically controlled oscillator 2221b is branched. Are input to the corresponding multipliers 2223b and 2223d. The first numerically controlled oscillator 2221a and the second numerically controlled oscillator 2221b may be the same as those in the first embodiment described above. Also, the phase of the corresponding sine wave is shifted by 90 degrees between the sub-phase modulation / phase rotators 222 (0) to 222 (3) configured in parallel, that is, the amplitude value of the corresponding sine wave is The first numerically controlled oscillator 2221a and the second numerically controlled oscillator 2221b are configured so as to complement each other in time with other amplitude values.

The phase / amplitude converter 2222 performs predetermined phase / amplitude conversion on the phase modulation signal and the amplitude modulation signal output from the digital signal processing unit 221 to perform weighting coefficients b1p [n], b2p [n], and b1m [ n] and b2m [n] are output. The predetermined phase / amplitude conversion is defined by, for example, Equation 10 where PH [n] is the phase modulation signal and ENV [n] is the amplitude modulation signal.
<Formula 10>
b1p [n] = cos (PH [n] + φ [n])
b2p [n] = sin (PH [n] + φ [n])
b1m [n] = cos (PH [n] −φ [n])
b2m [n] = sin (PH [n] −φ [n])
φ [n] = arccos (ENV [n] / 2A)
The weighting factors b1p [n] and b2p [n] are output to the digital multipliers 2223a and 2223b, respectively. On the other hand, the weighting factors b1m [n] and b2m [n] are output to the digital multipliers 2223c and 2223d, respectively.

  The digital multiplier 2223a multiplies the weighting coefficient b1p [n] by the digital sine wave of phase 0 degree and outputs the weighted first digital sine wave signal to the digital adder 2224a, while the digital multiplier 2223b The weighting coefficient b2p [n] is multiplied by the digital sine wave signal having a phase of 90 degrees, and the weighted second digital sine wave is output to the digital adder 2224a. The digital multiplier 2223c multiplies the weighting coefficient b1m [n] and the digital sine wave signal having a phase of 0 degrees, and outputs the weighted third digital sine wave signal to the digital adder 2224b, while performing digital multiplication. The multiplier 2223d multiplies the weighting coefficient b2m [n] by the digital sine wave signal having a phase of 90 degrees, and outputs the weighted fourth digital sine wave signal to the digital adder 2224b.

  The digital adder 2224a adds the multiplied signals and outputs the result to the multiplexer 2225a as a modulated digital sine wave signal. The multiplexer 2225a outputs the modulated digital sine wave signal to the DAC 231a of the transmitting analog front end unit 230 during the transmission mode, while it is not modulated during the reception mode, that is, a pure digital sine wave. The signal is output to the DAC 231a. The digital adder 2224b adds the multiplied signals and outputs the result to the multiplexer 2225b as a modulated digital sine wave signal. The multiplexer 2225b outputs the modulated digital sine wave signal to the DAC 231b of the analog front end unit 230 for transmission during the transmission mode, and outputs an unmodulated digital sine wave to the DAC 231b during the reception mode. To do. Thus, in the transmission mode, a modulated digital sine wave (more precisely, a parallel digital sine wave) whose phase is shifted by 90 degrees is output to the DAC 231a and the DAC 231b. .

  The phase / amplitude converter 2222 is not limited to the above-described configuration, and other configurations may be adopted as long as the above Expression 10 is satisfied. For example, the phase amplitude converter 2222 also uses the look-up table to weight the phase modulation signal PH [n] and the weight coefficients b1p [n] and b2p [n] and b1m [n] and b2m [corresponding to the amplitude modulation signal. n] may be read out.

  As described above, according to the present embodiment, in the radio communication IC 200 of the out-fading method, the phase modulation signal and the amplitude modulation signal have the same analog delay value in each path. Therefore, there is no need to provide a calibration mechanism. Further, in the wireless communication IC 200, since the RF channel selection is performed in the digital phase adjuster 222, not in the loop including the analog output oscillator and the PLL circuit, the conventional wireless communication IC 200 is provided. The frequency synthesizer that is essential in the communication apparatus is not necessary, and only the clock generation unit 210 that generates a clock with a constant frequency is required. As a result, the entire wireless communication IC 200 can be easily mounted, the circuit area can be reduced, and power consumption can be reduced. Furthermore, since the clock generation unit 210 only generates a clock having a constant frequency, it is irrelevant to satisfying the specified values of ACPR and EVM in the target wireless communication standard, and the startup time can be shortened. Therefore, power consumption can be reduced.

Moreover, according to this embodiment, since the digital phase modulation / phase rotator is used,
The amplitude of two digitally generated sinusoidal signals of different phases (0 degrees and 90 degrees) is digitally expressed using weighting factors b1p [n], b2p [n], b1m [n] and b2m [n]. Since the two are added after multiplication, the mismatch in phase rotation as seen in the conventional analog phase interpolator does not occur. Further, the digital phase modulation / rotator 222 can easily increase the resolution as necessary by increasing the number of bits of the multiplier.

(Simulation example)
The result by the simulation of the transmission signal supposing the OFDM system about the wireless communication IC according to the present invention configured as described above is shown.

(1) Polar Modulation Method FIGS. 13 and 14 are diagrams showing a spectrum of a transmission signal by a numerical calculation simulation for the wireless communication IC 100 according to the present invention that employs a polar modulation method. Specifically, FIG. 13 is a diagram illustrating a spectrum of a transmission signal when a sampling clock without jitter is used for the parallel DAC in the wireless communication IC 100 according to the present invention that employs a polar modulation method. . FIG. 14 is a diagram showing a spectrum of a transmission signal when a sampling clock in which random jitter is applied to a parallel DAC is used in the wireless communication IC 100 according to the present invention that employs a polar modulation method. Random jitter has a normal distribution with a standard deviation of about 10 psec.

The simulation conditions were as follows.
-In accordance with the output timing of the phase-modulated digital sine wave signal, the latency was given to the amplitude modulation signal and then input to the power amplifier. Note that the influence of the reconstruction filter is not considered.
・ The parallel configuration of each component is 4.
-The original sampling frequency Fs was 3.520 GHz. Therefore, each component configured in parallel was set to operate at 880 MHz.
The phase modulation signal and the amplitude modulation signal are updated once every 11 periods in the 880 MHz clock.
・ The numerically controlled oscillator outputs a 915 MHz sine wave.
The phase-modulated digital sine wave w [n] is 9 bits + signature 1 bit (1024 gradations).
The power amplifier of the transmission analog front end unit 130 has ideal linearity, and ideally multiplies the phase-modulated and analog-converted signal output by the amplitude-modulated signal.
The value of the coefficient 2cos2θ in the bandpass ΔΣ modulator is 1.875.
The multi-bit quantizer in the bandpass ΔΣ modulator has 7 gradations.
The power amplifier of the analog front end for transmission has ideal linearity and ideally multiplies the phase-modulated and analog-converted signal output by the amplitude-modulated signal.
The OFDM transmission signal uses an RF transmission band from 905 MHz to 94.6875 MHz, and has 64 subcarriers. At this time, the subcarrier interval is 0.3125 MHz.
In the transmission signal, a total of 52 subcarriers from the seventh to the 58th from the lowest frequency were used as active tones.
In the transmission signal, the 11th, 33rd, and 54th subcarriers from the lowest frequency are null tones (subcarriers having no data). This is to confirm the influence of nonlinearity of the power amplifier.
-Regarding the data pattern of the transmission signal, the modulation method of one subcarrier is QPSK, and the data of each subcarrier is random data.
-A second-order Butterworth analog bandpass filter having a passband in the vicinity of the RF transmission band is disposed immediately after output by the wireless communication IC 100 according to the present invention. Further, a third-order Butterworth analog low-pass filter having a cutoff frequency is arranged near 1.5 GHz.
-The point interval of Fast Fourier Transform (FFT) when evaluating the quality of the transmission signal was 2600 Hz coherent sampling.

  According to the result of the simulation according to the above conditions, as shown in FIG. 13, the transmission spectrum appears with distortion noise of about −30 dBc at the maximum. FIG. 14 shows a transmission spectrum when a sampling clock including random jitter is used. When comparing the transmission spectrum of FIG. 13 (in the case of no jitter) and FIG. 14 (in the case of jitter), FIG. Although there is a slight increase in the noise floor, it can be said that there is no big difference between the two as a whole. That is, the polar modulation type radio communication circuit according to the present invention has high resistance to random jitter. Therefore, the jitter performance required for the clock generation unit can be relaxed, so that the current consumption can be reduced.

  If there is a possibility that distortion due to nonlinearity of a circuit inherent in the wireless communication IC 100 does not satisfy the specified value of ACPR or EVM of the target wireless communication standard, the resolution of the quantizer is increased, or By taking measures such as increasing the resolution of the input modulated digital data w [n], the performance of the wireless communication IC 100 can be optimized.

  Further, in a frequency band far from the RF transmission band, the noise floor power may increase due to the noise shaping characteristics of the bandpass ΔΣ modulation. Therefore, when there is a possibility that this does not satisfy the spectrum mask stipulated in the Radio Law, etc., the value of 2 cos 2θ of the bandpass ΔΣ modulator is corrected, or the analog provided immediately after the output by the wireless communication IC 100 By appropriately adjusting the performance of the reconstruction filter, the performance of the wireless communication IC 100 can be optimized.

(2) Out-fading Modulation Method FIGS. 15 and 16 are diagrams showing the spectrum of a transmission signal by a numerical calculation simulation for the wireless communication IC 200 according to the present invention adopting the out-fading modulation method. Specifically, FIG. 15 is a diagram showing a spectrum of a transmission signal when a sampling clock having no jitter is used for the parallel DAC for the wireless communication IC 200 according to the present invention adopting the out-fading modulation method. is there. FIG. 16 is a diagram illustrating a spectrum of a transmission signal when a sampling clock in which random jitter is applied to a parallel DAC is used for the wireless communication IC 200 according to the present invention that employs the out-fading modulation method. . Similarly, the random jitter has a normal distribution with a standard deviation of about 10 psec.

The simulation conditions are the same as those of the polar modulation method described above except for the following points.
Each power amplifier 232a of the transmission analog front end unit 230 has ideal linearity.
-A second-order Butterworth analog bandpass filter having a passband in the vicinity of the RF transmission band is disposed immediately after output by the wireless communication IC 200 according to the present invention. Further, a third-order Butterworth analog low-pass filter having a cutoff frequency is arranged near 1.5 GHz.

  According to the result of the simulation according to the above condition, as shown in FIG. 15, the transmission spectrum appears with distortion noise of about -35 dBc at the maximum. FIG. 16 shows the transmission spectrum when a sampling clock including random jitter is used. When comparing the transmission spectrum of FIG. 15 (in the case of no jitter) and FIG. 16 (in the case of jitter), FIG. Although there is a slight increase in the noise floor, it can be said that there is no big difference between the two as a whole. That is, the out-fading modulation radio communication circuit according to the present invention has high resistance to random jitter. Therefore, the performance required for the clock generation unit can be relaxed, so that the current consumption can be reduced.

  If there is a possibility that distortion due to nonlinearity of the circuit inherent in IC 200 for wireless communication does not satisfy the specified values of ACPR or EVM of the target wireless communication standard, the resolution of the quantizer is increased, or By taking measures such as increasing the resolution of the input modulated digital data w [n], the performance of the wireless communication IC 200 can be optimized.

  Further, in a frequency band far from the RF transmission band, the noise floor power may increase due to the noise shaping characteristics of the bandpass ΔΣ modulation. Therefore, if there is a possibility that this does not satisfy the spectrum mask stipulated in the Radio Law, etc., the value of 2 cos 2θ of the bandpass ΔΣ modulator is corrected, or an analog provided immediately after output by the wireless communication IC 200 By appropriately adjusting the performance of the reconstruction filter, the performance of the wireless communication IC 200 can be optimized.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of wireless communication devices that employ wireless communication standards such as Wi-Fi.

100: IC for wireless communication
DESCRIPTION OF SYMBOLS 110 ... Clock generation part 120 ... Logic synthesis part 121 ... Digital signal processing part 122 ... Digital phase modulator 130 ... Analog front end part 131 for transmission ... Digital-analog converter (DAC)
132 ... Power amplifier 133 ... Switch 140 ... Reception analog front end unit 200 ... Wireless communication IC
210: clock generation unit 220 ... logic synthesis unit 221 ... digital signal processing unit 222 ... digital phase modulator 230 ... analog front end unit 231 for transmission ... digital-analog converter (DAC)
232 ... Power amplifier 233 ... Power combiner 234 ... Switch 240 ... Analog front end for reception

Claims (14)

An integrated circuit including a polar modulation type radio transmission circuit,
A clock generation circuit for generating a clock having a constant frequency;
Using the clock generated by the clock generation circuit, a predetermined digital sine wave signal according to the RF channel selection signal is phase-modulated based on the phase modulation signal based on the signal to be transmitted, and the phase-modulated digital sine wave A digital phase modulator that outputs a signal;
A DA converter that converts the phase-modulated digital sine wave signal into an analog sine wave signal using a clock generated by the clock generation circuit;
A power amplifier that amplifies the analog sine wave signal using an amplitude modulation signal based on the signal to be transmitted; and
The digital phase modulator is a parallelized digital phase modulator including a predetermined number of sub-phase modulators configured in parallel;
Each of the sub-phase modulators phase-modulates a parallel digital sine wave signal based on the phase modulation signal,
The DA converter is a parallelized DA converter including a predetermined number of sub DA converters configured in parallel.
The parallel DA converter performs analog conversion on the modulated parallel digital sine wave signal and outputs an analog sine wave signal.
Integrated circuit.   Each of the sub-phase modulators includes a numerically controlled oscillator that generates the parallelized digital sine wave signal such that each of the parallelized digital sine wave signals is in a time complementary relationship with each other. 1. The integrated circuit according to 1. Each numerically controlled oscillator of the sub-phase modulator is
A first numerically controlled oscillator for generating a first parallelized digital sine wave signal;
A second numerically controlled oscillator that generates a second parallelized digital sine wave signal that is 90 degrees out of phase with respect to the first parallelized digital sine wave;
Each of the sub-phase modulators further includes
A phase-amplitude converter that outputs a predetermined weighting factor for each of the first parallelized digital sine wave signal and the second parallelized digital sine wave signal based on the phase modulation signal;
A logic operation circuit that performs a logic operation based on the first parallelized digital sine wave signal and the second parallelized digital sine wave signal and the predetermined weighting factor,
The integrated circuit according to claim 2. The parallel DA converter further includes a digital filter that performs a predetermined filtering operation on the modulated parallel digital sine wave signal,
Each of the sub DA converters performs analog conversion on a corresponding signal among the output signals on which the predetermined filtering operation has been performed.
The integrated circuit according to claim 1. When the input signal x [n] and the output signal are y [n], the digital filter has the following equation regarding the input / output transfer function:
y [n] = x [n] -x [n-1] + y [n-4]
(Where n represents the overall signal consisting of a parallel digital sine wave signal)
A circuit configured to satisfy the relationship of
The integrated circuit according to claim 4.   5. The integrated circuit according to claim 4, wherein the parallel DA converter further includes a band pass ΔΣ modulator disposed in front of the digital filter. The bandpass ΔΣ modulator is configured such that the modulated parallel digital sine wave signal is w [n], the output signal to the digital filter is x [n], and the quantization noise is e [n], e [n]. When the angle constant that determines the position of the pole of the transfer function related to the noise shaping characteristic is θ (where 0 ° ≦ θ ≦ 90 °), the following equation regarding the input / output transfer function:
x [n] = w [n] + (1 / (1+ (2cos 2θ) * z ⁻² + z ⁻⁴ )) * e [n]
(Where n represents the overall signal consisting of a parallel digital sine wave signal)
A circuit configured to satisfy the relationship of
The integrated circuit according to claim 6.   The integrated circuit according to claim 1, further comprising a digital signal processing unit that outputs the phase modulation signal and the amplitude modulation signal based on the signal to be transmitted.   9. The integrated circuit according to claim 1, further comprising a receiving analog front end unit including a quadrature mixer.   The integrated circuit outputs a signal output from the DA converter to the power amplifier in a transmission mode, and outputs a signal output from the DA converter to the reception analog front end unit in a reception mode. The integrated circuit according to claim 9, further comprising a switch unit for controlling.   The integrated circuit according to claim 1, wherein the integrated circuit is a mixed digital / analog SoC. An integrated circuit including an out-fading wireless transmission circuit,
A clock generation circuit for generating a clock having a constant frequency;
Using a clock generated by the clock generation circuit, a phase modulated signal and an amplitude modulated signal based on a signal to be transmitted, in accordance with an RF channel selection signal, a pair of digital sine wave signals whose phases are shifted from each other by a predetermined rotation amount A digital phase modulation / phase rotator that respectively modulates based on the output and outputs the modulated pair of digital sine wave signals;
A pair of DA converters for converting the pair of modulated digital sine wave signals into analog sine wave signals, respectively, using the clock generated by the clock generation circuit;
The digital phase modulation / phase rotator is a parallel digital phase modulation / phase rotator including a predetermined number of sub-phase modulation / phase rotators configured in parallel;
Each of the sub-phase modulation / phase rotators modulates a pair of parallel digital sine wave signals based on the phase modulation signal and the amplitude modulation signal,
The DA converter is a parallelized DA converter including a predetermined number of sub DA converters configured in parallel.
The pair of parallel DA converters performs analog conversion on the modulated pair of parallel digital sine wave signals and outputs analog sine wave signals.
Integrated circuit.   Each of the sub-phase modulation / phase rotators includes a numerically controlled oscillator that generates the parallelized digital sine wave signal such that each of the parallelized digital sine wave signals is complementary in time to each other. The integrated circuit according to claim 12. Each numerically controlled oscillator of the sub-phase modulation / phase rotator is:
A first numerically controlled oscillator for generating a first parallelized digital sine wave signal;
A second numerically controlled oscillator that generates a second parallelized digital sine wave signal that is 90 degrees out of phase with respect to the first parallelized digital sine wave;
Each of the sub-phase modulation / phase rotators further includes
A phase-amplitude converter that outputs a pair of predetermined weighting factors for each of the first parallel digital sine wave signal and the second parallel digital sine wave signal based on the phase modulation signal and the amplitude modulation signal; ,
A logic operation circuit that performs a logic operation based on the first parallelized digital sine wave signal and the second parallelized digital sine wave signal and the pair of predetermined weighting factors,
The integrated circuit according to claim 13.