JP6105873B2 - Wafer processing method - Google Patents

Description

  The present invention relates to a method for processing a wafer on which a through electrode (Via electrode) is formed, and more particularly to a method for processing a wafer corresponding to downsizing.

  In recent years, as a three-dimensional mounting technique, development of a stacking technique for stacking a plurality of semiconductor chips and connecting the semiconductor chips, and a stacking technique for stacking a plurality of semiconductor wafers and connecting the semiconductor wafers is progressing. As this three-dimensional mounting technology, there is known a TSV (Through Silicon Via) process in which a Via electrode that penetrates a semiconductor chip or a semiconductor wafer is formed and the semiconductor chips or the semiconductor wafers are connected by the Via electrode (for example, Patent Literature 1). In the TSV process, compared to wire bonding, the connection length between semiconductor chips and between semiconductor wafers can be shortened by the Via electrode, and the apparatus can be miniaturized.

JP 2005-136187 A

  By the way, in the TSV process described in Patent Document 1, bumps are formed on the exposed portions of the Via electrodes on the surface of the semiconductor wafer, and the semiconductor wafer with the bumps is divided into individual semiconductor chips. In this case, there is a problem that it is difficult to divide the semiconductor wafer satisfactorily due to the influence of bumps and bumps and warpage of the semiconductor wafer. In the future, with the miniaturization of the apparatus, it is expected that the interval between the bumps on the semiconductor wafer will become narrower and it will become more difficult to divide the semiconductor wafer with bumps.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a wafer processing method capable of dividing a wafer having bumps on the surface in a TSV process.

The wafer processing method of the present invention includes a device region having a via electrode embedded on a surface of a semiconductor substrate by lines to be divided and embedded from the device electrode toward the back surface of the semiconductor substrate, and the device region. A wafer processing method in which a wafer having a chamfered portion in an outer peripheral surplus area surrounding the wafer is divided into individual devices, and a chamfered portion is formed by positioning a cutting blade in the outer peripheral surplus region and cutting to a predetermined depth to remove the chamfered portion. After the removing step and the chamfered portion removing step, the carrier plate arranging step of arranging the carrier plate on the surface of the wafer via the resin, and after the carrier plate arranging step, the depth of the Via electrode is adjusted from the back surface of the wafer. Via electrode detection process to detect, and after the Via electrode detection process, to the extent that the Via electrode is not exposed on the back surface A back grinding process for grinding and thinning the surface, and after the back grinding process, a laser beam having a wavelength that is transparent to the wafer from the back surface of the wafer is positioned in the interior corresponding to the division line. A modified layer forming step for forming the modified layer along the line to be divided, an etching step for etching the semiconductor substrate from the back surface of the wafer and projecting the Via electrode after the modified layer forming step, and the etching step Later, an insulating film coating process for coating the back surface of the wafer with an insulating film, and after the insulating film coating process, the Via electrode protruding from the back surface is cut and exposed from the insulating film, and the head of the Via electrode is flush with the insulating film. a finishing step of finishing the after the finishing process, a bump arranged step of disposing a bump on the head of the Via electrodes wafer modified layer is formed, after the bump arranged step A dividing step of dividing into individual devices along the surface of the wafer in the modified layer formed on the inside of external force is applied to the wafer and remove the carrier plate dividing line from configured.

  According to this configuration, since a laser beam having a wavelength that is transmissive to the wafer is irradiated before the insulating film is formed, a good modified layer can be formed without being affected by the insulating film. Further, since the wafer is supported by the carrier plate, it is possible to prevent problems caused by warpage of the wafer in the TSV process. In addition, a modified layer is formed inside the wafer along the planned division line before the bumps are arranged, and an external force is applied to the wafer along the modified layer after the bumps are arranged. Therefore, the wafer can be divided into individual devices satisfactorily without being affected by the bumps. In particular, in the wafer processing method of the present invention, since the modified layer is formed in the wafer before the bumps are arranged, the wafer can be divided well even when the interval between the bumps is narrow. In addition, since the depth of the Via electrode is detected before the modified layer is formed, the Via electrode is not erroneously detected by the modified layer.

  According to the present invention, by forming the modified layer inside the wafer before the bumps are disposed, the wafer having the bumps disposed on the surface in the TSV process can be favorably divided.

1 is an overall view of a wafer according to the present embodiment. It is a figure which shows an example of the chamfer part removal process which concerns on this Embodiment. It is a figure which shows an example of the carrier plate arrangement | positioning process which concerns on this Embodiment. It is a figure which shows an example of the Via electrode detection process which concerns on this Embodiment. It is a figure which shows an example of the back surface grinding process which concerns on this Embodiment. It is a figure which shows an example of the modified layer formation process which concerns on this Embodiment. It is a figure which shows an example of the etching process which concerns on this Embodiment. It is a figure which shows an example of the insulating film coating process which concerns on this Embodiment. It is a figure which shows an example of the finishing process which concerns on this Embodiment. It is a figure which shows an example of the bump arrangement | positioning process which concerns on this Embodiment. It is a figure which shows an example of the division | segmentation process which concerns on this Embodiment.

  The wafer processing method according to the present embodiment will be described with reference to the accompanying drawings. With reference to FIG. 1, a wafer on which a Via electrode to be processed is formed will be described. FIG. 1 is an overall view of a wafer. 1A shows a perspective view of the wafer, and FIG. 1B shows a cross-sectional view along the center line of the wafer.

  As shown in FIG. 1, the wafer W is configured by arranging a large number of devices 12 on a semiconductor substrate 11. The semiconductor substrate 11 is formed in a substantially disc shape, and is divided into a plurality of regions by grid-like division planned lines (not shown) arranged on the surface 13. In the center of the wafer W, a device 12 is formed in each region partitioned by the division planned lines. The surface 13 of the wafer W is divided into a device region 15 in which a plurality of devices 12 are formed and an outer peripheral surplus region 16 surrounding the device region 15. A chamfered portion 17 is formed in the outer peripheral surplus region 16 of the wafer W. A notch 18 indicating a crystal orientation is formed on the outer edge of the wafer W.

  In the device region 15 of the wafer W, a Via electrode 19 is embedded in the wafer W corresponding to each device 12. Each Via electrode 19 extends from the electrode of each device 12 toward the back surface 14 of the semiconductor substrate 11. The Via electrode 19 is formed slightly longer than the final finished thickness of the wafer W. The via electrode 19 is exposed from the back surface 14 of the wafer W when the wafer W is thinned to a finished thickness by grinding or CMP. A substantially spherical bump 21 (see FIG. 10) is formed on the exposed portion of the Via electrode. The wafer is not limited to a silicon wafer, and may be a semiconductor wafer such as gallium arsenide or silicon carbide.

  This wafer W includes a chamfered portion removing process, a carrier plate arranging process, a Via electrode detecting process, a back surface grinding process, a modified layer forming process, an etching process, an insulating film coating process, a finishing process, a bump arranging process, and a dividing process. It is processed after. In the chamfered portion removing step, the chamfered portion 17 formed on the outer periphery of the wafer W is removed by cutting (see FIG. 2). As a result, the chamfered portion 17 that can become a knife edge after the wafer W is thinned is removed from the outer periphery of the wafer W prior to grinding. In the carrier plate disposing step, the carrier plate 22 is disposed on the surface 13 of the wafer W via resin (see FIG. 3).

  In the Via electrode detection step, the depth from the back surface of the wafer W to the Via electrode 19 is detected (see FIG. 4). In the back surface grinding step, the back surface 14 of the wafer W is ground to the extent that the Via electrode 19 is not exposed from the back surface 14 of the wafer W based on the detection result of the Via electrode detection step (see FIG. 5). In the modified layer forming step, the modified layer 25 is formed inside the wafer W along the scheduled division line (see FIG. 6). In the etching process, the semiconductor substrate 11 is slightly etched, and the Via electrode 19 protrudes from the back surface 14 of the wafer W (see FIG. 7). In the insulating film coating step, the back surface of the wafer W is coated with the insulating film 27 in a state where the Via electrode 19 protrudes from the back surface 14 of the wafer W (see FIG. 8).

  In the finishing step, the back surface 14 of the wafer W covered with the insulating film 27 is polished by CMP, and the Via electrode 19 is exposed from the back surface 14 of the wafer W (see FIG. 9). In the bump disposing step, the bump 21 is disposed on the Via electrode 19 exposed from the back surface 14 of the wafer W (see FIG. 10). In the dividing step, an external force is applied to the modified layer 25, and the wafer W is divided into individual chips C along the division line (see FIG. 11). By such a series of processing, the wafer W can be divided into individual devices without being affected by the unevenness of the bumps 21 and the warpage of the wafer W.

  Hereinafter, a wafer processing method according to the present embodiment will be described in detail with reference to FIGS. 2 is a chamfered portion removing process, FIG. 3 is a carrier plate arranging process, FIG. 4 is a Via electrode detecting process, FIG. 5 is a back surface grinding process, FIG. 6 is a modified layer forming process, FIG. FIG. 9 is a diagram illustrating an example of an insulating film coating process, FIG. 9 is a finishing process, FIG. 10 is a bump disposing process, and FIG.

  As shown in FIG. 2, in the chamfered portion removing step, the wafer W is held on a chuck table 31 of a cutting device (not shown). The wafer W is held so that the surface 13 on the device 12 side faces upward and the center of the wafer W coincides with the rotation axis (Z axis) of the chuck table 31. The cutting blade 32 is positioned in the outer peripheral surplus area 16 (see FIG. 1A) of the wafer W so as to remove the chamfered portion 17 on the outer periphery of the wafer W. At this time, the rotation axis (Y axis) of the cutting blade 32 is aligned with the center line of the wafer W. Then, cutting water is ejected from an ejection nozzle (not shown) and the cutting blade 32 is rotated at a high speed, and the chamfered portion 17 of the wafer W is cut by the cutting blade 32.

  Subsequently, as the chuck table 31 rotates, the chamfered portion 17 on the upper side of the wafer W is cut, and a stepped groove 28 along the outer periphery of the wafer W is formed. In this case, the cutting blade 32 cuts deeper than the finished thickness in the back grinding process, which is a subsequent process. For this reason, the outer periphery of the wafer W after the back grinding process does not remain in a knife edge shape on the outer periphery of the wafer W. In addition, the rotation direction of the cutting blade 32 is set in a direction that causes a down cut with respect to the wafer W, and the cutting water containing cutting waste is prevented from being scattered on the wafer W.

  As shown in FIG. 3, a carrier plate disposing step is performed after the chamfered portion removing step. In the carrier plate arranging step, for example, the carrier plate 22 is arranged on the surface 13 of the wafer W by a liquid resin as an adhesive. The carrier plate 22 is formed in a disk shape from a highly rigid material such as glass, metal, ceramics, or rigid resin. The carrier plate 22 can stably support the wafer W thinned to 100 μm or less. In addition, since the warpage of the wafer W is suppressed by the carrier plate 22, problems due to the warpage of the wafer W in the subsequent process can be prevented.

  For example, the carrier plate 22 is formed with a thickness of 0.5 mm to 1.5 mm in the case of glass and ceramics, and 0.3 mm to 1.0 mm in the case of metal (for example, stainless steel). The adhesive is not particularly limited, and an ultraviolet curable resin, a thermosetting resin, a wax, or the like may be used depending on the material of the carrier plate 22. Further, the carrier plate disposing step may be performed by a dedicated device, or may be performed manually by an operator. Further, the carrier plate 22 only needs to be able to stably support the entire wafer W, and may be formed in a rectangular shape as well as a disk shape.

  As shown in FIG. 4, a Via electrode detection step is performed after the carrier plate placement step. In the Via electrode detection process, the wafer W is held on the chuck table 35 of the grinding device (not shown) via the carrier plate 22. A contact-type detector 36 is positioned above the wafer W. By irradiating light of a wavelength having transparency to the semiconductor substrate 11 (silicon) from the detector 36, the depth from the back surface 14 of the wafer W to the tip 29 of the Via electrode 19 is detected. The depth of the Via electrode 19 of each device 12 is detected by moving the detector 36 relative to the wafer W.

  As the detector 36 of the present embodiment, a liquid immersion type non-contact gauge is used, but any configuration may be used as long as the depth of the Via electrode 19 can be detected. By using a liquid immersion type non-contact gauge as the detector 36, it is not affected by the grinding water in the grinding apparatus. The detector 36 may be provided in the grinding device as in the present embodiment, or may be provided in a dedicated device for the Via electrode detection process. In the present embodiment, by using the detector 36 of the grinding device, the Via electrode detection process and the back surface grinding process can be continuously performed. Further, since the Via electrode 19 is detected before the modified layer 25 (see FIG. 6) is formed inside the wafer W, the modified layer 25 is not erroneously detected as the Via electrode 19.

  As shown in FIG. 5, a back surface grinding process is performed after the Via electrode detection process. In the back grinding process, the grinding unit 37 is positioned above the wafer W held on the chuck table 35. Then, the grinding wheel 38 of the grinding unit 37 approaches the chuck table 35 while rotating around the Z axis, and the wafer W is ground by rotating and contacting the grinding wheel 38 and the back surface 14 of the wafer W in parallel. During grinding, the thickness of the wafer W is measured in real time by a height gauge (not shown). Here, the target finishing thickness of the wafer W is set based on the detection result in the Via electrode detection step. The feed amount of the grinding unit 37 is controlled so that the measurement result of the height gauge approaches the finished thickness, and the wafer W is ground to such an extent that the tip 29 of the Via electrode 19 is not exposed from the back surface 14.

  When the wafer W is ground to the vicinity of the tip 29 of the Via electrode 19 by the grinding wheel 38, the grinding process by the grinding unit 37 is stopped. At this time, since the chamfered portion 17 (see FIG. 2) on the outer periphery of the wafer W is removed in advance in the chamfered portion removing step, the chamfered portion 17 remains on the outer periphery of the wafer W and is not formed in a knife edge shape. Therefore, chipping hardly occurs on the outer periphery of the thinned wafer W. Further, since the wafer W is supported by the carrier plate 22, even when the wafer W is thinned and the rigidity is lowered in the back surface grinding process, handling of the wafer W during transportation becomes easy.

  As shown in FIG. 6, the modified layer forming step is performed after the back grinding step. In the modified layer forming step, the wafer W is held via the carrier plate 22 on the chuck table 45 of a laser processing apparatus (not shown). Further, the exit of the processing head 46 is positioned on the division line of the wafer W, and a laser beam is irradiated from the back surface 14 side of the wafer W by the processing head 46. The laser beam has a wavelength that is transparent to the wafer W, and is adjusted so as to be condensed inside the wafer W. Then, the processing layer 46 is moved relative to the wafer W while the condensing point of the laser beam is adjusted, so that the modified layer 25 along the planned division line is formed inside the wafer W.

  In this case, first, the condensing point is adjusted near the surface 13 of the wafer W, and laser processing is performed so that the lower end portion of the modified layer 25 is formed along all the division lines. Then, each time the height of the condensing point is moved upward, the laser processing is repeated along the scheduled division line, so that the modified layer 25 having a predetermined thickness is formed inside the wafer W. In this way, a division starting point along the division planned line is formed inside the wafer W. In the present embodiment, since the division starting point is formed on the wafer W before the bump 21 (see FIG. 10) is arranged, the bump 21 can be divided without being affected by the unevenness of the bump 21 after the bump is arranged.

  The modified layer 25 refers to a region where the internal density, refractive index, mechanical strength, and other physical characteristics of the wafer W are different from the surroundings due to the irradiation of the laser beam, and the strength is lower than the surroundings. . The modified layer 25 is, for example, a melt treatment region, a crack region, a dielectric breakdown region, or a refractive index change region, and may be a region where these are mixed.

  As shown in FIG. 7, an etching process is performed after the modified layer forming process. In the etching process, the wafer W is held on the chuck table 41 of the etching apparatus (not shown) via the carrier plate 22. Then, an etching gas is sprayed toward the back surface 14 of the wafer W, and the etching gas is turned into plasma, whereby the back surface 14 of the wafer W is etched. As a result, only the semiconductor substrate 11 (silicon) of the wafer W is removed by several μm, and the tip 29 of the Via electrode 19 slightly protrudes from the back surface 14 of the wafer W. The grinding distortion generated on the back surface 14 of the wafer W in the back surface grinding step is removed by the etching step.

  In the etching process, etching may be performed so that the tip 29 of the Via electrode 19 protrudes from the back surface 14 of the wafer W, and is not limited to plasma etching. In the etching step, for example, the back surface 14 of the wafer W may be etched by wet etching. In the present embodiment, after the depth of the Via electrode 19 is measured in the Via electrode detection step, the grinding amount in the back surface grinding step is adjusted, so that the etching amount can be kept to a minimum.

As shown in FIG. 8, an insulating film coating step is performed after the etching step. In the insulating film coating step, the wafer W is held on the table 51 of the film forming apparatus (not shown) via the carrier plate 22. When the wafer W on the table 51 is heated in an oxygen atmosphere, the back surface 14 and the tip 29 of the Via electrode 19 are oxidized, and an insulating film 27 is formed. Note that a nitride film (SiN) as the insulating film 27 may be generated by the CVD method instead of the method of generating the oxide film (SiO ₂ ) as the insulating film 27 by the thermal oxidation method. Alternatively, an insulating film 27 such as a polyimide film may be formed on the back surface 14 of the wafer W by applying a liquid resin and heat treatment.

  In this embodiment, since the modified layer 25 (see FIG. 6) is formed before the insulating film 27 is formed, the insulating film 27 forms the modified layer 25 after the insulating film 27 is formed. Formation of the modified layer 25 is not hindered.

  As shown in FIG. 9, a finishing process is performed after the insulating film coating process. In the finishing process, the wafer W is held on the chuck table 55 of the polishing apparatus (not shown) via the carrier plate 22. Here, the back surface 14 of the wafer W is polished by CMP (Chemical Mechanical Polishing). In CMP, polishing is performed by relatively sliding the polishing pad and the wafer W while supplying a polishing liquid between the polishing pad and the wafer W. The insulating film 27 on the back surface 14 of the wafer W is polished by CMP, and the tip (head) 29 of the Via electrode 19 is exposed from the insulating film 27. Further, the tip 29 of the Via electrode 19 is finished on the same plane as the insulating film 27.

  In this way, the wafer W is penetrated by the Via electrode 19 from the front surface 13 to the rear surface 14 of the wafer W. The finishing step is not limited to polishing by CMP as long as the back surface 14 of the wafer W can be finish-polished. In the finishing step, for example, the back surface 14 of the wafer W may be polished using a polishing grindstone for finishing.

  As shown in FIG. 10, a bump disposing step is performed after the finishing step. In the bump disposing step, the bump 21 is disposed on the Via electrode 19 exposed from the back surface 14 of the wafer W. The bump 21 is formed by heat-melting the tip of a wire such as gold to form a ball and then thermocompression bonding to the exposed portion of the Via electrode 19. The bump 21 is formed in a substantially spherical shape with gold or copper. In the bump disposing step, it is only necessary that the bump 21 can be disposed on the tip 29 of the Via electrode 19, and the disposing method of the bump 21 is not particularly limited. In the bump disposing step, the bumps 21 may be disposed by an electroplating method, a screen printing method, or the like. Further, the shape of the bump 21 is not particularly limited to a substantially spherical shape.

  As shown in FIG. 11, a dividing step is performed after the bump disposing step. In the dividing step, the carrier plate 22 is removed from the surface 13 of the wafer W, and a dicing tape 64 stretched on the ring frame 63 is attached to the surface 13 of the wafer W. The wafer W held by the ring frame 63 is carried into a dividing device (not shown). In the dividing device, the ring frame 63 is held on the annular table 61, and the upper end of the expansion drum 62 is positioned between the wafer W and the ring frame 63. Then, when the ring frame 63 is lowered together with the annular table 61, the expansion drum 62 is raised relative to the annular table 61.

  As a result, the dicing tape 64 is expanded in the radial direction, and an external force is applied to the modified layer 25 of the wafer W via the dicing tape 64. The wafer W is divided into individual chips C along the planned division line, starting from the modified layer 25 having reduced strength. In the present embodiment, since the division starting points are formed inside the wafer W before the bumps 21 are arranged, the wafer W can be divided satisfactorily without being affected by the unevenness of the bumps 21 and the interval between the bumps 21. Therefore, it is effective for forming a small chip in which the interval between the bumps 21 is narrow. In the dividing step, it is only necessary that the wafer W can be divided using the modified layer 25 as a division starting point, and the dividing method is not limited to tape expansion. In the dividing step, the wafer W may be divided by braking using a pressing blade.

  The individual chips C divided in this way are appropriately processed in a later process according to the user's application. For example, the bumps 21 may be disposed on the surface side of the chip C by the bump disposing process. Further, each chip C may be picked up from the dicing tape 64 and mounted on a substrate or other chips.

  As described above, according to the wafer processing method according to the present embodiment, a laser beam having a wavelength that is transmissive to the wafer W is irradiated before the insulating film 27 is formed. And a good modified layer 25 can be formed. Further, since the wafer W is supported by the carrier plate 22, it is possible to prevent problems caused by the warpage of the wafer W in the TSV process. Further, the modified layer 25 is formed inside the wafer W along the planned division line before the bump 21 is disposed, and an external force is applied to the wafer W along the modified layer 25 after the bump 21 is disposed. Therefore, it is possible to divide the wafer W into the individual devices 12 without being affected by the unevenness caused by the bumps 21. In particular, in the wafer processing method of the present invention, since the modified layer 25 is formed in the wafer W before the bumps 21 are arranged, the wafer W can be divided well even when the distance between the bumps 21 is narrow.

  In addition, this invention is not limited to the said embodiment, It can change and implement variously. In the above-described embodiment, the size, shape, and the like illustrated in the accompanying drawings are not limited to this, and can be appropriately changed within a range in which the effect of the present invention is exhibited. In addition, various modifications can be made without departing from the scope of the object of the present invention.

  For example, in the above-described embodiment, the modified layer 25 is continuously formed along the planned division line. However, the present invention is not limited to this configuration. If the wafer W can be divided along the division line, the modified layer 25 may be intermittently formed along the division line. Moreover, in this Embodiment, each process may be implemented with a separate apparatus, and may be implemented with the same apparatus.

  As described above, the present invention has an effect that it is possible to satisfactorily divide a wafer having bumps disposed on the surface in the TSV process, and is particularly useful for a wafer processing method corresponding to downsizing. It is.

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Device 13 Front surface 14 Back surface 15 Device region 16 Peripheral surplus region 17 Chamfered portion 18 Notch 19 Via electrode 21 Bump 22 Carrier plate 25 Modified layer 27 Insulating film 28 Stepped groove 29 Tip (head)
32 Cutting blade 36 Detector 37 Grinding unit 46 Processing head

Claims (1)

A plurality of devices are partitioned by dividing lines on the surface of the semiconductor substrate, a device region having a Via electrode embedded from the device electrode toward the back surface of the semiconductor substrate, and a chamfered portion in an outer peripheral surplus region surrounding the device region A wafer processing method for dividing a wafer provided with a wafer into individual devices,
A chamfered portion removing step of positioning a cutting blade in the outer peripheral surplus area and cutting a predetermined depth to remove the chamfered portion;
A carrier plate disposing step of disposing a carrier plate via a resin on the surface of the wafer after the chamfered portion removing step;
Via electrode detection step of detecting the depth of the Via electrode from the back surface of the wafer after the carrier plate placement step;
After the Via electrode detection step, a back grinding step for grinding and thinning the back surface of the wafer to such an extent that the Via electrode is not exposed on the back surface;
After the back surface grinding step, a condensing point of a laser beam having a wavelength that is transmissive to the wafer from the back surface of the wafer is positioned and irradiated in the interior corresponding to the planned division line to form a modified layer along the planned division line. A modified layer forming step;
After the modified layer forming step, an etching step of etching the semiconductor substrate from the back surface of the wafer to project the Via electrode;
An insulating film coating step of coating the back surface of the wafer with an insulating film after the etching step;
After the insulating film coating step, a finishing step of cutting the Via electrode protruding from the back surface to be exposed from the insulating film and finishing the head of the Via electrode on the same surface as the insulating film;
After the finishing step, a bump disposing step of disposing a bump on the head of the Via electrode of the wafer on which the modified layer is formed ;
After the bump disposing step, the carrier plate is removed from the surface of the wafer, and an external force is applied to the wafer to divide the wafer into individual devices along the modified layer formed inside the division line.
The processing method of the wafer comprised from these.

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