JP6075073B2 - Asynchronous data receiving circuit - Google Patents

Description

  The present invention relates to a receiving side communication circuit in asynchronous data transmission with a clock.

  When receiving data accompanied by a clock (hereinafter also referred to as reception data) transmitted by the opposite device or the like, the reception data and reception clock are at a frequency higher than twice the frequency of the reception clock (hereinafter also referred to as reception clock). Or the received clock is written to the 2-port memory using the received clock, and the clock is replaced by reading the data from the 2-port memory with the system clock of the receiving circuit. Is common. However, for example, when a receiving circuit is configured with an inexpensive and low-speed FPGA (Field Programmable Gate Array) or a special purpose FPGA such as for space, a clock with a frequency higher than twice the receiving clock cannot be mounted. If the required number of write clocks cannot be secured, the above method cannot be employed.

  As a method for solving such a problem, the method of Patent Document 1 is disclosed. In Patent Document 1, the exclusive OR of the reception clock and the system clock is sampled with a clock that is slightly different in frequency from the system clock, and the amount of phase shift is measured by measuring the duty ratio of this exclusive OR, and the system clock By selecting whether to capture in the normal phase or the reverse phase, asynchronous data that is correctly received can be captured in the reception side circuit even when there is a phase shift between the reception clock and the system clock.

Japanese National Patent Publication No. 11-5147653 (Fig. 2)

  However, the method disclosed in Patent Document 1 is based on the premise that the frequency of the reception clock and the frequency of the system clock match, and data cannot be received correctly if there is a difference between the frequency of the reception clock and the system clock. There was a problem.

  The present invention has been made to solve the above-described problem, and is asynchronous data that correctly receives data even when there is a difference between the frequency of the reception clock input together with the data and the frequency of the system clock of the reception side circuit. An object is to obtain a receiving circuit.

The present invention is an asynchronous data receiving circuit that receives received data and a received clock according to the received data and receives the received data with a system clock having a frequency deviation due to a frequency deviation with respect to the received clock. the system clock of positive phase clock synchronized with the phase that approaches the predetermined range, and a receive clock phase and the system clock and the reverse phase inverted clock phase of the approaches to a predetermined range and A clock phase determination unit, a received data normal phase sampling unit that samples and captures received data with a normal phase clock, a received data reverse phase sampling unit that samples and captures received data with a reverse phase clock, and a clock phase determination unit and a reception clock phase and positive phase clock phase approaches Selects the output of the received data reverse-phase sampling unit when it is determined, the data for selecting the output of the received data positive phase sampling unit when the clock phase determination unit determines a reception clock phase and reverse phase clock phase and approaches And a selector.

  According to the present invention, when the phase of the reception clock is close to the phase of the system clock, that is, the reception data of the positive phase clock synchronized with the edge of the reception clock corresponding to the data value change timing of the reception data and the system clock is sampled. When the edge approaches, this is detected in advance, and the received data is captured with the opposite phase clock of the system clock, and when the phase of the received clock and the phase of the opposite phase clock approach, that is, reception Even when the edge of the received clock corresponding to the data value change timing of the data and the edge that samples the received data of the reverse phase clock approach each other, this can be detected in advance and the received data can be captured with the positive phase clock. If there is a difference between the frequency of the reception clock and the frequency of the system clock Correctly received data to be able to capture.

1 is a configuration diagram of an asynchronous data receiving circuit according to Embodiment 1 of the present invention. FIG. 2 is a timing diagram showing the phase relationship of each clock in the asynchronous data receiving circuit of FIG. 1. 2 is a timing diagram illustrating an operation of a clock phase determination unit 140a of the asynchronous data receiving circuit of FIG. 2 is a timing diagram illustrating an operation of a clock phase determination unit 140b of the asynchronous data receiving circuit of FIG. 3 is an operation logic table of a determination circuit 180 of the asynchronous data reception circuit of FIG. 1. 3 is a selection operation logic table of a data selector 190 of the asynchronous data receiving circuit of FIG. FIG. 2 is a two-dimensional plan view showing a phase relationship between each clock of the asynchronous data reception circuit of FIG. 1 and a reception clock. 2 is a timing diagram illustrating the operation of the asynchronous data receiving circuit of FIG. 1. 2 is a timing diagram illustrating the operation of the asynchronous data receiving circuit of FIG. 1. 2 is a timing diagram illustrating the operation of the asynchronous data receiving circuit of FIG. 1. 2 is a timing diagram illustrating the operation of the asynchronous data receiving circuit of FIG. 1.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
Embodiment 1 FIG.
1 is a block diagram of an asynchronous data receiving circuit according to Embodiment 1 of the present invention. In Figure 1, the asynchronous data receiving circuit 1, the receive clock 3 is a clock with the received data 2 and asynchronous data is asynchronous data received is inputted.

  Further, the asynchronous data receiving circuit 1 receives a system clock 4 of the receiving side circuit from a clock source (not shown), a frame section in which the received data 2 is valid data, and a gap section in which the received data 2 is invalid data. Is input from a valid data determination unit (not shown). Here, it is assumed that the frame valid flag 5 indicates a logical value 1 in the frame section and a logical value 0 in the gap section. The asynchronous data receiving circuit 1 outputs output data 6.

  The valid data determination unit detects a carrier signal on the transmission path of the received data 2 or detects a specific code such as a preamble or a delimiter transmitted before the valid data, and is transmitted between frames. What is necessary is just to comprise using an appropriate means according to a transmission medium, such as detecting the specific code | symbol which shows an idle.

  Next, the internal configuration of the asynchronous data receiving circuit 1 will be described. The clock generation circuit 100 receives the system clock 4 and is synchronized with the system clock 4. The positive phase clock 110 is synchronized with the system clock 4. The positive phase advance guard clock 111 whose phase is advanced by a predetermined angle from the positive phase clock 110. Are a positive phase delay guard clock 112 that is delayed by a predetermined angle, a reverse phase clock 120 that is opposite in phase to the normal phase clock 110, a negative phase advance guard clock 121 that is opposite in phase to the normal phase advance guard clock 111, and a normal phase delay guard clock 112. An antiphase lag guard clock 122 having an antiphase is output. Here, the predetermined angle may be determined according to the system to be applied, for example, 18 degrees as 10% of the half cycle of the clock. As shown in FIG. 1, the clock generation circuit 100 can be constituted by a delay circuit and an inverter, for example.

  FIG. 2 shows the phase relationship between the normal phase clock 110, the normal phase advance guard clock 111, the normal phase lag guard clock 112, the reverse phase clock 120, the reverse phase advance guard clock 121, the reverse phase lag guard clock 122, and the system clock 4. To do.

  The clock sampling unit 130 samples the received clock 3 with the normal phase advance guard clock 111, the normal phase delay guard clock 112, the reverse phase advance guard clock 121, and the antiphase delay guard clock 122, respectively. In this embodiment, flip-flops are used to constitute four clock sampling units (hereinafter also referred to as CkFF) 130a to 130d. In CkFFs 130a to 130d, the reception clock 3 is input to the D terminal, and the forward phase advance guard clock 111, the forward phase delay guard clock 112, the reverse phase advance guard clock 121, and the reverse phase delay guard clock 122 are input to the clocks, respectively.

  The clock phase determination unit 140 compares the phases of the four guard clocks (normal phase advance guard clock 111, normal phase lag guard clock 112, reverse phase advance guard clock 121, and antiphase lag guard clock 122) with the phase of the reception clock 3. It is a block for determining that the vehicle is approaching. In this embodiment, the clock phase determination units 140a to 140d are configured, and the outputs of the CkFFs 130a to 130d are respectively input. The clock phase determination units 140a and 140c detect a negative change from the logical value 1 to the logical value 0 of the input signal. On the other hand, the clock phase determination units 140b and 140d detect a positive change from the logical value 0 to the logical value 1 of the input signal. The clock phase determination units 140a to 140d can be configured by, for example, a differentiation circuit.

  FIG. 3 shows an operation example of the clock phase determination unit 140a. When the CkFF 130a samples the reception clock 3 with the positive phase advance guard clock 111, the output of the CkFF 130a changes from the logical value 1 to the logical value 0 at the timing shown in FIG. 3, so the clock phase determination unit 140a detects this. The clock phase determination unit 140c performs the same operation. FIG. 4 shows an operation example of the clock phase determination unit 140b. When the reception clock 3 is sampled by the FF 130b with the positive phase lag guard clock 112, the output of the CkFF 130b changes from the logical value 0 to the logical value 1 at the timing shown in FIG. 4, so the clock phase determination unit 140b detects this. The clock phase determination unit 140d performs the same operation.

  The OR circuit 151 calculates the logical sum of the outputs of the clock phase determination units 140a and 140b and inputs the logical sum to the set (S) terminal of the SR flip-flop (hereinafter also referred to as SRFF) 170. The OR circuit 152 takes the logical sum of the outputs of the clock phase determination units 140 c and 140 d and inputs the logical sum to the reset (R) terminal of the SRFF 170. The SRFF 170 uses the positive phase clock 110 as the clock.

  The reception data positive phase sampling unit 161 samples the reception data 2 with the positive phase clock 110 and shifts the data by a specified number of stages. The reception data anti-phase sampling unit 162 samples the reception data 2 with the anti-phase clock 120 and shifts it by the prescribed number of stages + 1. In this embodiment, all are configured using flip-flops. The reception data positive phase sampling unit 161 and the reception data negative phase sampling unit 162 of this embodiment are respectively a reception data normal phase sampling unit (hereinafter also referred to as PDFF) 161a to 161b and a reception data negative phase sampling unit (hereinafter referred to as NDFF). (Also referred to as) 162a to 162c shows a configuration in which the specified number of stages is 1. However, the present invention does not limit the number of stages to be shifted, and the operation timing in the asynchronous data receiving circuit 1 is adjusted to set the specified number of stages. It may be changed.

  The PDFF 161 a receives the received data 2 at the D terminal, and outputs data (positive phase 0 shift data) obtained by sampling the received data 2 with the positive phase clock 110.

  The PDFF 161b receives positive phase 0 shift data (PDFF 161a output) at the D terminal, and outputs data obtained by delaying the positive phase 0 shift data by one clock with the positive phase clock 110 (normal phase 1 shift data).

  The NDFF 162a receives the reception data 2 at the D terminal, and outputs data (reverse phase 0 shift data) obtained by sampling the reception data 2 with the reverse phase clock 120.

  The NDFF 162b receives the negative phase 0 shift data (output of the NDFF 162a) at the D terminal, and outputs data obtained by delaying the negative phase 0 shift data by one clock with the negative phase clock 120 (negative phase 1 shift data).

  The NDFF 162c receives the negative phase 1 shift data (NDFF 162b output) at the D terminal, and outputs data obtained by delaying the negative phase 1 shift data by one clock with the negative phase clock 120 (negative phase 2 shift data).

  The output data resynchronization unit 163 resynchronizes the output of the data selector 190c, which will be described later, with the positive phase clock 110, and outputs the output data 6. In this embodiment, a flip-flop is used.

  The determination circuit 180 controls data selectors 190a and 190b described later. The determination circuit 180 receives the outputs of the clock phase determination units 140b and 140c, the output of the SRFF 170, and the frame valid flag 5, and determines the selection operation of the data selectors 190a and 190b.

  FIG. 5 is a logic table for controlling the selection operation of the data selectors 190a and 190b performed by the determination circuit 180. In the table of FIG. 5, X indicates that the value does not affect the control.

  The data selector 190 selects one from the output of the received data normal phase sampling unit 161 and the output of the received data reverse phase sampling unit 162. In this embodiment, data selectors 190a to 190c are used.

  The data selector 190a receives normal phase 0 shift data (PDFF 161a output) and normal phase 1 shift data (PDFF 161b output), and selects and outputs one of them. The data selector 190b receives the reverse phase 1 shift data (NDFF 162b output) and the reverse phase 2 shift data (NDFF 162c output), and selects and outputs one of them.

  The data selector 190c selects and outputs one of the output of the data selector 190a and the output of the data selector 190b. The selection operation of the data selector 190c is controlled by the output of the SRFF 170.

  FIG. 6 is a truth table of the data selectors 190a, 190b, and 190c. When the S input for controlling the selection operation is a logical value 0, the value of the A input is output to the SEL output, and when the S input is the logical value 1, the value of the B input is output to the SEL output.

  The operations of the determination circuit 180 and the data selector 190a based on the logic table of FIG. 5 and the truth table of FIG. 6 are as follows. As shown in FIG. 5, when the frame valid flag 5 has a logical value 0, the S input of the data selector 190a has a logical value 0 regardless of other conditions. As a result, the data selector 190a selects A-phase positive phase 1 shift data (output of the PDFF 161b) and outputs it to the SEL output. That is, when the frame valid flag 5 is in the gap section where the logical value is 0, the normal phase 1 shift data (output of the PDFF 161b) is input to the data selector 190c.

  On the other hand, when the frame valid flag 5 is a logical value 1, the output of the SRFF 170 is a logical value 0, the output of the clock phase determination unit 140c is a logical value 1, and the data selector 190a of the current determination circuit 180 is supplied. The S input of the data selector 190a becomes a logical value 1 regardless of the output value of the clock phase determination unit 140b. Thereby, the data selector 190a selects B-phase positive phase 0 shift data (output of the PDFF 161a). In other combinations, the determination circuit 180 retains and does not change the previous value, and the selection of the data selector 190a is not switched.

  Further, regarding the operations of the determination circuit 180 and the data selector 190b, when the frame valid flag 5 has a logical value 0, the S input of the data selector 190b has a logical value 0 regardless of other conditions. As a result, the data selector 190b selects the A-phase reverse phase 1 shift data (output of the NDFF 162b) and outputs it to the SEL output. That is, in the gap section, the reverse phase 1 shift data (output of NDFF 162b) is input to the data selector 190c.

  On the other hand, when the frame valid flag 5 is a logical value 1, the output of the SRFF 170 is a logical value 1, the output of the clock phase determination unit 140b is a logical value 1, and the data selector 190b of the current determination circuit 180 is supplied. The S input of the data selector 190b is a logical value 1 regardless of the output value of the clock phase determination unit 140c. As a result, the data selector 190b selects B-phase reversed-phase two-shift data (output of the NDFF 162c). In other combinations, the determination circuit 180 retains and does not change the previous value, and the selection of the data selector 190b is not switched.

  Selection of the data selector 190c is controlled by the output value of the SRFF 170. When the output of the SRFF 170 is a logical value 0, the output of the data selector 190a is selected. When the output of the data selector 190 is a logical value 1, the output of the data selector 190b is selected. .

  FIG. 7 shows the phase of the positive phase clock 110 (210 in the figure), the phase of the positive phase advance guard clock 111 (211 in the figure), the phase of the positive phase lag guard clock 112 (212 in the figure), and the phase of the negative phase clock 120. (220 in the figure), the phase of the anti-phase advance guard clock 121 (221 in the figure), the phase of the anti-phase lag guard clock 122 (222 in the figure), and the phase of the reception clock 3 (230 in the figure) are two-dimensional. It is the figure represented to the plane.

  In FIG. 7, the phase 211 of the positive phase advance guard clock 111 is advanced with respect to the phase 210 of the positive phase clock 110, and the phase 212 of the positive phase delay guard clock 212 is delayed with respect to the phase 210 of the positive phase clock. . The phase 220 of the anti-phase clock 120, the phase 221 of the anti-phase advance guard clock 121, and the phase 222 of the anti-phase lag guard clock 122 are the phase 210 of the positive phase clock 110, the phase 211 of the positive phase advance guard clock 111, respectively. The phase is opposite to the phase 212 of the normal phase lag guard clock 112.

  On the other hand, since the clock source of the reception clock 3 is different from that of the normal system clock 4 and each transmission source has its own frequency deviation, the reception clock 3 and the system clock 4 are not strictly the same frequency. Accordingly, in FIG. 7, the phase 230 of the reception clock 3 rotates counterclockwise when the frequency of the reception clock 3 is higher than the frequency of the system clock 4 and clockwise when it is lower.

  When the reception data 2 is captured by the normal phase clock 110, the reception data 2 may be abnormally captured when the phase 230 of the reception clock 3 passes the point of the phase 210 of the positive phase clock 110. . In addition, when the reception data 2 is captured by the reverse phase clock 120, the reception data 2 may be abnormally captured when the phase 230 of the reception clock 3 passes the point of the phase 220 of the reverse phase clock 120. There is.

  According to the asynchronous data receiving circuit according to the present invention, the system clock and the clock obtained by inverting the system clock before the phase of the received clock together with the asynchronous data overlaps the phase of the system clock and the phase of the clock obtained by inverting the system clock. By detecting the approach with a guard clock whose phase is shifted by a specified angle and switching the clock that captures the received asynchronous data to the opposite phase, it is possible to capture the data received in the section where the received data is stable .

  Hereinafter, the operation will be described with reference to FIGS.

FIG. 8 shows that valid data is being received when the SRFF 170 outputs a logical value 0 and the output of the data selector 190a is selected by the data selector 190c (when valid data is being received, the frame valid flag 5 indicates a frame period). It is an operation timing chart when the clock phase determination unit 140a detects a negative change from the logical value 1 to the logical value 0 of the output signal of the CkFF 130a. In FIG. 7, when the phase 230 of the reception clock 3 passes the point of the phase 211 of the positive phase advance guard clock 111 clockwise, that is, the phase 211 of the positive phase advance guard clock 111 overtakes the phase 230 of the reception clock 3. Corresponds to the case. (Case 1)
First, the data selector 190a selects and outputs the positive phase 1 shift data (PDFF 161b output). Further, the data selector 190b selects and outputs the reverse phase 1 shift data (NDFF 162b output). The data selector 190c selects the output of the data selector 190a.

  As shown in FIG. 8, when the output of the CkFF 130a changes from the logical value 1 to the logical value 0 and the clock phase determination unit 140a detects this, the input to the set terminal of the SRFF 170 becomes the logical value 1. As a result, the output of the SRFF 170 changes from the logical value 0 to the logical value 1, and the data selector 190c is switched to select the output of the data selector 190b. As a result, as shown in FIG. 8, the output data 6 is the data that has normally received the received data 2.

FIG. 9 shows that the logical phase 1 of the output signal of the CkFF 130c is received by the clock phase determination unit 140c during reception of valid data in a state where the SRFF 170 outputs a logical value 1 and the output of the data selector 190b is selected by the data selector 190c. FIG. 10 is an operation timing chart when a negative change from 1 to a logical value 0 is detected. In FIG. 7, when the phase 230 of the reception clock 3 passes the point of the phase 221 of the reverse phase advance guard clock 121 in the clockwise direction, that is, the phase 221 of the reverse phase advance guard clock 121 exceeds the phase 230 of the reception clock 3. Corresponds to the case. (Case 2)
First, the data selector 190a selects and outputs the positive phase 1 shift data (output of the PDFF 161b). Further, the data selector 190b selects and outputs the reverse phase 1 shift data (output of the NDFF 162b). The data selector 190c selects the output of the data selector 190b.

  When the output of the SRFF 170 is in the logic value 1, the output of the CkFF 130c changes from the logic value 1 to the logic value 0, and when the clock phase determination unit 140c detects this, the data selector 190a detects the positive phase 0 shift data (PDFF 160a Select (Output) to switch to output. Further, as a result of detecting the change in the output value of the CkFF 130c by the clock phase determination unit 140c, the input to the reset terminal of the SRFF 170 becomes a logical value 1, and the output of the SRFF 170 changes from the logical value 1 to the logical value 0. Thereby, the data selector 190c is switched to select the output of the data selector 190a. As a result, as shown in FIG. 9, the output data 6 is data in which the received data 2 is normally captured.

In FIG. 10, the SRFF 170 outputs a logical value 0 and the clock phase determination unit 140b receives a logical value 0 of the output signal of the CkFF 130b during reception of valid data in a state where the output of the data selector 190a is selected by the data selector 190c. FIG. 10 is an operation timing chart when a positive change from 1 to a logical value 1 is detected. In FIG. 7, when the phase 230 of the reception clock 3 passes the point of the phase 212 of the positive phase lag guard clock 112 counterclockwise, that is, the phase 230 of the reception clock 3 passes the phase 212 of the positive phase lag guard clock 112. Corresponding to overtaking. (Case 3)
First, the data selector 190a selects and outputs the positive phase 1 shift data (output of the PDFF 161b). Further, the data selector 190b selects and outputs the reverse phase 1 shift data (output of the NDFF 162b). The data selector 190c selects the output of the positive phase capture data selector 190a.

  When the output of the SRFF 170 has a logic value 0, the output of the CkFF 130b changes from the logic value 0 to the logic value 1, and when the clock phase determination unit 140b detects this, the data selector 190b detects the negative-phase two-shift data (NDFF 162c Select (Output) to switch to output. Further, as a result of detecting the change in the output value of the CkFF 130b by the clock phase determination unit 140b, the input to the set terminal of the SRFF 170 becomes a logical value 1, and the output of the SRFF 170 changes from the logical value 0 to the logical value 1. As a result, the data selector 190c is switched to select the data selector 190b. As a result, as shown in FIG. 10, the output data 6 is the data that has normally received the received data 2.

In FIG. 11, the SRFF 170 outputs a logical value 1 and the clock phase determination unit 140d receives a logical value 0 of the output signal of the CkFF 130d during reception of valid data when the output of the data selector 190b is selected by the data selector 190c. FIG. 10 is an operation timing chart when a positive change from 1 to a logical value 1 is detected. In FIG. 7, when the phase 230 of the reception clock 3 passes the point of the phase 222 of the anti-phase lag guard clock 122 counterclockwise, that is, the phase 230 of the reception clock 3 passes the phase 222 of the anti-phase lag guard clock 122. Corresponding to overtaking. (Case 4)
First, the data selector 190a selects and outputs the positive phase 1 shift data (output of the PDFF 161b). Further, the data selector 190b selects and outputs the reverse phase 1 shift data (output of the NDFF 162b). The data selector 190c selects the output of the data selector 190b.

  As shown in FIG. 11, when the output of the CkFF 130d changes from the logical value 0 to the logical value 1 and the clock phase determination unit 140d detects this, the input to the reset terminal of the SRFF 170 becomes the logical value 1. As a result, the output of the SRFF 170 changes from the logical value 1 to the logical value 0, and the data selector 190c is switched to select the data selector 190a. As a result, as shown in FIG. 11, the output data 6 becomes data in which the received data 2 is normally captured.

  As described above, the asynchronous data receiving circuit shown in the first embodiment uses the positive phase advance guard clock whose phase is advanced by a predetermined angle from the positive phase clock synchronized with the system clock. The negative change in the signal sampled in step 1, the negative change in the signal sampled by the anti-phase advance guard clock whose phase is advanced by a predetermined angle from the anti-phase clock opposite in phase to the system clock, and the phase out of the positive phase clock A clock that detects positive changes in a signal sampled with a positive phase delay guard clock delayed by a predetermined angle and positive changes in a signal sampled with a negative phase delay guard clock whose phase is delayed by a predetermined angle from the negative phase clock. A phase determination unit is provided.

  In addition, the normal phase 0 shift data obtained by sampling the received data with the positive phase clock, the positive phase 1 shift data output by the positive phase 1 shift data delayed by one clock, and the received data are sampled with the negative phase clock. And receiving data anti-phase sampling section for outputting anti-phase 1 shift data delayed by 1 clock and anti-phase 2 shift data delayed by 2 clocks.

  In addition, a data selector is provided that selects and outputs one of the two data output from the received data normal phase sampling unit and the two data output from the received data negative phase sampling unit.

When the data selector selects the normal phase 1 shift data and the received data is valid data, the clock phase determination unit has passed the phase of the positive phase advance guard clock over the phase of the received clock. When this is detected, the selection is switched to the reverse phase 1 shift data. In addition, when reverse-phase 1-shift data is selected and the received data is valid data, the clock phase determination unit detects that the phase of the anti-phase advance guard clock has overtaken the phase of the received clock. Then, the selection is switched to normal phase 0 shift data. When positive phase 1 shift data is selected and the received data is valid, the clock phase determination unit detects that the phase of the received clock has overtaken the phase of the positive phase lag guard clock. Then, the selection was switched to the reverse phase 2 shift data. In addition, when reverse-phase 1-shift data is selected and the received data is valid data, the clock phase determination unit detects that the phase of the received clock has overtaken the phase of the reverse-phase lag guard clock Then, the selection is switched to normal phase 1 shift data.
When the received data is invalid data, the data selector determines that the clock phase determination unit has received that the phase of the positive phase advance guard clock has overtaken the phase of the reception clock or the phase of the positive phase lag guard clock. When it is detected that the phase of the clock has passed, the reverse phase 1 shift data is selected, and the clock phase determination unit detects that the phase of the reverse phase advance guard clock has overtaken the phase of the received clock, or the reverse phase lag guard clock. When it is detected that the phase of the received clock has overtaken this phase, the normal phase 1 shift data is selected.

As a result, the asynchronous data receiving circuit shown in the first embodiment can capture received data normally when there is a difference between the frequency of the reception clock and the frequency of the system clock.
The data selector selects the normal phase 1 shift data when the received data becomes invalid data when the normal phase 0 shift data is selected. Further, if the received data becomes invalid data when the reverse phase 2 shift data is selected, the reverse phase 1 shift data is selected.
As a result, the asynchronous data receiving circuit shown in the first embodiment can continuously capture the received data continuously when there is a difference between the frequency of the reception clock and the frequency of the system clock.

  In the case 1 described in the first embodiment, after the change in the output signal value of the CkFF 130a in the clock phase determination unit 140a is detected, the clock phase determination unit 140d may detect the change in the output signal value of the CkFF 130d. However, in such a case, it is preferable to protect the detection by the clock phase determination unit 140d by invalidating the detection when the output of the CkFF 130a has a logical value of 0. In the case of case 2, case 3, and case 4, the same protection should be provided.

  In the first embodiment, the configuration of the asynchronous data receiving circuit that can cope with both the case where the frequency of the system clock is higher than the frequency of the reception clock and the case where the frequency of the system clock is lower is shown. In order to deal with only a case where the frequency is higher than the frequency, the asynchronous data receiving circuit may be configured using a guard clock having a phase advanced from each of the system clock and the reverse phase clock of the system clock.

  Conversely, to support only when the frequency of the system clock is lower than the frequency of the reception clock, an asynchronous data reception circuit is configured using a guard clock that is delayed in phase from the system clock and the opposite phase clock of the system clock. You may do it.

  In the first embodiment, the case of receiving a reception clock that runs parallel to the received data has been described. However, when the strobe signal for reproducing the clock runs parallel to the received data, the period of the recovered clock is actually This is twice the clock cycle of the received data. In such a case, the clock phase determination unit detects a signal change by detecting the same value for two consecutive cycles, and captures the received data with the data captured with the normal phase clock of the system clock and with the reverse phase clock. Needless to say, the selection of data can be switched.

1 Asynchronous data reception circuit, 2 reception data, 3 reception clock, 4 system clock, 5 frame valid flag, 6 output data, 110 normal phase clock, 111 normal phase advance guard clock, 112 normal phase delay guard clock, 120 reverse phase clock 121, antiphase advance guard clock, 122 antiphase delay guard clock, 130, 130a-130d clock sampling unit (CkFF), 140, 140a-140d clock phase determination unit, 151-152 OR circuit, 161, 161a-161b received data Positive phase sampling unit (PDFF), 162, 162a to 162c Received data negative phase sampling unit (NDFF), 163 Output data resynchronization unit, 170 SR flip-flop, 180 decision circuit, 190, 190a to 190c data Selector, 210 phase of normal phase clock 110, 211 phase of positive phase advance guard clock 111, phase of 212 positive phase delay guard clock 112, phase of 220 reverse phase clock 120, phase of 221 reverse phase advance guard clock 121, 222 reverse Phase of phase lag guard clock 122, phase of 230 reception clock 3

Claims (6)

An asynchronous data receiving circuit that receives reception data and a reception clock accompanying the reception data, and receives the reception data with a system clock having a frequency deviation due to a frequency deviation with respect to the reception clock,
It approaches the range where said receive clock phase as the system clock of positive phase clock synchronized phase is predetermined, and the the receive clock phase as the system clock and reverse phase inverted clock phases of A clock phase determination unit for determining that the predetermined range has been approached;
A received data positive phase sampling unit that samples and captures the received data with the positive phase clock;
A reception data anti-phase sampling unit that samples and captures the reception data with the anti-phase clock; and
Wherein the clock phase decision section selects the output of the phase and the positive phase clock of the received data reverse-phase sampling unit when it is determined that the phase approaches the receive clock, the clock phase decision section the receive clock phase a data selector for selecting the output of the received data positive phase sampling unit when the the opposite-phase clock phase was determined to be close to the,
Asynchronous data receiving circuit. The clock phase determination unit
The phase of the positive phase advance guard clock whose phase is advanced from the normal phase clock by a predetermined angle has passed the phase of the reception clock, or the positive phase delay guard whose phase is delayed by a predetermined angle from the positive phase clock. determining that said the receive clock phase the positive phase clock phase when the phase of the clock has been detected that the receive clock phase overtakes approaches, also defined a phase from the inverted clock The phase of the anti-phase advance guard clock that is advanced by an angle has overtaken the phase of the reception clock, or the phase of the anti-phase-delay guard clock that is delayed by a specified angle from the phase of the anti-phase clock is the phase of the reception clock. determines the overtaking was possible with the receive clock phase when it detects the reverse phase clock phase and has approached,
The received data positive-phase sampling unit samples the received data with the positive-phase clock and further shifts the positive-phase 1-shift data obtained by shifting the predetermined number of stages by 1 or more, and the shift-stage number is one less than the positive-phase 1-shift data. Output normal phase 0 shift data,
The reception data anti-phase sampling unit samples the reception data with the anti-phase clock and further shifts the specified number of steps to anti-phase 1 shift data, and the anti-phase 1 shift data has one more shift stage than the anti-phase 1 shift data. 2 shift data is output,
When the data selector is selecting the positive phase 1 shift data and the received data is valid data, the clock phase determining unit determines that the phase of the positive phase advance guard clock is the received clock. When the phase is overtaken, the selection is switched to the reverse phase 1 shift data, and when the reverse phase 1 shift data is selected and the received data is valid data, When the clock phase determination unit detects that the phase of the anti-phase advance guard clock has overtaken the phase of the reception clock, the selection is switched to the normal phase 0 shift data, and the normal phase 1 shift data is selected. And when the received data is valid data, the clock phase determination unit sets the phase of the positive phase lag guard clock to the phase of the positive phase lag guard clock. When it is detected that the phase of the reception clock has overtaken, the selection is switched to the reverse phase 2 shift data, and when the reverse phase 1 shift data is selected and the received data is valid data When the clock phase determination unit detects that the phase of the reception clock has overtaken the phase of the negative phase lag guard clock, the selection is switched to the normal phase 1 shift data.
The asynchronous data receiving circuit according to claim 1. The clock phase determination unit
Wherein the receive clock phase and the positive phase clock phase is approaching when the positive phase clock from a prescribed phase angle positive phase advance of the guard clock advanced phase is detected that overtaking a phase of the reception clock When the phase of the anti-phase advance guard clock whose phase is advanced by a prescribed angle from the anti-phase clock is detected to have overtaken the phase of the reception clock, the phase of the reception clock and the phase of the anti-phase clock are detected. It is determined and the phase of the clock and has approached,
The received data positive-phase sampling unit samples the received data with the positive-phase clock and further shifts the positive-phase 1-shift data obtained by shifting the predetermined number of stages by 1 or more, and the shift-stage number is one less than the positive-phase 1-shift data. Output normal phase 0 shift data,
The reception data reverse phase sampling unit outputs the reverse phase 1 shift data obtained by sampling the reception data with the reverse phase clock and further shifting the specified number of stages,
The data selector is
When the positive phase 1 shift data is selected and the received data is valid data, the clock phase determination unit has passed the phase of the positive phase advance guard clock over the phase of the received clock. When this is detected, the selection is switched to the reverse phase 1 shift data, and when the reverse phase 1 shift data is selected and the received data is valid data, the clock phase determination unit When detecting that the phase of the anti-phase advance guard clock has overtaken the phase of the reception clock, the selection is switched to the normal phase 0 shift data.
The asynchronous data receiving circuit according to claim 1. The clock phase determination unit detects the phase of the reception clock and the phase of the reception clock when it detects that the phase of the reception clock has overtaken the phase of the positive phase delay guard clock whose phase is delayed by a specified angle from the normal phase clock. the phases were determined and the phase of the clock and approaches, also the reception when the phase of the provision from the anti-phase clock phase angular delayed inverse phase delayed guard clock is detected that the receive clock phase overtakes determining the phase of the clock and said reverse phase clock phase and has approached,
The received data positive phase sampling unit outputs the positive phase 1 shift data obtained by sampling the received data with the positive phase clock and further shifting by one or more specified stages,
The reception data anti-phase sampling unit samples the reception data with the anti-phase clock and further shifts the specified number of steps to anti-phase 1 shift data, and the anti-phase 1 shift data has one more shift stage than the anti-phase 1 shift data. 2 shift data is output,
The data selector is
When the positive phase 1 shift data is selected and the received data is valid data, the clock phase determination unit has passed the phase of the positive phase lag guard clock by the phase of the received clock. When this is detected, the selection is switched to the reverse phase 2 shift data, and the clock phase determination unit is selected when the reverse phase 1 shift data is selected and the received data is valid data. When detecting that the phase of the reception clock has overtaken the phase of the anti-phase delay guard clock, the selection is switched to the normal phase 1 shift data.
The asynchronous data receiving circuit according to claim 1. The data selector, if you select the positive phase 0 shift data, switches the selection the received data is invalid data to the positive phase 1 shift data, or the received data is invalid data during some, the clock phase decision section, the positive phase clock and switches the selection in the reverse-phase 1 shifts data when the phase is determined to have approached the receive clock, said reverse phase clock and the receive clock phase DOO switches the selection to the positive phase 1 shifts data when it is determined that close,
The asynchronous data receiving circuit according to claim 2 or 3 . The data selector switches the selection to the reverse phase 1 shift data when the reception data becomes invalid data when the reverse phase 2 shift data is selected, and the reception data is invalid data. Meanwhile, when the clock phase determination unit determines that the phase of the normal phase clock and the phase of the reception clock are close to each other, the selection is switched to the reverse phase 1 shift data, and the phase of the phase of the reverse phase clock and the reception clock is changed. Switch to the normal phase 1 shift data when it is determined that
The asynchronous data receiving circuit according to claim 2 or 4.

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