CN102480289A

CN102480289A - Design circuit capable of ensuring synchronous pilot frequency clock alignment

Info

Publication number: CN102480289A
Application number: CN2010105588789A
Authority: CN
Inventors: 迟志刚
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2010-11-25
Filing date: 2010-11-25
Publication date: 2012-05-30

Abstract

The invention provide a design circuit capable of ensuring synchronous pilot frequency clock alignment, which comprises a delaying unit, a sampling logic unit, a phase inversion distinguishing logic unit, an inverter and a selector. When the phases of a plurality of clocks in a circuit are not aligned, a sampling sequence output by the sampling logic unit is different from that when the phases of the clocks are aligned. Whether the phases of the clocks are aligned can be determined by distinguishing the sampling sequence. If the phases of the clocks are not aligned, correction is performed by the relevant inverter and the selector. The design circuit of the invention not only effectively ensures alignment of a plurality of clock circuits, but also ensures the simplicity of circuit design, thereby meeting the application requirements of a plurality of clocks in the circuit design.

Description

A kind of design circuit of synchronous alien frequencies clock alignment

Technical field

The present invention relates to a kind of clock circuit, relate in particular to a kind of design circuit of synchronous alien frequencies clock alignment.

Background technology

In IC design; Tend to use synchronous but a plurality of clocks of different frequency; Phase relation between these clocks is fixed; Therefore can be at control signal and the data path between the fixing Phase Processing different clock-domains, and need not adopt the synchronous logic of handling asynchronization clock domain signals.

In the clock circuit design of complicacy; Often adopt technology such as clock switch (Clock Gating), PLL (Phase Lock Loop phase-locked loop) close to reduce power consumption; And the PLL of clock, accomplish by different engineers often in the logical block of different clock-domains; Be easy to occur the problem that the phase place of the synchronous alien frequencies clock that caused by the design error does not line up, and then cause system's cisco unity malfunction.

Fig. 1 is the sketch map of synchronous alien frequencies clock phase alignment, and two clock CKA among Fig. 1 (a) and the CKB rising edge of clock at set intervals will align, and they are performances that clock aligns.Two clock CKA among Fig. 1 (b) and CKB can not find the rising edge clock of alignment, and they are the performances that do not line up.How can not only guarantee the succinct while of clock circuit design but also can make that the synchronous alien frequencies clock maintenance alignment in the circuit design is a problem to be solved by this invention.

Summary of the invention

The object of the invention provides a kind of design circuit of synchronous alien frequencies clock alignment, can be in the design of integrated circuit clock circuit has not only guaranteed the succinct while of its circuit design but also can guarantee the alignment of a plurality of clock circuits, satisfies the application demand in the circuit design.

A kind of design circuit of synchronous alien frequencies clock alignment comprises delay cell, sampling logical block, phasing back differentiation logical block, reverser and selector.

Delay cell is used to postpone the clock of being sampled.

The sampling logical block is used to the clock of sampling, and keeps the sample sequence of certain-length.

Logic is differentiated in phasing back, is used for the sample sequence that the analytical sampling logic is seen off, judges whether clock phase aligns.

Inverter is used for the clock negate.

Selector is used to select the clock of out of phase.

In circuit design, the selection of inverter and selector is two or more according to the circuit design demand.When two or more clock circuit generation phase places did not line up, the sample sequence that the sampling logical block is seen off had different when aliging with clock phase.Through discerning sample sequence, whether clock phase is alignd make judgement.If clock phase does not line up, correct through corresponding inverter and selector.Sample by the metastable state of sampling clock when adopting delay cell for fear of sampling clock.

Through content of the present invention, can guarantee the alignment of a plurality of clock circuits in the circuit effectively, guaranteed simultaneously the succinct of circuit design again, satisfy in the circuit design application demand of clock for a long time.

Description of drawings

The synchronous alien frequencies clock phase alignment of Fig. 1 sketch map

The design circuit structure chart of Fig. 2 synchronous alien frequencies clock alignment provided by the invention

Fig. 3 T _CKA/ T _CKB =2/3The structure chart of alignment circuit

Fig. 4 T _CKA/ T _CKB =2/3The sample sequence sketch map of alignment circuit.

Embodiment

In conjunction with each accompanying drawing that invention is provided, select most preferred embodiment that the content of invention record is carried out detailed description.

1, sampling clock and by the selection of sampling clock

The cycle of supposing CKA does T _CKA, the cycle of CKB does T _CKB, T _CKA/ T _CKB =n/m(n, m are positive integer, and n/m is for the simplest), if m is an odd number, then CKA is a sampling clock, CKB is by sampling clock.Satisfying under the prerequisite that m is an odd number, generally selecting the low clock of the high clock sampling frequency of frequency.

2, delay cell

The effect of delay cell is to adopt by the metastable state of sampling clock during for fear of sampling clock.If sampling clock CKA and differed too little by sampling clock CKB frequency, cause delay cell can't guarantee that each cycle of sampling clock do not sample metastable state, circuit of the present invention can't use.

3, the determination methods of clock phase alignment

M*T _CKAIn time, sampling clock sampling m time, when supposing the alignment of two clock phases, the gained sample sequence does XL _Right, when two clock phases did not line up, the gained sample sequence did XL _Wrong, then because of m is an odd number, XL _RightWith XL _WrongMust be inequality, the present invention judges in view of the above whether two clocks align.

4, phase place does not line up the adjustment of clock

Phasing back is recoverable with an inverter.

For n, m is the situation of odd number, and when detecting phase place and do not line up, selector A selects CKA, and selector B selects the clock after the CKB negate.For n is even number, and m is the situation of odd number, and when detecting phase place and do not line up, selector A selects the clock after the CKA negate, and selector B selects the clock after the CKB negate.During logic discrimination is differentiated in phasing back, selector A and B output low level.

With specific embodiment T _CKA/ T _CKB =2/3Be example, circuit structure diagram as shown in Figure 3, wherein the logic sampling unit is selected 3 registers for use.Fig. 4 is the sample sequence sketch map of alignment circuit, and Fig. 4 (b), Fig. 4 (c), Fig. 4 (d) have listed the sample sequence that the sampling logic obtained when counter-rotating took place for one or two among CKA and the CKB.Wherein among Fig. 4 (d), two clocks still align.

Sample sequence when the sample sequence of Fig. 4 (a) and Fig. 4 (d) is the alignment of two clocks:

XL _right=001,001,001,001,……

The sample sequence of Fig. 4 (b) and Fig. 4 (c) is the sample sequences of two clocks when not lining up:

XL _right=110,110,110,110,……

The value of logic determines register 0, register 1, register 2 is differentiated in phasing back, three worthwhile in if occur two 1, then not alignment of the phase place of two clocks.

If clock phase does not line up, then phasing back is differentiated the logical block judgement through control selector A

Proofread and correct with the clock after the equal gating negate of selector B, two clocks after the correction align again, input to the sequential logic unit in the clock zone respectively.

Claims

1. the design circuit of a synchronous alien frequencies clock alignment is characterized in that comprising delay cell, sampling logical block, phasing back differentiation logical block, reverser and selector.

2. the design circuit of a kind of synchronous alien frequencies clock alignment as claimed in claim 1, the number that it is characterized in that said inverter and selector is two or more, is used for the clock of phase calibration counter-rotating.

3. the design circuit of a kind of synchronous alien frequencies clock alignment as claimed in claim 1 is characterized in that said delay cell is used to avoid sampling clock to sample by the metastable state of sampling clock.

4. the design circuit of a kind of synchronous alien frequencies clock alignment as claimed in claim 1 is characterized in that the sample sequence that said phasing back differentiation logical block analytical sampling logical block is seen off, judges whether clock phase aligns.