JP6060887B2 - Physical quantity sensor - Google Patents

Description

  The present invention relates to a physical quantity sensor that generates digital data corresponding to a sensor signal indicating a physical quantity and transmits the generated digital data to a host.

  2. Description of the Related Art Conventionally, a physical quantity sensor is provided that transmits digital data corresponding to a sensor signal indicating a physical quantity such as acceleration to a host. In the host, for example, an event such as a collision is determined by performing signal processing on the change over time of the digital data received from the physical quantity sensor. In such a system in which the physical quantity sensor transmits digital data to the host, the cycle for acquiring the sensor signal (sampling cycle) may be different from the cycle for transmitting the digital data corresponding to the sensor signal (transmission cycle). There is sex. If these periods are different, the time difference from the timing of acquiring the sensor signal to the timing of transmitting the digital data varies. When the time difference varies, a sensor signal may be lost, or a waveform different from a waveform (raw waveform) indicating a change in physical quantity with time may be transmitted to the host. As a result, there is a problem that a change in physical quantity with time cannot be correctly reproduced by the host and erroneous determination occurs. In order to solve such a problem, Patent Documents 1 and 2 disclose a method of recording the time when the sensor signal is acquired together with digital data corresponding to the sensor signal when the sensor signal is acquired.

JP 2006-322840 A JP 2012-233841 A

  However, the methods disclosed in Patent Documents 1 and 2 require resources (means) for measuring the time when the sensor signal is acquired, further increases the amount of data transmitted to the host, and increases the communication speed. Need. As a result, there is a problem that the system becomes costly. In addition, the sensor signal is acquired at a cycle of about 10 [μs], for example, so that the sensor signal is acquired at high speed, and the latest digital data is always prepared for asynchronous communication. The problem can be solved. However, in this case, sensor signals are acquired more than necessary, and this case is also not practical from the viewpoint of cost. In addition, a method of simply synchronizing the timing of acquiring a sensor signal with the timing of receiving a command from the host is also conceivable. However, if the communication cycle for receiving a command from the host becomes faster, the processing cannot be completed within one cycle, the sensor signal cannot be obtained, or the digital filter processing is completed when the sensor signal is subjected to digital filter processing, for example. It becomes impossible. In the worst case, the program may run out of control. Further, if the sensor signal cannot be obtained or the digital filter processing cannot be performed, the continuity of the sensor signal is interrupted, so that a correct calculation result cannot be obtained as the calculation result of the digital filter processing.

  The present invention has been made in view of the above-described circumstances, and the object thereof is that a new resource is not required and the cost is not increased, and the communication cycle for receiving a command from the host is increased. However, an object of the present invention is to provide a physical quantity sensor that can transmit to the host a waveform that coincides with a waveform indicating a change in physical quantity with time, and can prevent erroneous determinations from occurring in the host.

  According to the first aspect of the present invention, the data processing means uses the clock generated by the clock generation means as an operation clock, acquires a sensor signal indicating a physical quantity from the sensor element, and performs digital processing according to the acquired sensor signal. Data update processing for storing data in the storage means is executed. The data processing means executes data transmission processing for transmitting the digital data stored in the storage means from the communication means to the host when the command from the host is received by the communication means. Here, the data processing means measures the period at which the command from the host is received by the communication means as the communication period, and clocks so that the data update processing time spent for the data update process becomes constant in synchronization with the communication period. The clock control unit adjusts the frequency of the clock output (supplied) from the generation unit.

  As a result, by adjusting the clock frequency so that the data update processing time is constant in synchronization with the communication cycle, the time difference from the sensor signal acquisition timing to the digital data transmission timing can be changed. This can be prevented and the time difference can be made constant. As a result, it is possible to transmit to the host a waveform that matches the waveform (raw waveform) that shows the change in physical quantity over time without causing the sensor signal to be lost. can do. In this case, since the clock frequency may be adjusted, resources (means) for measuring the time when the sensor signal is acquired are not required, and the amount of data transmitted to the host does not increase. Therefore, it can be easily realized without requiring new resources and without increasing costs.

  Also, if the communication cycle becomes fast, there is a possibility that the sensor signal cannot be acquired immediately after the communication cycle becomes fast, or that the digital filter processing cannot be completed when the sensor signal is subjected to digital filter processing, for example. is there. In this regard, since the data update process is executed without being synchronized (asynchronously) with the communication with the host, the data update process can be continuously executed regardless of the speed of the communication cycle. In response to the faster communication cycle, the clock frequency can be increased to increase the amount of instructions in the data update process. When the next command is received from the host, the sensor signal Acquisition and digital processing can be completed. As a result, after that, the data update process can be executed following the communication cycle, and the robustness can be improved.

Functional block diagram showing a first embodiment of the present invention Diagram showing the flow of sensor signals and digital data Circulation process flowchart Interrupt processing flowchart Timing chart The figure which shows the relationship between the waveform which shows the acquisition timing of a sensor signal, and the waveform which shows the transmission timing of digital data Flowchart of interrupt processing showing the second embodiment Diagram showing upper and lower limits for each periodic band Flow chart of the circulation process showing the third embodiment Timing chart

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to an automobile acceleration sensor (hereinafter referred to as an acceleration sensor) mounted on an automobile will be described with reference to FIGS. 1 to 6. As shown in FIG. 1, the acceleration sensor 1 (physical quantity sensor) includes a sensor element 2 and a control device 3. The sensor element 2 detects an acceleration (physical quantity) given to the automobile as a detection target, and outputs a sensor signal (analog signal) indicating the detected acceleration to the control device 3.

  The control device 3 includes an oscillation circuit 4, a clock generation circuit 5 (clock generation unit), a clock control circuit 6 (clock control unit), an analog signal processing unit 7, and a microcomputer 8. The oscillation circuit 4 outputs an oscillation signal having a predetermined oscillation frequency to the clock generation circuit 5. When an oscillation signal having a predetermined oscillation frequency is input from the oscillation circuit 4, the clock generation circuit 5 generates a clock having a predetermined frequency from the input oscillation signal, and the generated clock is used as the sensor element 2 and the analog signal processing unit 7. And output to the microcomputer 8. In this embodiment, a part of the signal line of the clock from the clock generation circuit 5 to the sensor element 2 and a part of the signal line from the clock generation circuit 5 to the analog signal processing unit 7 are common. That is, the frequency of the clock output from the clock generation circuit 5 to the sensor element 2 and the frequency of the clock output from the clock generation circuit 5 to the analog signal processing unit 7 are the same. A clock signal line from the clock generation circuit 5 to the sensor element 2 and the analog signal processing unit 7 and a clock signal line from the clock generation circuit 5 to the microcomputer 8 are separate. Therefore, the frequency of the clock output from the clock generation circuit 5 to the sensor element 2 and the analog signal processing unit 7 may be different from the frequency of the clock output from the clock generation circuit 5 to the microcomputer 8. The clock signal line from the clock generation circuit 5 to the sensor element 2 and the clock signal line from the clock generation circuit 5 to the analog signal processing unit 7 may be provided separately. In that case, the frequency of the clock output from the clock generation circuit 5 to the sensor element 2 may be different from the frequency of the clock output from the clock generation circuit 5 to the analog signal processing unit 7. Clocks output from the clock generation circuit 5 to the sensor element 2, the analog signal processing unit 7, and the microcomputer 8 are used as respective operation clocks. The clock control circuit 6 adjusts the frequency of the clock output from the clock generation circuit 5 according to a command input from a CPU (Central Processing Unit) 11 (data processing means) of the microcomputer 8.

  The analog signal processing unit 7 includes an amplifier 9 and an AD conversion circuit 10. When receiving a sensor signal from the sensor element 2, the amplifier 9 amplifies the input sensor signal and outputs the amplified signal to the AD conversion circuit 10. When the AD signal is input from the amplifier 9 as an analog signal, the AD converter circuit 10 converts the input sensor signal after voltage amplification from an analog signal to a digital signal. Then, the AD conversion circuit 10 outputs the sensor signal after the voltage amplification to the microcomputer 8 as a digital signal.

  The microcomputer 8 includes a CPU 11, a communication circuit 12 (communication means), a timer 13, a memory 14 (storage means), and an arithmetic circuit 15. The CPU 11 executes a computer program stored in the memory 14 to execute a data update process and a data transmission process as processes related to the present invention. As data update processing, the CPU 11 uses the clock output (supplied) from the clock generation circuit 5 to the microcomputer 8 as an operation clock, and digitally outputs the sensor signal after voltage amplification from the analog signal processing unit 7 (AD conversion circuit 10). When input as a signal, the input sensor signal is subjected to digital filter processing (calculation processing) to generate digital data (calculation result). Then, the CPU 11 temporarily stores the generated digital data in the memory 14. In this case, the CPU 11 outputs a calculation command to the calculation circuit 15 so that the calculation circuit 15 performs various calculations such as integration, addition, and subtraction for digital filter processing.

  Further, as a data transmission process, when a command from the host 16 is received by the communication circuit 12, the CPU 11 triggers the completion of reception of the command (triggered when the command is received) and temporarily stores it in the memory 14. The digital data stored in the communication circuit 12 is transmitted from the communication circuit 12 to the host 16 following the clock received by the communication circuit 12 from the host 16. The host 16 is an electronic control unit (ECU: Electronic Control Unit), and determines an event such as a collision, for example, by performing signal processing of a change over time of digital data received from the acceleration sensor 1. As described above, the CPU 11 uses the clock output from the clock generation circuit 5 as an operation clock to execute data update processing, and executes data transmission processing in response to completion of reception of a command from the host 16. That is, the CPU 11 executes the data update process and the data transmission process asynchronously. FIG. 2 shows a flow from when the sensor signal is output from the sensor element 2 to when the digital data is transmitted from the communication circuit 12.

  As described above, in the configuration in which the data update process and the data transmission process are executed asynchronously, the period for acquiring the sensor signal (sampling period) and the period for transmitting the digital data obtained by digital filtering the sensor signal to the host 16 ( (Transmission cycle) may be different. If these periods are different, there is a possibility that the time difference from the timing of acquiring the sensor signal to the timing of transmitting the digital data may vary. When the time difference varies, the sensor signal may be lost, or a waveform different from the waveform indicating the change in acceleration over time (raw waveform) may be transmitted to the host 16. As a result, the change in acceleration with time cannot be correctly reproduced by the host 16, and the host 16 cannot correctly determine a collision or the like. Considering such circumstances, in the present invention, the CPU 11 executes the following processing.

  Next, the operation of the above-described configuration will be described with reference to FIGS. The CPU 11 executes the data update process by a loop process (first loop process), and executes the data transmission process by an interrupt process for the loop process. Hereinafter, each of the circulation process and the interrupt process will be described.

(1) Circulation process When the CPU 11 starts the circulation process, the CPU 11 executes a data update process. That is, the CPU 11 inputs (acquires) the sensor signal after voltage amplification from the analog signal processing unit 7 as a digital signal (S1). Next, the CPU 11 performs digital filter processing on the input sensor signal to generate digital data (S2). Next, when the digital filter processing is completed, the CPU 11 temporarily stores the generated digital data in the memory 14 (S3). When the CPU 11 completes the data update process, the CPU 11 adjusts the round processing time spent on the round process including the data update process (S4). When the CPU 11 completes the adjustment of the circulation processing time, the CPU 11 ends the circulation processing. The round processing time includes the data update processing time spent for the data update processing.

  More specifically, the CPU 11 calculates the number of execution cycles from the count value of the timer at the end of the circulation processing (after storing the digital data in the memory 14) in order to keep the circulation processing time spent for the circulation processing constant. . In this case, when the reference cycle number is “x”, the CPU 11 sets the reference cycle number “x” as the maximum number of cycles assuming the number of occurrences of interrupt processing. When the actual number of cycles is insufficient with respect to the reference number of cycles “x”, the CPU 11 inserts and fills in the insufficient number of cycles by empty processing. Further, when the actual number of cycles exceeds the reference number of cycles “x” due to an unexpected interrupt process or the like, the CPU 11 compensates for the excess time when adjusting the frequency of the next clock. The frequency of the clock output from the clock generation circuit 5 to the microcomputer 8 is increased. The CPU 11 can keep the data update processing time spent for the data update processing constant by keeping the round processing time spent for the round processing constant.

(2) Interrupt processing The CPU 11 monitors whether or not a command from the host 16 is received by the communication circuit 12 during execution of the above-described circulation processing. When the command from the host 16 is received by the communication circuit 12, the CPU 11 suspends the running round process and starts the interrupt process when the reception of the command is completed. When starting the interrupt process, the CPU 11 measures the time elapsed from the reception timing of the previous command (previous interrupt) to the reception timing of the current command (current interrupt) as a communication cycle (S11). The CPU 11 determines whether or not the measured communication cycle exceeds a preset upper limit or lower limit (whether it is within a predetermined cycle band with reference to the reference cycle) (S12). The reference period is a period in which the host 16 transmits a command and is a period depending on the setting of the host 16.

  More specifically, for example, when the reference period is set to 500 [μs] so that the host 16 transmits a command at a cycle of 500 [μs], the CPU 11 sets ± 5% of the reference period to an upper limit and a lower limit. In this case, the upper limit is set to 525 [μs] and the lower limit is set to 475 [μs]. The upper and lower limits for the reference cycle may be set according to the accuracy required by the system. If the accuracy required by the system is relatively high, the range from the lower limit to the upper limit is set relatively narrow, If the accuracy required by the system is relatively low, the range from the lower limit to the upper limit may be set relatively wide.

  When the CPU 11 determines that the measured communication cycle does not exceed the upper limit and the lower limit (within a range from the lower limit to the upper limit and within a predetermined cycle band) (S12: NO), the CPU 11 temporarily stores the memory cycle. Read stored digital data. Next, the CPU 11 transmits the read digital data from the communication circuit 12 to the host 16 following the clock received by the communication circuit 12 from the host 16 (S13). Next, the CPU 11 outputs an instruction to the clock control circuit 6 and causes the clock control circuit 6 to adjust the clock frequency (S14). Then, when completing the adjustment of the clock frequency, the CPU 11 ends the interrupt processing.

  Specifically, the CPU 11 adjusts the frequency of the clock so that a clock having a frequency that allows the reference cycle number “x” to be processed in one cycle of the rounding process is output from the clock generation circuit 5 to the microcomputer 8. The clock control circuit 6 is made to perform. When the number of cycles exceeding the reference cycle number “x” within the range from the lower limit to the upper limit is the cycle number “y”, and the actual cycle number is “x + y”, the CPU 11 The clock control circuit 6 is caused to adjust the clock frequency so that a clock having a frequency capable of processing the cycle number “x + y” in a cycle is output from the clock generation circuit 5 to the microcomputer 8. That is, the CPU 11 causes the clock control circuit 6 to adjust the clock frequency so that the clock generation circuit 5 outputs the high-speed clock for compensating for the excess from the reference cycle number “x” to the microcomputer 8.

  For example, when the reference period is 500 [μs], the clock frequency is 8 [MHz], the cycle number of one cycle of the round process is 4000 [cycles], of which the interrupt process cycle number is about 50 [cycles], When a shortage (remainder) of the number of cycles in one cycle occurs at a maximum of about 100 [cycles], the CPU 11 inserts and fills this shortage by empty processing in one cycle. Further, if excessive interrupt processing occurs, the CPU 11 exceeds 50 [cycles] of interrupt processing, and if there is a surplus described above, it can be absorbed therein. On the other hand, if the CPU 11 cannot absorb, when adjusting the frequency of the next clock, the clock having a frequency that can process (4000 + 50) [cycle] within the period of 500 [μs] of the reference period is obtained. The clock frequency is adjusted to 8.1 [MHz] so as to be output from the clock generation circuit 5 to the microcomputer 8.

  On the other hand, when the CPU 11 determines that the measured communication cycle exceeds the upper limit or the lower limit (out of the range from the lower limit to the upper limit and outside the predetermined cycle band) (S12: YES), the error information is Following the clock received from the host 16 to the communication circuit 12, the communication circuit 12 transmits the error to the host 16 (error processing is executed) (S15), and the interrupt processing ends.

  As shown in FIG. 5, the CPU 11 executes the circulation process and the interrupt process described above, and after starting the circulation process (t1), when the reception of the command from the host 16 is completed, the rotation process being executed is executed. And interrupt processing is started (t2). When starting the interrupt processing, the CPU 11 measures a communication cycle (T0) from the previous interrupt to the current interrupt. Next, the CPU 11 causes the communication circuit 12 to transmit the digital data temporarily stored in the memory 14 in the previous rounding process to the host 16 and causes the clock control circuit 6 to adjust the clock frequency. When completing the adjustment of the clock frequency, the CPU 11 ends the interrupt process and resumes the interrupted loop process (t3). When the CPU 11 resumes the circulation processing, the digital data generated by digital filter processing of the sensor signal is temporarily stored (updated) in the memory 14 to prepare for transmission of the next digital data (t4). Then, when the CPU 11 completes the adjustment of the circulation processing time, the CPU 11 ends the current circulation process and starts the next circulation process (t5). Thereafter, the CPU 11 repeatedly executes the circulation process and the interrupt process (after t6 and t7).

  In this way, the frequency of the clock output from the clock generation circuit 5 to the microcomputer 8 is adjusted so that the data update processing time spent for the data update processing becomes constant in synchronization with the communication cycle. As a result, it is possible to prevent the occurrence of variations in the time difference from the timing of acquiring the sensor signal to the timing of transmitting the digital data, and the time difference can be made constant. That is, as shown in FIG. 6, in the conventional case where the clock frequency is not adjusted, there is a possibility that the sampling period and the transmission period are different. If the sampling period and the transmission period are different, the transmission of the sensor signal is lost. Or a waveform that does not match the waveform (raw waveform) indicating the change over time in acceleration is transmitted to the host 16. In contrast, in the present invention that adjusts the frequency of the clock, the possibility that the sampling period and the transmission period are different is eliminated, so that a waveform indicating a change in acceleration with time can be obtained without causing a transmission loss of the sensor signal. A matching waveform can be transmitted to the host 16.

  As described above, according to the first embodiment, when the acceleration sensor 1 completes reception of a command from the host 16, the period at which the command from the host 16 is received is measured as a communication period, and data update processing is performed. The frequency of the clock output from the clock generation circuit 5 to the microcomputer 8 is adjusted so that the data update processing time spent in the process becomes constant in synchronization with the measured communication cycle. Thereby, it is possible to prevent occurrence of variation in time difference from the timing of acquiring the sensor signal to the timing of transmitting the digital data, and the time difference can be made constant. As a result, it is possible to transmit to the host 16 a waveform that coincides with a waveform (raw waveform) indicating a change in acceleration with time without causing transmission loss of the sensor signal. Can be prevented. In this case, since it is sufficient to adjust the clock frequency, a resource (means) for measuring the time when the sensor signal is acquired is not required, and the amount of data transmitted to the host 16 does not increase. Therefore, it can be easily realized without requiring new resources and without increasing costs.

  Also, if the communication cycle becomes faster, there is a possibility that sensor signal acquisition and digital filter processing cannot be completed immediately after the communication cycle becomes faster. In this regard, since the data update process is executed without being synchronized (asynchronously) with the communication with the host 16, the data update process can be continuously executed regardless of the speed of the communication cycle. In response to the faster communication cycle, the clock frequency can be increased to increase the amount of instructions in the data update process. When the next command from the host 16 is received, the sensor Signal acquisition and digital filter processing can be completed. As a result, after that, the data update process can be executed following the communication cycle, and the robustness can be improved.

  Further, in the conventional assumed method of synchronizing the timing of acquiring the sensor signal with the timing of receiving the command from the host 16, the data update process cannot be started unless the command is received from the host 16. . It is also assumed that a timer is provided in case the command from the host 16 cannot be received, and the data update process is started when a timeout occurs. However, in this case, when a command from the host 16 is received after the data update process is started, the data update process being executed is interrupted and restarted from the beginning, so that the data update process can be executed accurately. It may not be possible. In order to cope with such a problem that occurs in the conventional method, in the present invention, the data update process is executed without being synchronized with the communication with the host 16, so that the data update process is continuously executed. Can do.

  In addition, the data transmission process is executed when the measured communication cycle does not exceed the upper limit and the lower limit. As a result, the digital data can be transmitted to the host 16 while allowing the communication cycle error to a certain extent. On the other hand, when the measured communication cycle exceeds the upper limit or lower limit, the data transmission process is not executed and error information is transmitted to the host 16. Thus, when the communication cycle error exceeds a certain range, the host 16 can be notified that the communication cycle error has exceeded a certain range. Further, it is not necessary to prepare an expensive crystal oscillator with a relatively high accuracy as the oscillation circuit 4, and an inexpensive CR oscillator with a relatively low accuracy can be used, thereby suppressing the cost increase. Can do.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In addition, description is abbreviate | omitted about the same part as above-mentioned 1st Embodiment, and a different part is demonstrated. The first embodiment is a configuration corresponding to one periodic band, but the second embodiment is a configuration corresponding to a plurality of periodic bands.

  As shown in FIG. 8, the CPU 11, for example, sets each reference period so that it can correspond to three period bands in which the reference periods are set to 500 [μs], 250 [μs], and 125 [μs], respectively. The upper and lower limits are set. Specifically, the CPU 11 sets the upper limit to 525 [μs] for the reference period of 500 [μs], sets the lower limit to 475 [μs], and sets the upper limit to the reference period of 250 [μs]. The lower limit is set to 225 [μs] and the upper limit is set to 150 [μs] and the lower limit is set to 100 [μs] with respect to the reference period of 125 [μs].

  In this case, if the CPU 11 determines in the interrupt process that the measured communication cycle exceeds the upper limit or the lower limit (S12: YES), the CPU 11 determines whether or not the measured communication cycle is within another cycle band. (S16). When the CPU 11 determines that the measured communication period is within another period band (S16: YES), the CPU 11 switches various settings (constants, etc.) associated with the change of the period band (S17). Then, the CPU 11 causes the clock control circuit 6 to adjust the clock frequency (S14), and when the adjustment of the clock frequency is completed, the interrupt process is terminated.

  On the other hand, if the CPU 11 determines that the measured communication period is not within another period band (S16: NO), the error information is sent from the communication circuit 12 following the clock received by the communication circuit 12 from the host 16. The data is transmitted to the host 16 (error processing is executed) (S15), and the interrupt processing is terminated. In this case, the CPU 11 does not adjust the clock frequency to the clock control circuit 6 so that the normal operation can be promptly restored immediately after the communication cycle is normalized.

  Specifically, for example, when the reference period is set to 500 [μs] and the period band is set in the range of 475 to 525 [μs], the CPU 11 has a measured communication period of, for example, 260 [μs]. The measured communication period is outside the range of 475 to 525 [μs], but is within the period band of 225 to 275 [μs] with the reference period being 250 [μs]. The setting is switched and the clock control circuit 6 adjusts the frequency of the clock. On the other hand, if the measured communication period is, for example, 200 [μs], the CPU 11 causes the error information to be transmitted from the communication circuit 12 to the host 16 because it is not in any period band. In addition, as a case where the periodic band is switched, there is a case where one host 16 dynamically changes the periodic band, or a case where the host 16 of the communication partner of the physical sensor 1 is switched.

  As described above, according to the second embodiment, in addition to being able to obtain the same effect as that described in the first embodiment, the measured communication period is within another periodic band. In this case, it is possible to cope with a change in the reference period by switching various settings accompanying the change in the period band and adjusting the clock frequency.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In addition, description is abbreviate | omitted about the same part as above-mentioned 1st Embodiment, and a different part is demonstrated. The third embodiment is configured to synchronize the starting point of the circulation processing with the communication cycle.

  When starting the circulation process, the CPU 11 determines whether or not the command from the host 16 has been received (S21), and determines whether or not the elapsed time since the previous command was received exceeds the upper limit. (S22). If the CPU 11 determines that the reception of the command from the host 16 has been completed before the elapsed time from the reception of the previous command exceeds the upper limit (S21: YES), also in this case, from the reception timing of the previous command. The time elapsed until the reception timing of this command is measured as a communication cycle (S23). Next, the CPU 11 determines whether or not the measured communication cycle exceeds a preset lower limit (S24). When the CPU 11 determines that the measured communication cycle does not exceed the lower limit (S24: NO), the CPU 11 reads the digital data temporarily stored in the memory 14, and communicates the read digital data from the host 16. The communication circuit 12 is made to transmit to the host 16 following the clock received by the circuit 12 (S25). Then, as in the first embodiment, the CPU 11 outputs an instruction to the clock control circuit 6 and causes the clock control circuit 6 to adjust the clock frequency (S26).

  When completing the adjustment of the clock frequency, the CPU 11 inputs (acquires) the sensor signal after voltage amplification from the analog signal processing unit 7 as a digital signal (S27). Next, the CPU 11 performs digital filter processing on the input sensor signal to generate digital data (S28). When the digital filter processing is completed, the CPU 11 temporarily stores the generated digital data in the memory 14 (S29), and when the digital data is completely stored in the memory 14, the circulation processing is terminated.

  On the other hand, if the CPU 11 determines that the elapsed time since the reception of the previous command has exceeded the upper limit before completing the reception of the command from the host 16 (S22: YES), error information is transmitted from the communication circuit 12 to the host 16. Are transmitted (error processing is executed) (S30). Then, the CPU 11 causes the clock control circuit 6 to adjust the clock frequency (S26). If the amount exceeding the upper limit with respect to the reference cycle number “x” exceeds the upper limit with respect to the reference cycle number “x”, the CPU 11 has a frequency clock that allows the cycle number “x + m” to be processed in one cycle of the next round process. Can be processed within the next communication cycle, including the number of cycles exceeding the upper limit “m”, by adjusting so that the clock is output from the clock generation circuit 5 to the microcomputer 8. The signal acquisition can be continued at a constant period.

  If the CPU 11 determines that the measured communication cycle exceeds the lower limit (S24: YES), the CPU 11 also causes error information to be transmitted from the communication circuit 12 to the host 16 (S30). Then, the CPU 11 causes the clock control circuit 6 to adjust the clock frequency (S26). The CPU 11 can process the cycle number “xn” in one cycle of the next round process if the shortage exceeding the lower limit with respect to the reference cycle number “x” is the cycle number “n”. By adjusting so that the clock is output from the clock generation circuit 5 to the microcomputer 8, it is possible to process within the cycle of the communication cycle including the insufficient number of cycles “n”, and to acquire the sensor signal. It can be continued at a fixed period. In the third embodiment, since the starting point of the circulation processing is synchronized with the communication cycle, the processing for adjusting the circulation processing time described in the first embodiment (processing corresponding to S4 in FIG. 3) is performed. It becomes unnecessary.

  As shown in FIG. 10, the CPU 11 starts the circulation process by executing the circulation process described above (t11), waits for the completion of reception of the command from the host 16, and receives the command from the host 16. When completed (t12), the communication cycle (T0) from the previous command reception timing to the current command reception timing is measured. Next, the CPU 11 causes the communication circuit 12 to transmit the digital data temporarily stored in the memory 14 in the previous round process to the host 16 (t13). When the transmission of the digital data is completed, the CPU 11 causes the clock control circuit 6 to adjust the frequency of the clock. When the adjustment of the clock frequency is completed, the CPU 11 acquires the sensor signal and performs digital filter processing on the acquired sensor signal. The digital data generated by the digital filter processing is temporarily stored (updated) in the memory 14 to prepare for transmission of the next digital data (t14). Then, the CPU 11 ends the current round process and starts the next round process (t15). Thereafter, the CPU 11 repeatedly executes the circulation process (after t16, t17).

  As described above, according to the third embodiment, the same effect as that described in the first embodiment can be obtained, and the starting point of the circulation processing is synchronized with the communication cycle. Therefore, the process for adjusting the round processing time described in the first embodiment can be made unnecessary.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be modified or expanded as follows. A plurality of modified examples may be combined.
For example, the present invention may be applied to an acceleration sensor of a two-wheeled vehicle as an application other than that of an automobile. For example, the present invention may be applied to various sensors such as a temperature sensor that detects temperature and a humidity sensor that detects humidity.
The sensor signal is not limited to digital filtering to generate digital data, but other processing other than digital filtering may be performed on the sensor signal. Further, the sensor signal may be stored in the memory as digital data as it is (without being processed).

  In the drawings, 1 is an acceleration sensor (physical quantity sensor), 2 is a sensor element, 5 is a clock generation circuit (clock generation means), 6 is a clock control circuit (clock control means), 11 is a CPU (data processing means), and 12 is A communication circuit (communication means), 14 is a memory (storage means), and 16 is a host.

Claims (8)

A sensor element (2) for outputting a sensor signal indicating a physical quantity;
Clock generation means (5) for generating a clock;
A communication means (12) for communicating with the host (16);
The clock is used as an operation clock, the sensor signal is acquired, a data update process is executed to store digital data corresponding to the acquired sensor signal in the storage means (14), and a command from the host is sent to the communication means The physical quantity sensor (1) includes: data processing means (11) for executing data transmission processing for transmitting the digital data stored in the storage means from the communication means to the host. )
A clock control means (6) for adjusting the frequency of the clock;
The data processing means measures a period at which a command from the host is received by the communication means as a communication period, so that a data update processing time spent for the data update process becomes constant in synchronization with the communication period. A physical quantity sensor characterized by causing the clock control means to adjust the frequency of the clock. The physical quantity sensor according to claim 1,
The data processing means adjusts the data update processing time after executing the data update process as a first round process, and triggered by the command from the host being received by the communication means, As the interrupt processing for the first loop processing, the communication cycle is measured, and when the measured communication cycle is within a predetermined cycle band with reference to a reference cycle, the data transmission processing is executed, and the data update is performed. A physical quantity sensor characterized by causing the clock control means to adjust the frequency of the clock so that the processing time becomes constant in synchronization with the communication cycle. The physical quantity sensor according to claim 2,
The physical quantity sensor according to claim 1, wherein the data processing means executes error processing when the measured communication cycle is outside the predetermined cycle band. The physical quantity sensor according to claim 2,
When the measured communication cycle is outside the predetermined cycle band and within another predetermined cycle band with another reference cycle as a reference, the data update processing time is longer than the other communication. A physical quantity sensor characterized by causing the clock control means to adjust the frequency of the clock so as to be constant in synchronization with a cycle. The physical quantity sensor according to claim 4,
The physical quantity sensor, wherein the data processing means executes error processing when the measured communication period is outside the predetermined period band and outside the other predetermined period band. The physical quantity sensor according to claim 1,
The data processing means determines whether or not a command from the host has been received by the communication means as the second rounding process, and triggered by the command from the host being received by the communication means, The communication cycle is measured, and when the measured communication cycle does not exceed a predetermined lower limit based on a reference cycle, the data update processing time is synchronized with the communication cycle after executing the data transmission process. The physical quantity sensor is characterized by causing the clock control means to adjust the frequency of the clock so as to be constant and executing the data update process. The physical quantity sensor according to claim 6,
The data processing means executes error processing when the measured communication cycle exceeds the predetermined lower limit, and sets the frequency of the clock so that the data update processing time becomes constant in synchronization with the communication cycle. A physical quantity sensor characterized by causing the clock control means to perform adjustment and executing the data update processing. The physical quantity sensor according to claim 6 or 7,
The data processing means, when a command from the host is not received by the communication means, and an elapsed time since the previous command was received by the communication means exceeds a predetermined upper limit based on the reference period Performing error processing, causing the clock control means to adjust the frequency of the clock so that the data update processing time becomes constant in synchronization with the communication cycle, and executing the data update processing. Characteristic physical quantity sensor.

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