JP2023110410A - Communication system, communication method, and program - Google Patents

Abstract

To calculate delay time with high accuracy.SOLUTION: A transmitter of a communication system includes: a transmission unit which outputs a clock signal with a predetermined period; a reference signal receiving unit which receives a reference signal which is a basis for time, from a reference signal transmitter; a first time information generation unit which generates, based on the clock signal and the reference signal, first time information indicating a time in the transmitter; and a communication control unit which transmits a packet including the first time information. The receiver includes: a transmission unit which outputs a clock signal with a predetermined period; a reference signal receiving unit which receives the reference signal from the reference signal transmitter; a second time information generation unit which generates, based on the clock signal and the reference signal, second time information indicating a time in the transmitter; a communication control unit which receives the packet from the transmitter; and a delay time calculation unit which calculates delay time on the basis of the first time information included in the packet and the second time information.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to communication systems, communication methods, and programs.

A communication system is known in which data is transmitted and received between a plurality of devices. When transmitting and receiving data in such a communication system, a delay may occur during data transmission. For example, in Patent Document 1, a master station and a slave station are connected by wire, time information (pseudo-noise code) is transmitted from the slave station to the master station by wired communication, and the master station transmits the information based on the time information. It is described that the delay time is obtained by

Japanese Patent No. 3107994

However, since a delay also occurs when time information is transmitted from a slave station to a master station as in Patent Document 1, there is a possibility that the delay time cannot be calculated with high accuracy. In addition, since the master station and slave stations are connected by wire, it may not be possible to calculate the delay time by communicating information between, for example, three or more devices.

An object of the present disclosure is to solve the problems described above, and to provide a communication system, a communication method, and a program capable of calculating a delay time with high accuracy.

A communication system according to the present disclosure is a communication system having a transmitter and a receiver that receives packets from the transmitter, wherein the transmitter includes a transmission unit that outputs a clock signal with a predetermined period, and a time a reference signal receiver that receives a reference signal serving as a reference from a reference signal transmitter; and a first time information generator that generates first time information indicating time in the transmitter based on the clock signal and the reference signal. , a communication control unit configured to transmit a packet including the first time information to the receiver, the receiver including a transmission unit configured to output a clock signal having a predetermined period; a second time information generating unit that generates second time information indicating the time in the receiver based on the clock signal and the reference signal; and receives the packet from the transmitter a communication control unit; and a delay time calculation unit that calculates a delay time based on the first time information and the second time information included in the packet.

A communication method according to the present disclosure is a communication method using a transmitter and a receiver that receives packets from the transmitter, comprising: causing the transmitter to output a clock signal with a predetermined cycle; receiving a reference signal from a reference signal transmitter as a reference for time; generating first time information indicating the time in the transmitter based on the clock signal and the reference signal; transmitting a packet containing time information to the receiver; causing the receiver to output a clock signal having a predetermined period; and causing the receiver to receive the reference signal from the reference signal transmitter. generating second time information indicating the time in the receiver based on the clock signal and the reference signal; causing the receiver to receive the packet from the transmitter; and calculating a delay time based on the included first time information and the second time information.

A program according to the present disclosure is a program that causes a computer to execute a communication method using a transmitter and a receiver that receives packets from the transmitter, and causes the transmitter to output a clock signal with a predetermined cycle. causing the transmitter to receive a reference signal serving as a time reference from a reference signal transmitter; and generating first time information indicating time in the transmitter based on the clock signal and the reference signal. transmitting a packet containing the first time information to the receiver; causing the receiver to transmit a clock signal with a predetermined period; receiving a reference signal; generating second time information indicating time in the receiver based on the clock signal and the reference signal; and causing the receiver to receive the packet from the transmitter. and calculating a delay time based on the first time information and the second time information included in the packet.

According to the present disclosure, the delay time can be calculated with high accuracy.

FIG. 1 is a schematic block diagram of a communication system according to the first embodiment. FIG. 2 is a schematic block diagram of a transmitter. FIG. 3 is a diagram showing an example of a time waveform of each signal. FIG. 4 is a schematic block diagram of a receiver. FIG. 5 is a flow chart explaining the processing flow of the transmitter and receiver according to the first embodiment. FIG. 6 is a schematic block diagram of a receiver according to the second embodiment. FIG. 7 is a graph showing an example of average delay times. FIG. 8 is a graph showing an example of average delay times. FIG. 9 is a flowchart for explaining the processing flow according to the second embodiment.

Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the present disclosure is not limited by this embodiment, and when there are a plurality of embodiments, the present disclosure also includes a combination of each embodiment.

(First embodiment)
(Communications system)
FIG. 1 is a schematic block diagram of a communication system according to the first embodiment. As shown in FIG. 1, a communication system 100 according to the first embodiment has a transmitter 10A and a receiver 10B. The transmitter 10A transmits data to the receiver 10B using the packet communication method, and the receiver 10B receives data from the transmitter 10A. Data transmitted from the transmitter 10A to the receiver 10B will be referred to as a packet P hereinafter. In this embodiment, the transmitter 10A and the receiver 10B transmit and receive packets P by wireless communication, but any communication method may be used, for example, wired communication may be used. In the example of FIG. 1, the communication system 100 has one transmitter 10A and one receiver 10B, but the number of transmitters 10A and receivers 10B may be arbitrary. For example, the communication system 100 may have a plurality of receivers 10B, and transmit packets P from the transmitter 10A to each of the plurality of receivers 10B. Further, for example, the communication system 100 may include a plurality of transmitters 10A, and transmit packets P from the plurality of transmitters 10A to the receiver 10B.

The transmitter 10A and the receiver 10B receive a reference signal SR as a time reference from a reference signal transmitter R, which is a common device. The reference signal SR may be any signal that serves as a reference for time, but in this embodiment, it is a pulse-like signal with a predetermined cycle generated by the reference signal transmitter R. FIG. The transmitter 10A and the receiver 10B receive the reference signal SR from the reference signal transmitter R by wireless communication. However, any communication method may be used. For example, the transmitter 10A and the receiver 10B may be wired to the reference signal transmitter R and receive the reference signal SR through wired communication.

The reference signal transmitter R may be any device that generates and transmits the reference signal SR, but in the example of this embodiment may be a satellite. That is, in this embodiment, the transmitter 10A and the receiver 10B receive the reference signal SR from the artificial satellite for GSNN (Global Navigation Satellite System).

(Transmitter)
FIG. 2 is a schematic block diagram of a transmitter. FIG. 3 is a diagram showing an example of a time waveform of each signal. As shown in FIG. 2, the transmitter 10A has a transmitter 20A, a reference signal receiver 22A, a frequency divider 24A, a communication section 26A, a storage section 28A, and a controller 30A.

(Transmitter)
20 A of transmission parts output the clock signal SCA of a predetermined period. As shown in FIG. 3, the clock signal SCA is a pulse signal with a predetermined cycle. In this embodiment, the transmission unit 20A is an oscillation element that outputs a clock signal SCA with a constant period, such as a crystal oscillator or a ceramic oscillator. However, the transmitter 20A may be any element that outputs the clock signal SCA. The frequency of the clock signal SCA is, for example, 12.8 MHz, but the frequency and period of the clock signal SCA may be arbitrary.

(reference signal receiver)
The reference signal receiver 22A receives the reference signal SR from the reference signal transmitter R. The reference signal receiver 22A is a module capable of receiving the reference signal SR from the reference signal transmitter R, and is, for example, a GSNN receiver in this embodiment. The reference signal SR is a pulse-like signal with a predetermined cycle, as described above. The period of the reference signal SR may be arbitrary, but in this embodiment it is longer than the period of the clock signal SCA.

(divider)
The frequency divider 24A receives the reference signal SR received by the reference signal receiver 22A and the clock signal SCA output from the transmitter 20A. Based on the reference signal SR received by the reference signal receiving section 22A, the frequency dividing section 24A divides the frequency of the clock signal SCA output from the transmitting section 20A to generate the first time signal STA of a predetermined cycle. That is, the frequency dividing section 24A converts the cycle (frequency) of the clock signal SCA based on the reference signal SR to obtain the first time signal STA. The frequency divider 24A is a frequency divider that divides the frequency of the clock signal SCA. The first time signal STA is a pulse signal with a predetermined cycle. The period of the first time signal STA may be arbitrary, but in this embodiment, it is longer than the period of the clock signal SCA and shorter than the period of the reference signal SR.

As shown in FIG. 3, in this embodiment, the frequency divider 24A generates the count-up signal SU by integrating the clock signal SCA based on the reference signal SR. The frequency dividing unit 24A starts accumulating the clock signal SCA at a timing corresponding to the timing at which the pulse of the reference signal SR is received (the same timing as the timing at which the pulse of the reference signal SR is received in the example of FIG. 3), A count-up signal SU is generated by integrating the clock signal SCA. That is, when the frequency divider 24A receives the pulse of the reference signal SR, it increases the signal strength of the count-up signal SU every time it receives the pulse of the clock signal SCA. Then, when the signal strength of the count-up signal SU becomes equal to or greater than the threshold value, that is, when a predetermined number of pulses of the clock signal SCA are accumulated, the frequency dividing section 24A resets the signal strength of the count-up signal SU and resets the clock signal SCA again. restarts integration. The frequency divider 24A generates the first time signal STA based on the clock signal SCA. More specifically, the frequency divider 24A generates the first time signal STA having a period corresponding to the period from the timing when the clock signal SCA starts to be accumulated until the count-up signal SU is reset. In the example of the present embodiment, the frequency dividing unit 24A divides the first time signal so that the period from the timing when the integration of the clock signal SCA is started to the timing when the count-up signal SU is reset is 1/2 cycle. Generate STA.

When the next pulse of the reference signal SR is received, the frequency divider 24A resets the signal strength of the count-up signal SU and then restarts the integration of the clock signal SCA. That is, when the next pulse of the reference signal SR is received, the frequency divider 24A forcibly resets the signal strength of the count-up signal SU even if the current signal strength of the count-up signal SU is less than the threshold. , resumes the accumulation of the clock signal SCA. Thereby, the period of the first time signal STA can be adjusted each time the reference signal SR is received.

(communication department)
The communication unit 26A is a communication module for transmitting and receiving data to and from the receiver 10B, and may be an antenna or a WiFi (registered trademark) module, for example. Note that the communication unit 26A and the reference signal reception unit 22A are separate pieces of hardware in the example of this embodiment, but the communication unit 26A and the reference signal reception unit 22A may be one piece of hardware.

(storage unit)
The storage unit 28A is a memory that stores information such as the calculation content of the control unit 30A and program information. and at least one of a storage device. The program for the control unit 30A stored in the storage unit 28A may be stored in a recording medium readable by the transmitter 10A.

(control part)
The control unit 30A is an arithmetic device and includes an arithmetic circuit such as a CPU (Central Processing Unit). The controller 30A includes a first time information generator 32A and a communication controller 34A. The control unit 30A reads out and executes a program (software) from the storage unit 28A to realize a first time information generation unit 32A and a communication control unit 34A, and executes these processes. Note that the control unit 30A may execute these processes by one CPU, or may be provided with a plurality of CPUs and may execute the processes by the plurality of CPUs. Also, at least part of the processing of the first time information generating section 32A and the communication control section 34A may be realized by hardware circuits. Also, the control section 30A may include a device control section that controls devices included in the transmitter 10A, such as the transmission section 20A, the reference signal reception section 22A, and the frequency division section 24A.

(First time information generator)
32 A of 1st time information production|generation parts produce|generate the 1st time information which shows the time in 10 A of transmitters based on the clock signal SCA and the reference signal SR. That is, the first time information indicates the internal time of the transmitter 10A. Specifically, the first time information generator 32A generates first time information based on the first time signal STA generated by the frequency divider 24A based on the clock signal SCA and the reference signal SR. Since the first time signal STA is a signal generated to have a predetermined period, the first time information generator 32A counts pulses of the first time signal STA, for example, based on the first time signal STA. Thus, the first time information can be generated. The first time information generator 32A sequentially updates the first time information by sequentially counting the pulses of the first time signal STA.

(Communication control unit)
34 A of communication control parts transmit the packet P containing the 1st time information produced|generated by 32 A of 1st time information production|generation parts to the receiver 10B via 26 A of communication parts. That is, the communication control unit 34A includes the first time information in the packet P and transmits the packet P including the first time information to the receiver 10B. The communication control unit 34A includes the first time information indicating the time when the packet P is transmitted, that is, the first time information indicating the latest time, in the packet P and transmits the packet P to the receiver 10B. Note that the packet P may be arbitrary information including the first time information. may contain. In this case, the receiver 10B uses the application information included in the packet P to perform predetermined processing.

(Receiving machine)
FIG. 4 is a schematic block diagram of a receiver. As shown in FIG. 4, the receiver 10B has a transmission section 20B, a reference signal reception section 22B, a frequency division section 24B, a communication section 26B, a storage section 28B, and a control section 30B.

(Transmitter)
The transmitter 20B outputs a clock signal SCB with a predetermined cycle. As shown in FIG. 3, the clock signal SCB is a pulse signal with a predetermined cycle. In this embodiment, the transmission unit 20B is an oscillation element that outputs a clock signal SCB with a constant period, such as a crystal oscillator or a ceramic oscillator. However, the transmitter 20B may be any element that outputs the clock signal SCB. The frequency of the clock signal SCB is, for example, 12.8 MHz, but the frequency and period of the clock signal SCB may be arbitrary.

(reference signal receiver)
The reference signal receiver 22B receives the reference signal SR from the reference signal transmitter R. The reference signal receiver 22B is a module capable of receiving the reference signal SR from the reference signal transmitter R, and is, for example, a GSNN receiver in this embodiment. The period of the reference signal SR may be arbitrary, but in this embodiment it is longer than the period of the clock signal SCB.

(divider)
The frequency divider 24B receives the reference signal SR received by the reference signal receiver 22B and the clock signal SCB output from the transmitter 20B. Based on the reference signal SR received by the reference signal receiving section 22B, the frequency dividing section 24B divides the frequency of the clock signal SCB output from the transmitting section 20B to generate a second time signal STB having a predetermined cycle. The frequency divider 24B is a frequency divider that divides the frequency of the clock signal SCB. The second time signal STB is a pulse signal with a predetermined cycle. The period of the second time signal STB may be arbitrary, but in this embodiment, it is longer than the period of the clock signal SCB and shorter than the period of the reference signal SR.

As shown in FIG. 3, in this embodiment, the frequency divider 24B generates the count-up signal SU by integrating the clock signal SCB based on the reference signal SR. The frequency divider 24B starts integrating the clock signal SCB at a timing corresponding to the timing at which the pulse of the reference signal SR is received (in the example of FIG. 3, the same timing as the timing at which the pulse of the reference signal SR is received). A count-up signal SU is generated by integrating the clock signal SCB. That is, when the frequency divider 24B receives the reference signal SR, it increases the signal strength of the count-up signal SU each time it receives a pulse of the clock signal SCB. Then, when the signal strength of the count-up signal SU becomes equal to or greater than the threshold value, that is, when a predetermined number of pulses of the clock signal SCB are accumulated, the frequency divider 24B resets the signal strength of the count-up signal SU, and resets the signal strength of the clock signal SCB again. restarts integration. The frequency divider 24B generates a second time signal STB based on the clock signal SCB. More specifically, the frequency dividing section 24B generates the second time signal STB with a period corresponding to the period from the timing when the clock signal SCB starts to accumulate until the count-up signal SU is reset. In the example of the present embodiment, the frequency dividing unit 24B divides the second time signal so that the period from the timing when the integration of the clock signal SCB is started to the timing when the count-up signal SU is reset is 1/2 cycle. Generate STB.

When the next pulse of the reference signal SR is received, the frequency dividing section 24B resets the signal strength of the count-up signal SU and then restarts the integration of the clock signal SCB. That is, when the next pulse of the reference signal SR is received, the frequency divider 24B forcibly resets the signal strength of the count-up signal SU even if the current signal strength of the count-up signal SU is less than the threshold. , resumes the integration of the clock signal SCB. Thereby, the period of the second time signal STB can be adjusted each time the reference signal SR is received.

(communication department)
The communication unit 26B is a communication module for transmitting and receiving data to and from the transmitter 10A, and may be an antenna or a WiFi module, for example. Note that the communication unit 26B and the reference signal reception unit 22B are separate pieces of hardware in the example of this embodiment, but the communication unit 26B and the reference signal reception unit 22B may be one piece of hardware.

(storage unit)
The storage unit 28B is a memory that stores information such as the calculation content and program information of the control unit 30B, and includes, for example, at least one of RAM, ROM, and an external storage device such as an HDD. The program for the control unit 30B stored in the storage unit 28B may be stored in a recording medium readable by the receiver 10B.

(control part)
The control unit 30B is an arithmetic device and includes an arithmetic circuit such as a CPU. The controller 30B includes a second time information generator 32B, a communication controller 34B, and a delay time calculator 36B. The control unit 30B implements the second time information generation unit 32B, the communication control unit 34B, and the delay time calculation unit 36B by reading out and executing a program (software) from the storage unit 28B, and executes these processes. do. Note that the control unit 30B may execute these processes by one CPU, or may be provided with a plurality of CPUs and may execute the processes by the plurality of CPUs. Moreover, at least part of the processing of the second time information generation unit 32B, the communication control unit 34B, and the delay time calculation unit 36B may be realized by hardware circuits. Further, the control section 30B may include a device control section that controls devices included in the receiver 10B such as the transmission section 20B, the reference signal reception section 22B, and the frequency division section 24B.

(Second time information generator)
The second time information generator 32B generates second time information indicating the time in the receiver 10B based on the clock signal SCB and the reference signal SR. That is, the second time information indicates the internal time of the receiver 10B. Specifically, the second time information generator 32B generates the second time information based on the second time signal STB generated by the frequency divider 24B based on the clock signal SCB and the reference signal SR. Since the second time signal STB is a signal generated to have a predetermined period, the second time information generator 32B counts pulses of the second time signal STB, for example, based on the second time signal STB. Thus, the second time information can be generated. The second time information generator 32B sequentially updates the second time information by sequentially counting the pulses of the second time signal STB.

(Communication control unit)
The communication control unit 34B receives the packet P including the first time information from the transmitter 10A via the communication unit 26B.

(Delay time calculator)
The delay time calculator 36B calculates the delay time based on the first time information included in the packet P received from the transmitter 10A and the second time information generated by the second time information generator 32B. The delay time calculator 36B calculates the difference between the time indicated by the first time information and the time indicated by the second time information as the delay time. The time indicated by the first time information here is the time corresponding to the timing at which the transmitter 10A transmitted the packet P (that is, the time at which the packet P was transmitted, measured by the transmitter 10A, for example). 2 The time indicated by the time information is the time corresponding to the timing at which the receiver 10B received the packet P (that is, the time at which the packet P was received, measured by the receiver 10B, for example). Therefore, the delay time can be said to be the delay time due to communication, and can be said to be the time required to transmit the packet P from the transmitter 10A to the receiver 10B.

The delay time calculator 36B may output the calculated delay time. For example, the delay time calculation unit 36B outputs the calculated delay time to the storage unit 28B to be stored in the storage unit 28B, transmits the calculated delay time to an external device, or displays the calculated delay time on a display (not shown). and so on. By outputting the calculated delay time in this way, it can be used for various purposes such as adjustment of the communication environment.

(processing flow)
A processing flow of processing of the transmitter 10A and the receiver 10B described above will be described. FIG. 5 is a flow chart explaining the processing flow of the transmitter and receiver according to the first embodiment. As shown in FIG. 5, the transmitter 10A acquires the clock signal SCA output by the transmitter 20A, and acquires the reference signal SR from the reference signal transmitter R by the reference signal receiver 22A (step S10A). Then, the frequency divider 24A of the transmitter 10A divides the frequency of the clock signal SCA based on the reference signal SR to generate the first time signal STA (step S12A), and the first time information generator 32A First time information is generated based on the first time signal STA (step S14A). The transmitter 10A uses the communication control unit 34A to transmit the packet P including the first time information to the receiver 10B (step S16).

The receiver 10B also acquires the clock signal SCB output by the transmitter 20B, acquires the reference signal SR from the reference signal transmitter R by the reference signal receiver 22B (step S10B), and The clock signal SCB is frequency-divided based on the reference signal SR to generate the second time signal STB (step S12B), and the second time information is generated by the second time information generator 32B based on the second time signal STB. Generate (step S14B). The receiver 10B generates the second time information, and when the packet P including the first time information is received, the delay time calculator 36B calculates the delay time based on the first time information and the second time information. (step S18).

As described above, in the present embodiment, the transmitter 10A generates the first time information based on the reference signal SR received from the reference signal transmitter R, and the receiver 10B is also the same device as the reference signal SR. Based on the reference signal SR received from the signal transmitter R, second time information is generated. Then, the receiver 10B receives the first time information from the transmitter 10A and compares the first time information with the second time information generated by itself to calculate the delay time. That is, in the present embodiment, since the first time information and the second time information can be synchronized by the reference signal SR obtained from a common device, the first time information and the second time information can be communicated. It is possible to suppress deviation due to delay or the like. Therefore, according to the present embodiment, it is possible to suppress the deviation between the first time information and the second time information and calculate the delay time with high accuracy.

(Second embodiment)
Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the average delay time is calculated from the delay time of each packet P, and the application execution start timing is adjusted for each packet P based on the average delay time. . In the second embodiment, descriptions of parts having the same configuration as in the first embodiment are omitted.

(Receiving machine)
FIG. 6 is a schematic block diagram of a receiver according to the second embodiment. As shown in FIG. 6, the control section 30Ba of the receiver 10Ba of the second embodiment includes a second time information generation section 32B, a communication control section 34B, a delay time calculation section 36Ba, and an execution section 38Ba.

(Packet transmission/reception)
In the second embodiment, the communication control unit 34A of the transmitter 10A transmits a packet P including first time information and application information to the receiver 10Ba. Application information is information for executing a predetermined process (predetermined application) by the receiver 10Ba. For example, when the receiver 10Ba performs image display as a predetermined process, the application information may be image data. However, the processing and application information performed by the receiver 10Ba are not limited to this and may be arbitrary.

The transmitter 10A sequentially transmits packets P with different first time information and application information to the receiver 10Ba. The communication control unit 34B of the receiver 10Ba sequentially receives packets P including the first time information and application information from the transmitter 10A.

(Calculation of average delay time)
FIG. 7 is a graph showing an example of average delay times. The delay time calculator 36Ba of the receiver 10Ba calculates the delay time for the packet P based on the first time information included in the packet P and the second time information at the timing when the packet P was received. The delay time calculator 36Ba calculates a delay time for each packet P received at different timings. The delay time calculator 36Ba calculates the average delay time based on the delay time of each packet P, that is, based on the calculated plurality of delay times. The delay time calculator 36Ba may calculate the average delay time by any method based on the delay time of each packet P. For example, the delay time calculation unit 36Ba may calculate the arithmetic mean value of the delay time for each packet P as the average delay time, or calculate the arithmetic mean value of the delay time for each packet P as each delay time may be calculated as the average delay time. Line L1 in FIG. 7 indicates the delay time for each packet P, and line L indicates the average delay time calculated from the delay time for each packet P. In FIG.

(Execution of processing)
Based on the application information included in the packet P, the execution unit 38Ba executes a predetermined process. That is, for example, the execution unit 38Ba performs image display, which is a predetermined process, using image data as application information.

FIG. 8 is a graph showing an example of average delay times. The executing unit 38Ba continuously executes the predetermined processing by sequentially updating the application information used for the predetermined processing using the application information included in the packets P that are sequentially received. That is, when the processing using the application information included in one packet P is completed, the executing unit 38Ba switches to the processing using the application information included in the next packet P, thereby continuing the processing. In this case, the execution unit 38Ba executes processing for each packet P based on the application information included in the packet P at a timing delayed from the timing at which the packet P is received by the average delay time. That is, the execution unit 38Ba starts processing based on each packet P with a delay of the common average delay time from the timing at which the packet P is received. Therefore, it is possible to prevent the execution of only some packets P from being delayed by fixing the cycle of the processing start timing for each packet P, so that the processing can be executed appropriately. . A line L2 in FIG. 8 indicates the delay time for each packet P. In FIG. As shown in FIG. 8, even if the actual delay time of packet P is shorter than the average delay time, the timing of starting processing using packet P is postponed until the average delay time has passed. As a result, even if there is variation in the delay time for each packet P, the cycle of the process start timing can be made constant by setting the process start timing using a constant value of the average delay time. Note that, as shown in FIG. 8, for a packet P whose delay time is longer than the average delay time, it is not necessary to perform processing using that packet P. FIG.

The execution unit 38Ba may compress the application information included in the packet P based on the packet P delay time. In this case, for example, the execution unit 38Ba may compress the application information included in the packet P when the delay time of the packet P is longer than the average delay time. As a result, even a packet P whose delay time is longer than the average delay time can be shortened by compressing it, so that the packet P can be appropriately processed. Further, for example, the execution unit 38Ba may increase the compression rate of the application information as the delay time of the packet P increases.

(processing flow)
The flow of processing according to the second embodiment described above will be described. FIG. 9 is a flowchart for explaining the processing flow according to the second embodiment. As shown in FIG. 9, the receiver 10Ba calculates the delay time based on the first time information included in the packet P and the second time information at the timing when the packet P is received by the delay time calculation unit 36Ba. Calculate (step S20). The delay time calculator 36Ba determines whether the amount of data of the calculated delay time is greater than or equal to a predetermined amount (step S22). An average delay time is calculated based on the delay time for each packet P calculated up to (step S24). On the other hand, if the data amount of the calculated delay time is less than the predetermined amount (step S22; No), the process returns to step S20 to continue calculating the delay time of the next packet P. FIG. It should be noted that the amount of delay time data being equal to or greater than a predetermined number may mean that the number of delay times calculated for each packet P is equal to or greater than a predetermined number. The period until the average delay time is calculated as described above is an initialization period, and processing (for example, image display) using the packet P received during the initialization period may not be executed. Further, for example, during the initialization period, the processing using the packet may be started each time the packet P is received without using the average delay time.

After calculating the average delay time, the receiver 10Ba sets the timing to start processing each packet P based on the average delay time for packets P to be received thereafter. That is, the receiver 10Ba receives the packet P by the communication control unit 34B (step S26), and causes the execution unit 38Ba to delay the timing of starting processing using the packet P by the average delay time. A process based on the application information included in the packet P is executed (step S28).

After that, if the process is to be terminated (step S30; Yes), the process is terminated. On the other hand, if the process is not finished (step S30; No) and the predetermined time has not elapsed since the average delay time was calculated (step S32; No), the process returns to step S26, and the next packet P is received and processing is continued using the calculated average delay time. On the other hand, if the predetermined time has passed after calculating the average delay time (step S32; Yes), the process returns to step S20 (that is, returns to the initialization period) to update the average delay time. That is, in the present embodiment, since the average delay time is updated each time the predetermined time elapses, it is possible to appropriately respond to changes in the communication environment. However, updating the average delay time is not essential.

(effect)
As described above, the communication system 100 according to the present disclosure has a transmitter 10A and a receiver 10B that receives packets P from the transmitter 10A. The transmitter 10A includes a transmitter 20A that outputs a clock signal SCA with a predetermined cycle, a reference signal receiver 22A that receives a reference signal SR as a time reference from a reference signal transmitter R, a clock signal SCA and a reference signal SR. and a communication control unit 34A for transmitting a packet P including the first time information to the receiver 10B. The receiver 10B includes a transmitter 20B that outputs a clock signal SCB with a predetermined cycle, a reference signal receiver 22B that receives a reference signal SR from a reference signal transmitter R, and a receiver 10B based on the clock signal SCB and the reference signal SR. 10B, a communication control unit 34B that receives the packet P from the transmitter 10A, the first time information included in the packet P, and the second time and a delay time calculator 36B that calculates the delay time based on the information.

According to the communication system 100 according to the present disclosure, the first time information and the second time information can be synchronized by the reference signal SR acquired from a common device, so that the first time information and the second time information are synchronized. , it is possible to suppress deviation due to communication delay or the like. Therefore, according to the present embodiment, it is possible to suppress the deviation between the first time information and the second time information and calculate the delay time with high accuracy.

The transmitter 10A further includes a frequency divider 24A that divides the frequency of the clock signal SCA based on the reference signal SR of the transmitter 10A to generate a first time signal STA having a predetermined period, and a first time information generator. 32A generates first time information based on the first time signal STA. The receiver 10B further includes a frequency divider 24B that divides the frequency of the clock signal SCB based on the reference signal SR on the receiver 10B side to generate a second time signal STB of a predetermined cycle, and a second time information generator. 32B generates second time information based on the second time signal STB. According to this embodiment, by using the first time signal STA and the second time signal STB frequency-divided based on the reference signal SR, the deviation between the first time information and the second time information is suppressed, and the delay time is reduced. can be calculated with high accuracy.

A reference signal receiver 22A of the transmitter 10A and a reference signal receiver 22B of the receiver 10B receive a reference signal SR from an artificial satellite as a reference signal transmitter R. By receiving the reference signal SR from the satellite, it is possible to appropriately synchronize the first time information and the second time information and calculate the delay time with high accuracy.

The delay time calculator 36Ba calculates a delay time for each packet P received at different timings, and calculates an average delay time based on each delay time. Further, the receiver 10B further includes an execution unit 38Ba that executes predetermined processing based on the application information included in the packet P. , performs a predetermined process based on the application information. As a result, it is possible to appropriately execute the processing with a fixed period of the timing of starting the processing for each packet P. FIG.

The execution unit 38Ba increases the compression rate of the application information included in the packet P as the delay time increases, and executes the predetermined process. As a result, the packet P having a long delay time can also be appropriately processed.

A communication method according to the present disclosure uses a transmitter 10A and a receiver 10B that receives packets P from the transmitter 10A. This communication method includes the steps of causing the transmitter 10A to output a clock signal SCA with a predetermined cycle, causing the transmitter 10A to receive a reference signal SR serving as a time reference from a reference signal transmitter R, and the steps of causing the transmitter 10A to receive the clock signal SCA. and a step of generating first time information indicating the time in the transmitter 10A based on the reference signal SR; a step of transmitting a packet P including the first time information to the receiver 10B; a step of outputting the clock signal SCB; a step of causing the receiver 10B to receive the reference signal SR from the reference signal transmitter R; and a second time indicating the time in the receiver 10B based on the clock signal SCB and the reference signal SR. a step of generating information, a step of causing the receiver 10B to receive the packet P from the transmitter 10A, and a step of calculating the delay time based on the first time information and the second time information included in the packet P; ,including. According to this communication method, the delay time can be calculated with high accuracy.

Although the embodiments of the present disclosure have been described above, the embodiments are not limited by the contents of the embodiments. In addition, the components described above include those that can be easily assumed by those skilled in the art, those that are substantially the same, and those within the so-called equivalent range. Furthermore, the components described above can be combined as appropriate. Furthermore, various omissions, replacements, or modifications of components can be made without departing from the gist of the above-described embodiments.

10A transmitter 10B receiver 20A, 20B transmitter 22A, 22B reference signal receiver 24A, 24B frequency divider 32A first time information generator 32B second time information generator 34A, 34B communication controller 100 communication system P packet R Reference signal transmitter SCA, SCB Clock signal SR Reference signal STA First time signal STB Second time signal

Claims (9)

A communication system comprising a transmitter and a receiver for receiving packets from the transmitter,
The transmitter is
a transmitter that outputs a clock signal with a predetermined cycle;
a reference signal receiver that receives a reference signal that serves as a time reference from a reference signal transmitter;
a first time information generator that generates first time information indicating time in the transmitter based on the clock signal and the reference signal;
a communication control unit that transmits a packet including the first time information to the receiver;
including
The receiver is
a transmitter that outputs a clock signal with a predetermined cycle;
a reference signal receiver that receives the reference signal from the reference signal transmitter;
a second time information generator that generates second time information indicating time in the receiver based on the clock signal and the reference signal;
a communication control unit that receives the packet from the transmitter;
a delay time calculation unit that calculates a delay time based on the first time information and the second time information included in the packet;
including,
Communications system. The transmitter further includes a frequency divider that divides the frequency of the clock signal based on the reference signal of the transmitter to generate a first time signal having a predetermined period, wherein the first time information generator comprises , generating the first time information based on the first time signal;
The receiver further includes a frequency dividing unit that divides the frequency of the clock signal based on the reference signal on the receiver side to generate a second time signal having a predetermined period, wherein the second time information generating unit 2. The communication system according to claim 1, wherein said second time information is generated based on said second time signal. 3. The reference signal receiving unit of the transmitter and the reference signal receiving unit of the receiver according to claim 1, wherein the reference signal is received from an artificial satellite as the reference signal transmitter. Communications system. 4. The delay time calculator according to any one of claims 1 to 3, wherein the delay time calculator calculates the delay time for each of the packets received at different timings, and calculates an average delay time based on the respective delay times. The communication system according to item 1. 5. The communication system according to claim 4, wherein said delay time calculator updates the average delay time each time a predetermined threshold time elapses. The receiver further includes an execution unit that executes predetermined processing based on the application information included in the packet,
6. The communication system according to claim 4, wherein said execution unit executes said predetermined processing based on said application information at a timing delayed by said average delay time from a timing at which said packet is received. 7. The communication system according to claim 6, wherein the longer the delay time, the higher the compression ratio of the application information included in the packet, and the execution unit executes the predetermined process. A communication method using a transmitter and a receiver that receives packets from the transmitter,
causing the transmitter to output a clock signal with a predetermined period;
causing the transmitter to receive a reference signal serving as a time reference from a reference signal transmitter;
generating first time information indicating time in the transmitter based on the clock signal and the reference signal;
transmitting a packet containing the first time information to the receiver;
causing the receiver to output a clock signal with a predetermined period;
causing the receiver to receive the reference signal from the reference signal transmitter;
generating second time information indicating time in the receiver based on the clock signal and the reference signal;
causing the receiver to receive the packets from the transmitter;
calculating a delay time based on the first time information and the second time information included in the packet;
including,
Communication method. A program that causes a computer to execute a communication method using a transmitter and a receiver that receives packets from the transmitter,
causing the transmitter to output a clock signal with a predetermined period;
causing the transmitter to receive a reference signal serving as a time reference from a reference signal transmitter;
generating first time information indicating time in the transmitter based on the clock signal and the reference signal;
transmitting a packet containing the first time information to the receiver;
causing the receiver to transmit a clock signal with a predetermined period;
causing the receiver to receive the reference signal from the reference signal transmitter;
generating second time information indicating time in the receiver based on the clock signal and the reference signal;
causing the receiver to receive the packets from the transmitter;
calculating a delay time based on the first time information and the second time information included in the packet;
causes the computer to execute
program.

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