JP6011136B2 - 半導体装置 - Google Patents
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- 244000126211 Hericium coralloides Species 0.000 description 1
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 1
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- 238000007363 ring formation reaction Methods 0.000 description 1
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Description
図10は、出力段MOSFET501の電流(Id)−電圧(Vd)特性図である。Idは出力段MOSFET501のドレイン電流であり、Vdは出力段MOSFET501のドレイン電圧である。このIdは出力段MOSFET501に流れるサージ電流や寄生トランジスタ65のコレクタ電流も示す。また、Vdは出力段MOSFET501に印加されるサージ電圧や寄生ダイオード65に印加されるサージ電圧も示す。
この発明の目的は、前記の課題を解決して、確実にサージ保護ができる小型で製造バラツキの影響を受け難いサージ保護素子を有する半導体装置を提供することにある。
前記第3半導体領域と前記活性領域との間の前記第2半導体領域の表面層に配置された第2導電型の第4半導体領域を有し、
前記第2半導体領域と前記第3半導体領域でガードリングを構成し、さらに前記第4半導体領域と前記第2半導体領域および前記第1半導体領域で寄生バイポーラトランジスタを構成し、該寄生バイポーラトランジスタがサージ保護素子となる構成とする。
ソース領域に挟まれた前記第2半導体領域上にゲート絶縁膜を介して配置されるゲート電極と、前記ドレイン領域に接続されたドレイン電極と、前記ソース領域と前記コンタクト領域に接続されたソース電極と、を備え、前記第1半導体領域と前記半導体基板に跨り該両者に接して配置され、前記第2半導体領域群を取り囲むように配置された第1導電型の第3半導体領域と、該第3半導体領域の表面層に配置され前記第3半導体領域より高濃度の第1導電型の第4半導体領域と、前記第4半導体領域と前記第2半導体領域との間の前記第3半導体領域の表面層に配置される第2導電型の第5半導体領域と、前記第4半導体領域と前記第5半導体領域に接続されたグランド電極と、を備え、前記第5半導体領域は前記第2半導体領域と前記第3半導体領域との間に配置された前記ドレイン領域に対向して配置され、前記第4半導体領域および前記第3半導体領域でガードリングを構成し、前記第1半導体領域、前記第3半導体領域および前記第5半導体領域からなる寄生バイポーラトランジスタでサージ保護素子を構成する。
また、特許請求の範囲の請求項7に記載の発明によれば、請求項2〜6のいずれか一項に記載の発明において、前記ドレイン領域を第1導電型のコレクタ領域に換えて横型のMOS型電界効果トランジスタ(MOSFET)を横型の絶縁ゲート型バイポーラトランジスタ(IGBT)に変更するとよい。
<実施例1>
図1は、この発明の第1実施例に係る半導体装置100の要部平面図である。図2は、図1のA部拡大図であり、同図(a)は出力段MOSFETの要部平面図、同図(b)は同図(a)のX−X線で切断した要部断面図である。図3は、図1の半導体装置100の電極配線の要部平面図である。
nウェル領域2と離して集積回路102(内部回路)を形成するnウェル領域21がp半導体基板1の表面層に配置される。nウェル領域21は前記のpウェル領域3に接し、nウェル領域2とnウェル領域21の間のpウェル領域3にp+領域20が配置される。このp+領域20は出力段MOSFET101と集積回路102の間を電気的に分離する分離領域である。
前記したように、ガードリング17に寄生トランジスタ15を配置し、この寄生トランジスタ15をESD保護素子などのサージ保護素子16として用いる。ESDなどのサージが印加されたとき、この寄生トランジスタ15をオンさせることで、サージから内部回路である集積回路102を保護することができる。
また、従来の寄生ダイオード65に比べて、寄生トランジスタ15のサージ保護素子16は動作抵抗が小さくなるため、出力段MOSFET101や内部回路となる集積回路102を確実にサージから保護することができる。
その理由は、n+領域8の横幅Wの割合が1倍未満になるとサージの保護機能が低下するためである。一方、n+領域8の横幅Wの割合が5倍超になると、それに対応してp+領域9の横幅Qが狭くなり、サージ電流密度が高まって破損することがあるためである。
<実施例2>
図5は、この発明の第2実施例に係る半導体装置200の要部平面図である。第1実施例の半導体装置100との違いは、p+領域9を島状に形成し、寄生トランジスタ15を構成するn+領域8を部分的に広げた点である。
<実施例3>
図6は、この発明の第3実施例に係る半導体装置300の要部断面図である。第1実施例の半導体装置100との違いは、n+領域8下およびp+領域9下のpベース領域(pウェル領域3)の一部を浅く形成した点である。nエミッタ領域(n+領域8)直下のpベース領域の一部を浅くすることで、pベース領域(p+領域9)の横方向抵抗Rが大きくなり、寄生トランジスタ15が動作し易くなる。その結果、サージの保護機能を向上させることができる。
1)ガードリング17に寄生トランジスタ15を形成し、この寄生トランジスタ15をサージ保護素子16とすることで、サージ保護素子16を有する小型の半導体装置100〜300を提供することができる。
2)寄生トランジスタ15をサージ保護素子16とすることで、寄生ダイオード65のサージ保護素子66に比べて動作抵抗を小さくすることができて、サージ保護機能を向上できる。
3)サージ保護素子16を各セル4a毎に設けずにガードリング17に一つのサージ保護素子16を設けることで、サージ保護機能に対する製造バラツキ(面内バラツキ)の影響を受け難くくすることができる。
4)ガードリング17にサージ保護素子16を形成するので、出力段MOSFET101の特性(耐圧、オン電圧)は影響を受けない。
また、説明は省略するが、前記の実施例1〜実施例3を組み合わせてもよい。
2 nウェル領域
3 pウェル領域
4 pウェル領域
4a セル
5 nドレイン領域
6 nソース領域
7 pコンタクト領域
8 n+領域
9 p+領域
10 LOCOS
11 ゲート電極
11a ゲート配線
12 ドレイン電極配線
13 ソース電極配線
14 グランド電極配線
15,15a 寄生トランジスタ
16 サージ保護素子
17 ガードリング
18 活性領域
20 p+領域
21 nウェル領域
100,200,300 半導体装置
101 出力段MOSFET
102 集積回路
Claims (7)
- 第1導電型の半導体基板の表面層に配置された第2導電型の第1半導体領域と、該第1半導体領域の表面層に配置された活性領域と、該活性領域を取り囲み前記第1半導体領域と前記半導体基板に跨り該両者に接して配置された前記半導体基板より高濃度の第1導電型の第2半導体領域と、該第2半導体領域の表面層に配置された該第2半導体領域より高濃度の第1導電型の第3半導体領域とを備える半導体装置において、
前記第3半導体領域と前記活性領域との間の前記第2半導体領域の表面層に配置された第2導電型の第4半導体領域を有し、
前記第2半導体領域と前記第3半導体領域でガードリングを構成し、さらに前記第4半導体領域と前記第2半導体領域および前記第1半導体領域で寄生バイポーラトランジスタを構成し、該寄生バイポーラトランジスタがサージ保護素子となることを特徴とする半導体装置。 - 第1導電型の半導体基板の表面層に選択的に配置された第2導電型の第1半導体領域と、該第1半導体領域の表面層に配置された第1導電型の複数の第2半導体領域と、前記第1半導体領域の表面層に前記第2半導体領域と離して配置され該第2半導体領域と交互に配置された複数の第2導電型のドレイン領域と、前記第2半導体領域の表面層に配置された第2導電型のソース領域と、該ソース領域と接して前記第2半導体領域の表面層に配置された第1導電型のコンタクト領域と、前記第1半導体領域上に選択的に配置された酸化膜と、前記第1半導体領域と前記ソース領域に挟まれた前記第2半導体領域上にゲート絶縁膜を介して配置されるゲート電極と、前記ドレイン領域に接続されたドレイン電極と、前記ソース領域と前記コンタクト領域に接続されたソース電極と、を備え、
前記第1半導体領域と前記半導体基板に跨り該両者に接して配置され、前記第2半導体領域群を取り囲むように配置された第1導電型の第3半導体領域と、該第3半導体領域の表面層に配置され前記第3半導体領域より高濃度の第1導電型の第4半導体領域と、前記第4半導体領域と前記第2半導体領域との間の前記第3半導体領域の表面層に配置される第2導電型の第5半導体領域と、前記第4半導体領域と前記第5半導体領域に接続されたグランド電極と、を備え、
前記第5半導体領域は前記第2半導体領域と前記第3半導体領域との間に配置された前記ドレイン領域に対向して配置され、前記第4半導体領域および前記第3半導体領域でガードリングを構成し、前記第1半導体領域、前記第3半導体領域および前記第5半導体領域からなる寄生バイポーラトランジスタでサージ保護素子を構成することを特徴とする半導体装置。
- 前記第3半導体領域と前記ドレイン領域との間の距離が、前記第2半導体領域と前記ドレイン領域との間の距離より短いことを特徴とする請求項2に記載の半導体装置。
- 前記第2半導体領域、前記ドレイン領域および前記第5半導体領域は細長の平面形状で互いに並行に配置され、前記第5半導体領域の長手方向に直角な方向の幅が前記ソース領域の長手方向に直角な方向の幅より広いことを特徴とすることを請求項2または3に記載の半導体装置。
- 前記第4半導体領域の平面形状が島状であり、該島状の第4半導体領域の間に前記第5半導体領域が延在していることを特徴とする請求項4に記載の半導体装置。
- 前記第3半導体領域の拡散深さを選択的に浅くすることを特徴とする請求項2〜5のいずれか一項に記載の半導体装置。
- 前記ドレイン領域を第1導電型のコレクタ領域に換えて横型のMOS型電界効果トランジスタを横型の絶縁ゲート型バイポーラトランジスタに変更することを特徴とする請求項2〜6のいずれか一項に記載の半導体装置。
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