JP5939060B2 - Circuit design support program, circuit design support apparatus, and circuit design support method - Google Patents

Description

  The present invention relates to a circuit design support program, a circuit design support apparatus, and a circuit design support method.

When designing a large scale integrated circuit such as a system LSI (Large Scale Integration), the power consumption (current) of the design target circuit is one of the important design constraints, and the low power consumption of the design target circuit is realized. It will be a strong product power.
Accurate estimation of power consumption is indispensable for correct low power design. By accurately estimating the power consumption at the design stage of the logic circuit of the design target circuit, the cause of the power waste can be accurately grasped and feedback can be applied to the logic circuit design.

In a very large scale integrated circuit such as a recent system LSI, a large number of memories of various sizes are generally incorporated. Therefore, the ratio of the power consumption by the memory to the total power consumption is also high.
The memory is provided as a macroblock IP (Intellectual Property) from a semiconductor manufacturer. The power information of the macro block IP is described in the library as the power per operation corresponding to the IP functional operation. For example, in the case of a memory, power 2 mJ per write operation and power 3 mJ per read operation are described in the library.

  The number of operations, that is, the number of times of writing, and the number of times of reading are obtained by counting with reference to the result waveform of the system level logic simulation. The value obtained by multiplying the acquired number of times of writing and the power 2 mJ per write operation is estimated as the power consumed in the write operation of the memory, and the obtained number of read times per read operation A value obtained by multiplying the power 2 mJ is estimated as the power consumed in the memory write operation.

  However, when attempting to dump all waveforms as a result of system-level logic simulation, the waveform file size becomes several TB (terabytes), and a dump file of all waveforms cannot be prepared. Alternatively, when a semiconductor manufacturing vendor estimates power from a customer's RTL (Register Transfer Level) description, a waveform dump file indicating the operation contents is sent from the customer to the semiconductor manufacturing to prevent leakage of detailed technical contents related to the design target circuit. Sometimes it is not provided to the vendor.

  For this reason, probabilistic motion information (also referred to as motion probability information) that eliminates the temporal order relationship is provided in place of the waveform dump file, and power consumption is estimated using the stochastic motion information. It has become. Probabilistic operation information is operation information averaged over time, and includes the following two pieces of information for each net of the circuit. One is the number of operations per unit time of signals (net, node) such as clock (CLK), chip enable signal (CE), and write enable signal (WE) (the number of toggles; the number of rising and falling times of the signal) Total). The other is a probability that the signal (net, node) has a state value “1”, that is, a “1” state probability. Specific motion probability information will be described later with reference to FIG. Such operation probability information is acquired from a logic simulation of the circuit to be designed.

Here, an input signal and an output signal of the memory will be described with reference to FIG. As shown in FIG. 12, the memory has an address, data input, a write enable signal (WE), a chip enable signal (CE), and a clock (CLK) as inputs, and a data output as an output.
WE is a control input for instructing a memory write / read operation. When WE is “1”, the memory performs a read operation. When WE is “0”, the memory performs a write operation.

CE is a control input for instructing operation / stop of the memory. When CE is “1”, the memory stops and does not operate regardless of the value (change) of other input signals, while CE is “0”. "", The memory operates.
CLK is a clock input. When CLK rises, that is, when CLK changes from “0” to “1”, the memory takes in the values of address, data input, WE, and CE and performs a specified operation. .

Therefore, when CE = 0 and WE = 0, the memory performs a write operation every time CLK rises. That is, the value designated by the data input is written to the address designated by the address in the storage area in the memory.
When CE = 0 and WE = 1, the memory performs a read operation every time CLK rises. That is, the address value specified by the address in the storage area inside the memory is output to the data output.

  By the way, in recent designs, the clock signal CLK is often stopped during a period when the circuit block is not used by using a low power design called clock gating. FIG. 13 shows an example of an input waveform of the memory shown in FIG. 12 including a CLK stop period due to clock gating. FIG. 14 shows an example of motion probability information acquired for the input waveform shown in FIG.

Hereinafter, an estimation method (estimation method) of the number of memory operations, that is, the number of write accesses and the number of read accesses based on the operation probability information illustrated in FIG. 14 will be described.
In FIG. 13, the input waveforms of the above-described signals CLK, CE, and WE are shown, and the write operation point and the read operation point in the input waveform are indicated by arrows. The write operation point is the rising point of CLK when CE = 0 and WE = 0, and the read operation point is the rising point of CLK when CE = 0 and WE = 1.

  In FIG. 13, a section in which CLK is fixed to “0” indicates a stop period of CLK due to the clock gating described above. In FIG. 13, the CLK stop period and the CE = 1 period (memory stop period, inactive period) are not synchronized, and the CLK stop period is shorter than the CE = 1 period (that is, CE = 0 period (memory operation period, active period is shorter than CLK operation period).

  The correct write access count and read access count in the input waveform shown in FIG. 13 are the number of write operation points and read operation points, respectively. In other words, the correct number of write accesses is six times the number of CLK rising operations when CE = 0 and WE = 0, and the number of correct read accesses is the number of CLK rising operations when CE = 0 and WE = 1. The number of times is six. Here, the number of CLK rising operations is the number of CLK operations (toggling) / 2.

  The motion probability information acquired for the input waveform shown in FIG. 13 is as shown in FIG. That is, for the clock CLK, 35.0% is acquired as the “1” state probability, and 28 times are acquired as the number of operations. Further, 40.0% is acquired as the “1” state probability for the chip enable signal CE, 4 times is acquired as the number of operations, and 70.0% is acquired as the “1” state probability for the write enable signal WE. 11 times are acquired as the number of operations.

In the existing estimation method, the number of write accesses and the number of read accesses are estimated using the operation probability information as shown in FIG. 14 as follows.
[Number of write accesses] = [Number of rising edges of CLK] × [Probability that the memory will be in a write state]
= [Number of CLK operations / 2] × [probability of CE = 0 and WE = 0]
= [28/2] x [(1-0.40) x (1-0.70)]
= 2.52
[Number of read accesses] = [Number of rising operations of CLK] × [Probability that the memory is in a read state]
= [Number of CLK operations / 2] × [probability of CE = 0 and WE = 1]
= [28/2] x [(1-0.40) x (0.70)]
= 5.88

JP 2003-256495 A JP 2008-234187 A

  In the example of the input waveform shown in FIG. 13, the memory operation / stop control by CE and the clock gating control are performed in an overlapping manner. However, the operation probability information shown in FIG. 14 does not include information related to the overlapping relationship between the memory operation / stop control by the CE and the clock gating control. The clock operation count after the clock gating control is included as the CLK operation count, and the memory operation / stop control information by the CE is included as the CE state probability. For this reason, in the above-described existing method, the memory operation / stop control by CE and the clock gating control are calculated as probabilities, and the number of CLK operations after clock gating control is multiplied by the CE state probability. Thus, the number of accesses is calculated. Therefore, the error of the estimation result (estimated value) of the number of write accesses and the number of read accesses becomes extremely large.

  Further, as a ratio between the read operation and the write operation (READ / WRITE ratio) of the memory, it is desirable to use a ratio only when the memory is operating, that is, when CE = 0. However, as shown in the input waveform of FIG. 13, when the memory is stopped, that is, when CE = 1, WE is fixedly set to “1”, and the memory is regarded as performing the reading operation. . This is presumably because the write operation to the memory destroys (rewrites) the data inside the memory, but the read operation to the memory retains and does not destroy the data inside the memory. Therefore, the “1” state probability of WE in the operation probability information shown in FIG. 14 includes the state probability of the read operation when the memory is stopped, that is, when CE = 1. However, the ratio of the read operation tends to increase. Due to such a tendency, an error in the estimation result (estimated value) of the number of write accesses and the number of read accesses is further increased.

As described above, when estimating the number of write accesses and the number of read accesses with the existing method based on the operation probability information as shown in FIG. 14, the error of the estimation result (estimated value) is large, and the power consumption of the memory is accurately determined. It cannot be estimated.
In one aspect, an object of the present invention is to accurately estimate the number of accesses to a memory of a circuit to be designed.

  In one proposal, the circuit design support program includes circuit data relating to a circuit to be designed, a number of operations per unit time of a clock to the memory of the circuit to be designed, and a first instruction for operating / stopping the memory. Based on the operation probability information including the state probability of the control signal, the computer for estimating the number of accesses to the memory controls the gating cell for performing the clock gating based on the circuit data, and the gating cell. When the first control cell and the operation information of the clock source of the clock are extracted and the gating cell is extracted, the operation information per unit time output from the clock source included in the operation information of the clock source is extracted. Clock gating indicating the ratio of the number of operations per unit time of the clock to the total number of operations When the gating cell is extracted by calculating an operation rate, a second control cell that outputs the first control signal is extracted based on the circuit data, and the first control cell, the second control cell, Based on the operation probability information, the clock gating operation rate, and the total number of operations, a process of calculating an estimated value of the number of accesses to the memory is executed.

  According to one embodiment, the number of accesses to the memory of the circuit to be designed can be accurately estimated.

It is a block diagram which shows the hardware constitutions and functional structure of the circuit design support apparatus of this embodiment. 3 is a flowchart for explaining the operation of the circuit design support apparatus shown in FIG. 3 is a flowchart for explaining clock gating analysis processing by the circuit design support apparatus shown in FIG. 1. It is a figure explaining the original clock (clock source) extracted by backtrace. It is a figure explaining the control cell extracted by backtrace. It is a figure explaining READ / WRITE analysis processing. (A), (B) is a figure explaining READ / WRITE analysis processing. (A)-(C) is a figure explaining READ / WRITE analysis processing. It is a figure which shows the specific example of the "1" state probability and the frequency | count of operation of a memory input clock and a large original clock (clock source). FIG. 10 is a diagram illustrating operation waveforms of a main clock (clock source) and a memory input clock corresponding to the specific example illustrated in FIG. 9. It is a figure which shows the write access frequency | count and read access frequency | count finally calculated as electric power operation information. It is a figure explaining the input signal and output signal of a memory. It is a wave form diagram which shows an example of the input waveform of the memory shown in FIG. It is a figure which shows an example of the operation | movement probability information acquired about the input waveform shown in FIG.

Hereinafter, embodiments will be described with reference to the drawings.
[1] Configuration and Function of Circuit Design Support Device FIG. 1 is a block diagram showing the hardware configuration and functional configuration of the circuit design support device 1 of this embodiment.

A circuit design support apparatus 1 shown in FIG. 1 estimates the number of accesses to a memory in a design target circuit such as a system LSI, and estimates power consumption of the design target circuit when designing a logic circuit for the design target circuit. Used for.
The circuit design support apparatus 1 includes a storage unit 10 and a processing unit (processor) 20.

  The storage unit 10 may be an internal storage device such as a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), or a solid state drive (SSD), or an external storage device. Also good. The storage unit 10 includes at least circuit data related to the design target circuit, operation probability information as described above with reference to FIG. 14, and a circuit design support program that causes the computer (processing unit 10) to operate as the circuit design support device 1. And remember. The operation probability information is acquired from the result of logic simulation of the design target circuit for each memory on the design target circuit, and includes the following information (a1) to (a6) as shown in FIG.

(a1) Number of operations per unit time of CLK to the memory on the design target circuit (number of toggles)
(a2) Probability that the CLK has the state value “1” (“1” state probability)
(a3) Number of operations per unit time of the first control signal CE instructing the operation / stop of the memory
(a4) “1” state probability of CE
(a5) The number of operations per unit time of the second control signal WE instructing the write / read operation of the memory
(a6) “1” state probability of the WE

  The processing unit 20 executes a circuit design support program to thereby describe a first extraction unit 21, a first calculation unit 22, a second extraction unit 23, a second calculation unit 24, a correction unit 25, and a third calculation unit 26, which will be described later. Serves as a function.

  The first extraction unit 21 is based on circuit data, a gating cell (CGC) that performs CLK gating, and a first control cell (control logic cell; for example, flip-flop (FF)) that controls the CGC And the operation information of the clock source (main clock) of CLK (see FIGS. 4 and 5). At this time, the first extraction unit 21 performs backtrace from the CLK input terminal in the memory based on the circuit data, thereby extracting operation information of the CGC, the first control cell, and the main clock. The CGC is, for example, an AND gate that outputs a logical product of the control signal from the first control cell and CLK (see FIG. 5).

  The first calculation unit 22 calculates a clock gating operation rate (CG operation rate) when CGC is extracted, that is, when CG is present. The CG operation rate is the [per unit time of CLK input to the memory with respect to [total number of operations per unit time (operation frequency) output from the main clock] included in the operation information of the main clock. Of operation count].

  When CGC is extracted, that is, when CG is present, the second extraction unit 23 extracts a second control cell (control logic cell; for example, FF) that outputs CE based on circuit data (see FIG. 5). At this time, the second extraction unit 23 extracts the second control cell by performing back tracing from the CE input terminal in the memory based on the circuit data.

Based on the first control cell, the second control cell, the operation probability information, the CG operation rate, and the total number of operations, the second calculation unit 24 performs the number of accesses to the memory as in the following items (b1) to (b5). The estimated value of is calculated.
(b1) When the state value of CE is always “1” (CE = 1), the memory is always stopped. Therefore, the memory is not accessed, and the second calculator 24 outputs 0 as the estimated number of accesses (see step S12 in FIG. 3).

  (b2) When the state value of CE is always “0” (CE = 0), the memory is always operating. Accordingly, since the memory is accessed at the rising timing of all CLK, the second calculation unit 24 calculates [the number of operations of CLK included in the operation probability information] / 2 times (see step S14 in FIG. 3). .

  (b3) When the CGC is not extracted, that is, when there is no CG, the number of accesses to the memory is not controlled by the CG but is controlled by the memory operation / stop switching by the CE. Therefore, the second calculation unit 24 uses ([number of operations per unit time of CLK to the memory included in the operation probability information] / 2) × [operation state probability of the memory] as the estimated number of accesses. Times are calculated (see step S21 in FIG. 3). Here, the operation state probability of the memory is a probability that the CE state value is “0” (= 1− [CE “1” state probability included in the operation probability information]).

  (b4) When the first control cell and the second control cell are the same, that is, when the CG and the CE are synchronized, the second calculation unit 24 uses [the operation probability information includes: The number of operations of CLK to the memory per unit time] / 2 times is calculated (see step S24 in FIG. 3).

  (b5) When the first control cell is different from the second control cell, that is, when the CG and the CE are not synchronized, the second calculation unit 24 calculates the estimated number of accesses as follows. That is, the second calculation unit 24 is the smaller of the memory operation state probability obtained based on the CE state probability included in the operation probability information and the CG operation rate calculated by the first calculation unit 22. Is selected as the operation rate of the memory (see step S26 in FIG. 3). Here, the operation state probability of the memory is a probability that the state value of CE is “0” (CE = 0), and corresponds to a period in which CE is enabled. The CG operation rate corresponds to the operation period of CLK by CG. Then, the second calculator 24 calculates ([total number of operations included in the operation information of the main clock] / 2) × [selected operation rate] times as an estimated value of the number of accesses (FIG. 3). Step S27).

  The correction unit 25 estimates the state of the WE when the memory is in a stopped state based on the state probability of the CE and the state probability of the WE included in the operation probability information, and reads out the memory from the memory based on the estimation result. Correct the ratio to the writing state (READ / WRITE ratio). At this time, the correction unit 25 estimates the state of the WE when the memory is in the stopped state as in the following items (c1) to (c4). Details of the state estimation conditions of the following items (c1) to (c4) and specific examples of correction of the WE state probability based on the state estimation conditions will be described later with reference to FIGS.

  (c1) The probability (hereinafter referred to as the read state probability) that the WE indicates a state (WE = 1) instructing the read operation (hereinafter referred to as the read state probability) (hereinafter referred to as the stop state probability). And the read state probability is greater than or equal to the probability that CE is in a state of instructing an operation (CE = 0) (= 1−the stop state probability; hereinafter referred to as the operation state probability). It is presumed that the state of the WE when the memory is stopped is fixed to the read state.

(c2) When the read state probability is greater than the stop state probability and the read state probability is less than the operation state probability, the state of the WE when the memory is in the stop state is fixed to the read state presume.
(c3) When the read state probability is less than or equal to the stop state probability and the read state probability is less than or equal to the operation state probability, the state of the WE when the memory is in the stop state is fixed to the write state Estimated.
(c4) When the read state probability is less than the stop state probability and the read state probability is larger than the operation state probability, the state of the WE when the memory is in the stop state is the WE “1” state probability. It is estimated that the read state and the write state are obtained at the corresponding ratio.

  The third calculator 26 calculates the number of write accesses and the number of read accesses to the memory based on the ratio corrected by the corrector 25 and the estimated number of accesses calculated by the second calculator 24. Specific examples of the number of write accesses and the number of read accesses calculated by the third calculator 26 will be described later with reference to FIGS.

[2] Operation of Circuit Design Support Device Next, the operation of the circuit design support device 1 configured as described above will be described with reference to FIGS.
FIG. 2 is a flowchart for explaining the operation of the circuit design support apparatus 1 shown in FIG. As shown in FIG. 2, the circuit design support apparatus 1 operates in two phases, namely, a clock gating analysis process (step S1) and a READ / WRITE analysis process (step S2).

  In the clock gating analysis process (step S1), based on the circuit data and the operation probability information, the presence / absence of clock gating (CG) for CLK input to the target memory and whether CG and CE are synchronized. The number of accesses to the target memory is estimated based on the check result. This clock gating analysis process is executed by the first extraction unit 21, the first calculation unit 22, the second extraction unit 23, and the second calculation unit 24 described above, and will be described later with reference to FIGS.

  In the READ / WRITE analysis process (step S2), the WE state when the target memory is in a stopped state is estimated based on the CE state probability and the WE state probability. The ratio to the writing state (READ / WRITE ratio) is corrected. Based on the corrected ratio and the number of accesses to the target memory estimated in the clock gating analysis process (step S1), the number of write accesses and the number of read accesses to the target memory are calculated, and the power operation of the target memory Output as information. This READ / WRITE analysis process is executed by the correction unit 25 and the third calculation unit 26, and will be described later with reference to FIGS.

[2-1] Clock Gating Analysis Process According to the flowchart shown in FIG. 3 (steps S11 to S27), the clock gating analysis process (step S1 in FIG. 2) by the circuit design support device 1 with reference to FIGS. Will be described. FIG. 4 is a diagram for explaining a large source clock (clock source) extracted by backtrace, and FIG. 5 shows control cells (first control cell and second control cell) extracted by backtrace. It is a figure explaining.

  First, the provided motion probability information is referenced to determine whether the CE state value is always “1” (CE = 1), that is, whether the “1” state probability of CE is 100%. (Step S11). If CE is always 1 (YES route in step S11), the memory is always stopped. Therefore, access to the target memory is not performed, and the second calculation unit 24 outputs 0 as the estimated number of accesses (step S12).

  If CE is not always 1 (NO route in step S11), whether or not the CE state value is always “0” (CE = 0), that is, whether or not the CE “1” state probability is 0%. Is determined (step S13). When CE = 0 is always set (YES route in step S13), the memory is always operating. Therefore, since the target memory is accessed at the rising timing of all CLK, the second calculation unit 24 calculates [number of times of operation of CLK included in the operation probability information] / 2 times (step S14).

  When CE is not always 0 (NO route of step S13), that is, when 0 <[CE “1” state probability] <1, the first extraction unit 21 receives the CLK input terminal of the target memory based on the circuit data. A back trace is performed (step S15). As a result, CGC (for example, an AND gate; see FIG. 5), a first control cell (control logic cell; for example, FF; see FIG. 5) for controlling the CGC, and operation information on the original clock of CLK (see FIG. 4) Are extracted (see FIGS. 4 and 5; steps S16 to S18). In the example shown in FIG. 4, the number of operations (operation frequency) of CLK (memory CLK input) input to the target memory is 56 MHz, and the number of operations (operation frequency) of the main clock of CLK is 80 MHz.

  When the CGC is extracted, the CG operation rate is calculated by the first calculation unit 22 (step S19). As described above, the CG operation rate is calculated based on [the total number of operations (operation frequency) per unit time output from the main clock] of CLK input to the memory included in the operation information of the main clock. It is calculated as a ratio of the number of operations per unit time.

After performing the processing of steps S15 to S19, it is determined whether or not CGC is extracted, that is, whether or not CG is present (step S20).
When there is no CG (NO route in step S20), the second calculation unit 24 uses the [number of operations per unit time of CLK to the target memory included in the operation probability information] / 2 as an estimated value of the number of accesses. ) × [operating state probability of target memory (probability of CE = 0)] times is calculated (step S21). Note that [number of operations per unit time of CLK to the target memory included in the operation probability information] / 2 is the number of rising times per unit time of CLK to the target memory (sometimes referred to as the number of times of rising operation). .

  If there is a CG (YES route in step S20), the second extraction unit 23 performs a back trace from the CE input terminal of the target memory based on the circuit data (step S22). Thus, the second control cell (control logic cell; for example, FF; see FIG. 5) that outputs CE is extracted. In the example shown in FIG. 5, the first control cell (FF that controls CGC) extracted by the first extraction unit 21 and the second control cell (FF that outputs CE) extracted by the second extraction unit 23. And CG and CE are synchronized.

Thereafter, it is determined whether or not the first control cell (FF that controls CGC) and the second control cell (FF that outputs CE) are the same, that is, whether or not CG and CE are synchronized. (Step S23).
When the first control cell and the second control cell are the same (YES route in step S23), the second calculation unit 24 calculates [the unit of CLK to the target memory included in the operation probability information] as the estimated number of accesses. The number of operations per time] / 2 times is calculated (step S24).

On the other hand, when the first control cell and the second control cell are different (NO route in step S23), the second calculation unit 24 calculates the estimated number of accesses as follows.
First, an overlap between the CG CLK operation period and the CE enabled period is estimated (step S26). At this time, the smaller of the operation state probability of the target memory corresponding to the CE enabled period (probability of CE = 0) and the CG operation rate calculated in step S19 is the operation rate (operation of the target memory). (State period) is selected (step S26).

In the present embodiment, it is assumed that the inclusion relationship (overlapping condition) between the control by CE and the control by CG tends to include the shorter period with the shorter period. Therefore, in this embodiment, when the CLK operation period is different from the CE enabled period, the shorter one is estimated as the actual CLK operation period.
Then, the second calculation unit 24 calculates ([total number of operations included in the operation information of the main clock] / 2) × [selected operation rate] times as the estimated value of the number of accesses (step S27). ). Note that [the total number of operations included in the operation information of the main clock] / 2 is the number of rising operations per unit time of the main clock.

[2-2] READ / WRITE Analysis Processing Next, referring to FIGS. 6, 7A, 7B, and 8A to 8C, the READ / WRITE analysis processing ( Step S2) in FIG. 1 will be described.
First, based on the CE state probability and the WE state probability, the correction unit 25 estimates the state of the WE when the target memory is in the stopped state (CE = 1).
Here, as described above, WE is a control input for switching between a read operation and a write operation of the target memory. For example, the “1” state probability and the number of operations of the WE in the operation probability information shown in FIG. 14 are values based on the entire period in which the operation of the target memory is measured, and the period in which the target memory is used (CE = 0). It is not calculated separately from the period when the target memory is not used (CE = 1).

  As described above, it is desirable to use a ratio only when the memory is operating, that is, when CE = 0, as the ratio between the read operation and the write operation of the memory (READ / WRITE ratio). However, conventionally, as shown in the input waveform of FIG. 13, when the memory is stopped, that is, when CE = 1, WE is fixedly set to “1” and the memory is regarded as performing a read operation. It is. For this reason, the ratio of the read operation is larger than that of the write operation, and the error of the estimation result (estimated value) of the number of write accesses and the number of read accesses is large.

  Therefore, in this embodiment, first, the correction unit 25 estimates the state value of the WE when the target memory is not used (when CE = 1) as shown in FIG. In the example shown in FIG. 6, the plane defined by two values of the probability of WE being “1” (WE “1” state probability) and the stop state probability (CE “1” state probability) is 4 The areas are classified into two areas (1) to (4), and correction processing is defined for each of the areas (1) to (4). In other words, the correction unit 25 determines a region to which the “1” state probability of WE and the “1” state probability of CE given by the motion probability information belong in FIG. 6, so that the target memory is not used ( The state value of WE at the time of CE = 1) is estimated, and correction processing according to the estimated state value is performed.

Here, the regions (1) to (4) shown in FIG. 6 will be described. Regions (1) to (4) shown in FIG. 6 correspond to the items (c1) to (c4) described above, respectively.
The region (1) corresponds to the item (c1), and [read state probability (WE “1” state probability)] ≧ [stop state probability (CE “1” state probability)] and [read state probability] ≧ [operating state probability (= 1−stop state probability)] region. When the “1” state probability of the WE and the “1” state probability of the CE given by the operation probability information belong to the region (1), the state of the WE when the target memory is in the stopped state is the read state (WE = 1). ) And the READ / WRITE ratio is corrected.

  The region (2) corresponds to the item (c2) and is a region of [reading state probability]> [stop state probability] and [reading state probability] <[operation state probability]. When the “1” state probability of the WE and the “1” state probability of the CE given by the operation probability information belong to the region (2), the state of the WE when the target memory is in the stopped state is the read state (WE = 1). ) And the READ / WRITE ratio is corrected. In the area (2), even when the WE is fixed to “1” when the memory is not used (when CE = 1), the WE is “0” when the memory is not used (when CE = 1). This is an area of values that can be taken even when fixed to. When both WE = 1 and WE = 0 can be taken, the write operation to the memory destroys (rewrites) the data inside the memory, but the read operation to the memory retains the data inside the memory and does not destroy it. Therefore, many designs for selecting the read operation (WE = 1) can be seen. For this reason, in the area (2), it is estimated that the state of the WE when the target memory is in the stopped state is fixed to the read state (WE = 1).

  The region (3) corresponds to the item (c3) and is a region of [reading state probability] ≦ [stop state probability] and [reading state probability] ≦ [operation state probability]. When the “1” state probability of the WE and the “1” state probability of the CE given by the operation probability information belong to the region (3), the state of the WE when the target memory is in the stopped state is the write state (WE = 0) and the READ / WRITE ratio is corrected.

  The region (4) corresponds to the item (c4) and is a region of [reading state probability] <[stop state probability] and [reading state probability]> [operation state probability]. When the “1” state probability of the WE and the “1” state probability of the CE given by the operation probability information belong to the region (4), the state of the WE when the target memory is stopped is “1” of the WE. It is estimated that a read state and a write state are entered at a READ / WRITE ratio corresponding to the state probability.

  As shown in FIG. 7A, when the WE is fixed to “1” when the memory is not used (when CE = 1), the “1” state probability of the WE and the “1” state of the CE The probability is always a value belonging to the region A. Further, as shown in FIG. 7B, when the WE is fixed to “0” when the memory is not used (when CE = 1), the “1” state probability of the WE and the “1” state of the CE The probability is always a value belonging to the region B. From the above, the determination according to the items (c1) to (c4) (the above regions (1) to (4)) is performed.

Thereafter, as shown in FIGS. 8A to 8C, the correction unit 25 reads and writes the target memory with respect to the target memory based on the estimation result when the target memory is operating (CE = 0). The ratio (READ / WRITE ratio) is calculated and corrected.
8A to 8C, r% is a “1” state probability (read state probability) of WE given by the operation probability information, and w (= 100−r)% is This is the writing state probability. Further, t% is the “1” state probability (stop state probability) of CE given by the operation probability information, and d (= 100−t)% is the operation state probability. Further, in FIG. 8C, r1% is the read state probability when the target memory is stopped, w1% is the write state probability when the target memory is stopped, and r2% is the operation of the target memory. Is a read state probability, and w1% is a write state probability during operation of the target memory. r1: w1 = r2: w2 = r: w, r = r1 + r2, w = w1 + w2.

  In FIG. 8A, according to the item (c1) or (c2) (areas (1), (2)), the state of WE is fixed to the read state (WE = 1) while the target memory is stopped. An example of correction of the READ / WRITE ratio is shown. In FIG. 8A, since the state of WE is fixed to the read state (WE = 1) while the target memory is stopped, the read state probability during the operation of the target memory is corrected to rt%, The writing state probability during the operation is w%.

  FIG. 8B shows the read / write when it is estimated that the state of WE is fixed to the write state (WE = 0) while the target memory is stopped according to the item (c3) (region (3)). An example of correcting the WRITE ratio is shown. In FIG. 8B, while the target memory is stopped, the state of WE is fixed to the write state (WE = 0), so the write state probability during the operation of the target memory is corrected to w−t%, The read state probability during the operation of the target memory is r%.

  FIG. 8C shows READ / WRITE when it is estimated that the ratio between the read state and the write state is the same regardless of whether the target memory is stopped or operating according to the item (c4) (region (4)). An example of correcting the ratio will be shown. At this time, the read state probability during operation of the target memory is corrected to d × r%, and the write state probability during operation of the target memory is corrected to d × w%.

  Then, the ratio corrected as described above (that is, the write state probability and the read state probability) by the third calculator 26 and the estimated number of accesses to the target memory obtained in the clock gating analysis process (step S1). Based on the above, the number of write accesses and the number of read accesses to the target memory are calculated as follows.

[Number of write accesses]
= [Estimated number of accesses] × [write state probability] / ([write state probability] + [read state probability])
[Read access count]
= [Estimated number of accesses] x [read state probability] / ([write state probability] + [read state probability])

[2-3] Specific Example Next, specific examples of the number of write accesses and the number of read accesses calculated and estimated by the present embodiment will be described with reference to FIGS. Again, the procedure for estimating the number of write accesses and the number of read accesses by the circuit design support apparatus 1 of the present embodiment based on the operation probability information shown in FIG. 14 acquired for the input waveform shown in FIG. Explained.

  First, the “1” state probability of the CE is checked. In the example shown in FIG. 14, since the CE “1” state probability is 40.0% (NO route in step S11 and NO route in step S13 in FIG. 3), back tracing is performed from the CLK input terminal of the target memory. (Step S15). Along with the backtrace, CGC (for example, an AND gate) is extracted (step S16).

  The control input terminal and the CLK input terminal of the CGC are often distinguished from each other as attributes of the input terminal. However, when a gate whose type is not defined in the pin, such as an AND gate, is used as the CGC, the number of operations It is recognized that the larger one is the CLK input terminal and the smaller one is the control input terminal. By going back to the CGC control input terminal, a register (first control cell, control logic cell) that is the source of the CGC control signal is extracted (step S17).

  On the other hand, from the CLK input terminal of the CGC, the logic is traced back to extract the clock source (large source clock) that is the source of CLK and its operation information (step S18). Then, the first calculation unit 22 sets the CG operation rate as the ratio of [number of operations per unit time of CLK input to the memory] to [total number of operations per unit time output from the main clock]. Calculated (step S19).

  Here, FIG. 9 shows a concrete example of the “1” state probability and the number of operations of the memory input clock and the master clock (clock source), and FIG. 10 shows the master corresponding to the concrete example shown in FIG. The operating waveforms of the clock and memory input clock are shown. In the examples shown in FIGS. 9, 10, and 13, the “1” state probability and the number of operations of the memory input clock (CLK) are 35% and 28, respectively. Are 50% and 40 times, respectively. Then, 28/70 = 70% is calculated as the CG operation rate.

  Thereafter, when the fan-in of the memory CE input and the fan-in of the clock gating control input are generated from the same cell (register, FF), that is, the first control cell extracted by the first extraction unit 21 When the second control cell extracted by the second extraction unit 23 is the same (YES route in step S23), it is determined that the clock gating and the memory CE control are synchronized. Otherwise (NO route of step S23), an overlap between the CG CLK operation period and the CE enabled period is estimated (step S25).

  In this specific example, the control logic (second control cell) of the memory CE input and the control logic of the CG (first control cell) are different and are not derived from a common signal even when going back to the circuit. To do. At this time, the smaller of the operation state probability of the target memory corresponding to the CE enabled period (the probability that CE = 0) and the CG operation rate calculated by the first calculation unit 22 is the smaller of the target memory. It is selected as the operation rate (operation state period) (step S26).

Here, in the operation probability information shown in FIG. 14, the operation state probability of the target memory (the probability that CE = 0) is 100−40 = 60%, and the CG operation rate calculated by the first calculation unit 22 is Since it is 70%, 60% is selected as the target memory operation rate.
Then, the second calculation unit 24 uses ([total number of operations included in the operation information of the original clock] / 2) × [selected operation rate] times = (40 times / 2) × 60% = 12 times is calculated (step S27).

  Next, the correction unit 25 corrects the ratio between the read state and the write state of the target memory as follows. In the motion probability information shown in FIG. 14, the stop state probability (CE “1” state probability) is 40%, and the WE “1” state probability is 70%. These values are in the region (1) shown in FIG. Therefore, it is estimated that the state of the WE when the target memory is in the stopped state is fixed to the read state (WE = 1). Therefore, as in the correction example shown in FIG. 8A, the write state probability during the target memory operation is corrected to 30%, the read state probability during the target memory operation is 30%, and the stop state probability of the target memory is 40%.

Then, based on the write state probability 30% and the read state probability 30% corrected as described above and the estimated number of access times 12 by the third calculator 26, the number of write accesses and the read access to the target memory are performed. The number of times is finally calculated as follows.
[Number of write accesses]
= [Estimated number of accesses] × [write state probability] / ([write state probability] + [read state probability])
= 12 × 30 / (30 + 30)
= 6 times
[Read access count]
= [Estimated number of accesses] x [read state probability] / ([write state probability] + [read state probability])
= 12 × 30 / (30 + 30)
= 6 times

In this way, the number of write accesses and the number of read accesses of 6 are finally calculated and output as power operation information as shown in FIG.
In the existing estimation method, when the number of write accesses and the number of read accesses are estimated using the operation probability information shown in FIG. 14, 2.52 times are obtained as the number of write accesses and 5.88 times as the number of read accesses. Was obtained.
On the other hand, according to the circuit design support device 1 of the present embodiment, the number of write accesses and the number of read accesses to the target memory are closer to the actual number of accesses compared to the existing method (this time actual access The same value as the number of times) is estimated.

[3] Effects of Circuit Design Support Device According to the circuit design support device 1 of the present embodiment, the presence / absence of CG is determined. If there is a CG, it is determined whether CG and CE are synchronized. . If CG and CE are not synchronized, the overlap between the CG CLK operation period and the CE enabled period is estimated. At this time, the smaller of the operation state probability of the target memory corresponding to the CE enabled period (probability of CE = 0) and the CG operation rate calculated by the first calculation unit 22 is the operation of the target memory. It is selected as a rate (operation state period), and the number of accesses is calculated based on the selected operation rate. Thus, by estimating the inclusion relationship between the CG CLK operation period and the CE enabled period, the number of accesses to the target memory can be accurately estimated based on the estimation result.

  Further, according to the circuit design support device 1 of the present embodiment, the correction unit 25 estimates the WE state value when the target memory is not used (when CE = 1), and according to the estimation result, The read state probability and the write state probability for the target memory are corrected. Then, based on the estimated number of accesses calculated by the second calculator 24 and the read state probability and write state probability corrected by the corrector 25, the third calculator 26 writes to the target memory. The number of accesses and the number of read accesses are calculated and estimated more accurately than in the existing method.

  Thus, according to the circuit design support apparatus 1 of the present embodiment, it is possible to accurately estimate the number of write accesses and the number of read accesses compared to the existing method based on the operation probability information as shown in FIG. Thus, the power consumption of the memory can be accurately estimated.

[4] Others While the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to such a specific embodiment, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.
In the embodiment described above, the case where the access count is estimated based on the operation probability information as shown in FIG. 14 acquired for the input waveform shown in FIG. 13 has been described, but the present invention is as shown in FIG. It is not limited to motion probability information.

  All or part of the functions of the first extraction unit 21, the first calculation unit 22, the second extraction unit 23, the second calculation unit 24, the correction unit 25, and the third calculation unit 26 described above are performed by a computer (CPU, information This is realized by executing a predetermined application program (circuit design support program) by a processing device and various terminals).

  The program is, for example, a flexible disk, CD (CD-ROM, CD-R, CD-RW, etc.), DVD (DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, etc.), Blu-ray Disc And the like recorded in a computer-readable recording medium. In this case, the computer reads the program from the recording medium, transfers it to the internal storage device or the external storage device, and uses it.

  Here, the computer is a concept including hardware and an OS (operating system), and means hardware operating under the control of the OS. Further, when the OS is unnecessary and the hardware is operated by the application program alone, the hardware itself corresponds to the computer. The hardware includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium. The circuit design support program functions as a first extraction unit 21, a first calculation unit 22, a second extraction unit 23, a second calculation unit 24, a correction unit 25, and a third calculation unit 26 on the above-described computer. The program code that realizes is included. Also, some of the functions may be realized by the OS instead of the application program.

[5] Supplementary Notes Regarding the above embodiment, the following supplementary notes are further disclosed.
(Appendix 1)
Circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory of the circuit to be designed, and the state probability of the first control signal instructing operation / stop of the memory; To estimate the number of accesses to the memory based on
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
Calculating an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations;
A circuit design support program that executes processing.

(Supplementary Note 2) Program Claim When the first control cell and the second control cell are different, the operation state probability of the memory obtained based on the state probability of the first control signal included in the operation probability information, and the The smaller of the clock gating operation rate is selected as the operation rate of the memory, and the estimated value is calculated based on the selected operation rate and the total number of operations.
The circuit design support program according to appendix 1, which causes the computer to execute processing.

(Appendix 3)
When the first control cell and the second control cell are the same, the estimated value is calculated based on the number of operations per unit time of the clock to the memory included in the operation probability information.
The circuit design support program according to appendix 1 or appendix 2, which causes the computer to execute processing.

(Appendix 4)
When the gating cell is not extracted, the estimated value is calculated based on the number of operations per unit time of the clock to the memory and the state probability of the first control signal included in the operation probability information. ,
The circuit design support program according to any one of supplementary notes 1 to 3, which causes the computer to execute processing.

(Appendix 5)
By performing a back trace from the clock input terminal in the memory based on the circuit data, operation information of the gating cell, the first control cell, and the clock source is extracted.
The circuit design support program according to any one of supplementary notes 1 to 4, which causes the computer to execute processing.

(Appendix 6)
Extracting the second control cell by performing a back trace from the input terminal of the first control signal in the memory based on the circuit data;
The circuit design support program according to any one of supplementary notes 1 to 5, which causes the computer to execute processing.

(Appendix 7)
The operation probability information includes a state probability of a second control signal instructing a write / read operation of the memory,
Based on the state probability of the first control signal and the state probability of the second control signal included in the operation probability information, the state of the second control signal when the memory is in a stopped state is estimated and estimated Based on the result, the ratio of the read state and the write state to the memory is corrected,
Calculating the number of write accesses and the number of read accesses to the memory based on the corrected ratio and the estimated value calculated by the second calculator;
The circuit design support program according to any one of supplementary notes 1 to 6, which causes the computer to execute processing.

(Appendix 8)
The probability that the second control signal is in a state of instructing a read operation (hereinafter referred to as a read state probability) is equal to or greater than the probability that the first control signal is in a state of instructing a stop (hereinafter referred to as a stop state probability). When the read state probability is equal to or higher than the probability that the first control signal is in a state of instructing an operation (= 1−the stop state probability; hereinafter referred to as the operation state probability), the memory is in the stop state. The state of the second control signal at a certain time is estimated to be fixed to the read state,
When the read state probability is greater than the stop state probability and the read state probability is less than the operation state probability, the state of the second control signal when the memory is in a stop state is a read state. Presumed to be fixed,
When the read state probability is less than or equal to the stop state probability and the read state probability is less than or equal to the operation state probability, the state of the second control signal when the memory is in a stop state is a write state Estimated to be fixed to
When the read state probability is less than the stop state probability and the read state probability is greater than the operation state probability, the state of the second control signal when the memory is in the stop state is the second state Estimating that the read state and the write state are obtained at a ratio corresponding to the state probability of the control signal.
The circuit design support program according to appendix 7, which causes the computer to execute processing.

(Appendix 9)
A circuit design support device for estimating the number of accesses to a memory of a circuit to be designed,
Stores circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory, and a state probability of a first control signal instructing operation / stop of the memory. A storage unit;
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and a first extraction unit that extracts operation information of a clock source of the clock;
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted A first calculation unit for calculating a gating operation rate;
A second extraction unit that extracts a second control cell that outputs the first control signal based on the circuit data when the gating cell is extracted;
A second calculation unit that calculates an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations. Circuit design support device.

(Appendix 10)
When the first control cell and the second control cell are different from each other, the second calculation unit is configured to obtain an operation state probability of the memory obtained based on a state probability of the first control signal included in the operation probability information. The circuit design according to appendix 9, wherein the smaller one of the clock gating operation rates is selected as the operation rate of the memory, and the estimated value is calculated based on the selected operation rate and the total number of operations. Support device.

(Appendix 11)
When the first control cell and the second control cell are the same, the second calculation unit calculates the estimated value based on the number of operations per unit time of the clock to the memory included in the operation probability information. The circuit design support apparatus according to Supplementary Note 9 or Supplementary Note 10, which is calculated.

(Appendix 12)
When the gating cell is not extracted, the second calculation unit is based on the number of operations per unit time of the clock to the memory and the state probability of the first control signal included in the operation probability information. The circuit design support device according to any one of Supplementary Note 9 to Supplementary Note 11, wherein the estimated value is calculated.

(Appendix 13)
The first extraction unit extracts operation information of the gating cell, the first control cell, and the clock source by performing backtrace from the clock input terminal in the memory based on the circuit data. The circuit design support device according to any one of 9 to appendix 12.

(Appendix 14)
The second extraction unit extracts the second control cell by performing a back trace from the input terminal of the first control signal in the memory based on the circuit data. Circuit design support device described in 1.

(Appendix 15)
The operation probability information includes a state probability of a second control signal instructing a write / read operation of the memory,
Based on the state probability of the first control signal and the state probability of the second control signal included in the operation probability information, the state of the second control signal when the memory is in a stopped state is estimated and estimated A correction unit that corrects a ratio between a read state and a write state with respect to the memory based on a result;
A third calculation unit for calculating the number of write accesses and the number of read accesses to the memory based on the ratio corrected by the correction unit and the estimated value calculated by the second calculation unit; The circuit design support apparatus according to any one of Supplementary Note 9 to Supplementary Note 14.

(Appendix 16)
The correction unit is
The probability that the second control signal is in a state of instructing a read operation (hereinafter referred to as a read state probability) is equal to or greater than the probability that the first control signal is in a state of instructing a stop (hereinafter referred to as a stop state probability). When the read state probability is equal to or higher than the probability that the first control signal is in a state of instructing an operation (= 1−the stop state probability; hereinafter referred to as the operation state probability), the memory is in the stop state. The state of the second control signal at a certain time is estimated to be fixed to the read state,
When the read state probability is greater than the stop state probability and the read state probability is less than the operation state probability, the state of the second control signal when the memory is in a stop state is a read state. Presumed to be fixed,
When the read state probability is less than or equal to the stop state probability and the read state probability is less than or equal to the operation state probability, the state of the second control signal when the memory is in a stop state is a write state Estimated to be fixed to
When the read state probability is less than the stop state probability and the read state probability is greater than the operation state probability, the state of the second control signal when the memory is in the stop state is the second state The circuit design support device according to appendix 15, wherein it is estimated that the read state and the write state are obtained at a ratio corresponding to the state probability of the control signal.

(Appendix 17)
Circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory of the circuit to be designed, and the state probability of the first control signal instructing operation / stop of the memory; A method for estimating the number of accesses to the memory by a computer,
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
A circuit design support method for calculating an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations.

(Appendix 18)
When the first control cell and the second control cell are different, the operation state probability of the memory and the clock gating operation rate obtained based on the state probability of the first control signal included in the operation probability information 18. The circuit design support method according to appendix 17, wherein the smaller one of the two is selected as the operation rate of the memory, and the estimated value is calculated based on the selected operation rate and the total number of operations.

(Appendix 19)
The operation probability information includes a state probability of a second control signal instructing a write / read operation of the memory,
Based on the state probability of the first control signal and the state probability of the second control signal included in the operation probability information, the state of the second control signal when the memory is in a stopped state is estimated and estimated Based on the result, the ratio of the read state and the write state to the memory is corrected,
The circuit design support method according to appendix 17 or appendix 18, wherein the number of write accesses and the number of read accesses to the memory are calculated based on the corrected ratio and the estimated value calculated by the second calculator. .

(Appendix 20)
A circuit design support device for estimating the number of accesses to a memory of a circuit to be designed,
Stores circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory, and a state probability of a first control signal instructing operation / stop of the memory. A storage unit;
A processor, and
The processor is
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
A circuit design support apparatus that calculates an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations.

(Appendix 21)
The processor is
When the first control cell and the second control cell are different, the operation state probability of the memory and the clock gating operation rate obtained based on the state probability of the first control signal included in the operation probability information 21. The circuit design support device according to appendix 20, wherein the smaller one is selected as the operation rate of the memory, and the estimated value is calculated based on the selected operation rate and the total number of operations.

(Appendix 22)
The operation probability information includes a state probability of a second control signal instructing a write / read operation of the memory,
The processor is
Based on the state probability of the first control signal and the state probability of the second control signal included in the operation probability information, the state of the second control signal when the memory is in a stopped state is estimated and estimated Based on the result, the ratio of the read operation and the write operation to the memory is corrected,
The circuit design support device according to appendix 20 or appendix 21, wherein the number of write accesses and the number of read accesses to the memory are calculated based on the corrected ratio and the estimated value calculated by the second calculator. .

(Appendix 23)
Circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory of the circuit to be designed, and the state probability of the first control signal instructing operation / stop of the memory; To estimate the number of accesses to the memory based on
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
Calculating an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations;
A computer-readable recording medium on which a circuit design support program for executing processing is recorded.

DESCRIPTION OF SYMBOLS 1 Circuit design support apparatus 10 Memory | storage part 20 Processing part (processor, CPU)
21 1st extraction part 22 1st calculation part 23 2nd extraction part 24 2nd calculation part 25 Correction part 26 3rd calculation part

Claims (10)

Circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory of the circuit to be designed, and the state probability of the first control signal instructing operation / stop of the memory; To estimate the number of accesses to the memory based on
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
Calculating an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations;
A circuit design support program that executes processing. When the first control cell and the second control cell are different, the operation state probability of the memory and the clock gating operation rate obtained based on the state probability of the first control signal included in the operation probability information The smaller one of the two is selected as the operation rate of the memory, and the estimated value is calculated based on the selected operation rate and the total number of operations.
The circuit design support program according to claim 1, which causes the computer to execute processing. When the first control cell and the second control cell are the same, the estimated value is calculated based on the number of operations per unit time of the clock to the memory included in the operation probability information.
The circuit design support program according to claim 1 or 2, which causes the computer to execute processing. When the gating cell is not extracted, the estimated value is calculated based on the number of operations per unit time of the clock to the memory and the state probability of the first control signal included in the operation probability information. ,
The circuit design support program according to any one of claims 1 to 3, which causes the computer to execute processing. By performing a back trace from the clock input terminal in the memory based on the circuit data, operation information of the gating cell, the first control cell, and the clock source is extracted.
The circuit design support program according to any one of claims 1 to 4, which causes the computer to execute processing. Extracting the second control cell by performing a back trace from the input terminal of the first control signal in the memory based on the circuit data;
The circuit design support program according to any one of claims 1 to 5, which causes the computer to execute processing. The operation probability information includes a state probability of a second control signal instructing a write / read operation of the memory,
Based on the state probability of the first control signal and the state probability of the second control signal included in the operation probability information, the state of the second control signal when the memory is in a stopped state is estimated and estimated Based on the result, the ratio of the read state and the write state to the memory is corrected,
Calculating the number of write accesses and the number of read accesses to the memory based on the corrected ratio and the estimated value calculated by the second calculator;
The circuit design support program according to any one of claims 1 to 6, which causes the computer to execute processing. The probability that the second control signal is in a state of instructing a read operation (hereinafter referred to as a read state probability) is equal to or greater than the probability that the first control signal is in a state of instructing a stop (hereinafter referred to as a stop state probability). When the read state probability is equal to or higher than the probability that the first control signal is in a state of instructing an operation (= 1−the stop state probability; hereinafter referred to as the operation state probability), the memory is in the stop state. The state of the second control signal at a certain time is estimated to be fixed to the read state,
When the read state probability is greater than the stop state probability and the read state probability is less than the operation state probability, the state of the second control signal when the memory is in a stop state is a read state. Presumed to be fixed,
When the read state probability is less than or equal to the stop state probability and the read state probability is less than or equal to the operation state probability, the state of the second control signal when the memory is in a stop state is a write state Estimated to be fixed to
When the read state probability is less than the stop state probability and the read state probability is greater than the operation state probability, the state of the second control signal when the memory is in the stop state is the second state Estimating that the read state and the write state are obtained at a ratio corresponding to the state probability of the control signal.
The circuit design support program according to claim 7, which causes the computer to execute processing. A circuit design support device for estimating the number of accesses to a memory of a circuit to be designed,
Stores circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory, and a state probability of a first control signal instructing operation / stop of the memory. A storage unit;
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and a first extraction unit that extracts operation information of a clock source of the clock;
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted A first calculation unit for calculating a gating operation rate;
A second extraction unit that extracts a second control cell that outputs the first control signal based on the circuit data when the gating cell is extracted;
A second calculation unit that calculates an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations. Circuit design support device. Circuit data relating to the circuit to be designed, operation probability information including the number of operations per unit time of the clock to the memory of the circuit to be designed, and the state probability of the first control signal instructing operation / stop of the memory; A method for estimating the number of accesses to the memory by a computer,
Based on the circuit data, a gating cell that performs gating of the clock, a first control cell that controls the gating cell, and operation information of the clock source of the clock are extracted.
A clock indicating the ratio of the number of operations per unit time of the clock to the total number of operations per unit time output from the clock source included in the operation information of the clock source when the gating cell is extracted Calculate the gating operating rate,
When the gating cell is extracted, a second control cell that outputs the first control signal is extracted based on the circuit data;
A circuit design support method for calculating an estimated value of the number of accesses to the memory based on the first control cell, the second control cell, the operation probability information, the clock gating operation rate, and the total number of operations.

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