JP5637178B2 - DMA transfer apparatus, DMA transfer method, and DMA transfer program - Google Patents

Description

  The present invention relates to an apparatus for performing DMA transfer.

  PC Express (PCI Express, hereinafter referred to as “PCIe”) is an I / O serial interface (a type of expansion bus). Local area network (Local Area Network, hereinafter referred to as “LAN”), disk (DISK), compact disk (also referred to as Compact Disk, etc.), DVD (also referred to as Digital Versatile Disk, etc.), cartridge magnetic tape One or more peripheral devices (hereinafter, these peripheral devices are collectively referred to as “peripheral devices”) including, for example, (Catridge Magnetic Tape, hereinafter referred to as “CGMT”) are computer systems via PCIe. Combine with. A central processing unit (Central Processing Unit, hereinafter referred to as “CPU”) also transmits information regarding addresses, counts, flags, etc. via PCIe (hereinafter referred to as “transfer information”). "Is abbreviated as" ") and communicates with a firmware (Firmware, hereinafter referred to as" FW ") control unit.

  An input / output processing device (Input Output Processor, hereinafter referred to as “IOP”) is a main memory controller (Main Memory Controller), which controls a CPU and a main storage device (also referred to as main memory, Main Memory, etc.). Independently from the above, a process related to input / output performed on the computer system is performed.

  The IOP exists between the peripheral device and the MMC. The IOP transfers data to be input / output between a main memory in a computer system and one or more peripheral devices while using direct memory access (hereinafter referred to as “DMA”). It has a function.

  The DMA transfer apparatus will be described with reference to FIG. FIG. 10 is a block diagram showing the configuration of the DMA transfer apparatus described in Patent Documents 1 to 3.

  Referring to FIG. 10, the IOP 85 includes an FW control unit 90 that controls the entire IOP, and a data transfer unit that controls DMA data transfer between the peripheral device 75 and the main memory 65 (hereinafter referred to as “IOC”). 95, a PCIe switch 45 that is a device for expansion to the peripheral device 75, a host bus adapter 50 that connects the peripheral device 75 and the PCIe switch 45, and an IO adapter 55 that connects the LAN 80 and the PCIe switch 45. Consists of The FW control unit 90 and the IOC 95 are connected via the PCIe 25. The IOC 95 and the PCIe switch 45 are connected via the PCIe 40.

  When viewed from a computer system, in the DMA transfer apparatus, one or more input / output (hereinafter referred to as “IO”) adapters 55 (for example, a SCSI card or a LAN network interface card) are provided outside the PCIe switch 45. (Network Interface Card, hereinafter abbreviated as NIC), etc. In addition, IOP85 is referred to as Input Output Adapter, hereinafter abbreviated as “IOA”), host channel adapter (Host_Channel_Adapter, hereinafter abbreviated as “HCA”), Host bus adapter 50 (Host_Bus_Adaptor, hereinafter referred to as “HBA”)). Further, a LAN 80 is connected to the outside of the IO adapter 55.

  The IOP 85 and the main memory controller 70 are connected via the PCIe 15. When performing DMA write (write) transfer, the peripheral device 75 first transmits transfer data to the IO adapter 55. Next, the IOC 95 receives the transfer data transmitted by the peripheral device 75 via the PCIe switch 45 and the PCIe 40. Thereafter, the IOC 95 further sends the received transfer data to the main memory controller 70 via the PCIe 15. Through the control as described above, the IOP 85 transfers the transfer data from the peripheral device 75 to the main memory 65 without mediating the CPU 60.

  The FW control unit 90 is a control mechanism equipped with an FW that controls the overall IO processing in the computer system. In response to an input / output request made by the CPU 60 or an operating system (hereinafter referred to as “OS”). The host bus adapter 50, the PCIe switch 45, the IOC 95, and the like constituting the IOP 85 are controlled. Under the control, the IOC 95 transfers the transfer data between the peripheral device 75 connected via the PCIe 40 and the main memory 65. Further, the FW control unit 90 has a function of converting a logical address designated by a channel program (hereinafter referred to as “CP”) into a physical address and a function of generating transfer information from the CP and transferring it to the IOC 95.

  The FW control unit 90 receives an instruction for starting an IO (hereinafter referred to as an “IO start instruction”) from the CPU 60, and uses a command necessary for executing the received IO start instruction and information specifying an address. The configured CP is acquired from the main memory 65. Next, the FW control unit 90 converts the logical address designated by the CP into a physical address, generates transfer information from the CP, and then transfers the generated transfer information to the IOC 95. Further, the FW control unit 90 receives a signal (hereinafter, referred to as “transfer information registration completion signal”) notifying that the process of registering transfer information has been completed from the IOC 95. Further, the FW control unit 90 receives a notification (hereinafter abbreviated as “DMA transfer completion notification”) from the IO adapter 55 (for example, NIC, HBA, HCA, etc.) notifying that the transfer in DMA has been completed. When receiving the transfer information registration completion signal and the DMA transfer completion notification, the FW control unit 90 reports to the CPU 60 that the DMA transfer (hereinafter also referred to as “DMA transfer”) has been completed.

  The IOC 95 includes a transfer information buffer 30 that stores transfer information read from the FW control unit 90, and a transaction (transaction, hereinafter referred to as “Txn”) buffer that temporarily stores transfer data sent from the peripheral device 75. 35. The IOC 95 transfers the transfer data existing in the Txn buffer 35 to the main memory 65 according to the transfer information in the transfer information buffer 30.

  According to the DMA transfer device disclosed in Patent Document 1, it is possible to reduce a decrease in efficiency that occurs as a result of accessing a logical address across pages existing in the main memory. The DMA transfer device disclosed in Patent Document 1 includes an address register or the like that holds an address as a physical address in order to reduce a decrease in efficiency.

  The DMA transfer device (also referred to as IOP) disclosed in Patent Document 2 reduces the occurrence of overflow and underflow in the internal memory caused by a command to be issued. As a result of reducing the occurrence, the DMA transfer device disclosed in Patent Document 2 can reduce the time for transferring the transfer data. In order to realize the effects as described above, the DMA transfer device disclosed in Patent Document 2 includes a data counter that measures the amount of transfer data, and only when the value of the data counter is within a predetermined range. Issue a command.

  The DMA transfer device disclosed in Patent Document 3 uses the characteristic that transfers that occupy all the buffers of all channels are rarely performed at the same time. The DMA transfer device disclosed in Patent Document 3 divides a data buffer into partitions, includes a flag indicating a use state in the divided partition, and dynamically allocates the data buffer according to the value of the flag. The DMA transfer device disclosed in Patent Document 3 reduces waste by reducing data buffers that are less likely to be used.

JP 2000-353146 A Japanese Patent Laid-Open No. 2008-083911 JP 2000-330923 A

  In the computer systems disclosed in Patent Documents 1 to 3, the IOP operates in accordance with instructions written in the CP. The FW control unit 90 registers transfer information in the CP in the transfer information buffer 30 in a plurality of stages, and then activates the DMA.

  Here, an example of the time required for processing in the IOP will be shown with reference to FIG. FIG. 11 shows an example of timing in a process in which a DMA transfer device disclosed in a patent document or the like transfers transfer data from the peripheral device 75 or the like to the main memory 65 (ie, “DMA write transfer”). FIG. The vertical axis in FIG. 11 represents the transition of time, and indicates that the time is advanced toward the bottom. 11 represents the CPU 60, the main memory 65, the FW control unit 90, the IOC 95, the host bus adapter 50, and the peripheral device 75. In FIG. 11, an arrow parallel to the horizontal axis represents an access request generated from each device and the like, and a line parallel to the vertical axis represents a processing time performed by each device (corresponding to the value on the horizontal axis). For example, when the FW control unit 90 performs the process of acquiring the CP from the main memory 65, the process proceeds from the FW control unit 90 to the main memory 65 between the FW control unit 90 and the main memory 65 in FIG. 11. And an arrow pointing from the main memory 65 to the FW control unit 90 are expressed by the presence of time (moving downward in the vertical axis).

  For example, in a computer system having a transfer information buffer (register) 30 with a maximum of 64 stages, as a pre-process for starting DMA, the time for registering transfer information for 64 stages in the transfer information buffer 30 is executed every time DMA is executed. Is necessary. Here, the time for registering the transfer information for one stage in the transfer information buffer 30, that is, “the FW control unit 90 acquires the CP, and then converts the logical address designated by the CP into a physical address, The processing time until the transfer information is registered in the transfer information buffer 30 ”is 4 (microseconds / stage, hereinafter, microseconds are expressed as“ μs ”). For example, in the DMA transfer device disclosed in Patent Documents 1, 2, or 3, DMA is activated as 4 (μs / stage) × 64 (stage) = 256 (μs) as the time to register in the transfer information buffer 30 Necessary for preprocessing.

  The FW control unit 90 registers the transfer information for 64 stages with the main memory 65 in the transfer information buffer 30 (time of “transfer information registration completed” in FIG. 11), that is, the FW control unit 90 After 256 (μs) from the start of acquiring the CP, the peripheral device 75 is activated by DMA. Thereafter, the peripheral device 75 transmits a ready signal notifying that the transfer data can be transferred. The FW control unit 90 receives the ready signal, and then transfers the transfer data using the IOC 95.

  On the other hand, in a computer system in which the process for registering transfer information in the transfer information buffer 30 and the process for starting DMA are independent, when DMA is started, the transfer information may not be supplied in time. If the supply is not in time, the computer system as described above sometimes becomes busy (hereinafter simply referred to as “busy”) that temporarily stops the PCIe bus. Due to the generated busy state, in the DMA transfer device disclosed in Patent Literature 1, 2, or 3, the efficiency of executing processing related to DMA is lowered.

  Accordingly, a main object of the present invention is to provide a DMA transfer device or the like with high processing efficiency.

  In order to achieve the above object, a DMA transfer apparatus according to the present invention has the following configuration.

That is, the DMA transfer apparatus according to the present invention is
A data transfer unit for transferring data from the peripheral device to the main memory controller;
A first process for storing a part of the transfer information regarding the data is performed, a second process for transmitting a signal for starting DMA transfer to the peripheral device is performed, and the remaining transfer information is stored. And a control unit that performs a fourth process of receiving a ready signal notifying that the peripheral device can transfer the data, and then starts the data transfer unit. Features.

As another aspect of the present invention, a DMA transfer method according to the present invention includes:
Among all transfer information related to data to be transferred from the peripheral device, a part of the transfer information is stored, a signal for starting DMA transfer is transmitted to the peripheral device, and the remaining transfer information is stored. A ready signal notifying that the data can be transferred is received, and then the data is transferred from the peripheral device to the main memory controller.

  The DMA transfer apparatus and the like according to the present invention can improve the efficiency of processing related to DMA.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the DMA transfer apparatus according to the first embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing the configuration of the DMA transfer apparatus according to the first embodiment of the present invention. The DMA transfer device 10 includes an IOC 17 that transfers transfer data from the peripheral device 75 to the main memory controller 70, and the control unit 20. First, the control unit 20 registers some transfer information in a buffer (not shown in FIG. 1). Next, the control unit 20 transmits a signal for starting DMA transfer to the peripheral device 75. Next, the control unit 20 registers the remaining transfer information in a buffer (not shown in FIG. 1).

  The peripheral device 75 receives a signal for starting DMA transfer. Next, the peripheral device 75 prepares to transfer the transfer data. When the preparation is completed, the peripheral device 75 transmits a ready signal notifying that the transfer data can be transferred. Next, the control unit 20 commands the IOC 17 to transfer the transfer data. Thereafter, the IOC 17 transfers the transfer data from the peripheral device 75 to the main memory controller 70.

  The DMA transfer apparatus 10 exchanges (accesses) information with the CPU 60 and the main memory 65 via the main memory controller 70. The DMA transfer device 10 also exchanges information with the peripheral device 75.

  Next, the flow of processing performed by the DMA transfer apparatus 10 will be described in detail with reference to FIG. 2 or FIG. FIG. 2 is a diagram illustrating an example of timing in processing in which the DMA transfer apparatus 10 according to the first embodiment of the present invention performs DMA write transfer. FIG. 3 is a flowchart showing the flow of processing in the DMA transfer apparatus according to the first embodiment of the present invention. Since FIG. 2 is the same type as FIG. 10 described above, a duplicate description is omitted. The vertical axis in FIG. 2 represents the transition of time, and indicates that the time is advanced as it goes down. 2 represents the CPU 60, the main memory 65, the control unit 20, the IOC 17, the HBA (not shown in FIG. 1), and the peripheral device 75.

  For example, it is assumed that 64-stage transfer information exists in a computer system. Referring to FIG. 2, the control unit 20 acquires a CP from the main memory 65, and then performs a process of converting a logical address designated by the CP into a physical address. In the example shown in FIG. 2, the control unit 20 registers transfer information for one stage (step S10 in FIG. 3), and then transmits a signal for starting DMA transfer to the peripheral device 75 (in FIG. 3). Step S20). Thereafter, the control unit 20 performs processing for registering the remaining 63 levels of transfer information (step S30 in FIG. 3).

  The peripheral device 75 receives a signal for starting the DMA transfer. Next, the peripheral device 75 prepares to transfer the transfer data. When the preparation is completed, the peripheral device 75 transmits a ready signal notifying that the transfer data can be transferred. Next, the control unit 20 receives a ready signal transmitted from the peripheral device 75 (step S40 in FIG. 3). Thereafter, the IOC 17 transfers the transfer data from the peripheral device 75 to the main memory 65 via the main memory controller 70 (step S50 in FIG. 3).

  While the peripheral device 75 performs the processing as described above, the control unit 20 performs processing for registering transfer information for the remaining 63 stages. The control unit 20 synchronizes the process of registering transfer information and the process of starting DMA transfer, thereby reducing the possibility of PCIe becoming busy and turning the turnaround time (Turn) for registering transfer information. Around Time (hereinafter abbreviated as “TAT”) can be shortened.

  In the example described above, the control unit 20 performs the process of starting the DMA transfer after registering the transfer information for one stage, but it is not always necessary to have one stage. For example, even if there are 2 stages, 3 stages, or in the middle of the 1st stage to the 2nd stage, 63 stages (that is, a value obtained by subtracting 1 from 64 stages of transfer information) When the transfer information is registered and then the DMA transfer is started, the processing performed by the peripheral device 75 and the control unit 20 registering the transfer information can be performed in parallel. The TAT can be shortened by the DMA transfer apparatus according to the embodiment.

  In the above example, it is assumed that the transfer information of 64 stages exists in the computer system, but it is not always necessary to have 64 stages.

  That is, according to the DMA transfer apparatus according to the first embodiment of the present invention, the efficiency of processing related to DMA can be improved.

<Second Embodiment>
Next, a second embodiment based on the above-described first embodiment will be described.

  In the following description, the characteristic parts according to the present embodiment will be mainly described, and the same reference numerals will be given to the same configurations as those in the first embodiment described above, and the redundant description will be omitted. To do.

  The DMA transfer apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the DMA transfer apparatus according to the second embodiment of the present invention.

  Referring to FIG. 4, the DMA transfer apparatus 11 further includes a transfer information buffer 30. The transfer information buffer 30 has a plurality of stages. The control unit 21 registers transfer information in the transfer information buffer 30. In the following description, the transfer information buffer 30 is described as having a plurality of stages. However, even if the stage corresponds to one transfer information buffer, the obtained effect does not change. That is, the DMA transfer device 11 may include a plurality of transfer information buffers 30.

  Similar to the example described in the DMA transfer apparatus according to the first embodiment, for example, it is assumed that 64-stage transfer information exists in a computer system. The control unit 21 registers transfer information for one stage in the transfer information buffer 30 for one stage, and then executes a process for starting DMA transfer. Thereafter, the control unit 21 performs processing for registering the remaining 63 stages of transfer information in the transfer information buffer 30.

  The peripheral device 75 performs processing from when the DMA transfer is started until the transfer data is transmitted to the DMA transfer device 11. While the peripheral device 75 performs processing, the control unit 21 performs processing for registering transfer information for the remaining 63 stages in the transfer information buffer 30. The control unit 21 registers the transfer information while reducing the possibility of PCIe becoming busy by performing the process of registering the transfer information in the transfer information buffer 30 and the process of starting the DMA transfer in synchronization. TAT can be shortened.

  In the above example, it is assumed that the transfer information of 64 stages exists in the computer system, but it is not always necessary to have 64 stages.

  That is, according to the DMA transfer apparatus according to the second embodiment of the present invention, the efficiency of processing related to DMA can be improved.

<Third Embodiment>
Next, a third embodiment based on the above-described second embodiment will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the second embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do. Similarly, the same reference numerals are assigned to configurations similar to those in the above-described Patent Documents 1, 2, or 3, and duplicate descriptions are omitted.

  A DMA transfer apparatus according to the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of a DMA transfer apparatus according to the third embodiment of the present invention.

  Referring to FIG. 5, the DMA transfer device 12 includes a control unit 22 that performs processing such as acquisition of a CP, an IOC 17 that performs DMA transfer processing, a PCIe switch 45, and an IO adapter 55 that connects a peripheral device 75 (or Host bus adapter 50).

  The control unit 22 calculates a processing amount of transfer information to be performed before transmitting a signal for starting DMA transfer to the peripheral device 75 by a predetermined calculation method. For example, the transfer data sent from the peripheral device 75 is temporarily stored in the Txn buffer 35 according to the peripheral device 75 such as the LAN 80 from the time when the transfer information is registered in the transfer information buffer 30 and when the control unit 22 activates the DMA. The number of stages of the transfer information buffer 30 to be registered is calculated from the time until it can be saved, before performing the process of starting the DMA.

  For example, the time required to register the transfer information for one stage in the transfer information buffer 30 is 4 (μs / stage), the number of stages in the transfer information buffer 30 is 64 (stages) at maximum, and the DMA is started It is assumed that the time required for the transfer data sent from the peripheral device 75 to be temporarily stored in the Txn buffer 35, that is, the time required for processing performed by the peripheral device 75 is 250 (μs).

  The time required for the process of registering all transfer information is a value obtained by multiplying the time required for one stage of processing by the number of stages. That is, the control unit 22 calculates the time required for the process of registering all transfer information as shown in Equation 1.

64 (stage) × 4 (μs) = 256 (μs) (Equation 1)
The above processing and the processing performed by the peripheral device 75 (required time is 250 (μs)) can be executed almost simultaneously. Therefore, the control unit 22 starts the DMA by subtracting the time required for temporarily storing the transfer data sent from the peripheral device 75 in the Txn buffer 35 from the time required for registering all transfer information. Calculate the pre-existing time. Here, it is assumed that the time until the transfer data sent from the peripheral device 75 can be temporarily stored in the Txn buffer 35 is 250 (μs). In the example described above, the control unit 22 calculates time as shown in Equation 2.

256 (μs) −250 (μs) = 6 (μs) (Expression 2)
When the value calculated according to the above-described process becomes a positive value, the time required for the process for registering all transfer information is longer than the time required for the process performed by the peripheral device 75. That is, when the control unit 22 performs the process of starting the DMA first, a busy state occurs, and as a result, the efficiency of the process related to the DMA is reduced in the computer system. Therefore, in order to reduce the busy state, the control unit 22 performs a process of registering transfer information according to the number of stages calculated according to the process described later before performing the process of starting the DMA. The control unit 22 can reduce the busy state by performing the processing as described above.

  When the value calculated according to the example shown in Expression 2 is 0 or less, the time required for the process of registering all transfer information is longer than the time required for the process performed by the peripheral device 75. It will be short. In such a case, even if the control unit 22 performs the process of starting the DMA first, the busy state does not occur. The control unit 22 performs processing for starting the DMA, and then performs processing for registering transfer information.

  When the control unit 22 determines that the value calculated according to the example shown in Equation 2 is a positive value, the control unit 22 divides the value calculated by Equation 2 by the time required to register the transfer information for one stage. To calculate the estimated value. In the example described above, the control unit 22 calculates the estimated value according to Equation 3.

6 (μs) ÷ 4 (μs / stage) = 1.5 (stage) (Equation 3)
When the estimated value calculated as described above is rounded down, that is, 1 (stage), a busy state occurs. However, there is a high possibility that the efficiency of processing related to DMA is improved as compared with the case where processing for registering transfer information and processing for starting DMA are performed independently.

  Alternatively, when the estimated value calculated as described above is rounded up after the decimal point, that is, when it is set to 2 (stages), the busy state does not occur. The control unit 22 performs processing for registering transfer information for the number of stages calculated as described above, performs processing for starting DMA, and then performs processing for registering transfer information for the remaining number of stages. By performing the processing in this way, the control unit 22 can improve the efficiency of processing related to DMA.

  In the above example, when the number of stages of the transfer information buffer 30 is 64, a busy state occurs if the value is 2 to 63 (that is, a value obtained by subtracting 1 from the number of stages of the transfer information buffer 30). Furthermore, the process of registering transfer information and the process performed by the peripheral device 75 can be performed in parallel. Therefore, the control unit 22 can improve the efficiency of processing related to DMA.

  In the example described above, the number of stages of the transfer information buffer 30 is 64 (stages), the time required for processing performed by the peripheral device 75 is 250 (μs), and transfer information for one stage is registered in the transfer information buffer 30. It is assumed that the time required for processing is 4 (μs / stage). However, the processing of the DMA transfer apparatus according to the third embodiment of the present invention is not limited to the above numerical values. In other words, the processing of the DMA transfer apparatus according to the third embodiment of the present invention can improve the efficiency of processing related to DMA by processing in the same manner even if the numerical value is other than the numerical values described above.

  The flow of processing performed by the DMA transfer apparatus according to the third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram illustrating processing timing when the DMA transfer apparatus according to the third embodiment of the present invention performs DMA write transfer. FIG. 6 shows the timing when it is the processing time in the above-described example, and is the same diagram as FIG.

  Referring to FIG. 6, when an IO activation command is issued from the CPU 60 to the control unit 22, the control unit 22 acquires a CP from the main memory 65. The CP is a command for executing an IO, information for specifying an address (hereinafter abbreviated as “address specification information”), information on a data chain indicating whether data exchanged by a command to be executed subsequently is continuous, or the like. Is included.

  When the address designation information in the CP to be acquired is described by a logical address, the control unit 22 exchanges information about the address with the main memory 65 at least once (hereinafter, “access is referred to as“ access ”). To express "). The control unit 22 converts the logical address specified by the CP into a physical address in the main memory 65 according to the information obtained by accessing. Thereafter, the control unit 22 creates transfer information and transfers the created transfer information to the IOC 17.

  Next, when receiving the transfer information described above, the IOC 17 stores the transfer information in the transfer information buffer 30 and then transmits a transfer information registration completion signal relating to the first stage to the control unit 22.

  Temporarily, the time required for the process of accessing the control unit 22 and the main memory 65 once is set to 1 (μs / stage), and the process of acquiring the CP converts the logical address specified by the CP from the physical address. It is assumed that the access is made four times and registered in the transfer information buffer 30 until the processing. In this case, the time required to register the transfer information for one stage is 4 (times) × 1 (μs / stage) = 4 (μs / stage). Further, when the computer system has a structure having the transfer information buffer 30 of 64 stages, the time required for the processing for storing all the transfer information in the transfer information buffer 30 is 64 ( Stage) × 4 (μs / stage) = 256 (μs).

  On the other hand, when the control unit 22 issues an instruction to start DMA transfer to the IO adapter 55 (for example, the host bus adapter 50), the IO adapter 55 starts access to the peripheral device 75.

  The speed at which transfer data is transferred differs depending on the type of interface, the type of peripheral device 75, whether or not a cache exists, and the like. For example, the transfer speed of the peripheral device 75 is currently 1 (Mega bit per second, hereinafter referred to as “Mbps”) to 1 (Giga bit per second, hereinafter referred to as “Gbps”) and is connected to the IO adapter 55. The LAN transfer rate is 10 (Mbps) to 10 (Gbps). Temporarily, the time required from the process of starting the DMA to the process of accessing data and starting the data transfer to the Txn buffer 35, that is, the time required to access the peripheral device 75 connected from the IO adapter 55 is 250. In the case of (μs), DMA write transfer is started after 250 (μs).

  For example, in the DMA transfer apparatus 12 according to the third embodiment of the present invention, the IOC 17 has the transfer information buffer 30 for 64 stages, and the transfer information in the transfer information buffer 30 for one stage is registered. It is assumed that the time required is 4 (μs / stage) (an arrow existing between the main memory and the control unit in FIG. 6). Furthermore, it is assumed that the time required from the start of DMA to the start of data transfer to the Txn buffer 35, that is, the access time to the peripheral device 75 is 250 (μs) (the peripheral shown in FIG. 6). Wavy lines representing the time course of the device).

  Further, as described above, when the control unit 22 calculates that the estimated value is two stages, the transfer information for two stages is registered in the transfer information buffer 30 (transfer information registration completion in FIG. 6 (second stage)). ). That is, the IOC 17 can issue a transfer information registration completion signal to the control unit 22 after 8 μs (= 4 (μs / stage) × 2 (stage)) (DMA activation in FIG. 6). According to the DMA transfer apparatus according to the embodiment, it is possible to improve TAT for 62 stages (that is, 62 stages × 4 μs / stage = 248 μs in terms of time). Furthermore, as described above, according to the DMA transfer apparatus according to the third embodiment of the present invention, it is possible to reduce the busy state and suppress the performance degradation.

  The predetermined calculation method exemplified above is as follows. That is, if the time at which the ready signal is received from the peripheral device 75 and the time at which the transfer information is registered in the transfer information buffer 30 are made coincident, the time T (“estimated time”) that exists before the DMA is started. Is also expressed as in Equation 3.

T = N × SD (Expression 4)
(However,
D is a time from the process in which the control unit 22 transmits a signal for starting DMA transfer to the peripheral device 75 until the process in which the control unit 22 receives a ready signal from the peripheral device 75 is completed.
N is the number of stages constituting the transfer information buffer 30;
S is the time required for the control unit 22 to register the transfer information in the transfer information buffer 30 for one stage).

  In Expression 4, “N × S” represents “the time required for the control unit 22 to register the transfer information for all the stages (64 stages in the above example) in the transfer information buffer 30”.

  When the time T is positive, it is converted into the number of stages D according to Equation 5.

      D = T ÷ S (Formula 5).

(However, select an integer value that is greater than or equal to the value rounded up after the decimal point of D and less than or equal to the number of stages in the first stage.)
Further, when the time T is negative, it is converted into the stage number D according to Equation 5.

      D = 0.

  The predetermined calculation method is not limited to the above-described method. For example, S may be a time required for the process of registering transfer information in the transfer information buffer 30 in a plurality of stages. In that case, S is converted into one stage of processing time, and thereafter, the obtained value is newly set as S, and the time T is calculated according to Equation 4.

  That is, according to the DMA transfer apparatus according to the third embodiment of the present invention, it is possible to improve the efficiency of processing related to DMA.

<Fourth Embodiment>
Next, a fourth embodiment based on the above-described third embodiment will be described.

  In the following description, characteristic parts according to the present embodiment will be mainly described, and the same components as those in the above-described third embodiment will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the DMA transfer apparatus according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing a configuration of a DMA transfer apparatus according to the fourth embodiment of the present invention.

  Referring to FIG. 7, the DMA transfer device 13 has a registration time measuring unit 23 that measures the registration time required to register transfer information for one stage in the transfer information buffer 30 and the time required for processing performed by the peripheral device 75. Is further provided with a storage time measuring unit 24 for measuring each peripheral device.

  The control unit 22 receives an IO activation command from the CPU 60 and then issues a signal for starting an IO (hereinafter referred to as an “IO activation start signal”) to the IOC 17. Thereafter, the IOC 17 receives the IO activation start signal, and thereafter activates the registration time measuring unit 23.

  When activated, the registration time measurement unit 23 starts measuring time, and ends the measurement when the process of registering transfer information for one stage is completed. Thereafter, the registration time measuring unit 23 sends the measured time to the control unit 22.

  The storage time measuring unit 24 uses, for example, a control port or a means for polling the peripheral device to access each peripheral device (the time required for the processing performed by each peripheral device 75 described above). ) To get. Thereafter, the storage time measuring unit 24 sends the access time to each peripheral device to the control unit 22. The method by which the storage time measuring unit 24 acquires the access time is not limited to the above-described example.

  The timing at which the storage time measurement unit 24 measures the access time to each peripheral device will be described with reference to FIG. FIG. 8 is a timing chart showing a process of measuring the access time to each peripheral device in the DMA transfer apparatus according to the fourth embodiment of the present invention. The horizontal axis of FIG. 8 represents time, and represents that the time advances as it goes to the left. A character string arranged in the vertical direction on the left side of FIG. 8 represents the name of each peripheral device.

  Referring to FIG. 8, upon receiving a signal for starting DMA transfer issued by FW (timing line of “DMA transfer start signal” in FIG. 8), the IOC 17 starts the storage time measuring unit 24 (“counter” in FIG. 8). ”Timing line). The IOC 17 sends a signal for starting DMA transfer to each peripheral device via a host bus adapter or the like. The storage time measuring unit 24 receives a signal generated by each peripheral device, and measures an access time to each peripheral device based on the received signal. Thereafter, the storage time measuring unit 24 sends the measured time to the control unit 22. Next, the IOC 17 receives the reset signal (the “reset signal” timing line in FIG. 8) and initializes the state.

  The data to be transferred for measuring the time may be dummy data or data in the header portion of the transfer data. The data transferred to measure time is not limited to the data shown above.

  Further, the method for measuring the access time to each peripheral device is not limited to the method described above. For example, the access time may be acquired by measuring the access time to each peripheral device in advance, storing the time, and referring to the stored time.

  The registration time measurement unit 23 measures the time required for the process of registering transfer information for one stage. The storage time measuring unit 24 measures the access time to each peripheral device. Therefore, according to the DMA transfer apparatus according to the fourth embodiment of the present invention, the number of stages of transfer information to be processed before the start of DMA transfer can be calculated according to the peripheral apparatus.

  That is, according to the DMA transfer apparatus according to the fourth embodiment of the present invention, the efficiency of processing related to DMA can be improved.

(Hardware configuration example)
FIG. 9 is a block diagram schematically illustrating a hardware configuration of a calculation processing device capable of realizing the DMA transfer device according to the embodiment.

  Next, a configuration example of hardware resources that realizes the DMA transfer device according to each of the above-described embodiments using one calculation processing device (information processing device, computer) will be described. However, the DMA transfer apparatus may be realized using at least two types of calculation processing apparatuses physically or functionally. The DMA transfer device may be realized as a dedicated device.

  FIG. 9 is a diagram schematically illustrating a hardware configuration of a calculation processing device capable of realizing the DMA transfer device according to the first to fourth embodiments. The calculation processing apparatus 100 includes a CPU (Central Processing Unit) 110, a memory 120, a disk 130, an output device 140, and an input device 150.

  That is, the CPU 110 copies a software program (computer program: hereinafter simply referred to as “program”) (FIG. 3) stored in the disk 130 to the memory 120 at the time of execution, and executes arithmetic processing. The CPU 110 reads data necessary for program execution from the memory 120. When display is necessary, the CPU 110 displays the output result on the output device 140. When inputting a program from the outside, the CPU 110 reads the program from the input device 150. The CPU 110 interprets and executes the DMA transfer program stored in the memory 120. The CPU 110 sequentially performs the processes described in the above embodiments.

It is a block diagram which shows the structure of the DMA transfer apparatus which concerns on the 1st Embodiment of this invention. It is a figure showing an example of the timing in the process in which the DMA transfer apparatus which concerns on the 1st Embodiment of this invention performs DMA write transfer. It is a flowchart which shows the flow of a process in the DMA transfer apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the DMA transfer apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the DMA transfer apparatus which concerns on the 3rd Embodiment of this invention. It is a figure showing the timing of a process when the DMA transfer apparatus which concerns on the 3rd Embodiment of this invention performs DMA write transfer. It is a block diagram which shows the structure of the DMA transfer apparatus which concerns on the 4th Embodiment of this invention. It is a timing chart showing the process which measures storage time in the DMA transfer apparatus which concerns on the 4th Embodiment of this invention. 1 is a block diagram schematically showing a hardware configuration of a calculation processing device capable of realizing a DMA transfer device according to an embodiment. It is a block diagram which shows the structure of the DMA transfer apparatus described in related literature etc. It is a figure showing an example of the timing in the process in which the DMA transfer apparatus described in related literature etc. performs DMA write transfer.

10 DMA transfer device 11 DMA transfer device 12 DMA transfer device 13 DMA transfer device 15 PCIe
17 IOC
20 Control Unit 21 Control Unit 22 Control Unit 23 Registration Time Measurement Unit 24 Storage Time Measurement Unit 25 PCIe
30 Transfer information buffer 35 Txn buffer 40 PCIe
45 PCIe switch 50 Host bus adapter 55 IO adapter 60 CPU
65 Main memory 70 Main memory controller 75 Peripheral device 80 LAN
85 IOP
90 FW control unit 95 IOC
100 calculation processor 110 CPU
120 memory 130 disk 140 output device 150 input device

Claims (10)

A first process for storing a part of transfer information among all transfer information relating to data to be transferred from the peripheral device to the main memory controller, and a second process for transmitting a signal for starting DMA transfer to the peripheral device, and executes a third process of storing the remaining transfer information, and the fourth processing line intends to control unit in which the peripheral device receives a ready signal indicating that it is possible to transfer the data,
A DMA transfer device comprising: a data transfer unit that transfers the data from the peripheral device to the main memory controller after the fourth process . The data transfer unit includes a plurality of buffers for storing the total transfer information,
2. The DMA according to claim 1, wherein the control unit controls the part of transfer information to be stored in a part of the buffer and controls the remaining transfer information to be stored in the remaining buffer. Transfer device. The control unit sets the estimated time calculated by a predetermined calculation method based on the first time required for the first process and the second time required for the completion of the fourth process from the second process. The DMA transfer apparatus according to claim 1 or 2, wherein the first processing is executed in response. The control unit sets the estimated time to the estimated time = ND
(However,
D is the second time,
N represents “time required for processing to store all the transfer information in the plurality of buffers”),
According to the formula
If the estimated time calculated is positive,
Estimated time / S
(However,
S represents “time required for processing to store transfer information in one of the plurality of buffers”)
The value calculated according to the formula is greater than or equal to the numerical value rounded up to the nearest decimal point, and one of the plurality of integer values equal to or smaller than the number is set as the processing number.
When the calculated estimated time is 0 or less, 0 is the number of processes,
The DMA transfer apparatus according to claim 3, wherein the first process is performed according to the number of processes. 5. The DMA according to claim 3, further comprising a registration time measuring unit that measures a time required to store one stage of transfer information corresponding to the part of the transfer information. Transfer device. A storage time measuring unit for measuring the second time for each peripheral device;
The DMA transfer device according to claim 3, wherein the number of processes is calculated according to the peripheral device. Among all transfer information related to data to be transferred from the peripheral device, a part of the transfer information is stored in a buffer, a signal for starting DMA transfer is transmitted to the peripheral device, and the remaining transfer information is stored in the buffer. , a ready signal the peripheral device informs that it is possible to transfer the data received from the peripheral device, then, DMA transfer method for transferring data to the main memory controller from the peripheral device. A first process for storing a part of transfer information among all transfer information relating to data to be transferred from the peripheral device to the main memory controller, and a second process for transmitting a signal for starting DMA transfer to the peripheral device, and it executes a third process of storing the remaining transfer information, and control functions intends rows fourth process of receiving a ready signal indicating that it is possible to transfer the peripheral device is the data,
A DMA transfer program for causing a computer to realize a data transfer function of transferring the data from the peripheral device to the main memory controller after the fourth process . The data transfer function uses a plurality of buffers for storing the total transfer information,
The DMA transfer according to claim 8, wherein the control function performs a process of storing the partial transfer information in a part of the buffer, and realizes a process of storing the remaining transfer information in the remaining buffer. program. The control function performs the first process according to an estimated time calculated by a predetermined calculation method from the time required for the first process and the time required from the second process to the completion of the fourth process. The DMA transfer program according to claim 8 or 9, which is realized.

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