JP2009059276A - Data processing apparatus and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus and a program for efficiently performing DMA transfer at higher speed compared with when the amount of transfer information constituting a transfer information group is always fixed when DMA transferring data on the basis of the transfer information group configured by connecting a plurality of transfer information. <P>SOLUTION: An information processing part 13 provided with a DMA controller 42 for DMA transferring data of each unit transfer amount on the basis of a transfer information group configured by connecting a plurality of transfer information of unit transfer amount including information necessary for direct memory access (DMA) transfer without interposing a CPU 24, determines the amount of transfer information constituting a transfer information group on the basis of a transfer speed when the DMA controller 42 transfers reference data with a predetermined data amount while changing the amount of transfer information constituting the transfer information group, and creates a transfer information group configured by connecting the determined amount of transfer information when DMA transferring the data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a program.

  In recent years, in order to transfer data at high speed, a direct memory access (DMA) transfer technique for transferring data without using a central processing unit (CPU) has been widely adopted in various information processing apparatuses.

  In order to efficiently perform the DMA transfer, in the image forming apparatus, in order to transfer the image data on the memory to the print engine at a high speed by DMA, the image data of each page is divided into a plurality of bands, and each band data is 1 In addition to transferring data at the same time, the CPU sets a transfer flag indicating whether or not to perform continuous DMA transfer for each DMA transfer and controls continuous transfer. By setting the DMA parameters (address, size, etc.), a technique has been proposed in which DMAs of a plurality of bands are continuously executed without intervals (see, for example, Patent Document 1).

In addition, by dividing the image data into a plurality of pieces, creating a descriptor for each divided portion, and including an instruction bit for instructing the operation performed by the DMA controller in the descriptor, continuous divided DMA transfer can be performed without CPU intervention. An apparatus that can be used automatically has also been proposed (see, for example, Patent Document 2).
JP 2000-148663 A JP 2002-140286 A

  The present invention relates to an information processing apparatus and program for performing DMA transfer of data to be transferred based on a transfer information group configured by connecting a plurality of transfer information, wherein the number of transfer information constituting the transfer information group is determined. It is an object of the present invention to provide an information processing apparatus and program capable of performing DMA transfer at high speed and efficiency as compared with the case where the constant is always maintained.

  The information processing apparatus according to claim 1 is a transfer information group comprising a plurality of pieces of transfer information for each unit transfer amount including information necessary for direct memory access (DMA) transfer without interposing a central processing unit (CPU). Transfer means for transferring the data to be transferred for each unit transfer amount based on the above, and reference data having a predetermined data amount by the transfer means while changing the number of transfer information constituting the transfer information group. Determining means for determining the number of transfer information constituting the transfer information group based on a transfer rate when DMA transfer is performed, and the number of transfer information determined by the determining means when transferring the data to be transferred; And creating means for creating a transfer information group composed of the above.

  The invention according to claim 2 is the information processing apparatus according to claim 1, further comprising storage means for storing the number of pieces of transfer information determined by the determination means in association with the data amount of reference data, Reads the number stored in the storage unit according to the amount of data to be transferred when DMA transfer of the data to be transferred, and creates a transfer information group configured by linking the read number of transfer information To do.

  According to a third aspect of the present invention, in the information processing apparatus according to the first or second aspect, when the creation unit creates a plurality of transfer information groups for DMA transfer of the transfer target data, For the information group or the transfer information group from the beginning to a predetermined number, create a transfer information group composed of a smaller number of transfer information than the number determined by the determining means, and for subsequent transfer information groups, A transfer information group comprising the number of transfer information determined by the determining means is created.

  According to a fourth aspect of the present invention, in the information processing apparatus according to any one of the first to third aspects, the creation unit creates a plurality of transfer information groups in order to DMA transfer the data to be transferred. In addition, a transfer information group for DMA transfer performed after the DMA transfer being executed is completed before the DMA transfer being executed by the transfer means is completed, and stored in the transfer information storage means in the order of creation, The transfer means reads the transfer information group from the transfer information storage means in the order of creation and performs DMA transfer.

  According to a fifth aspect of the present invention, in the information processing apparatus according to the fourth aspect, the creation unit creates the transfer information group when the CPU usage rate or the CPU occupation time does not exceed a predetermined value.

  According to a sixth aspect of the present invention, in the information processing apparatus according to the fifth aspect, when the creation means stores no unread transfer information group in the transfer information storage means, the CPU usage rate Alternatively, even if the CPU occupation time exceeds a predetermined value, a transfer information group for DMA transfer performed after the DMA transfer being executed is created.

  A program according to a seventh aspect of the invention is based on a transfer information group configured by connecting a plurality of pieces of transfer information for each unit transfer amount including information necessary for direct memory access (DMA) transfer without interposing a central processing unit (CPU). A computer provided with transfer means for DMA-transferring the data to be transferred for each unit transfer amount, while changing the number of transfer information constituting the transfer information group from reference data having a predetermined data amount. A determining unit that determines the number of transfer information constituting the transfer information group based on a transfer rate when the DMA transfer is performed by the transfer unit; and a number determined by the determining unit when the data to be transferred is DMA transferred. It is a program for functioning as a creation means for creating a transfer information group configured by linking the transfer information.

  According to the first aspect of the present invention, it is possible to obtain an effect that the DMA transfer can be performed at high speed and efficiently compared with the case where the number of transfer information constituting the transfer information group is always constant.

  According to the second aspect of the present invention, there is an effect that a transfer information group can be created quickly.

  According to the third aspect of the invention, the effect that the DMA transfer start of the transfer means can be accelerated can be obtained.

  According to the fourth aspect of the invention, it is possible to reduce the time required for DMA transfer compared to the case where all transfer information groups are created before the start of DMA transfer.

  According to the fifth aspect of the present invention, the CPU can be used efficiently so that the CPU load is not concentrated when the entire system is viewed, thereby enabling the DMA transfer without causing the performance degradation of other modules. An effect is obtained.

  According to the sixth aspect of the invention, it is possible to prevent the DMA transfer from being interrupted.

  According to the seventh aspect of the present invention, it is possible to obtain an effect that the DMA transfer can be performed at high speed and efficiently as compared with the case where the number of transfer information constituting the transfer information group is always constant.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of an image processing system 10 including an information processing unit as an embodiment according to the information processing apparatus of the present invention.

  The image processing system 10 includes an information processing unit 13 including a motherboard 12 and a controller board 14, an image input unit 16, an image output unit 18, a controller 20, and an LCD (liquid crystal display) 22.

  The motherboard 12 includes a CPU (Central Processing Unit) 24 and a memory 28 as a main memory. The CPU 24 and the memory 28 are connected by a dedicated bus via the hub 26. The memory 28 has an area for storing image data output (printed) by the image output unit 18 and image data read by the image input unit 16, and the image data is provided on a controller board 14 to be described later. DMA (direct memory access) is transferred to and from the memory 44 without the intervention of the CPU 24.

  The hub 26 is connected to an LCD 22 provided outside the mother board 12. The LCD 22 is a liquid crystal display device having a touch panel on the display surface, and functions as a user interface.

  A hub 26 for connecting a dedicated bus is connected to a hub 30 for connecting a general-purpose bus. An HDD (hard disk device) 32 and an I / O port 34 are connected to the hub 30 via a general-purpose bus. The HDD 32 stores programs executed by the CPU 24 and various data. The I / O port 34 functions as an input / output interface and is connected to peripheral devices of the image processing system 10.

  The recording medium for recording the program executed by the CPU 24 and various data is not limited to the HDD, and may be a CD-ROM, DVD disk, magneto-optical disk, IC card, ROM, or the like (not shown). It may be a transmission medium such as a carrier wave on a telecommunication line, and is not particularly limited.

  The motherboard 12 is provided with a general-purpose bus interface 36, which is also connected to a general-purpose bus interface 38 provided on the controller board 14.

  The controller board 14 includes a bus bridge 40, a memory 44, a logic circuit 46, a CPU 48, and an image processing circuit 50. The bus bridge 40, the memory 44, the CPU 48, and the image processing circuit 50 are connected to the logic circuit 46 and exchange data with each other via the logic circuit 46. The logic circuit 46 is a circuit programmed as a data transfer circuit, but only transfers data and does not control data transfer. The image processing circuit 50 is a circuit that performs predetermined image processing on input image data.

  The bus bridge 40 is connected to the interface 38 via a general-purpose bus and to the logic circuit 46. The bus bridge 40 has a bridge function between general-purpose buses and a bus master function. The bus master function is a function for exchanging data between the memory 44 and the image processing circuit 50 without using the CPU 48 on the controller board 14. Specifically, in the controller board 14, when the image output unit 18 outputs an image, the image data is DMA-transferred from the memory 44 to the image processing circuit 50 via the logic circuit 46, and the image is read by the image input unit 16. In this case, the image data obtained by reading is DMA-transferred from the image processing circuit 50 to the memory 44 via the logic circuit 46.

  On the other hand, the DMA function for transferring data between the memory 28 on the motherboard 12 and the memory 44 on the controller board 14 without using the CPU 24 on the motherboard 12 is separate from the bus master function of the bus bridge 40. This is realized by a DMAC (DMA controller) 42 provided in the bus bridge 40. The DMAC 42 is a circuit equipped with a scatter gather function capable of transferring data continuously to jumping addresses. The detailed operation of the DMAC 42 will be described later.

  The connector 52 provided on the controller board 14 is connected to a connector 56 provided on the controller 20 having a control mechanism for controlling the image input unit 16 and the image output unit 18. Further, the connector 52 of the controller board 14 is connected to the image processing circuit 50 described above. Image data subjected to image processing by the image processing circuit 50 is transmitted and received through the connector 52 and the connector 56.

  The controller board 14 is provided with a connector 54 different from the connector 52. The connector 54 is directly connected to the logic circuit 46 and is also connected to a connector 58 provided in the controller 20. Control data and messages are transmitted and received between the controller 20 and the controller board 14 via these connectors 54 and 58.

  Here, the function of the DMAC 42 will be described. The image processing system 10 handles image data with a large amount of data. Therefore, when image data is transferred in the system, DMA transfer without using the CPU 24 is used. The DMAC 42 performs DMA transfer based on the descriptor created by the CPU 24.

  A descriptor refers to transfer information including information necessary for DMA transfer. The CPU 24 creates descriptors for each predetermined unit transfer amount, and creates a descriptor list by connecting a plurality of the created descriptors. In this embodiment, the descriptor list is stored in a descriptor storage area provided in the memory 28, and its storage address is registered in a FIFO descriptor list management queue. Note that the descriptor list storage area is not limited to the memory 28, but may be the memory 44 of the controller board 14, and is not particularly limited.

  The CPU 24 sets the addresses registered in the descriptor list management queue in the DMAC 42 and activates the DMAC 42. Thus, the DMAC 42 sequentially reads and reads the descriptors one by one from the descriptor list stored in the set address. The DMA transfer is continuously executed according to the descriptor.

  When the DMA transfer is completed for all the descriptors linked to one descriptor list, an interrupt of the CPU 24 is generated. At this time, the CPU 24 reads the address of the next descriptor list from the descriptor list management queue and sets it in the DMAC 42. Then, descriptors linked to the descriptor list of the set address are sequentially read and DMA transfer is continuously performed. By repeating this, all the image data to be transferred is finally DMA transferred.

  FIG. 2 is a diagram showing an example of a descriptor list read by the DMAC 42 in a system adopting the virtual storage system.

  The memory 28 of the motherboard 12 is managed by a virtual storage method. As shown in FIG. 2A, physically discontinuous physical address areas are mapped and managed in continuous virtual address areas. When accessing the actually stored data, the continuous address range of the virtual address area is converted into the corresponding physical address range according to the address conversion table or the like and accessed. Although the minimum unit of physical memory that can be mapped to a virtual address is called a page, the CPU 24 checks the address of data physically distributed in units of page, and creates a descriptor for each.

  As shown in FIG. 2B, the descriptor according to the present embodiment includes information on the next descriptor address, transfer data amount, transfer source address, and transfer destination address.

  “Next descriptor address” is data indicating an address of a descriptor to be read by the DMAC 42 next to the descriptor among the plurality of descriptors linked to the descriptor list. If the descriptor is the descriptor read at the end of the descriptor list, data indicating the last descriptor in the descriptor list is stored in the area of the next descriptor address. With this next descriptor address, descriptors stored in physically discontinuous areas are continuously read out and DMA-transferred.

  The “transfer data amount” is data indicating the size of data to be DMA transferred by the descriptor. The “transfer source address” is data indicating an address of a memory in which data to be transferred is stored. The “transfer destination address” is data indicating an address at which data read from the transfer source address by the transfer data amount is written.

  In the present embodiment, the data amount that can be transferred by each descriptor has a maximum page size, and the “transfer data amount” of each descriptor is a fixed value (unit transfer amount) equal to or smaller than the page size. As a result, the number of descriptors constituting the descriptor list and the transfer time are in a proportional relationship. Hereinafter, the number of descriptors constituting each descriptor list is referred to as “number of blocks”.

  FIG. 3 is an explanatory diagram for explaining the structure of the descriptor list management queue for managing the descriptor list. In the descriptor list management queue, descriptor list pointers indicating addresses where descriptor lists are stored (more specifically, addresses where the first descriptor among the plurality of descriptors constituting the descriptor list are stored) are linked in a list structure. This is a buffer configured. Further, a predetermined register (or a predetermined area of the memory) of the CPU 24 stores a descriptor list management queue pointer that indicates the first descriptor list pointer in the descriptor list management queue. Since the descriptor list management queue uses the FIFO method, when the CPU 24 reads the first descriptor list pointer, the descriptor list management queue pointer is rewritten so that it points to the next descriptor list pointer.

  In addition, when a new descriptor list is created and stored in a predetermined storage area, the CPU 24 adds a descriptor list pointer indicating the address of the created descriptor list to the end of the descriptor list management queue. As a result, the addresses of the descriptor lists are registered in the order of creation.

  When no descriptor list is registered in the descriptor list management queue, the descriptor list management queue pointer is NULL.

  When executing the DMA transfer, the CPU 24 sets the first descriptor list pointer pointed to by the descriptor list management queue pointer in the DMAC 42 to cause the DMAC 42 to start the DMA transfer, and performs DMA transfer based on the descriptor list indicated by the descriptor list pointer. Let the transfer occur. The DMA transfer is continuously performed without interruption of the CPU 24 until the DMA transfer of one descriptor list is completed. On the other hand, during the DMA transfer by the DMAC 42, the CPU 24 creates the next descriptor list and subsequent descriptor lists within a range satisfying a predetermined creation condition and registers them in the descriptor list management queue.

  When DMA transfer by one descriptor list is completed, an interrupt of the CPU 24 is generated at that time. The CPU 24 sets the next descriptor list pointer pointed to by the descriptor list management queue pointer in the DMAC 42 and performs DMA transfer. As a result, the descriptor list is read out in the order registered in the descriptor list management queue, and DMA transfer is performed.

  In this embodiment, test reference data having a predetermined amount of data is DMA transferred, the DMA transfer rate is measured, and the optimum number of blocks in the descriptor list is determined from the measurement result.

  FIG. 4 is a flowchart showing the flow of a program for determining the number of blocks. This program is executed by the CPU 24 at a predetermined timing.

  In step 100, 0 is set to j and k. Here, j indicates a subscript of an array size_table that defines a plurality of types of data amounts of basic data. That is, data indicating different data amounts is stored in each element of the array size_table. K indicates a subscript of the array block_table that defines a plurality of types of blocks. That is, data indicating different numbers of blocks is stored in each element of the array block_table.

  In step 102, the subscript j of the array size_table is counted up, and the data amount of the reference data stored in the counted up subscript element is set in the variable data_size.

  In step 104, the subscript k of the array block_table is counted up, and the number of blocks stored in the counted subscript element is set in the variable block_count. In the present embodiment, the number of blocks stored in the array block_table increases as the subscript k increases.

  In step 106, the value of variable block_count is set to be the number of blocks in each descriptor list.

  In step 108, measurement of the DMA transfer rate is started.

  In step 110, the CPU 24 creates a descriptor list in which descriptors are linked by the number of variables block_count, causes the DMAC 42 to perform DMA transfer of reference data having a data amount indicated by the variable data_size, and performs a DMA transfer rate measurement process. Here, either one of DMA Write (write) or DMA read (read) may be performed, or both may be performed.

  In step 112, after the measurement is completed, a DMA transfer rate is obtained based on the time taken for the DMA transfer and the data amount indicated by the variable data_size, and the obtained DMA transfer rate is calculated using the value of the variable block_count (number of blocks) and the variable data_size A value (data amount) is associated and stored as measurement data.

  In step 114, the measurement for all the predetermined number of blocks has been completed, that is, the number of blocks that can be set has an upper limit naturally according to the variable data_size, so the measurement for all the number of blocks that can be set according to the variable data_size Determine if you did. Here, if a negative determination is made, the process returns to step 104, counts up k, sets the number of blocks stored in the next element of the array block_table to the variable block_count, and measures again in the same manner as described above. Do.

  On the other hand, if an affirmative determination is made in step 114, the process proceeds to step 116, where the optimum number of blocks when the data amount is the variable data_size is determined from the measurement result, and is registered in a predetermined table in association with the variable data_size. To do. Here, a specific example of a method for determining the number of blocks will be described.

  FIG. 5 is an example of a graph showing the measurement result of the DMA transfer rate when the 4 Mbyte reference data is DMA-transferred, and FIG. 6 is the DMA transfer rate measurement result when the 32 Mbyte reference data is DMA-transferred. FIG. 7 is an example of a graph showing a measurement result of the DMA transfer rate when 63 Mbytes of reference data is DMA-transferred.

  Here, the double descriptor method in the graph is a method for creating a descriptor list both at the time of CPU interrupt and during DMA transfer, and the single descriptor method is a method for creating a descriptor list only at the time of CPU interrupt. Say. In the graph, “guideline” generally indicates that a descriptor is created and DMA-transferred in units of pages, but the beginning and end of data are physically stored in units of pages on the memory 28. If it is not at the boundary, there may be some fluctuations in the number of interrupts of the CPU 24 and the size of one DMA transfer. Therefore, it is described as a guide here. However, since this variation is not large and can be ignored, the optimum number of blocks is determined using the measurement result as it is.

  As is clear from each graph, the transfer rate is low if the number of blocks is too small in any method, and the transfer rate gradually increases as the number of blocks increases, but if the transfer rate increases to some extent, it stabilizes there. Even if the number of blocks is increased, the transfer rate does not increase much. Therefore, in step 116, the CPU 24 determines the number of blocks when the transfer rate is stable as the optimum number of blocks in the data amount. Note that the number of blocks when stabilized may be, for example, the number of blocks when the rate of change in the transfer rate with respect to the change in the number of blocks falls within a predetermined range. In the example shown in FIGS. 5 to 7, the number of blocks surrounded by ○ is determined as the optimum number of blocks.

  As is clear from each graph, the number of blocks with a high transfer rate is other than the number of blocks surrounded by circles. However, in the present embodiment, the number of blocks is not the optimum number of blocks as follows. Because of the reason.

  If the number of blocks is too large, it takes a long time to create one descriptor list. As a result, not only the first DMA transfer start time is delayed, but the creation of the next descriptor list is not in time only during the DMA transfer period, and a waiting time is generated and the execution of the DMA transfer by the next descriptor list is delayed. There is also. Therefore, in this embodiment, the optimum number of blocks constituting one descriptor list is obtained as described above.

  After determining the number of blocks in this manner, as described above, the number of blocks is registered in a predetermined table in association with the variable data_size. FIG. 8 is an example of a table in which the optimum number of blocks is registered in association with the data amount (transfer size) of the reference data. Such a table is stored in the memory 28 or the HDD 32 so that the CPU 24 can refer to it at the time of DMA transfer described later. Hereinafter, the table in which the optimum number of blocks is registered is referred to as a block number table.

  In step 118, it is determined whether or not the DMA transfer measurement is completed for the data amount stored in all the elements of the array size_table. If a negative determination is made here, k is reset and the process returns to step 102, j is counted up, the data amount stored in the next element of the array size_table is set in the variable data_size, and the same as above Make a measurement.

  As described above, DMA transfer is performed while varying the number of blocks for each reference data, the transfer rate is measured, and the optimum number of blocks is determined for each transfer data amount based on the transfer rate.

  Although it is the timing for measuring and determining the optimum number of blocks, the transfer rate varies depending on the transfer performance of the DMA transfer system (in this case, the information processing unit 13), so such measurement is performed at the system development stage. Thus, the optimum number of blocks may be determined.

  Also, even in the same system, for example, if the type and number of modules operating on the system are different, the load of the CPU 24 may also fluctuate and the transfer rate may fluctuate. Such a measurement may be performed at the time of starting the system or every predetermined time to determine the optimum number of blocks, and the block number table may be updated.

  Further, the user may activate the program for determining the number of blocks at an arbitrary timing via the LCD 22 to update the block number table.

  The CPU 24 creates a descriptor list according to the number of blocks determined in this way and stored in the table, and causes the DMAC 42 to perform DMA transfer.

  FIG. 9 is a flowchart showing a flow of a program executed at the time of DMA transfer. This program is executed by the CPU 24.

  In step 200, data_size indicating the amount of data to be transferred is set in a variable remain_size. The variable “remain_size” is a variable indicating the amount of untransferred data, and as will be described later, the transferred data amount (TransferSize) is subtracted from the variable “remain_size” every time data transfer by one descriptor list is completed. In step 200, 0 is set to a flag DL_end_flag indicating whether or not all descriptor lists for transferring data to be transferred have been created.

  In step 202, it is determined whether or not all data to be transferred has been transferred. Here, when the variable remain_size becomes 0 and the flag DL_end_flag becomes 1, it is determined that the transfer of all data has been completed, and in other cases, it is determined that the transfer has not been completed.

  If the determination in step 202 is negative, it is determined in step 204 whether or not to create the first descriptor list.

  If an affirmative determination is made in step 204, the process proceeds to step 206.

  In step 206, the number of blocks corresponding to data_size is read from the block number table, and the number obtained by dividing the number of blocks by 2 is set as the number of blocks in the first descriptor list.

  Here, the number of blocks read from the block number table is divided by 2 to obtain the number of blocks in the first descriptor list. This shortens the creation time of the first descriptor list and increases the time until the DMAC 42 is activated. This is because the start timing of the first DMA transfer is advanced earlier. On the other hand, if the number of blocks in the first descriptor list is too small, it may not be possible to create the next descriptor list during the DMA transfer period by the first descriptor list. The number of blocks in the descriptor list is obtained. Note that when the amount of data to be transferred (data_size) is extremely small, the optimum number of blocks constituting the descriptor list is also small. Even if the number of read blocks is used as it is, the start of DMA transfer is not significantly affected. There are many cases. Therefore, in such a case, the number of read blocks may be used as it is without being divided by two.

  Here, the number of blocks in the first descriptor list is obtained by dividing by 2. However, the present invention is not limited to this. Depending on the amount of data, it may be divided by 3, or by subtracting a predetermined number. You may ask for it.

  In step 208, the first descriptor list is created with the number of blocks set in step 206 and registered in the descriptor list management queue so that the descriptor management queue pointer points to the first descriptor list pointer indicating the address of the created descriptor list. Set to. Then, after setting the first descriptor list pointer pointed to by the descriptor list management queue pointer in the DMAC 42, the DMAC 42 is activated. As a result, the DMAC 42 starts DMA transfer.

  On the other hand, if a negative determination is made in step 204, the process proceeds to step 210, where the optimum number of blocks corresponding to data_size is read from the block number table, and the number of blocks is set as the number of blocks in the descriptor list to be created.

  After the processing of step 208 or step 210, in step 212, the current usage rate of the CPU 24 or the occupation time of the CPU 24 is acquired. In this system, during the execution of this program, the usage rate of the CPU 24 or the occupation time of the CPU 24 is always monitored in the background. The occupation time of the CPU 24 is cumulatively counted from the start of DMA transfer by each descriptor list, and is reset when the DMA transfer ends (when the CPU 24 interrupts).

In step 214, it is determined whether or not the descriptor list creation condition is satisfied. The descriptor list creation conditions are stored and set in advance in a storage device such as the HDD 32 that can be referred to during execution of the program. In this embodiment,
1. The usage rate or occupation time of the CPU 24 does not exceed a predetermined value, and the number of descriptor lists created from the previous CPU 24 interrupt until the present time is the next interrupt (until the DMA transfer being executed is completed). ) Not exceed the number of descriptor lists that can be created,
2. No descriptor list is registered in the descriptor list management queue (that is, the descriptor list management queue pointer is NULL),
These two conditions are set as descriptor list creation conditions.

  In the present embodiment, if at least one of the two creation conditions is satisfied, the CPU 24 makes a positive determination in step 214.

  Note that since the time until the interrupt of the CPU 24 varies depending on the number of blocks in the descriptor list related to the DMA transfer being executed, the number of descriptor lists that can be created within that time also varies. Therefore, in the present embodiment, the number of descriptor lists that can be created during DMA transfer is set in advance in a storage device such as the HDD 32 according to the number of blocks in the descriptor list, and the CPU 24 refers to this. (Or by calculating each time instead of storing in advance), the number of descriptor lists that can be created before the next interrupt is obtained, and the maximum number of descriptors that can be created A list is created (refer to creation condition 1 above).

  If an affirmative determination is made in step 214, in step 216, the CPU 24 creates one descriptor list for the number of blocks read in step 210 and registers it in the descriptor list management queue.

  In step 218, it is determined whether or not all descriptor lists for transferring the transfer target data have been created. If a negative determination is made here, the process returns to step 202 and the above process is repeated. On the other hand, if an affirmative determination is made in step 218, the flag DL_end_flag is set to 1 in step 220, and the process returns to step 202.

  If it is determined in step 214 that the descriptor list creation condition is not satisfied, the CPU 24 proceeds to step 222 without further creating the descriptor list and terminates the currently executing DMA transfer. wait. When the DMA transfer is completed in the DMAC 42 and a signal is received from the interrupt handler, the process proceeds to step 224, and the data amount (TransferSize) transferred by the current DMA transfer is subtracted from the variable remain_size.

  In step 226, the CPU 24 retrieves the next descriptor list pointer from the descriptor list management queue based on the descriptor list management queue pointer.

  In step 228, the extracted descriptor list pointer is set in the DMAC 42, and then the DMAC 42 is activated. As a result, the DMAC 42 starts DMA transfer using the next descriptor list. After step 228, the process returns to step 202 and the same processing as described above is performed.

  When the transferred data amount is gradually subtracted from the variable maintain_size in step 224 to become 0 and the flag DL_end_flag becomes 1 in step 220, it is determined in step 202 that all the transfer target data has been transferred, finish.

  Next, a method for creating a descriptor list will be described more specifically with reference to a timing chart.

  FIG. 10 is a diagram illustrating an example of a timing chart when the number of blocks in the descriptor list is different between the first descriptor list and the other descriptor lists.

  In FIG. 10, the period indicated by “all image data transfer section” is a period for DMA transfer of all the data to be transferred, and more specifically, the DMA transfer function (the DMA transfer program described above). ) Is called and the program is terminated.

  In FIG. 10, each of a plurality of periods indicated by DMA transfer sections T1 to Tn is a period from the start to the end of DMA transfer based on one descriptor list (that is, the next period after the interruption of the CPU 24 ends). Period until an interrupt occurs).

  Each of the plurality of periods indicated by the descriptor list construction sections D1 to Dn represents a period for creating one descriptor list (one descriptor list is created in one construction section). In this example, the descriptor list corresponding to the DMA transfer interval T1 is created in the construction interval D1 before the start of the DMA transfer interval T1, and the descriptor list corresponding to the DMA transfer interval T2 is the previous DMA. The descriptor list corresponding to the DMA transfer period T3 created in the construction period D2 in the transfer period T1 is created in the construction period D3 in the previous DMA transfer period T2, and so on. Each descriptor list except the descriptor list is created in the previous DMA transfer section.

  As described above, in the present embodiment, the number of blocks in the first descriptor list is set to be smaller than the number of blocks in the second and subsequent descriptor lists. Therefore, as shown in FIG. 10, the construction section D1 is shorter than the construction sections D2 to Dn. Therefore, the start timing of the DMA transfer performed based on the first descriptor list is advanced. As described above, the second and subsequent descriptor lists are created with the optimum number of blocks determined by the block number determination program (here, the number of blocks registered in the block number table).

  Next, as in the DMA transfer program of the above-described embodiment, when the descriptor list creation condition is satisfied during the DMA transfer (in the DMA transfer interval), the DMA transfer performed after the DMA transfer being executed A specific example of the case where the descriptor list is created within a range in which the descriptor list can be created will be described with reference to FIGS.

  FIG. 11 is a diagram illustrating an example of a timing chart when a descriptor list is created while monitoring the usage rate of the CPU 24.

  FIG. 11 shows “system CPU usage rate” in addition to “all image data transfer period”, “DMA transfer period”, and “descriptor list construction period” shown in FIG. The CPU usage rate is the percentage of the time that a module or the like occupies the CPU 24 in%.

  In this example, if no descriptor list is registered in the descriptor list management queue, a descriptor list is created regardless of the CPU usage rate. Otherwise, the CPU usage rate is referred to and the CPU usage rate is set in advance. If the predetermined upper limit value is not exceeded, the descriptor list is created in advance within the number that can be created in the DMA transfer section. On the other hand, when the upper limit of the CPU usage rate is exceeded or the number of descriptor lists created in the DMA transfer section reaches the number that can be created in the DMA transfer section, the descriptor list is not created. The creation process is carried forward to the next DMA transfer section.

  As shown in FIG. 11, after one descriptor list with a small number of blocks is created in the construction section D1 before the DMA transfer section T1, two descriptor lists with the optimum number of blocks are created in the DMA transfer section T1. (Two in total in construction sections D2 and D3). In the next DMA transfer section T2, three descriptor lists are created in the three construction sections D4, D5, and D6. In the DMA transfer sections T1 and T2, since the CPU usage rate is lower than the upper limit value, as many descriptor lists as possible can be created according to the length of the DMA transfer section.

  However, the CPU usage rate exceeds the upper limit in the DMA transfer period T3. In addition, the descriptor list corresponding to the DMA transfer section T6 has already been created in the DMA transfer sections T1 and T2. Accordingly, since no descriptor list creation condition is satisfied in the DMA transfer period T3, no descriptor list is created. Further, in the DMA transfer section T4, since the CPU usage rate becomes equal to or less than the upper limit value from the middle, the descriptor list is created at that time (construction section D7).

  The method of creating the descriptor list while monitoring the CPU usage rate in this way is suitable for various systems such as a system that creates a descriptor list with a preemptive module in which execution modules are forcibly switched.

  FIG. 12 is a diagram illustrating an example of a timing chart when a descriptor list is created while monitoring the occupation time of the CPU 24.

  In FIG. 12, “CPU occupation time” is shown in addition to “all image data transfer section”, “DMA transfer section”, and “descriptor list construction section” shown in FIG. The CPU occupation time indicates the total amount of time that the module that creates the descriptor list occupies the CPU 24, and is obtained by the module that measures the occupation time of the CPU 24 incorporated in the image processing system 10 in advance. The CPU occupation time is reset to 0 each time an interrupt from the CPU 24 occurs.

  In this example, if no descriptor list is registered in the descriptor list management queue, a descriptor list is created regardless of the CPU occupation time. Otherwise, the CPU occupation time is referred to and the CPU occupation time is determined in advance. If the predetermined upper limit value is not exceeded, the descriptor list is created in advance within the number that can be created in the DMA transfer section. On the other hand, when the upper limit of the CPU occupation time is exceeded or the number of descriptor lists created in the DMA transfer section reaches the number that can be created in the DMA transfer section, the descriptor list is not created. The creation process is carried forward to the next DMA transfer section.

  As shown in FIG. 12, after one descriptor list with a small number of blocks is created in the construction section D1 before the DMA transfer section T1, two descriptor lists with the optimum number of blocks are created in the DMA transfer section T1. (Construction sections D2, D3). Since the CPU occupation time has reached the upper limit when the descriptor list creation is completed in the construction section D3, no further descriptor list is created in this DMA transfer section T1.

  Even in the next DMA transfer section T2, the CPU occupation time has reached the upper limit when two descriptor lists are created, so no further descriptor list is created. The same applies to the subsequent DMA transfer sections T3 and T4.

  In this way, the method for creating the descriptor list while monitoring the CPU occupation time is, for example, various systems such as a system for creating a descriptor list with a non-preemptive embedded module in which execution module switching is not forcibly performed. It is suitable for.

  Although various examples have been described above, the present invention is not limited to the above-described embodiments, and various design changes are made within the scope of the invention described in the claims. May be.

  For example, in the above embodiment, the number of blocks in the first descriptor list is obtained by calculation at the start of DMA transfer. However, the present invention is not limited to this, and the number of blocks in the first descriptor list is obtained in advance, as shown in FIG. In this way, it may be registered in advance in the block number table.

  In the present embodiment, an example in which only the number of blocks in the first descriptor list is reduced has been described. However, the present invention is not limited to this example. The number of blocks may be increased step by step. Even when the number of blocks is increased step by step, a descriptor list having the optimum number of blocks is created at the earliest possible stage so that transfer efficiency does not decrease.

It is a figure which shows the structural example of the image processing system containing the information processing part as embodiment which concerns on the information processing apparatus of this invention. It is a figure which shows an example of the descriptor list read by DMAC in the system which employ | adopted the virtual memory system. It is explanatory drawing explaining the structure of the descriptor list management queue which manages a descriptor list. It is a flowchart which shows the flow of the program for determining the number of blocks. It is a graph which shows the specific example of the measurement result at the time of measuring the DMA transfer rate in a certain system by changing the number of blocks of 4 Mbytes of reference data. It is a graph which shows the specific example of the measurement result at the time of measuring DMA transfer rate in a certain system by changing the number of blocks of the reference data of 32 Mbytes. It is a graph which shows the specific example of the measurement result at the time of measuring the DMA transfer rate in a certain system by changing the number of blocks of the reference data of 63 Mbytes. It is an example of a block number table in which an optimum number of blocks is registered in association with a transfer data amount (transfer size). It is a flowchart which shows the flow of the program performed at the time of DMA transfer. It is a figure which shows an example of the timing chart in the case of making the number of blocks of a descriptor list differ by the first descriptor list and other descriptor lists. It is a figure which shows an example of the timing chart in the case of producing a descriptor list | wrist while monitoring the usage rate of CPU. It is a figure which shows an example of the timing chart in the case of creating a descriptor list, monitoring the occupation time of CPU. It is a modification of a block number table.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image processing system 12 Mother board 13 Information processing part 14 Controller board 24 CPU
26 Hub 28 Memory 30 Hub 32 HDD
40 bus bridge 42 DMA controller 44 memory

Claims (7)

The unit transfer of the data to be transferred based on a transfer information group composed of a plurality of transfer information for each unit transfer amount including information necessary for direct memory access (DMA) transfer without intervention of a central processing unit (CPU) Transfer means for DMA transfer for each quantity;
The number of transfer information constituting the transfer information group based on the transfer speed when the transfer means performs DMA transfer by changing the number of transfer information constituting the transfer information group with reference data having a predetermined data amount A determination means for determining
Creating means for creating a transfer information group composed of a plurality of pieces of transfer information determined by the determining means when transferring data to be transferred by DMA;
An information processing apparatus including: A storage unit that stores the number of pieces of transfer information determined by the determination unit in association with the data amount of the reference data;
The creation unit reads the number stored in the storage unit according to the amount of data to be transferred when the transfer target data is DMA-transferred, and transfer information configured by connecting the read number of transfer information. The information processing apparatus according to claim 1, which creates a group.   In the case where the creation means creates a plurality of transfer information groups for DMA transfer of the data to be transferred, the decision means decides the first transfer information group or a transfer information group from the beginning to a predetermined number. A transfer information group composed of a smaller number of pieces of transfer information than the determined number is created, and a transfer information group comprising the number of pieces of transfer information determined by the determining means is created for the subsequent transfer information groups The information processing apparatus according to claim 1 or 2. The creating means performs the DMA transfer after the DMA transfer being executed until the DMA transfer being executed by the transfer means is completed when creating a plurality of transfer information groups for DMA transfer of the data to be transferred. A transfer information group for DMA transfer to be stored in the transfer information storage means in the order of creation,
The information processing apparatus according to claim 1, wherein the transfer unit performs DMA transfer by reading transfer information groups from the transfer information storage unit in the order of creation.   The information processing apparatus according to claim 4, wherein the creation unit creates the transfer information group when the CPU usage rate or the CPU occupation time does not exceed a predetermined value.   The creation means is executing even when the CPU usage rate or the CPU occupation time exceeds a predetermined value when no unread transfer information group is stored in the transfer information storage means. 6. The information processing apparatus according to claim 5, wherein a transfer information group for DMA transfer performed after the DMA transfer is created. The unit transfer of the data to be transferred based on a transfer information group composed of a plurality of transfer information for each unit transfer amount including information necessary for direct memory access (DMA) transfer without intervention of a central processing unit (CPU) A computer provided with a transfer means for performing DMA transfer for each quantity,
The number of transfer information constituting the transfer information group based on the transfer speed when the transfer means performs DMA transfer by changing the number of transfer information constituting the transfer information group with reference data having a predetermined data amount Determining means for determining the transfer information, and creating means for creating a transfer information group configured by linking the number of transfer information determined by the determining means when the transfer target data is DMA-transferred,
Program to function as.

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