JP5606411B2 - Wireless signal synchronization processor - Google Patents

Description

  The present invention relates to a radio signal synchronization processing apparatus that performs synchronization processing of received signals.

  Conventionally, as frequency modulation that performs communication with the instantaneous frequency proportional to the modulation baseband, GFSK (Gaussian-filtered Frequency Shift Keying) that limits the band by applying a Gaussian filter to the modulated signal, and the instantaneous frequency shift is orthogonal Communication systems such as GMSK (Gaussian-filtered Minimum Shift Keying) using the minimum instantaneous frequency are known.

  Further, as one of the time synchronization processes of general wireless communication, there is a method of correlating with a replica signal held in advance in a wireless receiver within a certain range while shifting a received signal for each sample. By using the training signal that constitutes the preamble part as the replica signal, the correlation power value becomes a large value when the correlation timing coincides with the preamble part. By utilizing this, it is possible to detect the frame position and the preamble signal.

  Also in the GMSK and GFSK communication systems, it is possible to detect the frame position and the preamble signal using the above system. Specifically, using the fact that the frequency shift of the alternating pattern of “1” and “0” in the preamble portion is very similar to a sine wave with respect to the GFSK signal, a correlation is obtained using the sine wave for the replica signal. Thus, a method for detecting a preamble portion is disclosed in Patent Document 1 below.

JP 2003-87155 A

  However, according to the above conventional technique, complex multiplication is required for the correlation calculation. For this reason, there is a problem that the amount of calculation increases and the power consumption increases. In addition, there is a problem that the preamble portion is effective only with an alternating pattern of “0” and “1”, and cannot be detected when the preamble portion is not an alternating pattern.

  The present invention has been made in view of the above, and an object of the present invention is to provide a wireless signal synchronization processing device capable of reducing the amount of correlation calculation and power consumption regardless of the pattern of the preamble portion. .

  In order to solve the above-described problems and achieve the object, the present invention frequency-modulates preamble data having the same pattern as the preamble portion added to the IQ reception signal, and uses the result of hard decision after delay detection as a replica signal. A correlation power value is calculated by performing a correlation operation between the replica signal generating means to output, the replica signal and the delay-detected IQ received signal, and a phase rotation amount due to a frequency offset is calculated from the phase of the correlation power value. Correlation calculating means for calculating an estimated frequency offset value, correlation power value peak detecting means for detecting a timing at which the maximum correlation power value is obtained from the correlation power value as frame timing, and the maximum correlation power value and a prescribed correlation power. Preamble detection means for outputting a result of comparison with a threshold as a preamble detection result; Using Tsu preparative estimate, characterized in that it comprises a AFC means and for frequency offset correcting the IQ received signal before delay detection.

  According to the present invention, there is an effect that the calculation amount and power consumption of the correlation calculation can be reduced regardless of the pattern of the preamble portion.

FIG. 1 is a diagram illustrating a configuration example of a wireless signal synchronization processing device. FIG. 2 is a diagram illustrating a configuration example of the replica signal generation unit. FIG. 3 is a diagram showing an image of hard decision. FIG. 4 is a diagram showing an image of ternary hard decision. FIG. 5 is a diagram showing a frame configuration. FIG. 6 is a flowchart showing synchronization processing in the wireless signal synchronization processing apparatus. FIG. 7 is a diagram showing an image of correlation calculation processing. FIG. 8 is a diagram illustrating a configuration example of the replica signal generation unit. FIG. 9 is a diagram illustrating an MSK modulated signal. FIG. 10 is a diagram illustrating a configuration example of a wireless signal synchronization processing device. FIG. 11 is a diagram illustrating a configuration example of the replica signal generation unit. FIG. 12 is a flowchart showing synchronization processing in the wireless signal synchronization processing apparatus.

  Embodiments of a wireless signal synchronization processing device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a wireless signal synchronization processing device according to the present embodiment. The radio signal synchronization processing apparatus includes a delay detection unit 10, a correlation calculation unit 20, a correlation power value peak detection unit 30, a preamble detection unit 40, an AFC (automatic frequency control) unit 50, and a replica signal generation unit 60. .

  The delay detection unit 10 performs delay detection on the IQ reception signal. The correlation calculation unit 20 performs a correlation calculation process using the IQ signal after delay detection and the replica signal. The correlation power value peak detection unit 30 performs peak detection of the correlation power value. The preamble detection unit 40 compares the correlation power value with the correlation power threshold value, and outputs a preamble detection result and frame timing. The AFC unit 50 performs frequency offset correction on the IQ reception signal using the frequency offset estimation value. The replica signal generation unit 60 performs GMSK modulation on the preamble data and performs a hard decision to generate a replica signal.

  FIG. 2 is a diagram illustrating a configuration example of the replica signal generation unit 60. The replica signal generation unit 60 includes a GMSK modulation unit 61, a reception Gauss filter unit 62, a delay detection unit 63, and a preamble signal hard decision unit 64. The GMSK modulation unit 61 and the reception Gaussian filter unit 62 GMSK-modulate the same preamble data ((a) in FIG. 2) as the preamble portion of the IQ reception signal, and the delay detection unit 63 uses the preamble data after GMSK modulation ( (B) in FIG. 2 is subjected to delay detection to generate a preamble signal ((c) in FIG. 2) after passing through the filter. Then, the preamble signal hard decision unit 64 makes a hard decision on the preamble signal after passing through the filter to a binary value of “1” or “−1” by IQ ((d) in FIG. 2). In addition, although the case where GMSK modulation was performed was demonstrated, it is not limited to this, It is also possible to use another frequency modulation, for example, GFSK modulation.

  FIG. 3 is a diagram showing an image of hard decision in the preamble signal hard decision unit 64. The preamble signal hard decision unit 64 makes a hard decision with respect to each of the preamble signals after passing through the filter as “1” if the IQ is a positive value and “−1” if it is a negative value. The replica signal generation unit 60 outputs the result of the hard decision made by the preamble signal hard decision unit 64 to the correlation calculation unit 20 as a replica signal.

  In addition, although the case where the hard decision is performed with the binary values “1” and “−1” as the hard decision has been described, the present invention is not limited to this. For example, it is possible to make a hard decision with three values “1”, “0”, and “−1”. FIG. 4 is a diagram showing an image of a hard decision with three values in the preamble signal hard decision unit 64. Here, the hard decision is made based on “0.5” or “−0.5” instead of positive and negative.

  FIG. 5 is a diagram showing a frame configuration according to the present embodiment. The frame includes a preamble part 100 and a data part 200. In the radio signal synchronization processing device, the received signal is subjected to correlation processing with a training signal constituting the preamble unit 100 as a replica signal for a certain period to detect the preamble unit 100, and detection of a desired preamble, frame data Detection of the head position (frame detection) and AFC (automatic frequency control) are performed.

  Note that the frame configuration shown in FIG. 5 is an example, and is not necessarily limited to this configuration. Other configurations may be used as long as the frame configuration includes a preamble portion.

  Next, synchronization processing for performing preamble detection, frame detection, and frequency offset estimation in the radio signal synchronization processing device will be described. FIG. 6 is a flowchart showing synchronization processing in the wireless signal synchronization processing apparatus.

  First, the delay detection unit 10 performs delay detection on the received baseband IQ signal (IQ reception signal) at intervals of one symbol (step S1). Note that one symbol interval is an example, and delay detection may be performed at intervals other than one symbol interval.

  Next, the correlation calculation unit 20 performs correlation processing using the IQ signal after delay detection and the replica signal generated by the replica signal generation unit 60 (step S2). Specifically, cross-correlation is performed for each sample, and a correlation power value for each sample is calculated. Here, it is assumed that the correlation calculation start position of the IQ signal after delay detection is the i-th sample. Further, the phase rotation amount due to the frequency offset at one symbol length is calculated from the phase of the correlation calculation result, and the phase rotation amount per sample averaged at one symbol length is calculated as the frequency offset estimated value. The correlation calculation unit 20 outputs the calculated correlation power value and the estimated frequency offset value to the correlation power peak detection unit 30 together with the sample start position i.

  Hereinafter, a specific method for calculating the frequency offset estimated value will be described. Assuming that the IQ received signal after delay detection in the presence of a frequency offset is S (i) and the replica signal is R (n), the IQ received signal S (i) and the replica signal R (n) are expressed by the equations (1) and (1), respectively. (2).

Here, A (i) and A ′ (n) are the amplitude of each signal, φ (i) and φ ′ (n) are the phases of each signal, N _s is the number of samples of one symbol, and i is the correlation calculation start position. Represents. N _s is the number of samples of one symbol in the case of delay detection at intervals of one symbol, but for example, when delay detection is performed at intervals of N symbols, N _s is the number of samples of N symbols. F _off indicates an offset frequency. When the correlation calculation result between the IQ reception signal S (i) and the replica signal R (n) is C (i), the correlation calculation result C (i) can be expressed by the following equation (3).

Multiplication “×” indicates complex multiplication, and “ ^* ” indicates complex conjugate. N _rep indicates the number of replica signal samples. Here, the influence of noise is ignored, and when the IQ reception signal S (i) is equal to the replica signal R (n), the correlation calculation result C (i) can be expressed by the following equation (4).

  Therefore, when the correlation calculation start position i of the IQ received signal S (i) is equal to the head of the preamble, the phase rotation amount in one symbol can be determined by obtaining the phase of the correlation calculation result C (i), and the frequency offset estimation can be performed. It becomes possible.

  Here, in the present embodiment, the replica signal R (n) is hard-determined in the replica signal generation unit 60. That is, since the IQ of the replica signal R (n) is “1”, “−1”, or “1”, “0”, “−1”, complex multiplication is not necessary, and correlation calculation is performed only by addition and subtraction. Is possible.

The correlation calculation unit 20 increments the correlation calculation start position i of the IQ signal after delay detection for starting the correlation calculation (step S3), and the correlation calculation count N _corr indicates that the correlation calculation start position i indicates the end of the correlation calculation start position. In the following cases, the process of step S2 is repeatedly executed (step S4: No). On the other hand, when the correlation calculation start position i is larger than the correlation calculation count N _{corr, the process proceeds} to the next correlation power value peak detection unit 30 (step S4: Yes).

FIG. 7 is a diagram showing an image of correlation calculation processing. This indicates that the correlation calculation with the frame side is performed by shifting the position of the replica signal between the correlation calculation start position i from 0 to the correlation calculation count N _corr . When the position of the replica signal is shifted and the correlation timing coincides with the preamble part, the correlation power value becomes a large value.

Next, the correlation power value peak detection unit 30 performs peak detection of the correlation power value (step S5). Specifically, the correlation power value peak detection unit 30 receives the sample position (maximum correlation power value) among the correlation power value and the frequency offset estimation value for each correlation calculation start position i received from the correlation calculation unit 20. The correlation power value sample position) i _max is searched. Then, the correlation power value peak detector 30, a maximum correlation electric power value sample position i _max as a frame timing, and outputs the preamble detection unit 40 together with correlation power value P _max of the maximum correlation electric power value sample position i _max. Further, correlation power value peak detection unit 30 outputs frequency offset estimation value F _off at maximum correlation power value sample position i _max to AFC unit 50.

Next, the preamble detector 40 compares the correlation power value P _max with a predetermined correlation power threshold value P _th stored in advance. Then, the comparison result between correlation power value P _max and correlation power threshold value P _th is output as a preamble detection result to a demodulator (not shown). Similarly, the maximum correlation power value sample position i _max is output as a frame timing to a demodulator (not shown) (step S6).

Finally, the AFC unit 50 performs frequency offset correction on the IQ reception signal using the frequency offset estimation value F _off output from the correlation power value peak detection unit 30 as AFC processing (step S7). Then, the signal after frequency offset correction is output as a received signal to a demodulator (not shown).

  A demodulator (not shown) inputs the preamble detection result, the frame timing, and the received signal, and performs demodulation processing.

  As described above, in the present embodiment, in the radio signal synchronization processing device, the GMSK communication or the GFSK communication in the frame configuration in which the preamble portion exists is generated from the same preamble data as the preamble portion of the received signal. When performing preamble detection, frame detection, and frequency offset estimation by performing correlation calculation with the replica signal, the hard-decided replica signal is used. Thereby, complex multiplication is not required in the correlation calculation, and the amount of calculation can be reduced and the power consumption can be reduced.

Embodiment 2. FIG.
In the first embodiment, the hard decision is made by binarization or ternarization of the replica signal to be used. In the present embodiment, preamble data is subjected to MSK modulation and extracted for each symbol is used as a replica signal. A different part from Embodiment 1 is demonstrated.

  The configuration of the radio signal synchronization processing apparatus of the present embodiment is the same as that of the first embodiment (see FIG. 1), but the configuration of the replica signal generation unit 60 is different. FIG. 8 is a diagram illustrating a configuration example of the replica signal generation unit 60. The replica signal generation unit 60 includes an MSK modulation unit 65 and a delay detection unit 66. The MSK modulation unit 65 performs MSK modulation on the preamble data, and the delay detection unit 66 performs delay detection. Here, the replica signal generation unit 60 outputs the signal after delay detection to the correlation calculation unit 20 as a replica signal.

  Next, the MSK modulated signal will be described. FIG. 9 is a diagram illustrating an MSK modulated signal. A dotted line indicates an MSK signal, and a solid line indicates an MSK replica. Since the MSK-modulated signal takes only “1” or “−1” at the symbol point, complex multiplication is not required in the correlation calculation with the replica signal as in the first embodiment. Since processes other than the replica signal generation unit 60 are the same as those in the first embodiment, a detailed description of the synchronization process in the radio signal synchronization processing apparatus is omitted.

  As described above, in this embodiment, a signal after MSK modulation is used as a replica signal. Also in this case, as in the first embodiment, complex multiplication is not required in the correlation calculation, and the amount of calculation can be reduced and the power consumption can be reduced.

Embodiment 3 FIG.
In calculating the frequency offset estimation value, the replica signal obtained by hard-deciding the preamble data is used in the first embodiment, and the replica signal obtained by MSK-modulating the preamble data is used in the second embodiment. However, when a hard decision or MSK modulated replica signal is used, an error occurs in the frequency offset estimation value. In the present embodiment, different replica signals are used for correlation calculation and frequency offset estimation. A different part from Embodiment 1, 2 is demonstrated.

  FIG. 10 is a diagram illustrating a configuration example of the radio signal synchronization processing device according to the present embodiment. The radio signal synchronization processing apparatus includes a delay detection unit 10, a correlation calculation unit 20a, a correlation power value peak detection unit 30a, a preamble detection unit 40, an AFC unit 50, a replica signal generation unit 60, and a replica signal generation unit. 70 and a frequency offset estimator 80.

  The correlation calculation unit 20a performs correlation calculation processing using the IQ signal and the replica signal after delay detection. Here, unlike Embodiment 1 (correlation calculation unit 20), frequency offset estimation is not performed. The correlation power value peak detection unit 30a performs peak detection of the correlation power value. The replica signal generation unit 70 generates a replica signal used by the frequency offset estimation unit 80 when estimating the frequency offset. Note that the replica signal generated by the replica signal generation unit 70 (second replica signal generation unit) is referred to as replica signal 2 (second replica signal), and is generated by the replica signal generation unit 60 (first replica signal generation unit). The replica signal to be used is the same as that in the first or second embodiment, but in this embodiment, the replica signal is assumed to be the first replica signal (first replica signal). The frequency offset estimation unit 80 performs frequency offset estimation using the replica signal 2 and the frame timing.

  FIG. 11 is a diagram illustrating a configuration example of the replica signal generation unit 70. The replica signal generation unit 70 includes a GMSK modulation unit 71, a reception Gaussian filter unit 72, and a delay detection unit 73. The GMSK modulation unit 71 and the reception Gaussian filter unit 72 perform GMSK modulation on the preamble data, and the delay detection unit 73 performs delay detection on the preamble data after GMSK modulation to generate a preamble signal after passing through the filter. The replica signal generation unit 70 outputs the preamble signal after delay detection as a replica signal.

  Next, synchronization processing for performing preamble detection, frame detection, and frequency offset estimation in the radio signal synchronization processing device will be described. FIG. 12 is a flowchart showing synchronization processing in the wireless signal synchronization processing apparatus.

  First, the delay detection unit 10 performs delay detection on the received baseband IQ signal (IQ reception signal) at intervals of one symbol (step S11). Note that one symbol interval is an example, and delay detection may be performed at intervals other than one symbol interval.

  Next, the correlation calculation unit 20a performs correlation processing using the IQ signal after delay detection and the replica signal 1 generated by the replica signal generation unit 60 (step S12). Specifically, cross-correlation is performed for each sample, and a correlation power value for each sample is calculated. Here, it is assumed that the correlation calculation start position of the IQ signal after delay detection is the i-th sample. The correlation calculation unit 20a outputs the calculated correlation power value to the correlation power peak detection unit 30a together with the sample start position i.

The correlation calculation unit 20a increments the correlation calculation start position i of the IQ signal after delay detection for starting the correlation calculation (step S13), and when the correlation calculation start position i is equal to or _smaller than the number of correlation calculations N _corr , The process is repeatedly executed (step S14: No). On the other hand, if the correlation calculation start position i is larger than the correlation calculation count N _{corr, the process proceeds} to the next correlation power value peak detection unit 30a (step S14: Yes).

Next, the correlation power value peak detection unit 30a detects the peak of the correlation power value (step S15). Specifically, the correlation power value peak detection unit 30a searches for the maximum correlation power value sample position i _max among the correlation power values for each correlation calculation start position i received from the correlation calculation unit 20a. Then, the maximum correlation power value sample position i _max is used as a frame timing, and is output to the preamble detector 40 together with the correlation power value P _max at the maximum correlation power value sample position i _max . The correlation power value peak detection unit 30a outputs the maximum correlation power value sample position i _max to the frequency offset estimation unit 80 as a frame timing.

The frequency offset estimation unit 80 includes an IQ reception signal that starts from the maximum correlation power value sample position i _max (frame timing) input from the correlation power peak detection unit 30a, and the replica signal 2 generated by the replica signal generation unit 70. The correlation calculation is performed once using, and the frequency offset estimated value F _off is calculated from the phase of the correlation calculation result (step S16). The frequency offset estimation unit 80 outputs the calculated frequency offset estimation value F _off to the AFC unit 50. Note that a specific method for calculating the frequency offset estimated value is the same as that in the first embodiment (step S2).

Next, the preamble detector 40 compares the correlation power value P _max with a predetermined correlation power threshold value P _th stored in advance. Then, the comparison result between correlation power value P _max and correlation power threshold value P _th is output as a preamble detection result to a demodulator (not shown). Similarly, the maximum correlation power value sample position i _max is output as a frame timing to a demodulator (not shown) (step S17).

Finally, the AFC unit 50 performs frequency offset correction on the IQ reception signal using the frequency offset estimation value F _off output from the frequency offset estimation unit 80 as AFC processing (step S18). Then, the signal after frequency offset correction is output as a received signal to a demodulator (not shown).

  A demodulator (not shown) inputs the preamble detection result, the frame timing, and the received signal, and performs demodulation processing.

  As described above, in the present embodiment, in the radio signal synchronization processing device, a hard decision or MSK modulated replica signal is used for correlation calculation for detecting the peak of correlation power, and frequency offset estimation is as follows. A replica signal that does not make a hard decision at a position where the correlation power reaches a peak is used. Thereby, the frequency offset estimation accuracy can be further improved while obtaining the same effects as those of the first and second embodiments.

  As described above, the radio signal synchronization processing device according to the present invention is useful for a radio receiver, and is particularly suitable for a radio receiver that receives a frame including a preamble portion.

DESCRIPTION OF SYMBOLS 10 Delay detection part 20, 20a Correlation calculating part 30, 30a Correlation power value peak detection part 40 Preamble detection part 50 AFC part 60, 70 Replica signal generation part 61, 71 GMSK modulation part 62, 72 Reception gauss filter part 63, 73 Delay Detection unit 64 Preamble signal hard decision unit 65 MSK modulation unit 66 Delay detection unit 80 Frequency offset estimation unit

Claims (4)

Replica signal generation for generating a replica signal by frequency-modulating preamble data having the same pattern as the preamble part added to the IQ reception signal, delay-detecting the frequency-modulated signal, and hard-decisioning the delay detection result Means,
A correlation power value is calculated by correlating the replica signal and the delay-detected IQ received signal, and a phase rotation amount due to a frequency offset is calculated from a phase of the correlation power value to calculate a frequency offset estimation value. Correlation calculation means;
Correlation power value peak detection means for detecting, as frame timing, the timing of taking the maximum correlation power value from the correlation power value;
Preamble detection means for outputting a result of comparing the maximum correlation power value and a specified correlation power threshold as a preamble detection result;
AFC means for correcting the frequency offset of the IQ reception signal before delay detection using the frequency offset estimation value;
A wireless signal synchronization processing apparatus comprising: A replica signal generation means for generating a replica signal by the preamble data of the preamble section of the same pattern being applied to the IQ received signals MSK modulation, and differential detection the MSK modulation signal,
A correlation power value is calculated by correlating the replica signal and the delay-detected IQ received signal, and a phase rotation amount due to a frequency offset is calculated from a phase of the correlation power value to calculate a frequency offset estimation value. Correlation calculation means;
Correlation power value peak detection means for detecting, as frame timing, the timing of taking the maximum correlation power value from the correlation power value;
Preamble detection means for outputting a result of comparing the maximum correlation power value and a specified correlation power threshold as a preamble detection result;
AFC means for correcting the frequency offset of the IQ reception signal before delay detection using the frequency offset estimation value;
A wireless signal synchronization processing apparatus comprising: The preamble data of the preamble section of the same pattern being applied to the IQ received signal frequency-modulated, and its frequency modulation signal to delay detection, further generates a first replica signal by hard decision the delay detection result First replica signal generating means;
Second replica signal generating means for generating a second replica signal by frequency-modulating preamble data having the same pattern as the preamble portion attached to the received IQ reception signal and delay-detecting the frequency modulation signal ; ,
Correlation calculating means for calculating a correlation power value by calculating a correlation between the first replica signal and the delay-detected IQ received signal;
Correlation power value peak detection means for detecting, as frame timing, the timing of taking the maximum correlation power value from the correlation power value;
Preamble detection means for outputting a result of comparing the maximum correlation power value and a specified correlation power threshold as a preamble detection result;
Said second replica signal, performs a correlation calculation using the IQ received signal to start the frame timing, and frequency offset estimation means for calculating a frequency offset estimate,
AFC means for correcting the frequency offset of the IQ reception signal before delay detection using the frequency offset estimation value;
A wireless signal synchronization processing apparatus comprising: The preamble data is MSK modulation of the preamble part of the same pattern being applied to the IQ received signal, and a first replica signal generating means for generating a first replica signal by differential detection the MSK modulation signal,
Second replica signal generating means for generating a second replica signal by frequency-modulating preamble data having the same pattern as the preamble portion attached to the received IQ reception signal and delay-detecting the frequency modulation signal ; ,
Correlation calculating means for calculating a correlation power value by calculating a correlation between the first replica signal and the delay-detected IQ received signal;
Correlation power value peak detection means for detecting, as frame timing, the timing of taking the maximum correlation power value from the correlation power value;
Preamble detection means for outputting a result of comparing the maximum correlation power value and a specified correlation power threshold as a preamble detection result;
Said second replica signal, performs a correlation calculation using the IQ received signal to start the frame timing, and frequency offset estimation means for calculating a frequency offset estimate,
AFC means for correcting the frequency offset of the IQ reception signal before delay detection using the frequency offset estimation value;
A wireless signal synchronization processing apparatus comprising:

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