JP5589881B2 - Differential single phase converter circuit - Google Patents

Description

  The present invention relates to a differential single-phase conversion circuit that converts a differential signal into a single-phase signal.

  A differential single-phase conversion circuit that converts a differential signal whose phase is shifted by 180 degrees into a single-phase signal is known. The differential signal is not easily affected by noise, and is mounted on, for example, an LSI used in a wireless device.

  FIG. 5 is a diagram showing a configuration of a conventional differential single-phase conversion circuit. By converting one of the differential signals by 180 degrees and synthesizing it with the other differential signal, conversion from the differential signal to the single-phase signal can be realized. In the circuit of FIG. 5 disclosed in Patent Document 1, one of the differential signals is input to the gate terminal of the common source N-type transistor and the drain terminal is used as the output, and a signal inverted by 180 degrees is extracted. The other side of the differential signal is input to the gate terminal of the common drain P-type transistor and the source terminal is used as the output. Dynamic single phase conversion is realized.

JP 2009-284245 A

  However, in the circuit of FIG. 5, if high CMRR (Common-Mode Rejection Ratio) characteristics are to be obtained even when the temperature changes or the process conditions change, the differential signal is positive. Since N-type and P-type transistors having different temperature and process condition variations are used on the phase input side and the reverse phase input side, and the connection methods are also different, CMRR characteristics also vary and adjustment becomes difficult.

  Furthermore, the frequency characteristics are different between the positive phase side and the negative phase side, and it is difficult to obtain high CMRR characteristics over a wide frequency range.

  Accordingly, the present invention is to provide a differential single-phase conversion circuit having high CMRR characteristics without being affected by variations in temperature and process conditions.

A differential single-phase conversion circuit for achieving the above object amplifies a first differential signal of a pair of differential signals having a reverse phase relationship and outputs the first differential signal in the same phase. A first amplifying circuit, a second amplifying circuit for amplifying a second differential signal of the differential signals and inverting the phase of the second differential signal and outputting the second differential signal, An output terminal for combining and outputting the output signal from the one amplifier circuit and the output signal from the second amplifier circuit, wherein the first amplifier circuit is applied with the first bias voltage at the gate; A first transistor having a drain connected to the source of the first transistor, the first differential signal being input to the drain, and a second bias voltage being applied to the gate; The second amplifier circuit has the first buffer at the gate. A third transistor to which an ass voltage is applied, a drain is connected to a source of the third transistor, the second differential signal is input to a gate, and the second bias voltage is applied to a gate The first to fourth transistors have the same size, and the amount of current flowing through the first to fourth transistors is the same.

  According to the disclosed differential single-phase conversion circuit, the first amplifier circuit and the second amplifier circuit can be configured using the same transistor by including the amplifier circuit including the cascode circuit. High CMRR characteristics can be obtained without being affected by variations in temperature and process conditions between the phase side and the opposite phase side.

It is a figure which shows the 1st structural example of the differential single phase conversion circuit in embodiment of this invention. It is a figure which shows the 2nd structural example of the differential single phase conversion circuit in embodiment of this invention. It is a figure which shows the temperature characteristic of the differential single phase conversion circuit of a 1st structural example and a 2nd structural example. It is a figure which shows the frequency characteristic of the differential single phase conversion circuit of a 1st structural example and a 2nd structural example. It is a figure which shows the structure of the conventional differential single phase conversion circuit.

  FIG. 1 is a diagram illustrating a first configuration example of a differential single-phase conversion circuit according to an embodiment of the present invention. One terminal (positive phase input terminal) IN of the differential input terminals IN and INX is connected to the gate terminal of the common source transistor M1 via the capacitor C1. The source terminal of the common source transistor M1 is grounded, and the drain terminal is connected to the source terminal of the common gate transistor M2. That is, the common source transistor M1 and the common gate transistor M2 are cascode-connected, and the common source transistor M1 and the common gate transistor M2 constitute a cascode circuit. The drain terminal of the common-gate transistor M2 is connected to the single-phase signal output terminal OUT via the capacitor C3.

  The other terminal INX (reverse phase input terminal) is connected to the source terminal of the common gate transistor M3 via the capacitor C2. The source terminal of the common gate transistor M3 is connected to a constant current source. The drain terminal of the common gate transistor M3 is common to the drain terminal of the common gate transistor M2, and is connected to the single-phase signal output terminal OUT via the capacitor C3. The same transistor is used for each of the transistors M1, M2, and M3.

  A load R1 is connected between the drain terminals of the common-gate transistors M2 and M3 and the power supply voltage VDD. A gate bias voltage Vb1 is applied to the gate terminal of the common source transistor M1, and a gate bias voltage Vb2 is applied to each gate terminal of the common gate transistors M2 and M3 via the load R2.

  Next, the operation of the first configuration example will be described.

  From the IN terminal, one input signal (positive phase signal) of the differential signal is input to the gate terminal of the common source transistor M1 via the capacitor C1. The input signal from the IN terminal is a signal on which the gate bias voltage Vb1 is placed. The input signal from the IN terminal is inverted in phase by the common-source transistor M1 (that is, in phase with the phase of the anti-phase signal), amplified by the common-gate transistor M2, and output from the common-gate transistor M2. Output from the drain terminal.

  On the other hand, the other input signal (reverse phase signal) of the differential signal is input from the INX terminal to the source terminal of the common-gate transistor M3 via the capacitor C2. The input signal from the INX terminal is a signal on which the gate bias voltage Vb2 is placed. This input signal is amplified by the grounded gate transistor M3 and output from the drain terminal of the grounded gate transistor M3. At this time, the phase of the input signal from the INX terminal is not inverted and remains in phase with the input signal.

  Therefore, the output signals from the drain terminals of the common-gate transistors M2 and M3 are combined in phase and output from the OUT terminal via the capacitor C3. In this way, the differential signal is converted into a single phase and output with a small loss.

  Since the impedance when the source grounded transistor M1 side is viewed from the drain side of the grounded gate transistor M2 in the cascode circuit is high, the output signal on the INX terminal side output from the drain terminal of the grounded gate transistor M3 is output to the OUT terminal side, It is combined with the output signal from the IN terminal side.

  Since the same transistor is used for each of the transistors M1, M2, and M3, even if the temperature and process conditions change, the IN terminal side and the INX side terminal change in the same way. Less susceptible to process conditions.

  Further, the gain Av of each transistor is defined by Av = gm × Rout (gm: mutual conductance, Rout: load resistance). By making the sizes of the transistors M1, M2, and M3 equal and setting the gate bias voltage of the transistor M1 and the current value of the constant current source so that equal currents flow through them, the amplifier circuit on the IN terminal side (source grounded transistor) The cascode circuit in which M1 and the grounded gate transistor M2 are cascode-connected) and the amplifier circuit (grounded gate transistor M3) on the INX terminal side have substantially the same gm and Rout, that is, the gain Av becomes substantially equal. As a result, both output signals have the same amplitude, and both in-phase output signals are synthesized at the same ratio.

  In addition, the gain of the common-source transistor M1 of the cascode circuit is about 1 time, and the influence of the so-called Miller effect that lowers the high-frequency transmission characteristic of the transistor can be suppressed. CMRR (Common-Mode Rejection Ratio) characteristics can be improved.

  FIG. 2 is a diagram illustrating a second configuration example of the differential single-phase conversion circuit according to the embodiment of the present invention. In FIG. 2, the same elements as those in the first configuration example of FIG. In the second configuration example, the constant current source in the first configuration example is configured by a common source transistor M4. A gate bias voltage Vb1 is applied to the gate terminal of the common source transistor M4 via the load R3. The source terminal of the common source transistor M4 is grounded, and the drain terminal is connected to the source terminal of the common gate transistor M3. The same transistor is used for each of the transistors M1, M2, M3, and M4.

  Next, the operation of the second configuration example will be described.

  The operation of the second configuration example is the same as the operation of the first configuration example. That is, one input signal (positive phase signal) of the differential signal is input from the IN terminal to the gate terminal of the common source transistor M1 via the capacitor C1. The input signal from the IN terminal is a signal on which the gate bias voltage Vb1 is placed. The input signal from the IN terminal is output from the drain terminal of the grounded gate transistor M2 with the phase inverted by the common source transistor M1 (that is, in phase with the phase of the negative phase signal).

  On the other hand, the other input signal (reverse phase signal) of the differential signal is input from the INX terminal to the source terminal of the common-gate transistor M3 via the capacitor C2. The input signal from the INX terminal is a signal on which the gate bias voltage Vb2 is placed. This input signal is output from the drain terminal of the common-gate transistor M3. At this time, the phase of the input signal from the INX terminal is not inverted and remains in phase with the input signal.

  Therefore, the output signals from the drain terminals of the common-gate transistors M2 and M3 are combined in phase and output from the OUT terminal via the capacitor C3. In this way, the differential signal is converted into a single phase and output with a small loss.

  The same transistor is used for each of the transistors M1, M2, M3, and M4. By making the size of the transistor M4 equal to the size of the transistors M1, M2, and M3 and making the gate bias voltage applied to the transistor M4 the same as the gate bias voltage Vb1 of the transistor M1 so that equal current flows, The potential of each terminal of each transistor changes in the same manner with respect to temperature changes and process variations. For this reason, even when the temperature and process conditions change, the gain of the amplifier circuit on the IN terminal side and the amplifier circuit on the INX terminal side are almost equal, and are not affected by the temperature and process conditions, and further suppress degradation of the CMRR characteristics. be able to.

  FIG. 3 is a diagram illustrating the temperature characteristics of the CMRR characteristics of the differential single-phase conversion circuit of the first configuration example and the second configuration example. FIG. 3 shows the CMRR characteristics with respect to the temperature of the first configuration example (circuit configuration 1) and the second configuration example (circuit configuration 2) at a frequency of 3 GHz. Both circuit configurations are sufficiently high within the operating temperature range. CMRR characteristics are obtained.

  FIG. 4 is a diagram illustrating the frequency characteristics of the CMRR characteristics of the differential single-phase conversion circuit of the first configuration example and the second configuration example. FIG. 4 shows CMRR characteristics with respect to the frequency of the first configuration example (circuit configuration 1) and the second configuration example (circuit configuration 2) at a temperature of 30 ° C., and is data common to both circuit configurations. A sufficiently high CMRR characteristic can be obtained over a wide frequency band.

  In the above-described embodiment, the input signal (positive phase signal) on the IN terminal side is input to the common source transistor M1 of the cascode circuit, and the input signal (negative phase signal) on the INX terminal side is input to the grounded gate transistor M3. However, the input signal may be reversed. That is, the input signal (normal phase signal) on the IN terminal side may be input to the common gate transistor M3, and the input signal (negative phase signal) on the INX terminal side may be input to the common source transistor M1 of the cascode circuit. . By inverting the phase by inputting one of the positive phase signal and the negative phase signal to the common source transistor M1 of the cascode circuit, and amplifying both signals with the same transistor, Variations in process conditions are absorbed, and frequency characteristics can be improved by using a cascode circuit.

  M1 to M4: transistors, R1 to R3: loads, C1 to C3: capacitors

Claims (1)

A first amplifying circuit for amplifying a first differential signal of a pair of differential signals in a reverse phase relationship and outputting the first differential signal in phase;
A second amplifying circuit for amplifying a second differential signal of the differential signals and inverting and outputting the phase of the second differential signal;
An output terminal for synthesizing and outputting the output signal from the first amplifier circuit and the output signal from the second amplifier circuit;
The first amplifier circuit includes:
A first transistor having a first bias voltage applied to the gate;
A second transistor having a drain connected to the source of the first transistor, the first differential signal input to the drain, and a second bias voltage applied to the gate;
Have
The second amplifier circuit is:
A third transistor having the first bias voltage applied to the gate;
A fourth transistor having a drain connected to a source of the third transistor, a gate to which the second differential signal is input, and a gate to which the second bias voltage is applied;
Have
The first to fourth transistors have the same size,
The differential single-phase conversion circuit, wherein the amount of current flowing through each of the first to fourth transistors is equal .

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