JP5547741B2 - Page buffer program command and method for programming a page without re-entering data into the memory device - Google Patents

Description

  This application claims the priority of US Provisional Patent Application No. 61 / 108,507 (Document Number: SAND-01388US0) filed Oct. 25, 2008, which is incorporated herein by reference.

  The present invention relates to a technique for storing data.

  Semiconductor memories are becoming increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal information terminals, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable read only memory (EEPROM) and flash memory such as NAND memory are among the most popular non-volatile semiconductor memories.

  Nonvolatile memories formed from reversible resistance switching elements are also known. For example, US Patent Application Publication No. 2006/0250836, which is incorporated herein by reference and whose title is “Rewriteable Memory Cell Compiling A Diode And A Resistance-Switching Material”, is a metal oxide or metal nitride. A rewritable nonvolatile memory cell is described that includes a diode connected in series with a reversible resistance switching material. These reversible resistance switching materials are attracting attention for use in non-volatile memory arrays. One resistance state may correspond to, for example, data “0”, and the other resistance state corresponds to data “1”. Some of these materials may be in more than two stable resistance states. Such switching elements are often arranged in a plurality of layers in a so-called three-dimensional memory device. In addition, various types of non-volatile memory devices such as DRAM are known. Both rewritable memory and write-once memory are known.

  A memory device can be inserted or otherwise a card or other component that can be connected to a host / user device such as a host cell phone, digital camera, or other device Can take the form of In other cases, the memory device is permanently attached within the host device. Examples of memory devices having a removable media format are sold under various trade names such as COMPACTFLASH (registered trademark), SMARTMEDIA, SECURE DEGITAL, MEMORY STICK, and XD-PICTURE CARD. New generation memory card formats with small form factors are marketed under the trade names RS-MMC, MINISD AND MICROSD, and INTELLIGENT STICK.

  During the write process, a unit of data called a page is written to a specified location in the memory array. For example, the host device supplies data to be written to the memory device together with the address of the memory array to which the data is written. The memory device includes a circuit that writes data to a specified address. However, if the write operation fails due to, for example, a problem associated with the memory element or circuit associated with the specified address, the input / output operations performed as a result of attempting to resolve the failure are excessive. You may run out of bandwidth.

US Patent Application Publication No. 2006/0250836

  A technique for efficiently handling a write operation failure in a memory device is required.

  A technique for efficiently handling a write operation failure in a memory device is provided.

  In one embodiment, a method of operating a memory device includes: (a) receiving at least one page of data and a first address in the memory device from an external host; (b) at least one page of data. Storing data in the page buffer of the memory device; (c) attempting to write at least one page of data from the page buffer to the memory array of the memory device at the location specified by the first address. (D) determining that an attempt to write at least one page of data was unsuccessful; (e) notifying an external host that an attempt to write at least one page of data was unsuccessful; (F) receiving a second address in the memory device from an external host; and (g) at least the external host. Without re-transmitting the data of one page in the memory device comprises a page buffer, in the memory array at the location specified by the second address, it attempts to write the data of at least one page, the.

  In another embodiment, a method of operating a memory device includes: (a) receiving at least a first page of data and a first address in the memory device from an external host; (b) a memory array of the memory device. Storing at least a first page of data in a first storage location of the memory device, (c) receiving a first write command, (d) in response to the first write command, Attempting to write at least a first page of data from a first storage location to a memory array at a location specified by a first address; (e) from an external host to a second address in the memory device (F) at least a first page of data outside the memory array with at least a first page of data held in the first storage location. Reading the memory array at the location specified by the second address to retrieve the page of data to the second storage location in the memory device; (g) storing at least the second page of data in the second storage Supplying from the location to the external host, (h) determining that an attempt to write at least the first page of data was unsuccessful, and (i) at least an attempt to write the data of the first page was unsuccessful. (J) a second address is received from the external host by the memory device, and (k) the external host retransmits at least the first page of data to the memory device. Without writing at least the first page of data from the first memory location to the memory array at the location specified by the second address. To attempt that comprises.

  In another embodiment, a method for operating an external host of a memory device includes: (a) at least one page of data, a first address, and at least one first command from the external host to the memory device; (At least one first command stores at least one page of data in the page buffer of the memory device, and the memory of the memory device at the location specified by the first address from the page buffer) Tells the memory device to attempt to write at least one page of data to the array), (b) at least one page of data at the location specified by the first address on the external host from the memory device. Receiving a status communication indicating that the attempt to write was unsuccessful, and (c) few external hosts Transmitting the second address and at least the second command from the external host to the memory device in response to the status communication without retransmitting at least one page of data to the memory device (second The command includes: telling the memory device to attempt to write at least one page of data from the page buffer to the memory array at the location specified by the second address).

  In another embodiment, a memory device includes a memory array of non-volatile storage elements formed on a substrate, a data cache, a page buffer, an interface to an external host, and one or more control circuits. The one or more control circuits receive (a) at least one page of data and a first address from the external host, and (b) store at least one page of data in the page buffer. c) Attempt to write at least one page of data from the page buffer to the memory array at the location specified by the first address, and (d) Attempt to write at least one page of data was unsuccessful. (E) notify the external host that the attempt to write at least one page of data has failed, (f) receive a second address in the memory device from the external host, (g ) From the page buffer to the location specified by the second address without the external host retransmitting at least one page of data to the memory device The kicking memory array, attempting to write the data of at least one page.

  In another embodiment, a memory device includes a memory array having a non-volatile storage device formed on a substrate, a page buffer, a data cache, an interface to an external host, a memory array, a page buffer, a data cache, and an interface. One or more control circuits in communication with. The page buffer receives the first page data, and the one or more control circuits cause an attempt to write the first page data from the page buffer to the memory array. Further, the data cache receives second page data from the memory array that bypasses the page buffer, while the page buffer stores the first page data. The one or more control circuits cause the second page data to be supplied from the data cache to the external host. In addition, the one or more control circuits cause an attempt to rewrite the first page data from the page buffer to the memory array.

  Corresponding methods, systems, and computer or processor readable storage devices having executable code for performing the methods presented herein are also provided.

1 is a block diagram of one embodiment of a memory system. It is a figure showing the sequence of communication between a host and a memory device at the time of writing page data to a memory array. FIG. 2b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 2a. FIG. 2b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 2a. FIG. 2b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 2a. FIG. 2b is a diagram representing a process corresponding to the sequence of FIG. 2a. FIG. 2d represents a host-side process corresponding to the process of FIG. 2e. It is a figure showing the sequence of communication between a host and a memory device at the time of writing the data of a page to a memory array, and receiving the data of another page in a data cache in the meantime. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIG. 3a. FIG. 3b is a diagram representing a process corresponding to the sequence of FIG. 3a. It is a figure showing the sequence of communication between a host and a memory device at the time of writing page data copied from a memory array to a memory array. Fig. 4b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of Fig. 4a. Fig. 4b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of Fig. 4a. Fig. 4b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of Fig. 4a. Fig. 4b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of Fig. 4a. Fig. 4b is a diagram representing the movement of data in the data cache, page buffer and memory array corresponding to the sequence of Fig. 4a. FIG. 4b is a diagram representing a process corresponding to the sequence of FIG. 4a. FIG. 4 is a diagram representing a first part of a sequence of communication between a host and a memory device when data of a page copied from a memory array is written to the memory array while another page of data is received in the data cache. is there. Fig. 5b is a diagram representing a second part of the sequence of communications following the sequence of Fig. 5a. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents the movement of data in the data cache, page buffer and memory array corresponding to the sequence of FIGS. 5a and 5b. FIG. 6 represents a process corresponding to the sequence of FIGS. 5a and 5b. FIG. 2 is a diagram representing a circuit to which a data cache is connected to receive data directly from a memory array or host. FIG. 5 is a diagram representing a circuit to which a page buffer is connected to receive data directly from a memory array or host. FIG. 8 is a diagram representing the functions provided by the circuits of FIGS.

  A technique for efficiently handling a write operation failure in a memory device is provided.

  FIG. 1 is a block diagram illustrating an example of a memory system that implements the techniques described herein. The memory system, in one possible approach, is configured as a card or other package that includes a portion 101 formed in a die and a controller 130 that communicates with an external host 136 via an input / output circuit or interface 134. A memory device 100 that may be included. The controller 130 includes system control logic 132 that performs the functions described herein. The controller 130 may be incorporated within the portion 101, as shown in the figure, or may be off-chip.

  The memory array 102 may be a two-dimensional array of memory cells, sometimes referred to as storage elements, or a three-dimensional memory array. In one implementation, the memory array 102 is a monolithic three-dimensional array. A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate, such as a wafer, without an intervening substrate. The layers that form a memory level are deposited or grown directly on top of the existing one or more levels. On the other hand, stacked memories form memory levels on separate substrates and attach the memory levels on top of each other, as in US Pat. No. 5,915,167 by Leedy, whose title is “Three Dimensional Structure Memory”. It is built by that. The substrate may be thinned or removed from the memory level prior to bonding, but such a memory is true because the memory level is first formed on a separate substrate. It is not a monolithic 3D memory array.

  In another possible embodiment, the memory array is a two-dimensional array of non-volatile storage elements connected in series in a string, such as a NAND string. Each string extends in a column between the drain side select gate and the source side select gate. The word line communicates with the control gates of the storage elements in the row. A bit line communicates with the drain end of each string, and a sensing component is coupled to the bit line to determine whether the selected storage element is conductive or non-conductive.

  The array terminal lines of the memory array 102 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other directions may be implemented.

  Memory system 100 includes a row control circuit 120 whose output 108 is connected to a respective word line of memory array 102. The row control circuit 120 receives a group of row address signals and one or more various control signals from the system control logic 130, and typically includes a row decoder 122, array for both read and write operations. A circuit such as the terminal driver 124 and the block selection circuit 126 may be included. Memory system 100 further includes a column control circuit 110 in which input / output 106 is connected to each bit line of memory array 102. The column control circuit 110 receives a group of column address signals and one or more various control signals from the system control logic 132, and typically includes a column decoder 112, an array terminal receiver or driver 114, a block selection circuit 116, and the like. In addition, a read / write circuit and an input / output multiplexer may be included. System control logic 132 receives data and commands from host 136 and provides output data to the host. In other embodiments, the system control logic 132 receives data and commands from a separate controller circuit and provides output data to this controller circuit in communication with the host. The system control logic 132 may include one or more state machines, registers, and other control logic that controls the operation of the memory system 100 as described herein.

  The column control circuit 110 further includes a page buffer 111 and a data cache 113 which may be part of the sense amplifier. The page buffer is a storage location that stores data that is written to or read from the memory array, or may further maintain a write verification result during a write operation. One or more page buffers may be used. The page buffer can store data for one page or more. If the word line stores only one page of data, a page buffer that stores only one page of data is sufficient. When the word line stores data for a plurality of pages, it is possible to provide one or more page buffers capable of storing data for one page or more. The page buffer 111 is connected to a bit line and a power supply line voltage for read, verify, program (write), and erase operations. Regarding the write verification, after the word line of the storage element in the memory array is written with the data stored in the page buffer 111, the word line is read back, and the read data is stored in the page buffer. Compared with A mismatch indicates that a defect (or other type of error) exists on the word line and the data should be rewritten to another word line. For further information, see, for example, US Pat. No. 7,317,636, incorporated herein by reference.

  Another possible approach is that instead of using a separate read operation, the write / unwrite state of each memory cell determines whether the word line content matches the page buffer content on a word line basis. Detectable, during which a memory cell write is attempted. This writing detection technique is described in detail in US Pat. No. 6,574,145 whose title is “Memory device and method for sensing while programming a non-volatile memory cell”, which is incorporated herein by reference. It is described in.

  The data cache 113 holds data read by the page buffer during the read operation and data to be supplied to the page buffer during the write operation. As will be further described below, the external host remote from the die 101 sends commands and data to the memory device 100, and the data is a combination of a data cache and page buffer as a first storage location and a second storage location. Used to memorize. Advantageously, the data to be written to the memory array has a write attempt that fails at one address in the memory array and another address in the memory array without the host re-entering the data into the memory device. Can be retained in the memory device. In addition, this rewrite capability allows the additional data to be received in the memory device, during which the rewrite process takes place, the rewritten data is copied from one location to another in the memory array. Scenarios (and possibly modified) and additional data are received in the memory device, during which a rewrite process takes place, and the rewritten data is transferred from one location in the memory array to another. It can be implemented in various scenarios, such as a scenario that is copied (and possibly modified) to a location. This page-based rewrite capability can be distinguished from techniques performed by a memory device to modify a portion of a page, such as a few bytes, using error correction, for example.

  In one embodiment, all of the components depicted in FIG. 1 are located on a single integrated circuit. For example, the system control logic 132, the column control circuit 110, and the row control circuit 120 are formed on the surface of the substrate. Further, the memory array 102 may be a monolithic three-dimensional memory array formed on a substrate (ie, on the system control logic 132, the column control circuit 110, and the row control circuit 120). In some cases, a portion of the control circuit can be formed on the same layer as a portion of the memory array.

  Integrated circuits that incorporate memory arrays typically divide the array into a number of subarrays or blocks. Blocks can be further collected, for example, in bays that store 16, 32, or various numbers of blocks. As frequently used, a subarray is generally a continuous group of memory cells having decoders, drivers, sense amplifiers, and continuous word lines and bit lines that are not disconnected by input / output circuits. There are various reasons for this. For example, the signal delay (ie, RC delay) resulting from the resistance and capacitance of such lines down the word and bit lines can be very significant in large arrays. These RC delays may be reduced by dividing the large array into smaller subarrays so that the length of each word line and / or each bit line is reduced. As another example, the power associated with a group of memory cells may dictate an upper limit on the number of memory cells that may be accessed simultaneously during a given memory cycle. As a result, large memory arrays are often divided into smaller sub-arrays to reduce the number of memory cells that are accessed simultaneously. Nevertheless, for simplicity of explanation, an array consists of a decoder, driver, sense amplifier, and a contiguous group of memory cells having contiguous word lines and bit lines that are generally not disconnected by input / output circuits. Sometimes used as a synonym for subarray to indicate. An integrated circuit may include one or more memory arrays. In addition to the memory array 102, any of the controller 130 and other components may be considered a control circuit.

  As pointed out at the beginning, if a write operation fails, the resulting I / O operation uses up excessive bandwidth in terms of the processor cycles used in the memory device and the amount of data transferred to the memory device. Sometimes. For example, the page data may store 2 KB or 4 KB data, for example. Typically, if the write process fails, the memory device notifies the external host when the external host polls for status, and the host issues a new write command and retransmits the data for this page to the memory device. Respond by sending. The host may poll every page after writing to find out if each page was written successfully.

  Specifically, at a memory card or other media type interface, failed page write attempts should typically be remapped to another physical location in the memory array. The host typically checks the state after writing, writes the new address, and resumes the writing sequence by retransmitting the data for this page. This is particularly inefficient when writing is performed using a data cache that superimposes input and output with internal operations.

  The techniques presented herein allow a failed page to be rewritten to another physical location in the memory array while avoiding the need to re-enter page data. This technique allows the host / user to enter another physical address and write the data that was to be written to the new location and temporarily stored in the memory device. This technique can be used within a single page or when writing with a data cache, and can be used in a page copy operation (single page or cache) as well. This technique is compatible with, for example, a memory system that uses a limited command code vocabulary, so as not to be complex and needs to be compatible with standardization and various host devices. This significantly reduces the bandwidth penalty, especially during writes using the data cache mode. As a result, write speed performance can be significantly improved.

  In one embodiment, this technique introduces a new setup command to the interface protocol. By using this command and sending the new address, the host can write to the memory device without retransmitting the page data remaining in the page buffer. Only a slight modification of the existing write flow is required.

  FIG. 2a shows a communication sequence between the host and the memory device when data for one page is written to the memory array. In this scenario, one page of data is rewritten without entering other data, and the data is not copied from another location in the memory array. The time axis represents a sequence of messages transmitted from the host to the memory device and from the memory device to the host. A ready / busy status line for the memory device monitored by the host is also provided. If the state is ready, the host can communicate with the memory device, eg, to request the state of a previous write operation, or to supply user data and addresses to the memory device. If the status is busy, the host needs to wait for communication with the memory device if there is any need other than checking the ready / busy status of the memory device or resetting the memory device.

  Furthermore, the instants t0, t1, t2,. . . Are not evenly spaced in time but are intended to represent a sequence of events. In some embodiments, a page buffer write command (8Dh) is introduced to save I / O time if the write process fails on a page. When this is done, the host can rewrite the same page to another physical location in the memory array, eg, another word line, or another page on a word line that has multiple pages. Try. You can use this new command to write to another page in memory from the page buffer. User data communicated between the host and the memory device is in units of pages and is one or more pages at the same time.

  Note that exemplary command codes (eg, 8Dh, 10h, 70h) suitable for specific implementations including smart media non-volatile memory cards are pointed out. However, these command codes are presented for illustration only because these concepts are generally suitable for various media types and protocols.

  In a single page write process, at t0, a data input command (80h) is supplied from the host to the memory device, followed by an address N at t1, and then at one page or more to be written at t2. User data (data X) is supplied. The memory device holds the address N in the working memory and stores the data X in the data cache 113 (FIG. 1). The host supplies a write command (10h) at t3. Command 10h suggests that the additional page data does not follow the current page. During the response, the memory device copies the data X to the page buffer 111 (FIG. 1) and then starts a write operation to write the data X to the address N of the memory array. Data can be written directly from the cache to the memory array without being copied to the page buffer, or data can be read directly from the memory array to the cache without passing through the page buffer In addition, it is considered that a direct path can be provided between the data cache and the memory array. See FIGS. 6-8 for further information. In general, the write process is performed automatically by the memory device without receiving further instructions from the host to execute the write command. That is, the memory device executes writing independently from the host.

  At this point, the busy state is set. At t4, the ready state is set, and in response, the host supplies a state request command (70h). Specifically, if the ready / busy signal goes up to indicate that it is in a ready state, the host polls the memory device to find this state. The memory device responds, for example, using a failure status message at t5.

  In response, the host informs the memory device at t6 that a rewrite attempt should be made using data for which the write process has failed and that the address to perform this rewrite will follow. 8Dh). The new address N 'is supplied by the host at t7, and subsequently, a write command (10h) is supplied at t8. Thus, a first instance and a second instance of the first write command code are supplied at t3 and t8, respectively. However, since the instance at t8 is preceded by the second command code instance at t6, it can be seen that in the memory device, the instance at t8 is interpreted differently than the instance at t3.

  In some cases, at t7.1, changed data for data X, called data X ', is communicated by the host. For example, data X 'may include several bytes of data that replace bytes in data X while in the page buffer. In this manner, the page buffer data at a predetermined position can be changed before the page buffer data is written to the memory array. This can be useful in various scenarios, such as when page data depends on the address in the memory array to which the page data is written. The address N ′ may include a byte that specifies a portion of the data X that is to be replaced by the data X ′, and further a byte that specifies the memory array address N ′. The write command 8Dh is interpreted as directly writing the data X ′ to the page buffer.

  At t8, the memory device attempts to write data X (indicated by X (X ′)), possibly modified by X ′, to a location in the memory array identified by address N ′. The busy state is set. Specifically, a write operation occurs when the ready / busy signal falls to indicate a busy state. At t9, the ready state is set, and in response, the host supplies a second instance of the status request command (70h). Specifically, if the ready / busy signal rises to indicate a ready condition, the host polls the memory device to find this condition. The memory device responds with a success status message, for example, at t10.

  2b-c represent the movement of data within the data cache, page buffer, and memory array corresponding to the sequence of FIG. 2a. In FIG. 2b, the data X transmitted by the host 136 is stored in the data cache 113 at t2. In FIG. 2c, at t3, during the write process based on the write command, data X is transferred from the data cache 113 to the page buffer 111, and a failed attempt writes the data X from the page buffer 111 to the address N of the memory array 102. Done for. In FIG. 2d, at time t8, during the rewrite process based on the write command, the data X is written from the page buffer 111 to the address N 'of the memory array 102, resulting in success. In some cases, as pointed out, the host 136 can supply the data X ′ directly to the page buffer 111 to replace a portion of the data X, and the change written to the address N ′ of the memory array 102. Provided data X (X ′). See FIGS. 6-8 for further details of circuitry that provides direct communication capability between the host and page buffer.

  FIG. 2e represents a process corresponding to the sequence of FIG. 2a. Step 250 includes inputting user data, a first address, and a write command to the memory device. Step 252 includes attempting to write data using the first address. A decision step 254 determines whether the write attempt is successful. If the write attempt is successful, the process ends at step 264. Step 256 includes notifying the host that the write attempt is not successful. Step 257 includes inputting a rewrite command and a second address. Step 258 optionally includes entering replacement bytes to change the data in the page buffer. Step 259 inputs a write command. Step 260 includes attempting to write data using the second address. Step 262 indicates to the host that the rewrite attempt was successful. The process ends at step 264.

  FIG. 2f represents a host side process corresponding to the process of FIG. 2e. Step 270 includes sending user data, a first address, and a write command to the memory device. Step 272 includes receiving a notification that the write attempt has failed. Step 273 includes sending a rewrite command and a second address. Step 274 optionally includes sending a replacement byte to change the data present in the page buffer. Step 275 sends a write command. Step 276 includes receiving a notification that the write attempt was successful. The process ends at step 278.

  FIG. 3a represents the sequence of communication between the host and the memory device when writing one page of data to the memory array while receiving another page of data in the data cache. This sequence allows additional data to be received and stored at the memory device while a previous data write request is pending. During this cache write sequence, command 8Dh can be used after a state failure is detected for a page write. In this case, as in the case of the page that has been successfully written, copying from the data cache to the page buffer is not performed after the write operation. Command 8Dh can be issued followed by a new page address and a cache write command (eg, 15h). Command 15h suggests that additional page data is received and enters the data cache, while the current page is being written to the memory array.

  In this case, page data is written to the new address. Since the remapping is omitted, the cache sequence is resumed as it is. In order to resume the cache sequence, the command 80h and the page address for the subsequent page are reissued. In this case, the command 80h does not automatically set the byte in the data cache. In a normal write operation without failure, all preceding data in the cache is set to FF (11111111) before the user begins to input data. This is because the writing is successful and the old data is already stored in the memory. In case of failure, the data in the cache is still the data to be written. We want the data to stay in the cache and allow the user / host to decide whether to change the data or keep the data in the cache.

  A data input command (80h) is supplied at t0, followed by an address N at t1, and data (data X) to be written at t2 from the host to the memory device. The memory device maintains the address N in the working memory and stores the data X in the data cache 113 (FIG. 1). The host supplies a write command (15h) at t3 assuming that any previous page written was successfully written. In response, the memory device initiates a write operation to write data X to address N of the memory array. Note that this can be done simultaneously with additional communication between the host and the memory device.

  At t3, the busy state is set. At t4, the ready state is set, and in response, the host supplies a data input command, followed by address M at t5 and data Y at t6. Data Y is stored in a data cache. In this way, additional data is input to the memory device while a write attempt for data X is being made. This results in an efficient use of bandwidth. At t7, a write command for writing data Y is supplied, but the execution of this command must wait until the previous data is successfully written. This write command is later replaced by a write command for Y 'at t16. The host waits for a ready signal. At t8, the ready state is set and in response, the host polls the memory device to find the state of the data X write attempt. The memory device responds, for example, using a failure status message at t9. There is no data copy from the data cache to the page buffer, otherwise the failed page data will be invalidated. The memory interrupts, an 8D command that attempts to write the data in the page buffer, or ignores the failure, invalidates this data in the page buffer (which stored the failed page), and resumes the cache operation Therefore, it waits for one of the 80 commands to copy data from the data cache to the page buffer.

  In response to the failure status communication at t9, the host should attempt to rewrite with data that the write process has failed at t10 and that the address to perform this rewrite will follow. A command (8Dh) for informing the memory device is supplied. At t11, the new address N 'is supplied by the host, and at t12, the write command (15h) is followed.

  In some cases, at t11.1, modified data for data X, referred to as data X ′, is communicated by the host to modify a portion of data X in the page buffer, as described above. . Prior to rewriting the page buffer data to the memory array, the page buffer data can be changed in place. The address N ′ can include a byte that specifies a portion of the data X to be replaced by the data X ′ and a byte that specifies the memory array address N ′.

  The ready / busy signal is set to busy at t12, and then set to ready at t13. Again, the memory device sees that at t12, the write command is interpreted as a rewrite from the page buffer because it is preceded by the command at t10. At t12, an attempt is made to write data X or X (X ') to address N'.

  At this point, the host knows that a rewrite attempt should be performed by the memory device. The host has the option of supplying modified data Y 'to be stored in the memory device in place of previously transmitted data Y. Furthermore, a new address M ′ for storing data Y ′ can be selected. For example, the data Y may be changed based on a new address M 'at which a rewrite is attempted. Data Y may store information indicating the location of data X in the memory array, where data Y can be changed based on the new location of data X. For example, the data Y can store data indicating the address of the data X. This data should be changed. This can happen if it is unlikely. Further, in response to a page failure, various data may be required for subsequent page writes (various data may be further required for failed pages). An example of this is a “link list” structure where pages are placed in a chain even if the physical addresses of the pages are not consecutive. Instead, each page stores the address of the previous page of this page, so software or firmware can track the entire chain. If the location of data X changes from N to N ', data Y needs to update the address portion for X from N to N'. If data Y is not changed, data Y can remain in the data cache.

  The host selects to supply a data input command at t13, followed by a changed address M ′ at t14, changed data Y ′ at t15, and a new write command for data Y ′ at t16. And the ready / busy signal becomes busy. The host can start changing data Y to data Y 'if a failure condition is received at t9. However, in order to improve efficiency, the host issues an 8Dh command, an address N ′, and data X ′, and then issues the next 10h / 15h command before data Y is changed. The data Y can be changed in parallel with the data X or X (X ′) being written. If the host does not intend to change the data Y, the data cycle can be omitted. Furthermore, even if the user does not intend to change the address M, an address cycle is still required, in which case the host re-enters the address M.

  This write command waits for execution since writing of data X has not yet been approved. At t17, the data X or X (X ′) at address N ′ successfully finishes writing, the ready / busy signal rises to indicate this ready state, and the host finds this state. Polls memory devices. The memory device responds to the write status for data X or X (X ') using a success status message at t18. Subsequently, the data Y ′ is written into the memory array at the address M ′.

  The host can issue another data entry command (not shown) for the next page of data to be written to the memory array, and the cache write process continues.

  Note that if the host chooses to ignore the failure notification at t9, the rewrite command at t10 can be omitted. In this case, after the command 15h is issued at t16, copying from the data cache to the page buffer is performed.

  3b-h represent the movement of data in the data cache, page buffer, and memory array corresponding to the sequence of FIG. 3a. In FIG. 3b, data X is sent by the host 136 and stored in the data cache 113 at t2. In FIG. 3 c, during the write process based on the write command at t 3, data X is transferred from the data cache 113 to the page buffer 111 and begins to be written from the page buffer 111 to the address N of the memory array 102. In FIG. 3d, during the write process, data Y is received at the cache at t6 and the write attempt for data X fails. In FIG. 3e, data Y is in the data cache and data X is in the page buffer (t8). In FIG. 3f, the data X starts to be rewritten to the address N ′ based on the write command at t12. In some cases, as described above, the host 136 replaces a portion of the data X and pages the data X ′ to provide modified data X (X ′) that is written to the address ′ of the memory array 102. The buffer 111 can be supplied directly. In FIG. 3g, the rewriting process continues and the trial is successful. In parallel, at t15, the changed data Y ′ is stored in the data cache. In FIG. 3h, data Y 'is transferred from the data cache to the page buffer (not shown after t18).

  FIG. 3i represents a process corresponding to the sequence of FIG. 3a. Step 350 includes inputting first user data, a first address, and a write command to the memory device. Step 352 includes attempting to write the first data using the first address. Step 354 includes inputting second data, a second address, and a write command to the memory device. A decision step 356 determines whether the first data write attempt is successful. If the write attempt is successful, the process continues at step 370 as data cache flow continues. Step 358 includes notifying the host that the first data write attempt was unsuccessful.

  Step 360 includes inputting a rewrite command and a third address. Step 362 optionally includes sending a replacement byte to change the first data (X) in the page buffer. Step 363 inputs a write command. Step 364 includes attempting to write the first data (possibly changed) using the third address. Note that the host can change the second data at this point to provide data Y '. Steps 362-364 can be omitted if the user chooses to do the above. Step 366 includes, for example, inputting changed second data that can change only a few bytes, a fourth address, and a write command to the memory device. Step 368 includes notifying the host that the first data rewrite attempt was successful. After step 366, the host waits for a ready / busy signal that remains low (busy) until the writing of data X or X (X ') is complete. The process continues at step 370.

  FIG. 4a represents a sequence of communication between the host and the memory device when writing page data copied from the memory array to the memory array. This sequence allows modified data, possibly modified, from the memory array to be written back to the memory array. During the page copy sequence, the command 8Dh and the new page address and a write command (eg, 10h) can be continued after the failure condition. As a result, the same page of data is written to the new page location.

  The read data input command (00h) is supplied from the host to the memory device at t0, after which the address N is continued at t1, and the read command (30h) is continued at t2, in response to the address N The data X located at is read out. At t2, the ready / busy signal becomes busy, and the page data at address N is loaded into the page buffer and then copied to the cache. When the ready / busy signal becomes ready, at time t3, data X is output from the data cache to the host. Data X may be toggled out.

  The host has the option of changing data X before it is copied / written back to the memory array. The host supplies a copy data input command (8Ch) at t4, and subsequently supplies changed data at t5, that is, data X 'at t6. At t7, an attempt is made to write the data X ′ to the address M in response to the write command (10h). Specifically, at t7, the ready / busy signal becomes busy and data X 'is copied from the data cache to the page buffer and then written to the physical location designated by M in the memory array. At t8, the ready / busy signal rises to indicate a ready condition and the host polls the memory device to find this condition. For example, at t9, the memory device responds to the write status for data X 'using a failure status message.

  In response to the failure status communication, the host may later report that at t10 the write process has failed and a rewrite attempt has been made using data that is still in the page buffer and the address at which this rewrite is to be performed. A command (8Dh) is supplied to inform the memory device that it will continue. The new address M ′ is supplied by the host at t11, and subsequently, a write command (10h) is supplied at t12. Similarly, in this case, the memory device is preceded by the command at t10, so that it can be understood that the write command at t12 is interpreted as rewriting from the page buffer. In some cases, at t11.1, the modified data of data X ′ called data X ″ is communicated by the host to modify a portion of the data X ′ in the page buffer, as already considered. Is done. In this way, the page buffer data can be changed at a predetermined location before the page buffer data is rewritten to the memory array. The address M ′ can include a byte that specifies a portion of the data X to be replaced by the data X ′ and a byte that specifies the memory array address M ′.

  At t12, the ready / busy signal is busy and the data X ′ or X ′ (X ″) in the page buffer has been successfully written to the physical location specified by M ′ in the memory array. To do. At t13, the ready / busy signal rises to indicate a ready state, and in response, a state request command related to an attempted write of data X ′ or X ′ (X ″) to address M ′. Supplied by the host. The success status message is supplied to the host by the memory device at t14.

  4b-f represent the movement of data within the data cache, page buffer, and memory array corresponding to the sequence of FIG. 4a. In FIG. 4b, data X is read based on the read command at t2. Data X is loaded from the memory array to the page buffer and from the page buffer to the data cache. In FIG. 4c, the data X is output to the host 136 at t3. A copy of the data X can remain in the page buffer 111. In FIG. 4d, changed data, ie, data X 'is received by the data cache at t6. In FIG. 4e, at t7, data X 'is copied to the page buffer in response to the write command, and an attempt is made to write this data X' to the memory array at address M, which fails. In FIG. 4f, at time t12, the data X ′ is successfully written to the memory array at the alternative address M ′ in response to the write command. In some cases, as indicated, the host 136 replaces a portion of the data X ′ and provides the data X ″ directly to the page buffer 111 to provide modified data X ′ (X ″). This data X ″ is written to the address M ′ of the memory array 102.

  FIG. 4g represents a process corresponding to the sequence of FIG. 4a. Step 450 includes inputting a first read address and a read command to the memory device. Step 452 includes reading the first data at the first read address and outputting the data to the host. In step 454, the host changes the first data, as the case may be. Step 456 includes inputting a first write address, changed data, and a write command to the memory device. Step 458 includes attempting to write the modified data using the first write address. If the attempted write is successful at decision step 460, the process ends at step 468.

  If the write attempted at decision step 460 is not successful, the host is notified at step 462. Step 463 includes inputting a rewrite command and a second write address. Step 464 optionally includes sending a replacement byte to further modify the modified data (X ') in the page buffer. Step 465 inputs a write command. Step 466 includes attempting to write modified data X ′ or X ′ (X ″) using the second write address (and possibly further modified). The process ends at step 468.

  FIG. 5a shows the first part of the sequence of communication between the host and the memory device when the page data copied from the memory array is written to the memory array while another page of data is received in the data cache. Represent. This sequence allows data to be copied from the memory array, possibly modified, and written back to the memory array, during which additional data can be received.

  In a page copy for a data cache sequence, if the page write fails, the data in the data cache will not be copied to the page buffer as in the case of the cache write. In this case, the host can use the command 8Dh to write the failed page to another address or to ignore the failed page and continue the sequence. In order to write the failed page to another address, the host sends a command 8Dh followed by a new page address and a cache write command (eg, 15h). To ignore the failed page, the host proceeds directly to the next step and resumes the cache copy sequence, followed by command 8Ch, followed by the address of the subsequent page (change allowed), and possibly data bytes. The change and then the cache write command intended for the subsequent page is entered into the memory device.

  At t0, a read data input command (00h) is supplied from the host to the memory device. Subsequently, an address N is supplied at t1, and a read command (30h) is supplied at t2, and the address N Thus, data X is read out. Specifically, at t2, the ready / busy signal becomes busy, data X is loaded into the page buffer, and then copied to the data cache. Data X is output to the host at t3 when the ready / busy signal is ready. The host has the option of changing data X before it is copied / written back to the memory array. At t4, the host supplies a copy data input command (8Ch). Subsequently, the host supplies address M at t5 and changed data, that is, data X 'at t6. At t7, an attempt is made to write the data X 'at the address M in response to the write command (15h). Specifically, the ready / busy signal goes busy and data X 'is copied from the data cache to the page buffer and then written to location M in the memory array. At t8, the ready / busy signal rises to indicate a ready state, and the host starts another read operation for the additional data X1. An attempt is made to write data X 'in the page buffer to address M in the array.

  A read data input command (00h) for another page to be read is supplied from the host to the memory device at t8, and subsequently, the read command (3Ah) is supplied at address N1 and t10 at t9. Accordingly, since the ready / busy signal is in a busy state, the data X1 at the address N1 is read out. Since data X1 is loaded directly into the data cache and output to the host at t11, data X 'can remain in the page buffer for subsequent rewrite attempts. See FIGS. 6-8 for further information. The host has the option to change the data X1 before the data X1 is copied / written back to the memory array. At t12, the host supplies a copy data input command (8Ch). Subsequently, at t13, the host supplies new address M1 and t14 of changed page data, that is, data X1 '. The write command (15h) at t15 for writing the data X1 'at the address M1 needs to be waited because the attempt to write the preceding data X' to the address M has not yet been completed. This write command is later replaced by a write command to the address M1 'at t24.

  FIG. 5b represents the second part of the sequence of communications that follows the sequence of FIG. 5a. At t16, the ready / busy signal rises to indicate a ready state, and in response, the host polls the memory device to find the state of data X 'on the address M write attempt. For example, at t17, the memory device responds to a failure status message that identifies a failure to write X 'to M. Due to this write failure, there is no copy of data X1 'from the data cache to the page buffer. In response to the failed status communication, the host performs the rewrite at t18 that the write process has failed and a rewrite attempt should still be made using the data still in the page buffer. A command (8Dh) is provided to signal the memory device that the address to be followed follows. At t19, a new address M 'is supplied by the host, and subsequently, at t20, a write command (15h) is supplied. Similarly, in this case, since the command at t18 precedes, the memory device understands that the write command at t20 is interpreted as rewrite from the page buffer. At t20, the ready / busy signal becomes busy, and the data X 'in the page buffer begins to be written to the memory array. In some cases, at t19.1, the modified data of data X ′, referred to as data X ″, is considered by the host to modify a portion of the data X ′ present in the page buffer, as discussed. Communicated by In this way, the page buffer data can be changed in place before the page buffer data is rewritten to the memory array. The address M ′ may include a byte that specifies a portion of the data X ′ to be replaced by the data X ″ and a byte that specifies the memory array address M ′.

  At this point, the changed data X1 ″ is supplied to the original memory device. The host can change the data X1 'to data X1 ". This is done immediately after a retry is initiated and the memory is ready. Specifically, at t21, a copy data input command is supplied, and subsequently, a new address M1 'at t22, data 1X' 'at t23, and a write command at t24. If the host does not intend to change the data X1 'to X1 ", the data cycle can be omitted. Furthermore, if the user does not intend to change the address M1, an address cycle is still required, in which case the host re-enters the address M1.

  The write command at t24 for writing the data X1 ″ to the address M1 ′ needs to wait because the previous write attempt of the data X ′ or X ′ (X ″) has not yet been completed. The writing of data X ′ or X ′ (X ″) to M ′ was provided to the host whose status request command was involved in attempting to write data X ′ or X ′ (X ″) to address M ′. In this case, the process ends safely by t25. The data X1 ″ is copied from the data cache to the page buffer. At t26, a success status message is provided by the memory device to the host and the sequence continues.

  Note that the rewrite command at t18 can be omitted if the host chooses to ignore the failure notification at t17. In this case, copying (transfer from the data cache to the page buffer) can be performed after the command 15h is issued at t20.

  FIGS. 5c-l represent the movement of data in the data cache, page buffer, and memory array corresponding to the sequence of FIGS. 5a and 5b. In FIG. 5 c, reading data X from address N includes loading data into page buffer 111 and copying to data cache 113 at t 2. In FIG. 5d, changed data, ie, data X 'is received from the host 136 into the data cache at t6. In FIG. 5e, at time t7, based on the write command, the data X ′ is supplied from the page cache 113 to the page buffer 111, and the data X is invalidated. In FIG. 5f, similarly, at t7, based on the write command, writing from the page buffer 111 to the memory array at the address M is attempted and fails. In FIG. 5g, at time t8, based on the read command, data X1 is read directly from the memory array to the data cache 113 at address N1, so that data X 'remains in the page buffer for subsequent rewrite attempts. In FIG. 5h, data X1 is output from the data cache.

  In FIG. 5 i, the changed data X <b> 1 ′ is received by the data cache 113 at t <b> 14. In FIG. 5j, data X1 'is in the data cache and data X' is in the page buffer. In FIG. 5k, based on the write command at t20, a write attempt is made for data X 'at address M'. In some cases, as indicated, the host 136 replaces a portion of the data X ′ and provides the data X ″ directly to the page buffer 111 to provide modified data X ′ (X ″). The modified data is written to the address M ′ of the memory array 102. In FIG. 5L, at t23, the additional data X1 ″ is received by the data cache in parallel with the rewriting of the data X ′ or X ′ (X ″). In this way, we have at least partially overlapping operations where data is read from the memory array, modified in the form of data X and data X1, and stored in the original memory array. Can be made.

  FIG. 5m represents a process corresponding to the sequence of FIGS. 5a and 5b. Step 550 includes inputting a first read address and a read command to the memory device. Step 552 includes reading the first data at the first read address and outputting the first data to the host. In step 554, the host optionally modifies the first data to provide X '. Step 556 includes inputting a first write address, first changed data, and a write command to the memory device. Step 558 includes attempting to write the first modified data at the first write address. Step 560 includes inputting a second read address and read command to the memory device. Step 562 includes reading the second data at the second read address and outputting the second data to the host. In step 564, the host changes the second data, as the case may be. Step 566 includes inputting a second write address, second modified data, and a write command to the memory device. Step 568 includes notifying the host that an attempt to write the first modified data to the first write address has failed. Step 569 includes inputting a rewrite command followed by a third write address. Step 570 optionally includes sending a replacement byte to further modify the first modified data (X ') in the page buffer. Step 571 inputs a write command. Step 572 includes attempting to write the first modified data (which may be further modified in some cases) at a third write address. At step 574, the host optionally further modifies the second data to provide X1 '. Step 576 includes inputting a fourth write address, further modified second data, and a write command to the memory device. At step 578, the attempt to write the first modified data to the third write address is successful, and at step 580, the host is notified accordingly.

  As the above discussion suggests, command 8Dh is used after page write fails. To use this feature, the host checks the written state each time a page is written. If the page write fails during the cache operation, copying from the data cache to the page buffer is stopped. The host then uses (a) command 8Dh sequence (8Dh → new address → (optional) new data → (cache) write command) to remap the data in the data buffer, or ( b) It is possible to omit the remapping and do nothing. In either case, the host can continue as follows. First, in the single page mode, when (a) is selected, a ready / busy signal is waited because the ready state is entered again. Second, in cache mode, the command sequence for subsequent pages (80h-address-data-write command) is repeated to resume the cache flow. In this case, the address and data can be changed from the original flow. Thereafter, it waits for the ready / busy signal to become ready again. After this step, the host should check the status if (a) is selected. If the status is another failure, the host can choose to select another page location by using the command 8Dh again, or omit the remapping, similar to the previous float. The retry limit (the maximum number of remappings allowed) can be used to avoid infinite loops.

  FIG. 6 represents a circuit 600 to which a data cache 620 is connected to receive data directly from a memory array or host. Data can be output from the data cache to the memory array or host as well as using appropriate circuitry via a “data output” path. As already pointed out, data can be loaded directly from the memory array to the data cache and output to the host, bypassing the page buffer, so that other data can be page buffered for subsequent rewrite attempts. Can stay inside. This further allows the host to change the failed page located in the page buffer by bypassing the data cache and accessing the page buffer directly. This should be changed in the page buffer using command 8Dh and the replacement byte followed (eg, by providing the byte address of the starting byte to be replaced) as discussed previously. It can be implemented using an address that suggests a data byte, a memory array address to which the modified page buffer data is written, and a replacement data bit that follows.

  In general, using the circuitry presented herein, the data cache can bypass the page buffer and connect directly to the memory array or host, and the page buffer can bypass the data cache. And can be directly connected to a memory array or a host. The presented implementation is one of various possibilities.

  The left half of the circuit interfaces with the memory array and the right half of the circuit interfaces with the host / user. The circuit includes a data cache 620, AND gates 608, 610, 632 and 634, inverters 606 and 640, nMOS transistors 613, 623, 633 and 643, and tri-state buffers 612, 614, 626 and 630. Including. Input signal IN is provided to the output of buffer 612 in communication with line 618 at the gate of transistor 613. Inverted signal XIN is provided to the outputs of buffers 614 and 630 at the gate of transistor 623 on line 631 communicating with line 627. Transistors 633 and 643 receive signal ENB5 on line 629 at their gates and are connected to transistors 613 and 623, respectively. The enable signal is provided by one or more control circuits.

  Tri-state buffers have output ports that can take conventional zero and one levels in addition to high impedance or floating states that effectively remove the buffer from the circuit. Enable signal ENB1 on line 616 controls buffers 612 and 614, and enable signal ENB2 on line 628 controls buffers 626 and 630. Further, on the memory array side, the control signal C is supplied to the line 602, and data from the memory array, that is, data 1 is supplied to the line 604. On the host side, a control signal C is provided on line 636 and data from the user, ie data 2 is provided on line 638. Line 618 connects the output of buffer 626 to the gate of transistor 613. Data XQ on line 622 is the inverse of data Q on line 624. Data cache 620 and transistors 613 and 623 form a latch.

  To write data from the memory array to the data cache, we set C = 1, ENB1 = 1, ENB2 = 0 and ENB5 = 1. Setting C = 1 causes AND gate 608 to pass data 1 through buffer 612, setting ENB1 = 1 causes buffer 612 to pass data 1, and setting ENB2 = 0 causes buffer 626 to pass. Floats. When ENB5 = 1 is set, data can be written into the data cache 620.

  In order to write data from the host to the data cache, when we set C = 1, the AND gate 632 passes the data 2 to the buffer 626, and when ENB1 = 0 is set, the buffer 612 floats. , ENB2 = 1 is set, the buffer 626 allows data 2 to pass. Similarly, as described above, ENB5 = 1.

  When writing to the page buffer, the data cache can be stopped by setting ENB1 = 0, ENB2 = 0, and ENB5 = 0. Setting ENB5 = 0 prevents floating inputs to transistors 613 and 623 from tampering with data in the data cache.

  FIG. 7 represents a circuit 700 to which a page buffer 720 is connected to receive data directly from a memory array or host. Data can also be output from the page buffer to the memory array or host using appropriate circuitry via a “data output” path. Components 702, 704, 706, 708, 710, 712, 713, 714, 716, 718, 722, 723, 724, 726, 727, 728, 729, 730, 731, 732, 733, 734, 736, 738, 740 And 743 are components 602, 604, 606, 608, 610, 612, 613, 614, 616, 618, 622, 623, 624, 626, 627, 628, 629, 630, 631, 632 in FIG. , 633, 634, 636, 638, 640 and 643. Additionally, enable signals ENB3 and ENB4 are provided to buffers 712/714 and 726/730, respectively, by one or more control circuits, and ENB6 is provided on line 729. Page buffer 720 and transistors 713 and 723 form a latch.

  In order to write data from the memory array to the page buffer, when the inventors set D = 1, the AND gate 708 passes the data 1 to the buffer 712, and when ENB3 = 1 is set, the buffer 712 When 1 is passed and ENB4 = 0 is set, the buffer 726 floats. Further, when ENB6 = 1 is set, data can be written to the page buffer 720.

  In order to write data from the host to the page buffer, when the inventors set D = 1, the AND gate 732 passes the data 2 to the buffer 726, and when ENB3 = 0 is set, the buffer 712 floats. , ENB4 = 1 is set, the buffer 726 can pass the data 2. Similarly, as described above, ENB6 = 1.

  When writing to the data cache, the page buffer can be stopped by setting ENB3 = 0, ENB4 = 0, and ENB6 = 0. Setting ENB6 = 0 prevents floating inputs to transistors 713 and 723 from tampering with data in the page buffer.

  FIG. 8 represents the functionality provided by the circuits of FIGS. The page buffer 111 and the host 136 can exchange data directly, while the page buffer 111 communicates more directly with the memory array. The page buffer and data cache 113 can further communicate. Furthermore, the data cache 113 and the memory array 102 can exchange data directly, while the data cache 113 further communicates with the host 136. As indicated, this allows the ability to independently write data to and read data from the data cache and page buffer.

  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above disclosure. The described embodiments best illustrate the principles of the invention and the practical application of the invention, so that those skilled in the art will be familiar with the various embodiments and suitable for the particular use discussed. Selected to make the best use of the invention along with various modifications. It is intended that the scope of the invention be defined by the appended claims.

Claims (15)

A method of operating a memory device, comprising:
Receiving from the external host (136) at least one page of data (X) and a first address (N) in the memory device (100);
Storing at least one page of data (X) in a data cache (113) of the memory device;
Transferring at least one page of data (X) from the data cache (113) to a page buffer (111) of the memory device;
Attempting to write the data (X) for at least one page from the page buffer (111) to the memory array (102) of the memory device at the location specified by the first address (N) . ,
Between attempting to write the at least one page of data (X) from the page buffer (111) to the memory array (102) at the location specified by the first address (N). Receiving at least an additional page of data (Y) comprising data indicating the first address (N) from the external host (136);
Storing the at least one additional page of data (Y) in a data cache (113) of the memory device;
Determining that the attempt to write the data (X) for the at least one page was unsuccessful;
Notifying the external host (136) that the attempt to write the data (X) for the at least one page was unsuccessful;
Receiving a second address (N ′) in the memory device from the external host (136) ;
Receiving at least one additional page of data change (Y ′) from the external host (136), wherein the at least one additional page of data change (Y ′) is Receiving, comprising data indicating the second address (N ′),
Storing the change (Y ′) of the at least one additional page of data in the data cache (113) instead of the at least one additional page of data (Y), and the external The host (136) from the page buffer (111) at the location specified by the second address (N ′) without retransmitting the data (X) for the at least one page to the memory device. Attempting to write at least one page of data (X) to the memory array (102) ;
A method comprising: Receiving a replacement byte in the memory device from the external host;
Receiving an indication of a portion of the at least one page of data in the page buffer to be replaced by the replacement byte; and
Before attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the second address, based on the indicator, the at least in the page buffer The method of claim 1, further comprising replacing the portion of the data for one page with the replacement byte. Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address is in response to receiving an initial write command from the external host. Executed,
The at least one page of data from the page buffer to the memory array at the location specified by the second address without the external host retransmitting the at least one page of data to the memory device. Is executed in response to receiving a page buffer write command, the subsequent second address (N ′), and a subsequent additional write command from the external host. And
The page buffer write command informs the memory device that a rewrite attempt is to be performed using data in the page buffer and that an address to which the rewrite attempt is to be made follows. Item 3. The method according to Item 1 or 2. The memory device does not receive a command other than the page buffer write command and the additional write command from the external host, and transfers the memory device to the memory array at the location specified by the second address from the page buffer. 4. The method of claim 3 , automatically attempting to write the at least one page of data. Before SL transfer the executed in response to receiving an initial write command from the external host,
Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address is performed in response to receiving the initial write command. The method according to any one of claims 1 to 4. Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address comprises performing a write process from the external host. Executed in response to receiving a first instance of a first command code informing a memory device;
Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the second address may include an instance of a second command code from the external host Executed in response to receiving the subsequent second address and the subsequent second instance of the first command code;
The instance of the second command code informs the memory device that a new address is being provided for a rewrite attempt using data in the page buffer;
6. The method of any one of claims 1-5, wherein the second instance of the first command code informs the memory device to perform the write process. Receiving an address (M) from the external host to store the at least one additional page of data; and
Receiving a new address (M ′) from the external host to store the change in the at least one additional page of data;
The method according to claim 1, wherein the change of the at least one additional page of data is based on the new address (M ′) . The method according to any one of claims 1 to 7, wherein the at least one page of data and the at least one additional page of data comprise pages arranged in a chain .   The at least one page of data includes data read from the memory array and changed by the external host based on the second address before being received by the memory device The method according to any one of claims 1 to 8. A memory device,
Means for receiving from the external host (136) at least one page of data (X) and a first address (N) in the memory device (100);
Means for storing at least one page of data (X) in a data cache (113) of the memory device;
Means for transferring at least one page of data (X) from the data cache (113) to a page buffer (111) of the memory device;
Means for attempting to write the data (X) for at least one page from the page buffer (111) to the memory array (102) of the memory device at the location specified by the first address (N) ,
Between attempting to write the at least one page of data (X) from the page buffer (111) to the memory array (102) at the location specified by the first address (N). Means for receiving at least an additional page of data (Y) comprising data indicating the first address (N) from the external host (136);
Means for storing the at least one additional page of data (Y) in a data cache (113) of the memory device;
Means for determining that an attempt to write at least one page of data (X) was unsuccessful;
Means for notifying the external host (136) that an attempt to write the data (X) for at least one page has failed;
Means for receiving a second address (N ′) in the memory device from the external host (136) ;
Means for receiving at least an additional page of data change (Y ′) from the external host (136), wherein the at least an additional page of data change (Y ′) is Said means for receiving comprising data indicating said second address (N '),
Means for storing the change (Y ′) of the at least one additional page of data in the data cache (113) in place of the at least one additional page of data (Y), and the external The host (136) from the page buffer (111) at the location specified by the second address (N ′ ) without retransmitting the data (X) for the at least one page to the memory device. Means for attempting to write the data (X) for at least one page to the memory array (102) ;
A memory device. Means for receiving a replacement byte in the memory device from the external host;
Means for receiving an indication of the portion of the at least one page of data in the page buffer that is to be replaced by the replacement byte; and
Before attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the second address, based on the indicator, the at least in the page buffer The memory device according to claim 10, further comprising means for replacing the portion of the data for one page with the replacement byte. Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address is in response to receiving an initial write command from the external host. Executed,
The at least one page of data from the page buffer to the memory array at the location specified by the second address without the external host retransmitting the at least one page of data to the memory device. Is executed in response to receiving a page buffer write command, the subsequent second address (N ′), and a subsequent additional write command from the external host. And
The page buffer write command informs the memory device that a rewrite attempt is to be performed using data in the page buffer and that an address to which the rewrite attempt is to be made follows. Item 12. The memory device according to Item 10 or 11. The memory device does not receive a command other than the page buffer write command and the additional write command from the external host, and transfers the memory device to the memory array at the location specified by the second address from the page buffer. 13. The memory device according to claim 12, wherein the memory device automatically attempts to write the data for at least one page. Before SL transfer the executed in response to receiving an initial write command from the external host,
Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address is performed in response to receiving the initial write command. The memory device according to any one of claims 10 to 13. Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the first address comprises performing a write process from the external host. Executed in response to receiving a first instance of a first command code informing a memory device;
Attempting to write the at least one page of data from the page buffer to the memory array at the location specified by the second address may include an instance of a second command code from the external host Executed in response to receiving the subsequent second address and the subsequent second instance of the first command code;
The instance of the second command code informs the memory device that a new address is being provided for a rewrite attempt using data in the page buffer;
15. A memory device according to any one of claims 10 to 14, wherein the second instance of the first command code informs the memory device that the write process is to be executed.

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