JP2007310680A - Nonvolatile storage device and its data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for copy processing of data between flash memories, in a nonvolatile storage device having a plurality of flash memories. <P>SOLUTION: This nonvolatile storage device shares a command/data bus 130 between a controller 120 and a nonvolatile memory 110A and a command/data bus 130 between the controller 120 and a nonvolatile memory 110B. In the copy processing of reading data from the nonvolatile memory 110A and writing the data into the nonvolatile memory 110B, the controller 120 directly transfers the data read from the nonvolatile memory 110A to the nonvolatile memory 110B via the command/data bus 130 without transferring it to the controller 120. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a non-volatile storage device using a so-called multi-chip package as a storage medium, in which a plurality of semiconductor memory chips are integrated and housed in a single package, and a data transfer method thereof, and more particularly, between semiconductor memory chips The present invention relates to a nonvolatile storage device that can perform copy processing at high speed by transferring data at high speed.

  In recent years, a memory card equipped with a non-volatile memory has been expanded as a memory card for digital cameras and mobile phones. In digital cameras, higher image quality and high-speed recording are demands on the market, and in order to meet these demands, larger capacity memory cards and memory cards that operate at higher speeds are desired.

  In order to mount a non-volatile memory having as large a capacity as possible in a small memory card, there is a method such as MCP (multi-chip package) in which a plurality of chips are enclosed in one package. On the other hand, in order to operate a memory card at high speed, some NAND type flash memories, which are typical nonvolatile memories, have a function of copying data in a flash memory chip.

  Hereinafter, the internal configuration and basic operation of a memory card using a flash memory will be described with reference to FIGS.

  FIG. 11 is a block diagram showing a configuration of a general memory card. In FIG. 11, reference numeral 100 denotes a memory card, and reference numeral 200 denotes a host that writes data to and reads data from the memory card 100. The memory card 100 performs I / F between the flash memory 110 that is a kind of nonvolatile memory that stores data sent from the host 200 and the host 200, writes data to the flash memory 110, and flash memory The controller 120 is configured to control reading of data from 110.

  FIG. 12 is a diagram showing details of signal lines between the flash memory 110 and the controller 120 in the memory card 100. Signals from the controller 120 to the flash memory 110 include a chip enable signal indicating the selected / unselected state of the flash memory 110, a command latch enable signal indicating a command input cycle, and an address latch indicating an address input cycle. An enable signal, a command at the time of command input, an address at the time of address input, and a command / data bus which is a bus for transferring data at the time of data writing / reading, command input, address input and data transfer at the time of data transfer There are a write enable signal that is a clock, a read enable signal that is a clock for performing read data transfer, and a write protect signal that prohibits writing and erasing operations on the flash memory 110. On the other hand, a signal from the flash memory 110 to the controller 120 includes a ready / busy signal indicating that a write or erase operation is being performed.

  FIG. 13 is a timing chart of the command input cycle. The controller 120 sets the chip enable signal to “L” (active), sets the command latch enable signal to “H” (active), and outputs a valid command to the command / data bus, and is a command input clock. The command is input by toggling the write enable signal from “H” → “L” → “H” and applying the rising edge of the write enable signal to the flash memory 110.

  FIG. 14 is a timing chart of the address input cycle. The controller 120 is an address input clock in a state where the chip enable signal is set to “L” (active) and the address latch enable signal is set to “H” (active), and a valid address is output to the command / data bus. The address is input by toggling the write enable signal from “H” → “L” → “H” and applying the rising edge of the write enable signal to the flash memory 110.

  On the other hand, FIG. 15 is a timing chart of write data transfer. The controller 120 sets the chip enable signal to “L” (active), outputs valid data to the command / data bus, and changes the write enable signal that is a clock for writing data transfer from “H” to “L” to “H”. And the data is transferred to the flash memory 110 by applying the rising edge of the write enable signal to the flash memory 110. Although not shown in the timing chart, the command latch enable signal and the address latch enable signal are both “L” (inactive).

  FIG. 16 is a timing chart of read data transfer. The controller 120 sets the chip enable signal to “L” (active) and outputs a valid data to the command / data bus, and changes the read enable signal that is a clock for reading data transfer from “H” to “L” to “H”. Toggle "" and apply the "L" state of the read enable signal to the flash memory 110 to request data output from the flash memory 110. The flash memory 110 receives the “L” state of the read enable signal and outputs read data to the command / data bus after a certain delay. Although not shown in the timing chart, the command latch enable signal and the address latch enable signal are both “L” (inactive).

  Next, FIG. 17A is a diagram simply showing the internal configuration of the flash memory 110. In the figure, reference numeral 111 denotes a memory cell array, which is composed of a plurality of physical blocks 114. The physical block 114 is a data erasing unit in the flash memory 110. 112 is a page buffer for temporarily storing write data and read data, and 113 is a control circuit for controlling the entire flash memory 110.

  On the other hand, FIG. 17B is a diagram showing the internal configuration of the physical block 114. The physical block 114 includes a plurality of physical pages 115. The physical page 115 is a data writing unit in the flash memory 110. The capacity of the physical page 115 differs depending on the type of flash memory, but here, a capacity value of 2112 B in total of 2 KB in the data area and 64 B in the management area is used.

  FIG. 18 is a diagram illustrating a situation where data copy processing is performed in the flash memory chip. When data for one physical page is written from the host 200 in a state where data has been written to all the physical pages of the physical block #a, data cannot be overwritten in the flash memory 110. For this reason, the data from the host 200 is written into the erased physical block, here, the first physical page # 0 (indicated by an arrow) of the physical block #b. When the write data from the host 200 is only one page, thereafter, (M−1) pages of data from the physical page # 1 to the physical page #M of the physical block #a are stored in the physical block #b. It is necessary to copy from physical page # 1 to physical page #M.

  When copying the data in the flash memory 110, basically, the data is once read from the flash memory 110 to the controller 120, and then the data of the controller 120 is written to the flash memory 110.

  FIGS. 19A and 19B are timing charts showing data reading from the flash memory 110 and data writing to the flash memory 110, respectively. In the figure, the control signal line group includes a chip enable signal, a command latch enable signal, an address latch enable signal, a command / data bus, a write enable signal, and a read enable signal.

  In the data reading shown in FIG. 19A, the host 200 transfers a read command (read command) and a read target address (read address) to the flash memory 110. In response to this, the flash memory 110 outputs a busy state for a predetermined time required for data reading as a ready / busy signal. Thereafter, after the flash memory 110 becomes ready, data is read from the flash memory 110 (read data).

  The time required for this processing is about 152 μs. The breakdown is that the busy period of the flash memory 110 is 25 μs, and the time required for reading data is about 127 μs. Here, the data is (2 KB + 64 B) and the cycle time is calculated as 60 ns. The processing time for the read command (read command) and the read target address (read address) is negligible.

  Next, in the data write shown in FIG. 19B, the host 200 transfers a write start command (write start command) and a write target address (write address) to the flash memory 110. Thereafter, write data is transferred to the flash memory 110 (write data), and finally a command for executing writing (write execution command) is transferred. In response to this, the flash memory 110 outputs a busy state for a predetermined time required for data writing to a ready / busy signal.

  The time required for this processing is about 327 μs. The breakdown is that the busy period of the flash memory 110 is 200 μs, and the time required for transferring write data is about 127 μs. Here, the data is (2 KB + 64 B) and the cycle time is calculated as 60 ns. The processing time of a command for starting writing (write start command), an address to be written (write address), and a command for executing writing (write execution command) is negligible.

  As a result, it takes about 479 μs (= 152 μs + 327 μs) to read data from the flash memory 110 to the controller 120 and then write the data of the controller 120 to the flash memory 110.

  Since this process is performed in the flash memory chip, there is a data copy function. Copying data in the flash memory chip is realized by holding the data read to the page buffer 112 even after it is read to the host 200 and using it as data for writing. A timing chart when the data copy function is used is shown in FIG.

  First, in reading, the controller 120 transfers a copy source data read command (copy read command) and a copy source data target address (copy read address) to the flash memory 110. In response to this, the flash memory 110 outputs a busy state for a predetermined time required for data reading to the ready / busy signal. At this time, the data to be read is stored in the page buffer 112. Thereafter, after the flash memory 110 becomes ready, data is read from the flash memory 110 (copy read data). This reading is performed in order to detect when a bit error or the like has occurred in the read data. Even after this processing, the data stored in the page buffer 112 is held as it is.

  Next, in writing, the controller 120 transfers to the flash memory 110 a command for starting copy writing (copy write start command) and a copy destination write target address (copy write address). Thereafter, the write data is transferred to the flash memory 110 (write data). This data is error correction data in the case where an error has occurred in the data in the management area portion or the data read out earlier, and only a part of the page buffer 112 is updated. Finally, a command for executing copy writing (copy write execution command) is transferred. In response to this, the flash memory 110 outputs a busy state for a predetermined time required for data writing to the ready / busy signal, and ends the data copy process.

  The time for this treatment is about 352 μs. The breakdown is that the read busy period of the flash memory 110 is 25 μs, the time required for data read is about 127 μs, and the write busy period of the flash memory 110 is 200 μs. Here, the data is (2 KB + 64 B) and the cycle time is calculated as 60 ns. Processing time for command input and address input is negligible.

  In other words, when the data copy function of the flash memory 110 is used, the processing time is about 352 μs, which is nearly 30% faster than the processing time of about 479 μs when data is once transferred to the controller 120 and then written to the flash memory 110. Can be processed.

  The data copying process described above can be performed only inside the flash memory chip, and cannot be used when controlling a plurality of flash memory chips. For example, as shown in FIG. 21, when the two flash memories 110A of the flash memory 110A and the flash memory 110B are controlled by one controller 120, the controller 120 sends two chip enable signals, chip enable 1 and chip enable 2. It is controlled individually by providing. Control signals other than the chip enable signal are shared between the flash memory 110A and the flash memory 2.

FIG. 22 is a timing chart showing data copy processing from the flash memory 110A to the flash memory 110B in the configuration shown in FIG. First, read processing similar to that in FIG. 19A is performed with chip enable 1 set to “L” (active), and then chip enable 1 is set to “H” (inactive) and chip enable 2 is set to “L” (inactive). Active) and the same writing process as in FIG. 19B is performed.
JP 2004-30784 A

  In order to increase the capacity of the memory card 100, it is effective to increase the number of flash memories 110 mounted on the memory card 100. In order to increase the number of flash memories, there is a multi-chip package (MCP) in which a plurality of flash memory chips are sealed in one package. FIGS. 23A and 23B are examples.

  23A is a cross-sectional view of a package in which a plurality of flash memory chips 110 are stacked in the same direction, and FIG. 23B is a cross-sectional view of a package that seals two flash memory chips 110 back to back. In the figure, 140 is a substrate for fixing the flash memory chip 110, 150 is an insulating adhesive, 160 is a sealing resin, and 170 is a lead wire.

  In either case of FIGS. 23A and 23B, it can be classified by the number of chip enable signals output to the outside of the package, and as shown in FIG. 24A, the flash memory chip 110A existing inside the package 180, A chip enable signal corresponding to each of 110B is individually output to the outside of the package, and a chip enable signal of the flash memory chip existing inside the package 180 as shown in FIG. There is a type in which the operation of the two flash memories 110 </ b> A and 110 </ b> B is set to be switched according to an address designated by the controller 120 inside the package 180.

  In the type of FIG. 24B, a bank terminal indicating which address area corresponds to “H” for a multi-chip terminal which is a terminal setting indicating that a chip enable is shared by two flash memory chips. Are applied with “H” and “L” having different polarities.

  Data copy processing in the configuration of FIG. 24A is performed in the same manner as the timing chart of FIG. The data copy processing in the configuration of FIG. 24B is performed according to the timing chart of FIG. The timing chart of FIG. 25 is the same as the timing chart of FIG. 22 except for the chip enable signal, and thus description thereof is omitted.

  24A and 24B, the controller 120 that controls a plurality of flash memory chips once reads data from the flash memory 110A and transfers it to the controller 120 when performing data copy processing. After that, it is necessary to transfer data from the controller 120 again and write it to the flash memory 110B.

  As described above, in the MCP that realizes a large-capacity memory card, it is necessary to control a plurality of nonvolatile memories. Therefore, the data copy function for high-speed writing cannot be used effectively, and the data When copy processing is required, it is necessary to read data from the non-volatile memory and transfer it to the controller, and then transfer and write the data to the non-volatile memory again, which requires extra time for processing. .

  An object of the present invention is to solve the above-described problems and provide a nonvolatile memory device capable of performing data copy processing at high speed.

In order to solve the above problem, the first nonvolatile memory device of the present invention provides:
First and second nonvolatile memories for storing data;
A controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories;
A bus for transferring a command, an address or data between the controller and the first nonvolatile memory or the second nonvolatile memory;
Sharing a bus between the controller and the first nonvolatile memory and a bus between the controller and the second nonvolatile memory;
The controller reads the data read from the first non-volatile memory via the bus during the copy process of reading the data from the first non-volatile memory and writing the data to the second non-volatile memory. Transfer to the second non-volatile memory.

  In the first nonvolatile memory device of the present invention, the controller controls to read data from the first nonvolatile memory and writes data to the second nonvolatile memory during the copy process. It is preferable to perform the control simultaneously.

  In the nonvolatile memory device of the present invention, it is preferable that the controller obtains data transferred by the bus and performs ECC calculation of data read from the first nonvolatile memory during a copy process. Similarly, it is preferable that the controller further corrects write data for the second nonvolatile memory based on the ECC calculation result.

  In the first nonvolatile memory device of the present invention, the first nonvolatile memory and the second nonvolatile memory may be sealed in the same package. In this case, the write control line and the read control line in the first nonvolatile memory and the second nonvolatile memory are individually output to the outside of the package and connected to the controller.

  Alternatively, the first nonvolatile memory and the second nonvolatile memory may be sealed in different packages.

Next, the second nonvolatile memory device of the present invention is
First and second nonvolatile memories for storing data;
A controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories;
A bus for transferring a command, address or data between the controller and the first nonvolatile memory or the second nonvolatile memory;
An internal I / F that directly transfers data between the first and second nonvolatile memories,
During a copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory, the data read from the first nonvolatile memory is transferred to the first nonvolatile memory via the internal I / F. It transfers to 2 non-volatile memory, It is characterized by the above-mentioned.

In the second nonvolatile memory device of the present invention, it is preferable that the internal I / F can be controlled from either the first nonvolatile memory or the second nonvolatile memory.
In the second nonvolatile memory device of the present invention, data transfer from the first nonvolatile memory to the second nonvolatile memory via the internal I / F, and via the bus It is preferable to simultaneously read data from the first nonvolatile memory to the controller. Similarly, data transfer from the first nonvolatile memory to the second nonvolatile memory via the internal I / F, and the controller to the second nonvolatile memory via the bus It is preferable to write data to the memory simultaneously.

  Furthermore, in the second nonvolatile memory device of the present invention, the first nonvolatile memory and the second nonvolatile memory may be sealed in the same package. In this case, selection of the first nonvolatile memory and the second nonvolatile memory by the controller designates an address. The nonvolatile memory device according to claim 12, wherein Similarly, the internal I / F is connected only within the package and is not output to the outside of the package.

  Alternatively, the first nonvolatile memory and the second nonvolatile memory may be sealed in different packages.

Next, a data transfer method of the first nonvolatile memory device of the present invention is as follows.
A first and second nonvolatile memory for storing data; a controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories; A data transfer method for a nonvolatile storage device that shares a bus between the controller and the first nonvolatile memory and a bus between the controller and the second nonvolatile memory,
The controller reads data from the first nonvolatile memory via the bus during the copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory. The data is transferred to the second non-volatile memory.

The data transfer method of the second nonvolatile memory device of the present invention is as follows:
A first and second nonvolatile memory for storing data, a controller for writing data to the first and second nonvolatile memories, and reading data from the first and second nonvolatile memories; A data transfer method for a nonvolatile storage device comprising an internal I / F that directly transfers data between the first and second nonvolatile memories,
During the copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory, the data read from the first nonvolatile memory is transferred to the first nonvolatile memory via the internal I / F. It transfers to 2 non-volatile memory, It is characterized by the above-mentioned.

  According to the nonvolatile memory device of the present invention, in data copy processing, data transfer between a plurality of nonvolatile memory chips mounted in the device can be performed at the same level as data transfer within the same chip. Thus, a nonvolatile memory device capable of writing data at high speed can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing an internal configuration of a nonvolatile memory device according to Embodiment 1 of the present invention. In order to control the flash memories 110A and 110B, which are two nonvolatile memories, a chip enable signal, a write enable signal, and a read enable signal are output for each chip. The other signal lines including the command / data bus are shared by the two flash memories. By adopting such a configuration, it is possible to simultaneously perform reading from the flash memory and writing to the flash memory while sharing the data bus.

  FIG. 2 is a timing chart for one cycle when data is transferred from one flash memory to the other flash memory in the configuration of FIG. FIG. 2 shows only the part related to data transfer. Actually, it is necessary to input a read command and a read target address before this for a flash memory that reads data, and a write start command and a write target address before this for a flash memory that writes data. And then a write execution command must be input.

  Here, a case where data is transferred from the flash memory 110A to the flash memory 110B is shown. In data transfer, the controller 120 first sets both chip enable 1 and chip enable 2 to “L” (active). Then, the read enable 1 is set to “L” (active) to request the output of read data from the flash memory 110A. Upon receiving “L” (active) of read enable 1, the flash memory 110 A outputs valid data to the command / data bus 130. The controller 120 toggles the write enable signal 2 from “H” → “L” → “H” during a period in which data is output from the flash memory 110A, so that the command / data bus 130 is sent to the flash memory 110B. Valid data output from the flash memory 110A is input as write data via the. The controller 120 sets the read enable signal 1 to “H” (inactive) to finish outputting data from the flash memory 110A to the command / data bus 130.

  As described above, the controller 120 transfers data from the flash memory 110A to the flash memory 110B.

  FIG. 3 is a diagram showing a control signal application state and data flow in the period shown in the timing chart of FIG. 2 in the configuration of FIG. As indicated by the thick arrows, the controller 120 activates the chip enable signals (chip enable 1 and chip enable 2) of both the flash memory 110A that is the data transfer source and the flash memory 110B that is the data transfer destination. By activating read enable 1 of the flash memory 110A that is the copy source, data is read from the flash memory 110A and output to the command / data bus 130. In this state, the data read from the flash memory 110A is written and transferred to the flash memory 110B by toggling the write enable signal of the flash memory 110B that is the copy destination.

  FIG. 4 is a timing chart when data is copied from the flash memory 110A to the flash memory 110B using the data transfer of FIG. First, the controller 120 sets only the chip enable 1 of the flash memory 110A, which is the copy source flash memory, to “L” (active), and the chip enable 2 is in the “H” (inactive) state. Command) and the target address (read address) of the copy source data. In response to this, the flash memory 110A outputs a busy state for a predetermined time required for data reading as a ready / busy signal.

  Next, the controller 120 sets the chip enable 1 of the flash memory 110A to “H” (inactive), sets the chip enable 2 of the flash memory 110B of the copy destination to “L” (active), and starts a write start command (write Start command) and target address (write address) of copy destination data.

  The controller 120 waits for the ready / busy signal of the flash memory to become “H” (ready state) and sets the chip enable 1 to “L” (active), that is, both the flash memory 110A and the flash memory 110B are selected. As described above, data transfer (read data / write data) from the flash memory 110A to the flash memory 110B is performed. This is performed by the required number of cycles based on the timing chart shown in FIG. This is performed by toggling the read enable 1 for the flash memory 110A and toggling the write enable signal 2 for the flash memory 110B.

  At this time, the controller 120 also performs ECC calculation of data read from the flash memory 110A through the command / data bus 130. In other words, the data output from the flash memory 110A during this period is transferred as write data to the flash memory 110B and sent to the controller 120 for ECC calculation.

  Thereafter, the controller 120 sets the chip enable 1 to “H” (inactive) to transfer data only to the flash memory 110B, and transfers write data such as management information while only the flash memory 110B is selected. And ECC correction (write data). That is, the ECC calculation result of the data read from the flash memory 110A is reflected in the write data to the flash memory 110B. The transfer of write data required for ECC correction is about several bytes because of the correction capability. Finally, a write execution command is issued to the flash memory 110B to finish the process.

  The time for this treatment is about 352 μs. The breakdown is that the flash memory read busy period is 25 μs, the data read time is approximately 127 μs, and the flash memory write busy period is 200 μs. Here, the data is (2 KB + 64 B) and the cycle time is calculated as 60 ns. Processing time for command input and address input is negligible.

  This time is equivalent to the time required to copy data using the copy function in a single flash memory chip. That is, not only the chip enable signal but also the reading and writing of a plurality of flash memories to be controlled are independently controlled, so that data can be copied between the flash memories at a high speed while the command / data bus 130 is shared. it can.

  As shown in FIG. 5, even in a configuration in which two flash memories 110A and 110B are sealed in one flash memory package 180 and the command / data bus 130 is shared, chip enable, write enable, and read enable are independently performed. By controlling, data can be copied between a plurality of flash memory chips at high speed.

(Embodiment 2)
FIG. 6 is a diagram showing an internal configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. Inside the memory card 100, which is a non-volatile storage device, there is one controller 120 and one flash memory package 180. Inside the package 180, two flash memories 110A, 110B, which are non-volatile memories, are sealed. . 24B, which shows a conventional memory card, has an internal I / F 190 that spans between two flash memories sealed in a package 180. FIG. The internal I / F 190 is not output to the outside of the flash memory package.

  FIG. 7 is a detailed view of the internal I / F 190 of FIG. The flash memories 110A and 110B include an internal bus for transmitting data as an input / output, as an internal I / F signal, a transmission clock and a start pulse as outputs, a reception clock and a counter as inputs.

  When the flash memory 110A and the flash memory 110B are connected by the internal I / F 190, the transmission clock output of the flash memory 110A is the reception clock of the flash memory 110B, the start pulse output of the flash memory 110A is the counter reset input of the flash memory 110B, The transmission clock output of the flash memory 110B is connected to the reception clock of the flash memory 110A, the start pulse output of the flash memory 110B is connected to the counter reset input of the flash memory 110A, and the internal bus of the flash memory 110A is connected to the internal bus of the flash memory 110B. Connected.

  When transferring data from the flash memory 110A to the flash memory 110B, the flash memory 110A outputs a start pulse to the flash memory 110B. The flash memory 110A that has output the start pulse is in an output state for driving the internal bus, and the flash memory 110B that has received a counter reset by the start pulse of the flash memory 110A is in the input state of the internal bus. In this state, the flash memory 110A toggles the transmission clock while outputting data to the internal bus. A timing chart at this time is shown in FIG. The rising edge of the transfer clock output is output during the period when the transfer data is valid data.

  In data transfer using the internal I / F 190, data is transferred from the page buffer 112 of the transfer source flash memory 110A to the page buffer 112 of the transfer destination flash memory 110B. Data is not read from the memory array of the flash memory or written to the memory array of the flash memory.

  By providing the internal bus configuration in the package as described above, data transfer between a plurality of flash memories can be performed independently of the control of the command / data bus 130 from the controller 120.

  FIG. 9 is a diagram showing a control signal application state and data flow during the period shown in the timing chart of FIG. 8 in the configuration of FIG. As indicated by the thick arrows, data is transferred only within the package 180 with the flash memory 110A as the data transfer source and the flash memory 110B as the data transfer destination.

  FIG. 10 is a timing chart when data is copied from the flash memory 110A to the flash memory 110B using the internal I / F 190. First, the controller 120 sets the chip enable to “L” (active) and transfers a read command (copy read command) and a target address (copy read address) of copy source data, which is an address corresponding to the flash memory 110A. In response to this, the flash memory 110A outputs a busy state for a predetermined time required for data reading as a ready / busy signal. At this time, the flash memory 110B does not operate because the address is not the target.

  The flash memory 110A sets the ready / busy signal to “H” (ready) after transferring read data to the internal page buffer 112, and uses the internal I / F 190 to transfer data from the flash memory 110A to the flash memory 110B. Start transfer (data transfer). Although this data transfer is not executed by a normal read command, the flash memory 110A transfers data to the flash memory 110B independently of the control of the controller 120 in response to the copy read command being issued.

  At the same time, the controller 120 waits until the ready / busy signal of the flash memory becomes “H” (ready state) and starts transfer of read data (copy read data).

  At this time, the controller 120 reads data to perform ECC calculation. That is, the controller 120 performs ECC calculation of data transferred from the flash memory 110A to the flash memory 110B during this period. However, the data used for the ECC calculation is not the data transferred from the flash memory 110A to the flash memory 110B via the internal I / F 190, but from the flash memory 110A as another path via the command / data bus 130. Data read to the controller 120.

  After tracking the data read, the controller 120 transfers a copy destination write start command (copy write start command) and a copy destination target address (copy write address) corresponding to the flash memory 110B. In response to this, the flash memory 110B becomes ready to receive data from the controller 120. The flash memory 110A does not operate because the address is not a target.

  Then, write data such as management information is transferred and ECC is corrected (copyright data). That is, the result of the ECC calculation of the data read from the flash memory 110A is reflected in the write data to the flash memory 110B. Note that the transfer of the write data required for the ECC correction is for the correction capability, and is about several bytes. . Finally, a write execution command is issued to finish the process. In response to the write execution command, the flash memory 110B writes the data in the page buffer 112 to the target address of the memory array.

  The time for this treatment is about 352 μs. The breakdown is that the flash memory read busy period is 25 μs, the data read time is approximately 127 μs, and the flash memory write busy period is 200 μs. Here, the data is (2 KB + 64 B) and the cycle time is calculated as 60 ns. Processing time for command input and address input is negligible.

  This time is equivalent to the time required to copy data using the copy function in a single flash memory chip. That is, by providing the internal I / F 190 between the flash memories 110A and 110B instead of the signal via the controller 120, data can be copied between the flash memories at high speed.

  As described above, the nonvolatile memory device of the present invention can be handled in the same manner as a single semiconductor chip despite the fact that a plurality of semiconductor chips are mounted inside the device. Suitable for memory cards that require large capacity.

Block diagram of the nonvolatile memory device according to Embodiment 1 of the present invention Timing chart of data transfer between nonvolatile memories in the first embodiment The figure which showed the flow of the data in Embodiment 1 Timing chart of data copy between flash memories in the first embodiment The block diagram which shows the other structure of the non-volatile memory device in Embodiment 1 Block diagram of a nonvolatile memory device according to Embodiment 2 of the present invention The figure which shows I / F between the flash memories in Embodiment 2 Timing chart of data transfer between flash memories in the second embodiment The figure which shows the flow of the data in Embodiment 2 Timing chart of data copy between flash memories in the second embodiment Block diagram showing the configuration of a general memory card Diagram showing details of signal lines inside memory card Command input timing chart to flash memory Timing chart of address input to flash memory Flash memory write data transfer timing chart Flash memory read data transfer timing chart Block diagram showing the internal structure of the flash memory Illustration of data copy inside the flash memory Flash memory data read and write timing chart Flash memory data copy timing chart A block diagram of a conventional nonvolatile memory device Timing chart of data copy between flash memories in the storage device of FIG. Cross-sectional view of MCP packaged with multiple flash memories Block diagram of conventional nonvolatile memory device using MCP Timing chart of data copy between flash memories in the storage device of FIG.

Explanation of symbols

100 Memory Card 110 Flash Memory 112 Page Buffer 113 Control Circuit 114 Physical Block 115 Physical Page 120 Controller 130 Command / Data Bus 190 Internal I / F
200 hosts

Claims (22)

First and second nonvolatile memories for storing data;
A controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories;
A bus for transferring a command, an address or data between the controller and the first nonvolatile memory or the second nonvolatile memory;
Sharing a bus between the controller and the first nonvolatile memory and a bus between the controller and the second nonvolatile memory;
The controller reads the data read from the first non-volatile memory via the bus during the copy process of reading the data from the first non-volatile memory and writing the data to the second non-volatile memory. And transferring the data to the second nonvolatile memory.   The controller is configured to simultaneously perform control for reading data to the first nonvolatile memory and control for writing data to the second nonvolatile memory during a copy process. The non-volatile memory device according to 1.   3. The nonvolatile memory according to claim 1, wherein the controller obtains data transferred through the bus and performs an ECC operation on data read from the first nonvolatile memory during a copy process. 4. Sex memory device.   4. The nonvolatile memory device according to claim 3, wherein the controller further corrects write data for the second nonvolatile memory based on an ECC calculation result. 5.   The nonvolatile memory device according to claim 1, wherein the first nonvolatile memory and the second nonvolatile memory are sealed in the same package.   The write control line and the read control line in the first nonvolatile memory and the second nonvolatile memory are individually output to the outside of the package and connected to the controller. Item 6. The nonvolatile memory device according to Item 5.   The nonvolatile memory device according to claim 1, wherein the first nonvolatile memory and the second nonvolatile memory are sealed in different packages. First and second nonvolatile memories for storing data;
A controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories;
A bus for transferring a command, address or data between the controller and the first nonvolatile memory or the second nonvolatile memory;
An internal I / F that directly transfers data between the first and second nonvolatile memories,
During the copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory, the data read from the first nonvolatile memory is transferred to the first nonvolatile memory via the internal I / F. A non-volatile memory device, wherein the non-volatile memory device is transferred to a non-volatile memory.   9. The nonvolatile memory device according to claim 8, wherein the internal I / F can be controlled from either the first nonvolatile memory or the second nonvolatile memory.   Data transfer from the first nonvolatile memory to the second nonvolatile memory via the internal I / F, and data from the first nonvolatile memory to the controller via the bus 10. The nonvolatile memory device according to claim 8 or 9, wherein the reading is simultaneously performed.   Data transfer from the first nonvolatile memory to the second nonvolatile memory via the internal I / F, and data from the controller to the second nonvolatile memory via the bus The nonvolatile memory device according to claim 8, wherein writing is simultaneously performed.   The nonvolatile memory device according to claim 8, wherein the first nonvolatile memory and the second nonvolatile memory are sealed in the same package.   13. The nonvolatile memory device according to claim 12, wherein selection of the first nonvolatile memory and the second nonvolatile memory by the controller is performed by designating an address.   The nonvolatile memory device according to claim 12, wherein the internal I / F is connected only within the package and is not output to the outside of the package.   The nonvolatile memory device according to claim 8, wherein the first nonvolatile memory and the second nonvolatile memory are sealed in different packages. A first and second nonvolatile memory for storing data; a controller for controlling data writing to the first and second nonvolatile memories and data reading from the first and second nonvolatile memories; A data transfer method for a nonvolatile storage device that shares a bus between the controller and the first nonvolatile memory and a bus between the controller and the second nonvolatile memory,
The controller reads data from the first nonvolatile memory via the bus during the copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory. A data transfer method for a nonvolatile memory device, wherein the data is transferred to the second nonvolatile memory.   2. The copy process according to claim 1, wherein the controller simultaneously performs control for reading data from the first nonvolatile memory and control for writing data to the second nonvolatile memory. The data transfer method of the non-volatile storage device according to claim 16.   18. The nonvolatile memory according to claim 16, wherein the controller obtains data transferred through the bus and performs an ECC operation on data read from the first nonvolatile memory during a copy process. Data transfer method for volatile storage device.   19. The data transfer method for a nonvolatile memory device according to claim 18, wherein the controller further corrects write data for the second nonvolatile memory based on an ECC calculation result. A first and second nonvolatile memory for storing data, a controller for writing data to the first and second nonvolatile memories, and reading data from the first and second nonvolatile memories; A data transfer method for a nonvolatile storage device comprising an internal I / F that directly transfers data between the first and second nonvolatile memories,
During the copy process of reading data from the first nonvolatile memory and writing the data to the second nonvolatile memory, the data read from the first nonvolatile memory is transferred to the first nonvolatile memory via the internal I / F. A method for transferring data in a nonvolatile memory device, wherein the data is transferred to a nonvolatile memory of 2.   Data is transferred from the first nonvolatile memory to the second nonvolatile memory via the internal I / F, and data is read from the first nonvolatile memory to the controller via a bus. 21. The data transfer method of the nonvolatile memory device according to claim 20, wherein ECC calculation is performed by the controller.   The non-volatile memory according to claim 21, wherein the controller transfers data that has been subjected to error correction based on an ECC calculation result to the second non-volatile memory via the bus and writes the data. Device data transfer method.

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