JP5503207B2 - Transmitter and communication system - Google Patents

Description

  The present invention relates to a transmitter and a communication system.

  In recent years, with the increase in screen size and definition of flat-screen televisions, the amount of data transmission within the television has increased, and data transmission speed, parallelism, and space saving between channels have been promoted. An example of such a data transmission system is LVDS (Low Voltage Differential Signaling). LVDS is a method for transmitting and receiving signals by changing the direction of current in a pair of differential transmission lines terminated with resistors.

  As described above, in a transmission method in which data transmission is performed using a plurality of transmission lines, when the data rate is increased and the space between channels is narrowed, interference between channels (crosstalk) occurs, leading to deterioration in data transmission quality. In particular, in a data transmission method using a clock data recovery (CDR) circuit in which data transition information plays an important role, it is temporally at the data edge (data transition point) due to crosstalk between channels. Fluctuations (hereinafter referred to as jitter) occur and data transmission quality deteriorates.

  Therefore, for example, in the signal transmission device described in Patent Document 1, the first delay unit is provided in the transmission device, and the second signal delay time is generated in the reception device with the same configuration as the first delay unit. A delay unit is provided. Accordingly, the first signal (clock signal) is delayed in the first delay unit with respect to the second signal (video signal) transmitted from the transmission device, and the first signal and the second signal are By shifting the synchronization timing, jitter due to the influence of crosstalk is suppressed, and the second signal transmitted from the transmission device is subjected to the same signal time delay as the first signal in the second delay unit in the reception device. As a result, the first signal and the second signal are finally synchronized.

JP 2007-195055 A

  In the above conventional signal transmission device, a signal delay time is generated in the first signal (clock signal) transmitted from the transmission device, thereby reducing jitter caused by crosstalk. However, in this signal transmission device, the delay amount is a fixed value because the signal is delayed due to the length of the circuit element and the wiring. For this reason, for example, when the clock frequency (data rate) is changed in a variable frequency system, there is a problem that the change in the frequency cannot be handled.

  The present invention has been made to solve the above-described problems, and provides a transmitter and a communication system that can cope with a change in frequency and can reduce jitter caused by crosstalk. Objective.

The transmitter of the present invention is a transmitter that transmits _N serial data signals S _{1 to} S _N to a receiver via _N transmission lines L _{1 to} L _N (N is an integer of 2 or more). , the reference clock _{CK ref} to input an oscillation circuit for generating and outputting the different phases N-phase clocks _CK 1 _{~CK N} and having the same period, the clock _CK 1 _~CK output from the oscillator circuit enter the _n, each clock CK n _(n is 1 or more n or less respective integers), characterized in that it comprises a transmitting unit for transmitting to the synchronized serial data signal S _n with the transmission line L _n, a.

In the transmitter generates a clock CK ₁ ~CK _N of different phases N phase and having the same period, the receiver via the transmission line L _n in synchronism with the serial data signal S _n in each clock CK _n Send to. Thereby, the serial data signals S _{1 to} S _N transmitted through the _N transmission lines L _{1 to} L _N are transmitted in synchronization with CK ₁ to CK _N in which a delay (skew) has occurred due to the phase difference. Therefore, the edge of data can be shifted so that crosstalk does not occur between adjacent transmission lines L _{1 to} L _N , and jitter due to crosstalk can be reduced. Further, even when the frequency changes, the clocks CK _{1 to} CK _N having the same period are always generated and output with the same positional relationship (phase difference), so that it is possible to cope with a change in frequency. . Therefore, it is possible to cope with a change in frequency and to reduce jitter caused by crosstalk.

The oscillation circuit, it is preferable that the phase generating and outputting a clock _CK 1 _{~CK N} of 2 [pi / N shifted N phases. In this case, since the data edges are in a positional relationship where the crosstalk hardly occurs between the adjacent transmission lines L _{1 to} L _N , the jitter due to the crosstalk can be further reduced.

Further, the communication system of the present invention includes a transmitter for transmitting _N serial data signals S _{1 to} S _N via _N transmission lines L _{1 to} L _N (N is an integer of 2 or more), and this transmission. And a receiver for receiving serial data signals S _{1 to} S _N transmitted from a transmitter, wherein the transmitter receives a reference clock CK _ref and has the same period and phases with each other. an oscillation circuit for generating and outputting a different n-phase clocks _CK 1 ～CK _n, input the clock _CK 1 ～CK _n output from the oscillation circuit, following each respective clock _CK n (n is 1 or more n and a transmission unit for transmitting to synchronize the serial data signal S _n in the transmission line L _n an integer), the receiver, the serial data signal S transmitted synchronously from transmitter clock CK ₁ ~CK _n the ₁ ~S _N A receiving unit signals to, enter the serial data signal _S 1 to S _N synchronized with the clock _CK 1 _{~CK N} received by the receiving unit, the data _D 1 ~ on the basis of the serial data signal _S 1 to S _N a clock recovery unit which performs restore D _N and the clock _CK 1 _{~CK N,} by entering the restored data _D 1 to D _N and the clock _CK 1 _{~CK N} by the clock recovery unit, the transmission line _{L 1} of the N And a deskew circuit that adjusts and outputs a phase shift between _{LN and LN} .

The communication system generates a clock CK ₁ ~CK _N of different phases N phase and having the same period, the receiver via the transmission line L _n in synchronism with the serial data signal S _n in each clock CK _n Send to. Then, the receiver restores the data _D 1 to D _N and the clock _CK 1 _{~CK N} from the serial data signal _S 1 to S _N received, adjusts the phase shift between the transmission lines _L 1 ~L _N Output. With such a configuration, the serial data signals S _{1 to} S _N transmitted through the _N transmission lines L _{1 to} L _N are transmitted in synchronization with CK ₁ to CK _N in which a delay is caused by the phase difference. Therefore, the edge of data can be shifted so that crosstalk does not occur between adjacent transmission lines L _{1 to} L _N , and jitter due to cross talk can be reduced. Further, even when the frequency changes, the clocks CK _{1 to} CK _N having the same period are always generated and output with the same positional relationship (phase difference), so that it is possible to cope with a change in frequency. . Therefore, it is possible to cope with a change in frequency and to reduce jitter caused by crosstalk.

  According to the present invention, it is possible to cope with a change in frequency and to reduce jitter caused by crosstalk.

It is a block diagram of the communication system containing the transmitter which concerns on this embodiment. It is a circuit diagram of an oscillation circuit. It is a circuit diagram of VCO. It is a figure which shows the clock and the edge of data in a comparative example. It is a figure which shows the clock and the edge of data in this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a configuration diagram of a communication system including a transmitter according to the present embodiment. The communication system 1 shown in this figure includes a transmitter 2 and a receiver 3. The transmitter 2 and the receiver 3 are connected by _N high-speed serial transmission lines L _{1 to} L _N. The high-speed serial transmission lines L _{1 to} L _N are signal lines that transmit signals sent from the transmitter 2 to the receiver 3. N is an integer of 2 or more, and n is an integer of 1 to N (the same applies hereinafter).

  The transmitter 2 includes an oscillation circuit 4 and a transmission unit 5. The transmitter 2 is a device that transmits, for example, image (video) data to the receiver 3.

Oscillation circuit 4 inputs the reference clock _{CK ref,} phase generates and outputs a clock _CK 1 _{~CK N} different N-phase (multi-phase) with each other and having the same period. As shown in FIG. 2, the oscillation circuit 4 is a PLL (Phase-Locked Loop) circuit, a phase comparator 41, a CP (Charge Pomp) 42, and a VCO (Voltage Controlled Oscillator). ) 43 and a frequency dividing circuit 44.

Here, the VCO 43 of the oscillation circuit 4 is configured by a ring oscillator. Specifically, this will be described with reference to FIG. FIG. 3 is a circuit diagram of the VCO 43. As shown in the figure, the VCO 43 includes, for example, five inverters I _{1 to} I ₅ , and the inverters I _{1 to} I ₅ are connected in a ring shape to constitute a ring oscillator. Each of the inverters I _{1 to} I ₅ has a configuration in which the drain terminal of the PMOS transistor and the drain terminal of the NMOS transistor are connected to each other. Each of the inverters I _{1 to} I ₅ is controlled by the control voltage V _c based on the output of the CP 42, thereby outputting clocks CK _{1 to} CK ₅ having the same period and different phases from the output end. . This clock _CK 1 _{~CK 5,} for example adjacent clock _CK 1 _{~CK 5} between the phases are shifted by 2 [pi / 5. The oscillation circuit 4 outputs the generated clocks CK _{1 to} CK _N to the transmission unit 5. Note that the number of connections of the inverter I _m (m is an integer greater than or equal to ₁ ) is appropriately changed according to the required number of phases of the clocks CK _{1 to} CK _N (the number of high-speed serial transmission lines L _{1 to} L _N ). Is done.

In the oscillation circuit 4, as shown in FIG. 2, _{one of} the clocks CK _{1 to} CK _N output from the VCO 43 is supplied as an oscillation signal C _{out to the} frequency divider circuit 44. The oscillation signal _Cout is _divided to generate and output a divided signal Cd. The _divided signal _Cd is fed back to the phase adjustment comparator 41. The phase comparator 41 detects a phase difference between the reference clock _{CK ref} and the divided signal _{C d,} and outputs the comparison signal up which represents the phase difference detection, a down to CP42. Then, the CP42, the comparison signal up input, the amount of current corresponding to the phase difference down represents is generated, the control voltage _{V c} that based on this current is outputted to the VCO 43.

Returning to FIG. 1, the transmission unit 5 receives the parallel data signal P _data input to the transmitter 2, converts the parallel data signal P _data into serial data signals S _{1 to} S _N, and converts the parallel data signal P _data to a high-speed serial transmission line. Transmit to L _{1 to} L _N respectively. The transmission unit 5 includes a plurality of transmitters 5 _{1 to} 5 _N. The transmitter _{5 1} inputs the parallel data signal _{P data,} converts the parallel data signal _{P data} into a serial data signal _{S 1,} by inputting the clock CK ₁ output from the oscillator circuit 4, the clock The serial data signal S ₁ is synchronized with CK ₁ and sent to the receiver 3 via the high-speed serial transmission line L ₁ . Likewise the transmitter _{5 n,} converts the parallel data signal _{P data} in the serial data signal _{S n,} and sends the serial data signal _{S n} to the receiver 3 in synchronism with the clock CK _n.

Here, as described above, the phases of the clocks CK _{1 to} CK _N are shifted by 2π / N. Thus, in Figure 1, serial data and the serial data signal S _1, is sent from the transmitter 5 _n through a high speed serial transmission line L _n sent from the transmitter 5 ₁ via the high-speed serial transmission lines L ₁ signal data edge of the phase of the S _n is (2π / n) × (n -1) only be transmitted offset.

The receiver 3 includes a receiving unit 6, clock recovery units 7 _{1 to} 7 _N , serial-parallel conversion units 8 ₁ to 8 _N , a deskew circuit 9, and a logic circuit 10. The receiver 3 constitutes a part of an LCD (Liquid Crystal Display) panel, for example.

Receiving unit 6 receives from the transmitter 2 receives the serial data signal _S 1 to S _N sent through a high speed serial transmission line _L 1 ~L _N, clocks the serial data signal _S 1 to S _N Output to the recovery unit 7. The receiving unit 6 is a latch circuit, for example.

The clock recovery units 7 _{1 to} 7 _N receive the serial data signals S _{1 to SN} output from the reception unit 6, and based on the serial data signals S _{1 to SN} , the data D _{1 to DN} and the clock CK _{1 to} CK _N are restored. Specifically, the clock recovery section ₇₁ may be from the serial data signals S ₁ and play to restore the clock CK _1, performs a phase comparison between the recovered clock CK ₁ edge data D ₁ of the edge in to adjust the phase, it reproduces the frequency of the same clock as the bit rate of the data D _1. Similarly, the clock recovery unit 7 _n, reproduced to restore the clock CK _n from the serial data signal S _n, the phase adjustment by performing a phase comparison between the edge and the data D _n of the recovered clock CK _n performed, to reproduce the frequency of the same clock as the bit rate of the data D _n. The clock recovery units 7 _{1 to} 7 _N output the restored data D _{1 to DN} and the clocks CK _{1 to} CK _N to the parallel-serial conversion units 8 ₁ to 8 _N.

Serial - parallel converter ₈ 1 to 8 _N receives the clock recovery section ₇₁ output from the to _7-N data _D 1 to D _N and the clock _CK 1 _{~CK N,} serial data data _D 1 to D _N To parallel data. The serial-parallel converters 8 ₁ to 8 _N output the data D _{1 to DN} converted into parallel data and the clocks CK _{1 to} CK _N to the deskew circuit 9.

Deskew circuit 9, the serial - to adjust the phase of the data output from the parallel conversion unit ₈ 1 _{~8 N D} 1 ~D _N and the clock _CK 1 _{~CK N.} Specifically, deskew circuit 9, the serial - to enter the parallel converter 8 ₁ data D ₁ is output from the and the clock CK _1, the input data D ₁ and the clock CK ₁ phase serial - parallel converter The phase shift (phase difference) applied to the clocks CK ₁ and CK _n is adjusted (deskewed) in the oscillation circuit 4 so as to coincide with the data D _n and the clock CK _n output from the unit 8 _n . The deskew circuit 9 outputs phase-adjusted data D _{1 to DN} and clocks CK _{1 to} CK _N to the logic circuit 10.

Logic circuit 10 receives the output data _D 1 to D _N and the clock _CK 1 _{~CK N} from deskew circuit 9, the data _D 1 to D _N and the clock _CK 1 _{~CK N} parallel received data _{PR data} Generate and output as. The logic circuit 10 outputs the parallel reception data PR _data to the display unit of the LCD as image data, for example.

  Next, operations and effects of the communication system 1 of the present embodiment including the transmitter 2 will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram illustrating clock and data edges in the comparative example, and FIG. 5 is a diagram illustrating clock and data edges in the present embodiment.

As shown in FIG. 4, in the communication system of the comparative example, the serial data signal is synchronized with the clock CK having the same phase and sent to, for example, the high-speed serial transmission lines L ₁ and L _n . edge (data transition point) matches with the high-speed serial transmission lines L ₁ and the high-speed serial transmission line L _n. Therefore, crosstalk occurs between the adjacent high-speed serial transmission lines L ₁ and L _n , and jitter due to the crosstalk occurs.

In contrast, as shown in FIG. 5, in the communication system 1 of the present embodiment, in with that (Figure 5 shift clock _CK 1 _{~CK N} between the phase of adjacent 2 [pi / N in the case of n = 2 And π is shifted). That is, as the transition of the serial data signals S ₁ and the serial data signal S _n do not overlap, the data is output. Thus, serial data signals S ₁ synchronized with the clock CK _1, the edges of the serial data signal S _n in synchronism with the clock CK _n also be similarly out of phase. Therefore, since the edge of the data in the position which are not cross-talk between the adjacent high-speed serial transmission line to L ₁ and the high-speed serial transmission line L _n is located, it is possible to reduce the jitter due to crosstalk.

Above, in the communication system 1 comprises a transmitter 2 according to the present actual embodiment, the transmitter 2, the phase generates a clock CK ₁ ～CK _N of different N-phase and having the same period, the respective clock CK _n and transmits the serial data signal S _n synchronize with the transmission line L _n via the receiver 3. Then, the receiver 3 restores the data _D 1 to D _N and _CK 1 _{~CK N} clock from the serial data signal _S 1 to S _N received, adjusts the phase shift between the transmission lines _L 1 ~L _N Output. With such a configuration, the serial data signals S _{1 to} S _N transmitted through the _N transmission lines L _{1 to} L _N are transmitted in synchronization with CK ₁ to CK _N in which a delay is caused by the phase difference. Therefore, the edge of data can be shifted so that crosstalk does not occur between adjacent transmission lines L _{1 to} L _N , and jitter due to cross talk can be reduced. Further, even when the frequency changes, the clocks CK _{1 to} CK _N having the same period are always generated and output with the same positional relationship (phase difference), so that it is possible to cope with a change in frequency. . Therefore, it is possible to cope with a change in frequency and to reduce jitter caused by crosstalk.

In this embodiment, the serial data signals S _{1 to} S _N are delayed by the phase difference between the clocks CK _{1 to} CK _N generated by the oscillation circuit 4. For example, the delay circuit and the crosstalk are corrected. Therefore, a simple configuration can be achieved without the need for a circuit or the like.

The oscillation circuit, the phase, and outputs the generated clock _CK 1 _{~CK N} of 2 [pi / N shifted N phase, in between the transmission lines _L 1 ~L _N adjacent edge of the data is the most crosstalk The positional relationship does not match, and jitter due to crosstalk can be further reduced.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the ring oscillator comprising the inverters I _m as an oscillation circuit 4 for generating a multiphase clock oscillation circuit 4 phase different N phases from each other with the same period clock (multi-phase Clock generator), and is not limited to a ring oscillator. For example, an LC oscillator, a DLL (Delay-Locked Loop), or the like may be used.

1 ... communication system, 2 ... transmitter, 3 ... receiver, 4 ... oscillation circuit, 5 ... transmission unit, 6 ... receiving _{unit, 7} 1 to 7-N _... clock recovery unit, 9 ... deskew _circuit, CK 1 _{~CK N} ... _{clock, L} 1 ~L N _... high-speed serial transmission _{line, S} 1 to S N _... serial data signal.

Claims (3)

A transmitter for transmitting _N serial data signals S _{1 to} S _N to a receiver via _N transmission lines L _{1 to} L _N (N is an integer of 2 or more),
Enter the reference clock _{CK ref,} which has the same period with phase generates and outputs a clock _CK 1 _{~CK N} mutually different Ri and always the same positional relationship der Ru N phase, the clock _CK 1 ~ An oscillation circuit capable of changing the frequency of CK _N ;
Converts the parallel data signal _{P data} corresponding parallel data signal _{P data} to input to the serial data signal _S n (n is 1 or more N or less of each integer), the clock _CK 1 ～CK output from the oscillator circuit enter the _n, the synchronized serial data signal S _n in each clock CK _n, and, the serial data signal S when the frequency of the clock CK ₁ ~CK _n output from the oscillation circuit is changed A transmission unit that changes the frequency of _{1 to} S _N and sends it to the transmission line L _n ;
A transmitter comprising: The oscillation circuit, a transmitter according to claim 1, wherein the phase generating and outputting a clock CK ₁ ～CK _N of 2 [pi / N shifted N phases. A transmitter that transmits _N serial data signals S _{1 to} S _N via _N transmission lines L _{1 to} L _N (N is an integer of 2 or more), and the serial data signal transmitted from the transmitter A communication system including a receiver that receives S1 to SN,
The transmitter is
Enter the reference clock _{CK ref,} which has the same period with phase generates and outputs a clock _CK 1 _{~CK N} mutually different Ri and always the same positional relationship der Ru N phase, the clock _CK 1 ~ An oscillation circuit capable of changing the frequency of CK _N ;
Converts the parallel data signal _{P data} corresponding parallel data signal _{P data} to input to the serial data signal _S n (n is 1 or more N or less of each integer), the clock _CK 1 ～CK output from the oscillator circuit enter the _n, the synchronized serial data signal S _n in each clock CK _n, and, the serial data signal S when the frequency of the clock CK ₁ ~CK _n output from the oscillation circuit is changed A transmission unit that changes the frequency of _{1 to} S _N and sends it to the transmission line L _n ;
With
The receiver
A receiver for receiving the serial data signals S _{1 to} S _N transmitted from the transmitter in synchronization with the clocks CK _{1 to} CK _N ;
The serial data signals S ₁ to _SN synchronized with the clocks CK _{1 to} CK _N received by the receiving unit are input, and data D _{1 to DN} and data D ₁ to _DN based on the serial data signals S ₁ to _SN are input. A clock recovery unit that restores the clocks CK _{1 to} CK _N ;
Wherein by inputting the clock recovery unit the data _D 1 to D _N and the clock _CK 1 _{~CK N} restored by, and outputs the adjusted phase shift between the N of the transmission line _L 1 ~L _N deskew Circuit,
A communication system comprising:

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