JPH05199273A - Signal isolation transmitter - Google Patents

Abstract

PURPOSE:To attain high speed isolation transmission without use of a control signal line by distributing serial data into plural systems according to a serial clock of a sender side add sending the data through a transmission line isolated by a photocoupler. CONSTITUTION:A switch control circuit 7 of a transmission section 4 selectively closes switches SWT1-SWT4 for each clock synchronization according to a serial clock CLT of a sender side and distributes the inputted serial data to transmission lines L1-L4. Synchronization detection circuits SYD1-SYD4 of a reception section 6 detect a data change state of the transmission lines L1-L4 connected respectively to them and output the result to a switch control circuit 8. The switch control circuit 8 decides a phase of the clock CLR at the receiver side used to sample data of the transmission lines L1-L4 and closes selectively the switches SWT1-SWT4 to switch and output the serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal-insulated transmission device, and more particularly to speeding up serial data transmission.

[0002]

2. Description of the Related Art For example, an isolated amplifier for converting an analog signal into a digital signal and outputting the digital signal is as shown in FIG.
The analog output signal of the amplifier 1 is applied to the A / D converter 2 to be converted into a digital signal, and the converted digital signal is insulatedly transmitted to the next signal processing unit via the photocoupler 3. This is based on the fact that when the analog signal is transmitted through the photocoupler, the level may change due to the non-linearity of the photocoupler.

In transmitting the output data of the A / D converter 2, parallel transmission in which a plurality of bits are simultaneously transmitted in parallel and serial transmission in which data is transmitted in a bit string in series can be considered. Serial transmission is generally adopted because it is disadvantageous in terms of cost and circuit space.

[0004]

By the way, the photocoupler used for the insulation transmission of such a signal is required to have a sufficient insulation breakdown voltage for safety. However, in general, in order to increase the withstand voltage, it is necessary to increase the distance between the light emitting diode and the light receiving element of the photocoupler, and if the distance is increased, the transmission speed will decrease. That is, increasing the dielectric strength is an obstacle to speeding up the isolation amplifier.

As a countermeasure for this, it is conceivable to provide a plurality of serial transmission lines for time division transmission. However, if the number of control signal lines for time division control increases, the transmission system can be simplified. The advantages of serial transmission are diminished. The present invention solves such a problem, and an object thereof is to realize a signal insulation transmission device capable of high-speed insulation transmission of serial data with a simple configuration that does not use a control signal line.

[0006]

In order to solve such a problem, the present invention provides a transmitting section including a data distributing circuit for distributing serial data to be transmitted to a plurality of systems according to a serial clock of a transmitting side, By sequentially outputting multiple lines of serial data distributed by the data distribution circuit via the photocoupler and serial data transmitted via each transmission line according to the serial clock of the receiving side And a receiving section including a data synthesizing circuit for synthesizing and reproducing serial data before distribution.

[0007]

According to the present invention, the serial data to be transmitted is distributed to a plurality of systems by the data distribution circuit according to the serial clock on the transmission side, and is transmitted to the receiving unit via the transmission line insulated by the photocoupler. Then, the serial data before distribution is synthesized and reproduced by sequentially outputting the received serial data in accordance with the serial clock on the receiving side.

Thus, time-division transmission of serial data can be performed without providing a control signal line on the transmission line, and the transmission speed can be increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the principle of the present invention. In the figure, reference numeral 4 denotes a transmission unit, which includes a data distribution circuit that distributes serial data to be transmitted to a plurality of systems according to a serial clock on the transmission side. 5 are photocoupler PCs
A plurality of transmission lines having a plurality of lines transmit serial data of a plurality of systems distributed by the data distribution circuit of the transmitter 4. 6
The receiving section includes a data synthesizing circuit for synthesizing and reproducing the serial data before distribution by sequentially outputting the serial data transmitted through each transmission line 5 according to the serial clock on the receiving side.

FIG. 2 is a concrete circuit diagram of FIG. 1, showing an example in which serial data is distributed to four systems and transmitted. That is, the transmission unit 4 includes four switches SWT1 to SWT4 that form a data distribution circuit whose input side is connected in parallel to the serial data input line DIN and whose output side is connected to each transmission line L1 to L4, and the transmission side. And the switch control circuit 7 to which the serial clock CLT is input. In addition, each switch SWT1 to SWT4
A latch circuit for holding each output data until the next data switching is provided on the output side of (1) as needed, but it is not shown.

The receiving unit 6 includes four switches SWR1 to SWR4, which form a data synthesizing circuit whose output side is connected in parallel to the serial data output line DOUT and whose input side is connected to the respective transmission lines L1 to L4, and Transmission line L1
To 4 synchronization detection circuits SYD1 to SY connected to L4
D4 and the switch control circuit 8 to which the serial clock CLR on the receiving side and the output signals of the synchronization detection circuits SYD1 to SYD4 are input.

FIG. 3 shows the synchronization detection circuit SYD1 used in FIG.
7 is a specific example diagram of SYD4, and an exclusive OR gate EOR
And a delay element DLY having a delay time shorter than at least the serial clock, the input of the transmission line is applied to one input terminal of the exclusive OR gate EOR, and the delay element DLY is added to the other input terminal. The output terminal is connected via. These synchronization detection circuits SYD1 to
The SYD 4 detects a change in data on each of the transmission lines L1 to L4 and inputs the output signal to the switch control circuit 8.

The operation of such a configuration will be described. The switch control circuit 7 of the transmitter 4 uses the serial clock C on the transmitter side.
According to LT, for example, the switch SWT1 at every clock cycle
~ SWT4 is selectively turned on sequentially, and the input serial data is sequentially distributed to the transmission lines L1 to L4. The synchronization detection circuits SYD1 to SYD4 of the reception unit 6 detect the change state of the data of the transmission lines L1 to L4 connected to the synchronization detection circuits SYD1 to SYD4, and output it to the switch control circuit 8. The switch control circuit 8 determines the phase of the clock CLR on the reception side for sampling the data of the transmission lines L1 to L4, selectively turns on the switches SWR1 to SWR4 sequentially, and inputs the data via the transmission lines L1 to L4. Serial data to be sequentially output.

Here, the serial clock CL of the transmitter 4
Since the frequency of T and the serial clock CLR of the receiving unit 6 is equal to the frequency of the transmission clock, each switch SWT
1 to SWT4 and SWR1 to SWR4 are turned on in a cycle four times as long as the serial clock, and the optimum time relationship is as shown in FIG. In FIG. 4, (a) shows a serial clock, (b) shows a change state of any serial data of the transmission lines L1 to L4, and (c) shows a timing of sampling the serial data. .
In this case, the timing for sampling the serial data is 3 clocks later.

A specific example will be described. It is assumed that the serial data string is configured as shown in FIG. In FIG. 5, 1 represents data having no significance, B _S represents a start bit, B _{7 to} B ₀ represent data bits having significance, and B _P
Represents a parity bit, and B _T represents a stop bit. Since each data B _S , B _{7 to} B ₀ , B _P , and B _T forming such a serial data string is updated at the same period as the serial clock, the data distributed to each transmission line L1 to L4 is serial. It is updated every time four clocks are input.

FIG. 6 shows a timing chart of such an operation. In FIG. 6, (a) is a transmission clock, and the serial data input to the transmission unit 4 changes in synchronization with the transmission clock as shown in (b). (C) ~
(F) shows a drive signal applied from the switch control circuit 7 of the transmission unit 4 to each of the switches SWT1 to SWT4 constituting the data distribution circuit. As a result, the transmission line L1
The data distributed to L4 changes every four transmission clocks as shown in (g) to (j). The order of such data distribution is summarized in FIG.

In the receiver 6, as described above, the switches SWR1 to SWR4 constituting the data synthesizing circuit are selectively sequentially turned on to sequentially switch and output serial data input via the transmission lines L1 to L4. Serial clock CLT of transmitter 4 and serial clock CLR of receiver 6
Since they have the same frequency but are independent, the reading order is L1 → L2 → L3 → L4 or L2 → L3 → L4 → L1.
There are several cases as described above, but in any case, a data string equal to the input serial data can be combined and reproduced.

As a result, high speed transmission by time division transmission can be realized without providing a special control signal line between the transmitter and the receiver. It should be noted that in the above embodiment, an example was described in which serial data is dividedly transmitted to four transmission lines and combined and reproduced, but the number of divided transmissions may be increased or decreased as appropriate according to the application.

[0019]

As described above, according to the present invention,
It is possible to realize a signal isolation transmission device that can perform high-speed isolated transmission of serial data with a simple configuration that does not use a control signal line, and for various types of high-speed signal isolation transmission such as an isolation amplifier that converts analog signals into digital signals and outputs them. It is valid.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a specific circuit example diagram of FIG.

FIG. 3 is a specific example diagram of a synchronization detection circuit used in FIG.

FIG. 4 is a timing chart illustrating an outline of the operation of FIG.

FIG. 5 is a specific example diagram of a transmission serial data string.

FIG. 6 is a timing chart illustrating the operation of each unit in FIG.

7 is an explanatory diagram of the order of data distributed to the transmission line of FIG.

FIG. 8 is a conceptual configuration diagram of an insulating amplifier that converts an analog signal into a digital signal and outputs the digital signal.

[Explanation of symbols]

 4 transmitter 5 transmission line 6 receiver 7 and 8 switch control circuit SWT and SWR switch PC photocoupler SYD sync detection circuit

Claims (1)

[Claims] 1. A transmission unit including a data distribution circuit that distributes serial data to be transmitted to a plurality of systems in accordance with a serial clock on the transmission side, and a plurality of systems of serial data distributed by the data distribution circuit via photocouplers, respectively. A plurality of transmission lines to be transmitted, and a receiving unit including a data synthesizing circuit for synthesizing and reproducing serial data before distribution by sequentially outputting serial data transmitted via each transmission line in accordance with a serial clock on the receiving side. A signal-insulated transmission device characterized by being configured.