JP5332692B2 - Data transfer control device, data transfer control method, data transfer control program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer control device, a data transfer control method, a data transfer control program and a recording medium for efficiently performing data transfer. <P>SOLUTION: In an image processing apparatus 1, when a data transfer request is made from a plurality of DMAC 20a to 50a through a main CPU 3, an internal arbiter 70 controls the permission/non-permission of data transfer to fairly permit data transfer only in a prescribed transfer period in response to the data transfer request, and after the lapse of the transfer period of the permitted data transfer, when controlling mask processing for masking the data transfer from the DMAC 20a to 50a only in a mask period, obtains the data quantity of the internal buffer of the main CPU 3 in each flow control processing time, and determines the data transfer situations by the main CPU 3 based on the obtained data amounts of the internal buffer, and controls the mask processing based on the determination result. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a data transfer control device, a data transfer control method, a data transfer control program, and a recording medium, and more specifically, a data transfer control device, a data transfer control method, a data transfer control program, and a recording that efficiently perform data transfer. It relates to the medium.

  In recent years, in an image processing apparatus such as a composite apparatus, a printer apparatus, a copying apparatus, a scanner apparatus, and a facsimile apparatus that handle data, each unit such as a scanner unit, a printer unit, and a controller having a main memory is connected with a general-purpose bus. By connecting and sharing an interface, an increase in useless circuits and control software in expansion of a unit or the like is suppressed, and expandability is improved.

  However, in such an image processing apparatus using a bus system, the scanner unit reads the image data of the document, the printer unit prints the image based on the image data, and the scanner unit reads the image data. When copying the printed image data with the printer unit, the scanner unit or printer unit must operate at a constant speed, so a certain amount of data is routed between the scanner unit or printer unit and the main memory of the controller. The bus traffic temporarily increases significantly. This phenomenon becomes more prominent with high-speed machines.

  In the image processing apparatus, the general-purpose bus can be connected to an external IF (interface) of a communication system such as IEEE1394 or USB (Universal Serial Bus). In general, data is transmitted / received to / from an external device such as a card (Secure Digital memory card) or a USB device and a network.

In the configuration of the image processing apparatus in which a plurality of scanner units, printer units, communication interface devices, and the like exist as master devices in the general-purpose bus in this way, the general-purpose bus is connected to the main memory via the main CPU incorporating the arbiter. The bus arbitration method of the arbiter is important, but conventionally, a fixed priority method, a round robin method, or the like is generally used as the bus arbitration method. This fixed priority ordering method is a method in which when a bus request is simultaneously generated from a plurality of master devices, the right to use the bus is given to the higher priority order according to the priority order of the master device that is fixedly set in advance. In the round robin method, the priority order is not fixed. For the master device that has acquired the right to use the bus, the priority order is set to the lowest immediately after acquiring the right to use the bus. It is a method of mediation.

  Each of these conventional bus arbitration methods has advantages and disadvantages. For example, the fixed priority method has an advantage that a master device with a higher priority is always guaranteed to acquire a bus, but a master device with a lower priority has a higher priority than a master device with a higher priority than itself. There is a disadvantage that a situation in which the right to use cannot be obtained occurs.

  In addition, the round robin method has the advantage that arbitration of bus acquisition can be performed fairly for all master devices, but conversely, the bus usage rate is reduced to the transfer data amount, density, etc. for each master device. There is a disadvantage that it is not suitable when you want to make it different depending on the situation.

  In particular, in the round robin method, the data transfer capability inherent to the bus itself (bus width × data transfer time per predetermined bus width) is a device such as an input image controller (scanner unit) or an output image controller (printer unit) ( The closer the limit is to the amount of data that must be transferred when the unit is operating, the more inconvenience may arise.

  That is, the scanner unit needs to transfer image data to the main memory while sequentially performing image processing on the read image, and it is necessary to ensure the bandwidth. Further, in the case of the electrophotographic system, the printer unit needs to transfer image data from the main memory while writing to the photosensitive drum with a laser, and it is necessary to ensure the bandwidth. Furthermore, for example, when receiving data from the network, the external IF must start receiving once it has to transfer the received network packet to the main memory and respond within a certain time. There is.

  In general, a DMA (Direct Memory Access) data transfer method is used for data transfer in the image processing apparatus. In addition, the bus connection is generally handled by the arbiter built in the main CPU, and there is a demand for a technology that allows the arbiter operating in the round robin method to secure data transfer of the scanner unit and printer unit with priority. Is done.

  Therefore, in the conventional round-robin bus arbiter, in response to a bus acquisition request from a low-priority bus master other than the first bus master when a specific event occurs, the next bus acquisition request after giving the bus use right is issued. A technique has been proposed in which the frequency of bus use is temporarily reduced by masking for a certain period to ensure the data transfer efficiency of the first bus master (see Patent Document 1). That is, in this prior art, when a bus use right is given to a transfer request from an external IF, the next bus acquisition request is masked for a certain period, so that data transfer of the scanner unit or printer unit is given priority. It is said.

However, in the above prior art, if data transfer is permitted to a bus master with a low priority, it is simply masked for the next fixed period, so efficient bus acquisition arbitration (ie, bus control) is performed. There was a need for improvements in efficient data transfer.

  That is, in the prior art, in a round robin method in which arbitration of bus acquisition is performed fairly for all master devices, a plurality of devices are connected to a low-priority bus master, for example, an external IF. In order to secure the bus bandwidth by the scanner unit or the printer unit, a mask period is set for the device to which the bus use right is given. However, since the amount of data that can be transferred in one round robin is determined, when the amount of data transferred from the external IF device to the main memory exceeds the amount of data that can be transferred in this one round robin, a plurality of data can be transferred from the external IF device. There will be one bus acquisition request. However, once the right to use the bus is granted and one round-robin data transfer is performed, a mask period starts. During this mask period, for example, a bus acquisition request for a bus transfer with a narrow bus bandwidth used, such as descriptor transfer, is made. When the right to use the bus is given, the right to use the bus is granted to the external IF device even if there is no other bus acquisition request until one round-robin bus transfer of the right to use the bus is completed. Not given. When one round of bus transfer with a narrow bus bandwidth is completed, a bus acquisition request is obtained from the external IF and the right to use the bus is acquired. The bus transfer of entering the mask period is repeated. As a result, there is a need for improvement in performing efficient data acquisition by arbitrating for efficient bus acquisition, and the arbiter built in the main CPU only holds the data transferred from the external IF. The internal buffer is required and the cost is high.

  SUMMARY An advantage of some aspects of the invention is that it provides a data transfer device, a data transfer method, a data transfer program, and a recording medium that are capable of performing data transfer in a cheap and more efficient round robin method.

To achieve the above Symbol purpose, the data transfer control device of the present invention includes a storage unit, is connected to the storage means, having a first internal buffer, the data transfer using the first internal buffer A data transfer control means for controlling the data transfer, a plurality of data transfer request means for making a data transfer request for data transfer with the outside, and in response to the data transfer request from any of the plurality of data transfer request means, A data transfer request control means for performing control for permitting or not permitting a data transfer request for a predetermined period, and a second bus connected to the data transfer control means for acquiring and storing the data amount of the first internal buffer A transfer interface unit having an internal buffer, wherein the data transfer request control unit is configured to receive the data transfer request from the outside. Based on the amount of change in the first internal buffer obtained and stored in the second internal buffer when the request relates to data transfer with the storage means Determining that when the free space in the first internal buffer is sufficient, permitting the data transfer request and transferring data to and from the storage means via the transfer interface means, space of one internal buffer, characterized in that disallowed the data transfer request when it is judged not to be sufficient.

The data transfer control method of the present invention is a data transfer control process for controlling data transfer using the first internal buffer by the data transfer control means connected to the storage means and having the first internal buffer. A plurality of data transfer request processing steps for making a data transfer request related to data transfer with the outside by a plurality of data transfer request means, and a data transfer request control means from any one of the plurality of data transfer request means In response to the data transfer request, a data transfer request control processing step for performing control for permitting or not permitting the data transfer request for a predetermined period of time, and a second of the transfer interface means bus-connected to the data transfer control means Transfer interface processing for acquiring and storing the data amount of the first internal buffer by an internal buffer In the data transfer request control processing step, when the external data transfer request is a request related to data transfer with the storage means, the free state of the first internal buffer Is determined based on the change amount of the first internal buffer acquired and stored in the second internal buffer, and the data transfer request is determined when it is determined that the free space of the first internal buffer is sufficient. Is permitted and data is transferred to and from the storage means via the transfer interface means, and the data transfer request is not permitted when it is determined that the free space of the first internal buffer is not sufficient. It is characterized by .

Further, the data transfer control program of the present invention provides a data transfer control program executed by a computer, is connected with the storage means, the data transfer control means having a first internal buffer, internal the first A data transfer control processing step procedure for controlling data transfer using a buffer, a plurality of data transfer request processing step procedures for making a data transfer request for data transfer with the outside by a plurality of data transfer request means, and data Procedure of a data transfer request control processing step for performing control for permitting or not permitting the data transfer request for a predetermined period in response to the data transfer request from any of the plurality of data transfer requesting means by the transfer request control means And a second internal buffer of the transfer interface means bus-connected to the data transfer control means. And a transfer interface processing step procedure for acquiring and storing the data amount of the first internal buffer, and in the procedure of the data transfer request control processing step, the data transfer request from the outside is Based on the change amount of the first internal buffer acquired and stored in the second internal buffer when the request is related to data transfer with the storage means. Determining that when the free space in the first internal buffer is sufficient, permitting the data transfer request and transferring data to and from the storage means via the transfer interface means, space of one internal buffer, characterized in that disallowed the data transfer request when it is judged not to be sufficient.

In addition, the recording medium of the present invention is characterized in that the procedure of each step the computer is capable of recording read at the data transfer control program.

According to the present invention, when the data transfer request control means performs data transfer with the storage means via the data transfer control means in response to an external data transfer request, the data transfer request control means includes the first internal buffer and the data Based on the change amount of the second internal buffer of the transfer interface means, which is connected to the transfer control means by a bus and acquires and stores the data amount of the first internal buffer, the permission / non-permission of the data transfer request is controlled. Therefore, it can be controlled by grasping the data transfer status better, can be performed cheaper and more efficient data transfer.

1 is a block diagram of an image processing apparatus to which an embodiment of the present invention is applied. The detailed block block diagram of external IFASIC. Explanatory drawing of the bus connection of main CPU and external IFASIC. The flowchart which shows a DMA write process. The flowchart which shows a DMA read process. The figure which shows an example of the format of a descriptor. FIG. 6 is a timing diagram of transfer request mask processing. The flowchart which shows a mask control process. FIG. 6 is a timing chart when unmasking when a transfer request relates to a descriptor. FIG. 6 is a timing chart when canceling the mask when there is a free memory bandwidth.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 10 are diagrams showing an embodiment of a data transfer control device, a data transfer control method, a data transfer control program, and a recording medium according to the present invention. FIG. 1 shows a data transfer control device, data according to the present invention. 1 is a block configuration diagram of an image processing apparatus 1 to which an embodiment of a transfer control method, a data transfer control program, and a recording medium are applied. FIG.

  1, an image processing apparatus 1 includes a controller ASIC 2, a main CPU 3, a main memory 4, a scanner ASIC 5, a scanner unit 6, a plotter ASIC 7, a plotter unit 8, a hard disk (HDD) 9, an external IFASIC 10, a network 11, an external device 12, and the like. It has.

  As the scanner unit 6, for example, an image scanner using a CCD (Charge Coupled Device) is used. The scanner 6 scans and sub-scans a document, reads an image of the document with a predetermined resolution, and binarizes the scanner. Output to ASIC5.

  The scanner ASIC 5 performs appropriate image processing on the image data of the document read by the scanner unit 6 and outputs the image data after the image processing to the controller ASIC 2.

  The controller ASIC 2 is connected to the scanner ASIC 5, the hard disk 9, and the main CPU 3. The controller ASIC 2 controls image data transfer between the scanner ASIC 5, the hard disk 9, and the main CPU 3, and controls the hard disk 9 under the control of the main CPU 3. Drive control and drive control of the scanner unit 6 via the scanner ASIC 5 are performed.

  The controller ASIC 2 controls read / write to the hard disk 9, and the hard disk 9 stores various image data.

  The plotter unit 8 receives image data received by a host computer (not shown) or facsimile received or image data read by the scanner unit 6 from the plotter ASIC 7 in a predetermined printing method, for example, an electrophotographic method, and an image is generated based on the image data. Is printed on paper.

  The plotter ASIC 7 performs appropriate image processing on the image data received from the main CPU 3 and outputs the image data to the plotter unit 8.

  The main memory 4 is connected to the main CPU 3 and is composed of a RAM (Random Access Memory) or the like. The main memory 4 stores data such as image data to be processed, a program, a descriptor, and the like under the control of the main CPU 3, and as this program, the basic program as the image processing apparatus 1 and the data transfer of the present invention are efficiently performed. A data transfer control program for executing a data transfer control method performed automatically is stored.

  The image processing apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), and a DVD. A data transfer control program for executing the data transfer control method of the present invention recorded on a computer-readable recording medium such as a (Digital Video Disk), an SD (Secure Digital) card, or an MO (Magneto-Optical Disc) is read. Thus, it is constructed as an image processing apparatus including a data transfer control device that executes a data transfer control method for efficiently performing data transfer, which will be described later, by being introduced into the main memory 4 and the hard disk 9. This data transfer control program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. And can be distributed.

  The external IFASIC 10 is connected with a network 11 and an external device 12 as external device units, and the external IFASIC 10 exchanges data (packet data) between the network 11 and the external device 12. The network 11 is, for example, a LAN (Local Area Network), the Internet, or the like, and the external device 12 is an SD card, a USB device, or the like.

A main memory 4 is connected to the main CPU (data transfer control means) 3, and the main CPU 3 controls writing of data and the like to the main memory 4 and reading of data and descriptors from the main memory 4. That is, the image processing apparatus 1 performs data transfer by DMA (Direct Memory Access) using a PCIe bus, and the main CPU 3 has an internal buffer 3b (see FIG. 3) as will be described later, and the internal CPU 3 A plurality of data transfers using the buffer 3b are controlled .

  As shown in FIG. 2, the external IFASIC 10 includes external device controllers 20 to 50 for external devices to be connected, a PCIe controller 60 with the main CPU 3, an internal arbiter 70, and the like. Means) 20 to 50 are, for example, the network controller 20, the SD card controller 30, the USB controller 40, the IC card controller 50, and the like. Note that PCIe is an abbreviation for PCI (Peripheral Component Interconnect) Express, and in this embodiment, in order to explain in detail data transfer with the network 11 connected to the external IFASIC 10, FIG. The network controller 20 is a diagram showing the internal configuration in detail.

  The network controller 20 includes a DMAC (Direct Memory Access Controller) 20a, an internal buffer 20b, a network control unit 20c, and the like. The network control unit 20c is connected to the network 11 and the internal buffer 20b, and controls communication with the network 11. The internal buffer 20b is a buffer having a predetermined capacity, and is transferred data between the network control unit 20c and the DMAC 20a. Perform the buffer processing. The DMAC 20 a is connected to the internal arbiter 70, makes a data transfer request to the internal arbiter 70, and transfers data between the network 11 and the main memory 4. The external device controllers 30 to 50 have the same configuration as that of the network controller 20, and perform data transfer between the corresponding external device and the main memory 4 by performing processing similar to that of the network controller 20. Although not shown, the external device controllers 30 to 50 other than the network controller 20 also include a control unit and an internal buffer in addition to the DMACs 30a to 50a, as with the network controller 20.

  The internal arbiter (data transfer request control means) 70 includes a transfer request control unit 70a, and the transfer request control unit 70a arbitrates data transfer requests from the DMACs 20a to 50a of the controllers 20 to 50 in a round robin manner. The bus usage by the DMACs 20a to 50a of the controllers 20 to 50 is controlled.

  The PCIe controller 60 includes a PCIe end point 60a, and the PCIe end point (transfer interface means, data transfer status determination means) 60a is connected to the internal arbiter 70 and to the main CPU 3.

  As described above, the main memory 3 is connected to the main CPU 3, and is connected to the controller ASIC 2, the plotter ASIC 7, and the like. The main CPU 3 is usually provided with an arbiter, as shown in FIG. PCIe root complex 3a, and PCIe root complex 3a has an internal buffer 3b. Further, the PCIe end point 60a of the PCIe controller 60 has an internal buffer 60b as shown in FIG.

  The main CPU 3 and the external IFASIC 10 are connected by the PCIe 80, and the PCIe route complex 3a and the PCIe end point 60a are counterparts periodically (every predetermined reference time) by flow control defined in the transaction layer of the PCIe 80. The status (data amount etc.) of the internal buffers 3b and 60b is exchanged.

  When the internal arbiter 70 gives the right to use the bus to the controllers 20 to 50, the internal arbiter 70 executes a mask process for masking the right to use the bus of the controller 20 to 50 for a predetermined mask period. Further, the internal arbiter 70 cancels the mask set in the controllers 20 to 50 based on the status (data amount, etc.) of the internal buffer 3b provided in the PCIe root complex 3a of the main CPU 3, and determines whether or not the mask can be set. Perform mask control.

  Next, the operation of this embodiment will be described. The image processing apparatus 1 according to the present embodiment performs bus control by a round robin method and efficient control of mask processing.

In the following description, bus control with mask control in data transfer to the main memory 4 via the network controller 20 and the main CPU 3 in the internal arbiter 70 of the external IFASIC 10 will be described. However, the bus connected to the external IFASIC 10 The target device to be controlled is not limited to the network 11 and can be similarly applied to other external devices 12 such as an SD card and a USB device. In the following description, there is a data reception request from the network 11, the network controller 20 of the external IFASIC 10 makes a bus acquisition request to the internal arbiter 70, and DMAs the data to the main memory 4 via the main CPU 3 through the PCIe 80. The case of the transfer will be described. However, the bus is not limited to PCIe 80, and the data transfer control means, which is a part that executes the bus control on the main CPU 3 side, is equipped with an internal buffer, and the state of the internal buffer is predetermined. By acquiring at every interval, a bus with mask control according to the access status of the other device to the main memory 4 is obtained by grasping the status of other devices accessing the main memory 4 via the main CPU 3. It can be applied to control.

  When the image processing apparatus 1 receives a data reception request from the network 11, the network controller 20 of the external IFASIC 10 controls the data reception request by the network control unit 20 and stores necessary data in the internal buffer 20b. The DMAC 20a makes a bus acquisition request (transfer request) to the internal arbiter 70, and the internal arbiter 70 basically gives a bus use right in a round-robin manner to the bus acquisition requests from the controllers 20 to 50. Take control.

  The image processing apparatus 1 performs data transfer between the main memory 4 and each device by DMA transfer, for example, performs DMA data transfer between the network controller 20 and the main memory 4 as shown in FIGS. 4 and 5. Data write and data read to the memory are performed. That is, in the case of data write for writing data to the main memory 4, the DMAC 20a of the network controller 20 performs read transfer for reading the DMA descriptor on the main memory as shown in FIG. 4 (step S101), and the network control unit 20c. To perform network control and start data reception (step S102). When transfer data accumulates in the internal buffer 20b (step S103), the DMAC 20a performs write transfer of the DMA packet (step S104), and checks whether the packet end is transferred to the main memory 4 (step S105). When the packet end is not transferred to the memory, the DMAC 20a checks whether the descriptor is chained (step S107). When the descriptor is chained, the process returns to step S101 and performs the same processing as described above.

  When the packet end is transferred to the memory in step S105, the DMAC 20a writes the DMA descriptor to the main memory 4 and writes it back (step S106), and checks whether the descriptor is chained (step S107). When chaining descriptors in step S107, the process returns to step S101 to perform the same processing as described above from read transfer of memory descriptors (steps S101 to S107). If descriptor chaining is not performed in step S107, DMA write processing is performed. Exit.

  In the case of data read in which data on the main memory 4 is read and transferred to the network 11, the DMAC 20a first performs read transfer for reading the DMA descriptor on the main memory 4 (step S201), and based on the descriptor. Read transfer in which the DMA packet (data) on the main memory 4 is read and written to the internal buffer 20b is started (step S202). When the DMAC 20a starts read transfer of the DMA packet, the DMAC 20a performs network control, starts data transmission (step S203), and checks whether the packet end is transmitted to the network 11 (step S204). When the packet termination is not transmitted to the network 11, the DMAC 20a checks whether there is a space in the internal buffer 20b (step S206). If there is no space in the internal buffer 20b, the DMAC 20a returns to step S203 and continues receiving data. When the end of the packet is transmitted to the network NW in step S204, the descriptor is written back in the DMA descriptor tally transfer (step S205), and it is checked whether the internal buffer is free (step S206).

  If there is no free space in the internal buffer in step S206, the process returns to step S203 to transfer data to the network 11 in the same manner as described above (steps S203 to S206). If the internal buffer is free in step S206, the descriptor is chained. It is checked whether to do (step S207). When chaining descriptors in step S207, the DMAC 20a returns to step S201 and performs the same processing as described above from the read transfer of the descriptor in the main memory 4 (steps S201 to S207), and does not perform descriptor chaining in step S207. Sometimes, the DMA read process ends.

  That is, in DMA transfer, data transfer is performed by repeatedly performing operation processes such as descriptor read, data read, data write, and descriptor write.

  The DMAC 20a of the network controller 20 makes a bus acquisition request to the internal arbiter 70 every time this operation process is accessed, and the data from the network 11 is transferred to the internal buffer 20b until the bus use right is given and data transfer is started. A transfer wait occurs that is stored and waited.

  The descriptor used in this DMA transfer is generally formatted as shown in FIG. 6, and includes a next descriptor address, a transfer address, a transfer size, and DMA control / packet information. The next descriptor address stores the address of the descriptor to be read next on the main memory 4, and “0x0” indicates that there is no descriptor to be read next. The transfer address stores the data storage destination on the main memory 4, and the transfer size stores the amount of data transferred to the main memory 4. In the DMA control, control information for temporarily stopping the DMA or generating an interrupt is stored, and the packet information is an area in which the DMA writes to indicate the end of the packet. This descriptor has a small data amount of 128 bits, and the influence of the descriptor transfer on the bus bandwidth is very small.

  On the other hand, in bus control, not only the network 11 and the external device 12 connected to the external IFASIC 10 but also the device that accesses the main memory 4 via the main CPU 3 is preferentially secured to use the bus as the image processing apparatus 1. There are necessary data transfer from the scanner unit 6 and data transfer to the plotter unit 8 (hereinafter referred to as priority data transfer as required), and the use of the PCIe bus 80 of the main CPU 3 is used for such priority data transfer. It must be prioritized.

  Therefore, when the internal arbiter 70 of the external IFASIC 10 gives the bus use right to the network controller 20 and other external driver controllers 30 to 50 for only one round robin and the use of the bus use right is completed, it is shown in FIG. As described above, the bus acquisition requests (transfer requests) from the DMACs 20a to 50a of the controllers 20 to 50 to which the bus use right is given are masked for a certain period (100 clocks in FIG. 7).

  However, as described above, when the bus use right is given and the one round period ends, and the mask process of masking only the mask period when the bus use is completed is performed, the control of ignoring the use status of the PCIe 80 of the main CPU 3 is ignored. Therefore, efficient bus control cannot be performed.

  Therefore, the internal arbiter 70 of the external IFASIC 10 uses the exchange function of the internal buffer status of the opposite device by the flow control defined in the PCIe transaction layer, as shown in FIG. As for the usage status, the status (data amount, etc.) of the internal buffer 3b provided in the PCIe root complex 3a of the main CPU 3 is grasped, and the control ASIC 2, the plotter ASIC 7, etc., which are other devices, are determined from the status of the internal buffer 3b. The CPU 3 judges the usage status of the PCIe bus and performs mask control on the external devices 20 to 50 such as the network controller 20.

  Further, when a bus acquisition request is generated, the internal arbiter 70 determines the influence of the bus acquisition request on the bus bandwidth based on the content of the bus acquisition request, and performs mask control. The internal arbiter 70 performs mask control by determining the influence on the bandwidth of the PCIe bus based on the amount of transfer data and the type of bus acquisition request. For example, as described above, since the descriptor has a small data amount of 128 bits, if the bus acquisition request is a read request or write request for the descriptor, the descriptor is controlled so as not to be masked or the mask already applied is set. Mask control is performed to control the release.

  That is, as shown in FIG. 8, the internal arbiter 70 gives a bus use right only for one round robin period in response to a bus acquisition request from the DMAC 20a of the network controller 20, and when the bus use ends, the mask period ( In FIG. 7, FIG. 9, and FIG. 10, "100" clock period) is set in the mask period counter (step S301), the mouse period counter starts counting down (step S302), and then a transfer request is sent from the DMAC 20a. If there is a bus acquisition request, it is checked whether the bus acquisition request is a bus acquisition request related to descriptor read or descriptor write (step S303). That is, the DMAC 20a of the network controller 20 adds information (control signal or the like) indicating the type of the transfer request to a normal bus acquisition request (transfer request) and inputs the request to the internal arbiter 70.

  In step S303, if the bus acquisition request is a request for a descriptor, it is determined that the bus use bandwidth is narrow, and the internal arbiter 70 clears the mask period counter to “0” as shown in FIG. A bus use right is granted to the bus acquisition request (step S304), transfer is permitted, and when transfer by the bus use right is completed, the process returns to step S301 to perform the same processing as described above. In FIG. 9, when REQ1, which is a transfer request from the DMAC 20a, is a descriptor, the mask period counter is set to “100”, counted down to “99”, cleared to “0”, and transferred. The state where permission (bus use right) is given is shown.

  In step S303, when the transfer request is not a descriptor, for example, when the request is a data read or data write transfer request, the internal arbiter 70 determines that the amount of data is large, and sets the bus bandwidth to the PCIe bus memory bandwidth of the main CPU 3. It is checked whether there is enough space for granting the bus use right to the acquisition request (step S305). Note that checking whether there is sufficient space in the memory bandwidth will be described later.

  When there is sufficient free memory bandwidth in step S305, the internal arbiter 70 clears the mask period counter to “0” as shown in FIG. 10, and gives the bus use right to the bus acquisition request. (Step S304) When transfer is permitted and transfer by the right to use the bus is completed, the process returns to Step S301 to perform the same processing as described above.

  If there is not enough free memory bandwidth in step S305, the internal arbiter 70 checks whether the mask period counter is “0”, that is, whether the mask period has passed (step S306), and the mask period has passed. If not, as shown in FIG. 7, the process returns to step S302 without releasing the mask, and the same processing as described above is performed from the countdown of the mask period counter (steps S302 to S306).

  If the mask period counter is “0” in step S306, the internal arbiter 70 determines that the mask period has passed, grants a bus use right to the bus acquisition request (step S304), and permits transfer. When the transfer with the bus use right is completed, the process returns to step S301 and the same processing as described above is performed.

  Whether or not the memory bandwidth of the PCIe bus of the main CPU 3 has enough space to give a bus use right in response to a bus acquisition request depends on the status of the internal buffer 3b of the PCIe root complex 3a of the main CPU 3. Judgment based on. That is, the internal arbiter 70 of the external IFASIC 10 utilizes the function of exchanging the status of the internal buffer 3b of the opposite device by flow control defined in the PCIe transaction layer, as shown in FIG. Is used, the status (data amount, etc.) of the internal buffer 3b of the PCIe root complex 3a of the main CPU 3 is grasped. For example, the PCIe end point 60a acquires and stores the internal buffer state of the PCIe root complex 3a of the main CPU 3 at a certain flow control processing time by flow control, and stores the next flow control processing in the next flow control processing. The status of the internal buffer 3b of the PCIe root complex 3a at the time is acquired. The PCIe end point 60a obtains the amount of change between the status of the internal buffer 3b of the PCIe route complex 3a acquired at the time of the current flow control process and the status of the internal buffer 3b at the time of the previous flow control. Is compared with a preset change threshold value, and the data transfer process progress status is determined as to whether the data transfer process using the PCIe bus has progressed during the flow control process interval. For example, when the amount of change is larger than the change threshold, the transfer request control unit 70a does not generate data transfer involving the scanner unit 6 or the plotter unit 8 and smoothly transfers data from the main CPU 3 to the main memory 4. If the change amount is smaller than the change threshold value, it can be determined that the data transfer related to the scanner unit 6 and the plotter unit 8 frequently occurs. Note that the amount of change in the state of the internal buffer 3b of the PCIe root complex 3a is not limited to the amount of change between successive flow control processes, but the internal amount at the time of the flow control process at a predetermined number of flow control processing intervals. It may be the amount of change in the status of the buffer 3b.

  Then, the PCIe end point 60a passes the determination result to the internal arbiter 70, and the internal arbiter 70 determines whether or not there is sufficient space in the memory band based on the determination result in step S305.

  In the process of FIG. 8, the mask is released based on whether the transfer request (bus acquisition request) is a transfer request related to a descriptor and whether there is sufficient free memory bandwidth. The mask may be canceled based on the data amount (transfer request data amount) requested by the transfer request (bus acquisition request). In this case, the internal arbiter 70 acquires the transfer request data amount from the bus acquisition request from the DMAC 20a, compares the acquired transfer request data amount with a preset data threshold, and the transfer request data amount exceeds the data threshold. The mask is released only when there are few, and the right to use the bus is set according to the bus acquisition request.

  When the amount of data in the internal buffer 3b of the PCIe root complex 3a is smaller than a predetermined amount, the internal arbiter 70 permits a bus acquisition request for a small amount of data and transfers the data from the internal buffer 3b. The situation may be monitored by flow control, the mask may be released based on the monitoring result, and a bus use right may be granted to permit data transfer with a large amount of data.

As described above, the image processing apparatus 1 according to the present embodiment includes the internal buffer 3b and requests for bus acquisition (data transfer request) via the PCIe route complex 3a that controls a plurality of data transfers using the internal buffer 3b. However, if there are a plurality of DMACs 20a to 50a, the data transfer request is controlled to permit / non-permit data transfer for a predetermined transfer period fairly, and the permitted data transfer determines the transfer period. When the time elapses, the data amount of the internal buffer 3b of the PCIe root complex 3a is set for each predetermined reference time (for each flow control) when controlling mask processing for disallowing data transfer requests from the DMACs 20a to 50a for a predetermined mask period. ) And the PCIe route comp based on the data amount of the acquired internal buffer 3b. It determines the data transfer status by box 3a, and controls the masking process based on the determination result.

  Therefore, the mask processing for masking the data transfer request by the source of the bus acquisition request (data transfer request) for which the data transfer in the round robin method has been completed can be controlled by grasping the data transfer status, and inexpensively. More efficient round robin data transfer can be performed.

  Further, the image processing apparatus 1 according to the present embodiment controls the mask processing based on the transfer load applied to the data transfer in the PCIe root complex 3a in response to the data transfer request from the DMACs 20a to 50a.

  Therefore, it is possible to more appropriately grasp and control the data transfer status, and it is possible to perform data transfer by a round robin method that is cheaper and more efficient.

  Furthermore, the image processing apparatus 1 of this embodiment determines the magnitude of the transfer load based on the amount of transfer data requested by the data transfer request.

  Therefore, it is possible to more appropriately grasp and control the data transfer status, and it is possible to perform data transfer by a round robin method that is cheaper and more efficient.

Further, in the image processing apparatus 1 according to the present embodiment, the PCIe root complex 3a controls data transfer by DMA data transfer, the data transfer request is a DMA data transfer request, and the transfer load is set to DMA data. transfer request is determined by whether the data transfer request is a descriptor transfer request.

  Therefore, round robin data transfer in DMA data transfer can be performed at low cost and efficiently.

  Further, in the image processing apparatus 1 of the present embodiment, the internal arbiter 70 performs mask setting control as to whether or not to set a mask based on a data transfer request from the DMACs 20a to 50a and cancels the mask period of the set mask. Whether or not to perform masking period control is performed.

  Therefore, it is possible to perform pre-control of mask setting and control of the set mask period, and it is possible to perform data transfer in a round robin manner more appropriately and efficiently.

  In the above-described embodiment, the case where the present invention is applied to the image processing apparatus 1 such as a composite apparatus or a copying apparatus that performs scanner processing and plotter processing has been described. However, the data transfer apparatus is not limited to the image processing apparatus. The present invention can be generally applied to a device that performs data transfer in a round robin manner.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention is used in a data transfer control device, an image processing device, a data transfer control method, a data transfer control program, and a recording medium that perform data transfer in a round robin manner and prioritize transfer of an intended device by performing mask processing. can do.

1 Image processing device 2 Controller ASIC
3 Main CPU
3a PCIe root complex 3b internal buffer 4 main memory 5 scanner ASIC
6 Scanner unit 7 Plotter ASIC
8 Plotter section 9 Hard disk (HDD)
10 External IFASIC
11 Network 12 External Device 20 Network Controller 20a DMAC
20b Internal buffer 20c Network control unit 30-50 External device controller 30a-50a DMAC
60 PCIe controller 60a PCIe end point 60b internal buffer 70 internal arbiter 70a transfer request control unit 80 PCIe

Japanese Patent No. 4024484

Claims (9)

Storage means;
Is connected to the storage means, having a first internal buffer, and the data transfer control means for controlling data transfer by using the first internal buffer,
A plurality of data transfer request means for making a data transfer request related to data transfer with the outside ;
To the data transfer request from any one of said plurality of data transfer request means, the data transfer request control means for controlling that the data transfer request for a predetermined period allowed or disallowed,
The data transfer control means and connected by a bus to a data transfer control device and a transfer interface means having a second internal buffer and stores the acquired data amount of said first internal buffer,
The data transfer request control means, when the external data transfer request is a request related to data transfer with the storage means, indicates the availability of the first internal buffer in the second internal buffer. Judgment is made based on the change amount of the first internal buffer acquired and stored, and when it is determined that the free space of the first internal buffer is sufficient, the data transfer request is permitted and the storage means The data transfer control device is configured to transfer the data between the first and second data via the transfer interface means, and disallow the data transfer request when it is determined that the free space of the first internal buffer is not sufficient. . 2. The data transfer control device according to claim 1, wherein the data transfer request control means compares the change amount of the first internal buffer with a preset change threshold value, and as a result, the change amount is greater than the change threshold value. determines that the free space is sufficient when large, the amount of change features and to Lud over data transfer control device that determines that the free space is not enough when less than the variation threshold. 3. The data transfer control device according to claim 1, wherein the data transfer request control means sends the data transfer request from the data transfer request means for a predetermined mask period when the permitted data transfer has passed a predetermined transfer period. only disallowed to masking the data transfer control means and the data transfer characteristics and to Lud over data transfer control device to control based on the magnitude of the transfer load on the at. 4. The data transfer control device according to claim 3, wherein the data transfer request control means determines the magnitude of the transfer load based on a transfer data amount requested by the data transfer request from the data transfer request means. features and to Lud over data transfer control device. 4. The data transfer control device according to claim 3, wherein said data transfer control means controls data transfer by DMA data transfer, said data transfer request means makes a DMA data transfer request as said data transfer request, and said data transfer request control means, the transfer load of the size of the DMA data transfer request features and to Lud over data transfer control device be determined by whether the data transfer request is a descriptor transfer request. 6. The data transfer control device according to claim 3, wherein the data transfer request control unit determines whether to set the mask processing based on the data transfer request from the data transfer request unit. mask setting control and the set features and to Lud over data transfer control device that performs whether mask period control to release the mask period of the mask processing. A data transfer control processing step for controlling data transfer using the first internal buffer by the data transfer control means connected to the storage means and having the first internal buffer;
A plurality of data transfer request processing steps for performing a data transfer request related to data transfer with the outside by a plurality of data transfer request means;
A data transfer request control processing step for performing a control for permitting or not permitting the data transfer request for a predetermined period with respect to the data transfer request from any of the plurality of data transfer requesting means by a data transfer request controlling means; ,
A transfer interface processing step of acquiring and storing a data amount of the first internal buffer by a second internal buffer of the transfer interface means connected by bus to the data transfer control means,
In the data transfer request control processing step, when the external data transfer request is a request related to data transfer with the storage unit, the availability of the first internal buffer is determined as the second internal buffer. The storage means permits the data transfer request when it is determined based on the change amount of the first internal buffer acquired and stored in step S1 and when it is determined that the free space of the first internal buffer is sufficient. Data transfer control , wherein the data transfer request is not permitted when it is determined that the first internal buffer has insufficient free space. Way . A data transfer control program executed by a computer,
A procedure of a data transfer control processing step for controlling data transfer using the first internal buffer by the data transfer control means connected to the storage means and having the first internal buffer;
A plurality of data transfer request processing steps for performing a data transfer request related to data transfer with the outside by a plurality of data transfer request means;
A data transfer request control means for performing a control for permitting or not permitting the data transfer request for a predetermined period in response to the data transfer request from any of the plurality of data transfer request means. Procedure and
A transfer interface processing step for acquiring and storing a data amount of the first internal buffer by a second internal buffer of the transfer interface means connected by bus to the data transfer control means, and
In the procedure of the data transfer request control processing step, when the external data transfer request is a request related to data transfer with the storage means, the free state of the first internal buffer is set to the second state. Judgment is made based on the change amount of the first internal buffer acquired and stored in the internal buffer, and when the free space of the first internal buffer is determined to be sufficient, the data transfer request is permitted and the the data between the storage means and transferred through said transfer interface unit, characterized in that the free space of the first internal buffer is not permitted to the data transfer request when it is determined that not enough data Transfer control program . 9. A recording medium in which the procedure of each step in the data transfer control program according to claim 8 is recorded so as to be readable by a computer.

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