JP5278323B2 - Manufacturing method of high brightness light emitting diode - Google Patents

Manufacturing method of high brightness light emitting diode Download PDF

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JP5278323B2
JP5278323B2 JP2009529974A JP2009529974A JP5278323B2 JP 5278323 B2 JP5278323 B2 JP 5278323B2 JP 2009529974 A JP2009529974 A JP 2009529974A JP 2009529974 A JP2009529974 A JP 2009529974A JP 5278323 B2 JP5278323 B2 JP 5278323B2
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政孝 渡辺
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    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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Description

本発明は、高輝度発光ダイオードを製造する方法および発光素子基板並びに高輝度発光ダイオードに関するものである。
The present invention relates to a method of manufacturing a high brightness light emitting diode, a light emitting element substrate, and a high brightness light emitting diode.

近年、発光ダイオードの高輝度化が研究されており、発光層全域での発光と側面からの光取り出し効率を飛躍的に向上させるため、電流拡散層が厚膜化されている。図11は、光吸収タイプの高輝度発光ダイオードの断面を示した概略図である。この高輝度発光ダイオード51は、GaAs基板52上に4元発光層53、接続層54’、電流拡散層54を有しており、特に従来の電流拡散層の厚さが約8μmだったのに対して、高輝度発光ダイオードの電流拡散層54は約50〜150μmの厚膜を有する。これにより従来の発光ダイオードに比べて、約2倍以上の高輝度化が図れる。また、この図11の光吸収タイプの高輝度発光ダイオード51は、以下のようにして製造される。   In recent years, research on increasing the brightness of light emitting diodes has been conducted, and in order to dramatically improve the light emission in the entire light emitting layer and the light extraction efficiency from the side surface, the current diffusion layer is made thicker. FIG. 11 is a schematic view showing a cross section of a light-absorbing type high-intensity light-emitting diode. This high-intensity light-emitting diode 51 has a quaternary light-emitting layer 53, a connection layer 54 ′, and a current diffusion layer 54 on a GaAs substrate 52, especially when the thickness of the conventional current diffusion layer is about 8 μm. On the other hand, the current diffusion layer 54 of the high-intensity light emitting diode has a thick film of about 50 to 150 μm. As a result, the brightness can be increased by about twice or more compared to the conventional light emitting diode. Further, the light absorption type high-intensity light-emitting diode 51 of FIG. 11 is manufactured as follows.

先ず、有機金属化学気相成長(Metal−Organic Chemical Vapor Deposition:MOCVD)のリアクター内にてGaAs基板52の上に4元系の化合物半導体(例えばAlGaInP)で構成される発光層53をエピタキシャル成長させ、その上に電流拡散層54を成長させるための接続層54’をヘテロエピタキシャル成長させ、取り出す。続いてハイドライド気相成長(Hydride Vapor Phase Epitaxy:HVPE)のリアクター内に入れ、接続層54’の上に光取り出し用の窓であるGaP等の電流拡散層54をホモエピタキシャル成長させ、そして、真空蒸着法により光取出し側電極56及び裏面電極57を取付けてチップ化する。   First, a light emitting layer 53 composed of a quaternary compound semiconductor (for example, AlGaInP) is epitaxially grown on a GaAs substrate 52 in a reactor of metal-organic chemical vapor deposition (MOCVD), A connection layer 54 ′ for growing the current diffusion layer 54 is heteroepitaxially grown thereon and taken out. Subsequently, it is placed in a reactor of hydride vapor phase epitaxy (HVPE), a current diffusion layer 54 such as GaP as a light extraction window is homoepitaxially grown on the connection layer 54 ', and vacuum deposition is performed. The light extraction side electrode 56 and the back surface electrode 57 are attached by the method to form a chip.

このように製造された高輝度発光ダイオード51は、4元発光層53の発光波長域においてGaAs基板52の光吸収が大きいため、光吸収タイプの高輝度発光ダイオードとして知られている。   The high-intensity light-emitting diode 51 manufactured in this way is known as a light-absorption type high-intensity light-emitting diode because the light absorption of the GaAs substrate 52 is large in the emission wavelength region of the quaternary emission layer 53.

一方、光透過タイプの高輝度発光ダイオードは、光吸収タイプの高輝度発光ダイオード51と同じ製造方法で、第一の電流拡散層54を形成した後、GaAs基板52をエッチング液で除去した後、GaAs基板52を除去した面に、第二の電流拡散層をヘテロエピタキシャル成長させ形成する。その後、電極を付けてチップに加工して光透過タイプの高輝度発光ダイオードを得る。このように製造された光透過タイプの高輝度発光ダイオードは、発光素子側面のみならず透明基板側からの光の取り出し効果を上げている(米国特許第5008718号明細書)。   On the other hand, the light transmission type high-intensity light emitting diode is manufactured by the same manufacturing method as the light absorption type high-intensity light emitting diode 51, and after forming the first current diffusion layer 54, the GaAs substrate 52 is removed with an etching solution. A second current diffusion layer is heteroepitaxially grown on the surface from which the GaAs substrate 52 has been removed. Then, an electrode is attached and processed into a chip to obtain a light-transmitting high-intensity light-emitting diode. The light-transmitting high-intensity light-emitting diode manufactured as described above has an effect of extracting light not only from the side surface of the light-emitting element but also from the transparent substrate side (US Pat. No. 5,0087,18).

しかし、このような光透過タイプの高輝度発光ダイオードにおいて、GaAs基板を除去した面に第二の電流拡散層を形成する際に、格子のズレ量が大きくなると生じる格子歪による応力が原因で、エピタキシャル中の成長膜が破壊されてしまう問題がある。   However, in such a light transmissive type high-intensity light emitting diode, when the second current diffusion layer is formed on the surface from which the GaAs substrate is removed, due to the stress due to lattice strain that occurs when the amount of lattice displacement increases, There is a problem that the growth film in the epitaxial layer is destroyed.

また、GaAs基板を除去した面に第二の電流拡散層を形成する際に、格子のズレ量が大きくなると生じる格子不整合が原因で、成長初期段階の界面に略球形で直径が数十nm〜数μmのマイクロ穴欠陥ができてしまい、このマイクロ穴欠陥により、部分的に接合不良が発生してしまうため問題となる。
In addition, when forming the second current diffusion layer on the surface from which the GaAs substrate has been removed, due to lattice mismatch that occurs when the amount of lattice misalignment increases, the interface at the initial stage of growth is substantially spherical and has a diameter of several tens of nanometers. A micro-hole defect of ˜several μm is formed, and this micro-hole defect causes a problem of partial bonding failure.

本発明はこのような問題点に鑑みてなされたもので、高輝度発光ダイオードの製造方法において、GaAs基板を除去した面に、第二の電流拡散層を形成する際に起こる、エピタキシャル中の成長膜の破壊を防ぎ、成長初期段階の界面に発生するマイクロ穴欠陥を抑えることができる高輝度発光ダイオードの製作を目的とする。   The present invention has been made in view of such problems, and in the method of manufacturing a high-intensity light emitting diode, the growth during epitaxial that occurs when the second current diffusion layer is formed on the surface from which the GaAs substrate has been removed. An object of the present invention is to manufacture a high-intensity light-emitting diode capable of preventing film breakage and suppressing micro-hole defects generated at the interface at the initial stage of growth.

上記課題を解決するために、本発明は、少なくとも、GaAs基板の第一主表面側上に4元発光層をエピタキシャル成長により形成する工程と、該4元発光層上に第一の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、前記GaAs基板を除去する工程と、前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、得られた基板をチップに加工する工程、とを行う高輝度発光ダイオードの製造方法において、
前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程は、供給する原料ガスの形成当初のIII/V比を3以上にし、その後前記III/V比が相対的に低くなるように変化させ、第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程とし、該工程において前記形成当初のIII/V比を3以上にして第二の電流拡散層を形成する時の成長温度を、III/V比を相対的に低くして成長する時の温度よりも、低温域である550℃〜700℃、III/V比を5以上にする場合は550℃〜730℃の範囲内の温度として成長を開始し、その後III/V比を相対的に低くして成長する時の温度と同じ温度まで昇温させることを特徴とする高輝度発光ダイオードの製造方法を提供する。
In order to solve the above-described problems, the present invention provides at least a step of forming a quaternary light emitting layer on the first main surface side of a GaAs substrate by epitaxial growth, and a first current diffusion layer on the quaternary light emitting layer. A step of forming a group III-V compound semiconductor by HVPE growth, a step of removing the GaAs substrate, and forming a group III-V compound semiconductor by HVPE growth as a second current diffusion layer on the surface from which the GaAs substrate has been removed. And a method of manufacturing a high-intensity light-emitting diode that performs a process of processing the obtained substrate into a chip,
The step of forming a group III-V compound semiconductor as a second current diffusion layer on the surface from which the GaAs substrate has been removed by HVPE growth has an initial III / V ratio of 3 or more, and then III / V ratio is changed so as to be relatively low, and a III-V compound semiconductor is formed as a second current diffusion layer by HVPE growth, and the initial III / V ratio is 3 or more in this step. Thus, the growth temperature when forming the second current diffusion layer is 550 ° C. to 700 ° C., which is a lower temperature range than the temperature when growing with a relatively low III / V ratio, and the III / V ratio. When the temperature is 5 or more, the growth is started at a temperature in the range of 550 ° C. to 730 ° C., and then the temperature is raised to the same temperature as that at the time of growth with a relatively low III / V ratio. High To provide a method of manufacturing a degree emitting diode.

ここで、前記供給する原料ガスの形成当初のIII/V比を、3より高くし、前記第二の電流拡散層を形成する時の成長温度を、550℃〜700℃の範囲内の温度とすることができる。   Here, the initial III / V ratio of the source gas to be supplied is made higher than 3, and the growth temperature when forming the second current diffusion layer is set to a temperature within a range of 550 ° C. to 700 ° C. can do.

光透過タイプの高輝度発光ダイオードの製造において、GaAs基板を除去した面に、第二の電流拡散層を成長する際に、格子のズレ量が大きくなると生じる格子歪による応力が原因で、エピタキシャル中の成長膜が破壊されてしまう問題がある。特に原料ガスの供給口から離れた位置で製造された基板ほど、成長膜が破壊され、マイクロ穴欠陥が生じてしまう傾向が強い。従って、上記問題は、第二の電流拡散層の形成過程で、電流拡散層の原料ガスであるIII族ガスの欠乏が理由と考えられる。
そこで、形成当初のIII/V比を3以上、より好ましくは3より高くし、III族ガスがすべての基板に十分行き渡った状態で、III/V比を相対的に低くすることで、上記問題が解決され、成長膜の破壊を防止することができる。
このように、本発明の当該製造方法により、原料ガスの供給口から離れた位置で製造された基板でも成長膜の破壊を抑えることができ、高品質な高輝度発光ダイオードを製造することができる。
In the manufacture of light-transmitting high-intensity light-emitting diodes, during growth of the second current diffusion layer on the surface from which the GaAs substrate has been removed, stress due to lattice strain that occurs when the amount of lattice displacement increases causes There is a problem that the growth film is destroyed. In particular, the substrate manufactured at a position away from the supply port of the source gas has a strong tendency to destroy the growth film and cause a microhole defect. Therefore, it is considered that the above problem is caused by the lack of the group III gas that is the source gas of the current diffusion layer in the process of forming the second current diffusion layer.
Therefore, the above problem is solved by setting the III / V ratio at the initial stage to 3 or more, more preferably higher than 3, and making the III / V ratio relatively low in a state where the group III gas is sufficiently distributed to all the substrates. Is solved, and the destruction of the growth film can be prevented.
As described above, according to the manufacturing method of the present invention, it is possible to suppress the destruction of the growth film even on the substrate manufactured at a position away from the supply port of the source gas, and it is possible to manufacture a high-quality high-intensity light-emitting diode. .

また、光透過タイプの高輝度発光ダイオードの製造において、GaAs基板を除去した面に第二の電流拡散層を形成する際に、格子のズレ量が大きくなると生じる格子不整合が原因で、成長初期段階の界面にマイクロ穴欠陥ができてしまい、このマイクロ穴欠陥により、部分的に接合不良が発生してしまうため問題となる。
しかし、形成当初のIII/V比を3以上、より好ましくは3以上にした状態で、後のIII/V比を相対的に低くして成長するときの温度(例えば750℃)に昇温する途中の550〜700℃、III/V比を5以上にする場合は550℃〜730℃といった低温域の温度で成長を開始することで、格子のズレ量を小さくし、マイクロ穴欠陥の発生を抑えることができる。また、成長開始温度を下げることにより線膨張率差による反りを軽減することもできる。
その結果、部分的な接合不良を抑えた電流拡散層を形成することができ、チップ工程での基板割れも防止することができる。それは、原料ガスの供給口から離れた位置で製造された基板でも同様の効果が得られる。
Also, in the manufacture of light-transmitting high-intensity light-emitting diodes, when the second current diffusion layer is formed on the surface from which the GaAs substrate is removed, the initial growth is caused by a lattice mismatch that occurs when the amount of lattice displacement increases. A micro-hole defect is formed at the interface at the stage, and this micro-hole defect causes a problem in that a partial bonding failure occurs.
However, with the III / V ratio at the beginning of formation being 3 or more, more preferably 3 or more, the temperature is raised to a temperature (for example, 750 ° C.) for growth with a relatively low III / V ratio. In the middle of 550 to 700 ° C., when the III / V ratio is 5 or more, start growth at a low temperature range of 550 ° C. to 730 ° C., thereby reducing the amount of lattice misalignment and generating micro hole defects. Can be suppressed. Further, the warp due to the difference in linear expansion coefficient can be reduced by lowering the growth start temperature.
As a result, it is possible to form a current diffusion layer that suppresses partial bonding failure, and it is possible to prevent substrate cracking in the chip process. The same effect can be obtained even with a substrate manufactured at a position away from the source gas supply port.

この場合、前記成長させる第一、第二の電流拡散層を、GaPまたはGaAsP窓層とすることができる。   In this case, the first and second current diffusion layers to be grown can be GaP or GaAsP window layers.

このように電流拡散層としては、GaPまたはGaAsPとすることができ、高輝度とすることができる。   As described above, the current diffusion layer can be made of GaP or GaAsP and can have high luminance.

この場合、前記形成当初のIII/V比を3以上にする方法を、III/V比を相対的に低くする時よりも、V族原料ガスの供給量を少なくすることにより、III/V比を相対的に高くすることが好ましい。   In this case, the method of setting the initial III / V ratio to 3 or more reduces the III / V ratio by lowering the supply amount of the group V source gas than when the III / V ratio is relatively low. Is relatively high.

III族原料ガスの供給量を一定にし、V族原料ガスの供給量を少なくすることで、原料濃度を下げて、III/V比が高い環境を整えることができ、成長膜の破壊を防止し、マイクロ穴欠陥の発生を抑えることができる。また、高III/V比の電流拡散層が形成された後、V族原料ガスの割合を上げることにより、高速成長させることができ、生産性が良く、急激な成長で格子緩和を促進して、反りが小さく、割れにくい電流拡散層を備えた高輝度発光ダイオードを製造することができる。   By keeping the supply amount of Group III source gas constant and reducing the supply amount of Group V source gas, it is possible to reduce the concentration of the source material and prepare an environment with a high III / V ratio, and prevent the growth film from being destroyed. The occurrence of micro hole defects can be suppressed. Also, after the formation of a current diffusion layer with a high III / V ratio, it is possible to grow at a high speed by increasing the proportion of the group V source gas, which is good in productivity and promotes lattice relaxation by rapid growth. In addition, a high-intensity light emitting diode having a current diffusion layer that has a small warpage and is difficult to break can be manufactured.

また、本発明では、少なくとも、4元発光層と第一、第二の電流拡散層とからなる発光素子基板であって、前記第二の電流拡散層の界面における直径1μm以上のマイクロ穴欠陥数が200個未満/cm、好ましくは80個/cm未満、より好ましくは0個/cmであることを特徴とする発光素子基板が得られる。   According to the present invention, there is also provided a light emitting element substrate including at least a quaternary light emitting layer and first and second current diffusion layers, and the number of microhole defects having a diameter of 1 μm or more at the interface of the second current diffusion layer. Is less than 200 / cm, preferably less than 80 / cm, and more preferably 0 / cm, whereby a light-emitting element substrate is obtained.

このように、例えば、4元発光層と第一、第二の電流拡散層とからなる発光素子基板において、第二の電流拡散層の界面における直径1μm以上のマイクロ穴欠陥数が200個未満/cm、好ましくは80個/cm未満、より好ましくは0個/cmである発光素子基板であれば、接合不良のない高品質な発光素子基板となる。   Thus, for example, in a light emitting element substrate composed of a quaternary light emitting layer and first and second current diffusion layers, the number of microhole defects having a diameter of 1 μm or more at the interface of the second current diffusion layer is less than 200 / A light-emitting element substrate having a cm of preferably less than 80 / cm, more preferably 0 / cm, is a high-quality light-emitting element substrate having no bonding failure.

さらに、本発明では、少なくとも、4元発光層と第一、第二の電流拡散層とからなる発光ダイオード素子であって、前記第二電流拡散層界面における直径1μm以上のマイクロ穴欠陥数が200個未満/cm、好ましくは80個/cm未満、より好ましくは0個/cmであることを特徴とする高輝度発光ダイオード素子が得られる。   Furthermore, the present invention is a light emitting diode element comprising at least a quaternary light emitting layer and first and second current diffusion layers, wherein the number of microhole defects having a diameter of 1 μm or more at the interface of the second current diffusion layer is 200. A high-intensity light-emitting diode element characterized in that the number is less than 80 / cm, preferably less than 80 / cm, more preferably 0 / cm is obtained.

このように、例えば、4元発光層と第一、第二の電流拡散層とからなる発光ダイオード素子において、第二電流拡散層界面における直径1μm以上のマイクロ穴欠陥数が200個未満/cm、好ましくは80個/cm未満、より好ましくは0個/cmであることを特徴とする高輝度発光ダイオード素子であれば、接合不良がなく、良好なVf値やライフ特性を持つ高輝度発光ダイオード素子となる。   Thus, for example, in a light emitting diode element composed of a quaternary light emitting layer and first and second current diffusion layers, the number of microhole defects having a diameter of 1 μm or more at the interface of the second current diffusion layer is less than 200 / cm, A high-intensity light-emitting diode element that has a good Vf value and life characteristics without a defective junction, as long as the high-intensity light-emitting diode element is preferably less than 80 / cm, more preferably 0 / cm It becomes.

このような本発明の高輝度発光ダイオードの製造方法であれば、GaAs基板を除去した面に第二の電流拡散層を成長する際に、エピタキシャル中の成長膜の破壊を効果的に防止し、成長初期段階の界面に発生してしまうマイクロ穴欠陥を効果的に抑えることができ、これは原料ガスの供給口から離れた位置で製造された基板でも同様の効果が得られるため、高品質な高輝度発光ダイオードを高い生産性で製造することができる。
With such a method of manufacturing a high-intensity light emitting diode of the present invention, when the second current diffusion layer is grown on the surface from which the GaAs substrate has been removed, it is possible to effectively prevent the growth film from being destroyed during the epitaxial process. Micro-hole defects that occur at the interface at the initial stage of growth can be effectively suppressed, and the same effect can be obtained even with a substrate manufactured at a position away from the source gas supply port. A high-intensity light emitting diode can be manufactured with high productivity.

本発明に係る高輝度発光ダイオードの製造方法を工程順に示した概念図である。It is the conceptual diagram which showed the manufacturing method of the high-intensity light emitting diode which concerns on this invention in process order. 実施例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。A substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film at (a) upstream, (b) intermediate flow, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Example 1 It is an observation photograph of the surface. 比較例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。A substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 1 It is an observation photograph of the surface. 比較例2における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。A substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 2 It is an observation photograph of the surface. 比較例3における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。The substrate of the high-intensity light-emitting diode obtained by forming the n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 3 It is an observation photograph of the surface. 実施例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡で500倍に拡大したn層界面の観察写真である。A substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film at (a) upstream, (b) intermediate flow, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Example 1 It is the observation photograph of the n layer interface expanded 500 times with the color laser microscope. 比較例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡で500倍に拡大したn層界面の観察写真である。A substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 1 It is the observation photograph of the n layer interface expanded 500 times with the color laser microscope. 比較例2における、n型GaP窓層の原料ガスの供給口からみて上流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡で500倍に拡大したn層界面の観察写真である。In Comparative Example 2, the n-layer interface magnified 500 times with a color laser microscope of the substrate of the high-intensity light-emitting diode obtained by forming the n-type GaP film upstream from the source gas supply port of the n-type GaP window layer It is an observation photograph. 比較例3における、n型GaP窓層の原料ガスの供給口からみて上流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡で500倍に拡大したn層界面の観察写真である。In Comparative Example 3, the n-layer interface magnified 500 times with a color laser microscope of the substrate of the high-intensity light-emitting diode obtained by forming the n-type GaP film upstream from the source gas supply port of the n-type GaP window layer It is an observation photograph. 実施例、比較例および実験例で用いた原料ガスを供給する装置の(a)断面図と(b)正面図である。It is (a) sectional drawing and (b) front view of the apparatus which supplies the source gas used by the Example, the comparative example, and the experiment example. 光吸収タイプの高輝度発光ダイオードの断面を示した概略図である。It is the schematic which showed the cross section of the high-intensity light emitting diode of a light absorption type.

以下、本発明の実施の形態を添付の図面を参照して、さらに詳しく説明する。
本発明者は、高輝度発光ダイオードの製造方法において、GaAs基板を除去した面に第二の電流拡散層を成長する際に、エピタキシャル中の成長膜の破壊を防止し、成長初期段階の界面に発生してしまうマイクロ穴欠陥を抑えることができる高輝度発光ダイオードの製造方法を開発すべく鋭意検討を重ねた。
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
In the method of manufacturing a high-intensity light-emitting diode, the inventor prevents the growth film from being destroyed during the growth of the second current diffusion layer on the surface from which the GaAs substrate has been removed, so that the interface at the initial stage of growth is prevented. In order to develop a manufacturing method of a high-intensity light-emitting diode that can suppress the micro-hole defect that has occurred, intensive studies were conducted.

その結果、本発明者は、特に原料ガスの供給口から離れた位置で製造された基板ほど、成長膜が破壊され、マイクロ穴欠陥が生じてしまう傾向が強いことから、III族原料が消費され、III/V比が低くなると成長膜の破壊が生じるのではないかと考えた。そして、形成当初にIII/V比が3以上の環境だと、エピタキシャル中の成長膜の破壊を防止することができ、炉内に導入する原料ガスのモル比を変えることで形成当初のIII/V比を3以上にした状態で、後のIII/V比を相対的に低くして成長するときの温度(例えば750℃)に昇温する途中の550〜700℃、III/V比を5以上にする場合は550℃〜730℃といった低温域の温度で成長を開始することで、マイクロ穴欠陥の発生を抑えることができ、チップ工程での基板割れの防止もでき、それは、原料ガスの供給口から離れた位置で製造された基板でも同様の効果が得られることを見出し、本発明を完成させた。   As a result, the present inventor consumes Group III raw materials because the growth film is more likely to be destroyed and micro-hole defects are generated, particularly in a substrate manufactured at a position farther from the supply port of the raw material gas. It was considered that the growth film was destroyed when the III / V ratio was lowered. If the III / V ratio is an environment of 3 or more at the beginning of formation, it is possible to prevent the growth of the epitaxially grown film from being destroyed, and by changing the molar ratio of the source gas introduced into the furnace, In a state where the V ratio is 3 or more, the temperature is increased from 550 to 700 ° C. while the temperature is increased to a temperature (for example, 750 ° C.) when the later III / V ratio is relatively lowered, and the III / V ratio is 5 In the case of the above, by starting the growth at a low temperature range of 550 ° C. to 730 ° C., it is possible to suppress the occurrence of microhole defects and to prevent substrate cracking in the chip process. The inventors have found that the same effect can be obtained with a substrate manufactured at a position away from the supply port, and completed the present invention.

以下、本発明の高輝度発光ダイオードの製造方法について説明する。
本発明の高輝度発光ダイオードの製造方法は、少なくとも、GaAs基板の第一主表面側上に4元発光層をエピタキシャル成長により形成する工程と、該4元発光層上に第一の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、前記GaAs基板を除去する工程と、前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、得られた基板をチップに加工する工程とを行う、高輝度発光ダイオードを製造する方法において、前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程は、供給する原料ガスの形成当初のIII/V比を3以上にし、その後前記III/V比が相対的に低くなるように変化させ、第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程とし、該工程において前記形成当初のIII/V比を3以上にして第二の電流拡散層を形成する時の成長温度を、III/V比を相対的に低くして成長する時の温度よりも、低温域である550℃〜700℃、III/V比を5以上にする場合は550℃〜730℃の範囲内の温度として成長を開始し、その後III/V比を相対的に低くして成長する時の温度と同じ温度まで昇温させることを特徴とする高輝度発光ダイオードの製造方法である。
図1は、本発明に係る高輝度発光ダイオードの製造方法を工程順に示した概念図である。以下、各工程についてさらに詳しく説明する。
Hereinafter, the manufacturing method of the high-intensity light emitting diode of this invention is demonstrated.
The manufacturing method of the high-intensity light-emitting diode according to the present invention includes at least a step of forming a quaternary light-emitting layer on the first main surface side of the GaAs substrate by epitaxial growth, and a first current diffusion layer on the quaternary light-emitting layer. A step of forming a group III-V compound semiconductor by HVPE growth, a step of removing the GaAs substrate, and forming a group III-V compound semiconductor by HVPE growth as a second current diffusion layer on the surface from which the GaAs substrate has been removed. And a step of processing the obtained substrate into a chip, wherein a III-V group compound semiconductor is provided as a second current diffusion layer on the surface from which the GaAs substrate has been removed. In the process of forming by HVPE growth, the initial III / V ratio of the raw material gas to be supplied is set to 3 or more, and then the III / V ratio is relatively And forming a group III-V compound semiconductor by HVPE growth as the second current spreading layer, and in this step, the initial III / V ratio is set to 3 or more to form the second current spreading. When the growth temperature at the time of forming the layer is set to 550 ° C. to 700 ° C., which is a lower temperature range than the temperature at which the III / V ratio is relatively lowered, and the III / V ratio is 5 or more A high-luminance light-emitting diode characterized by starting growth at a temperature in the range of 550 ° C. to 730 ° C. and then raising the temperature to the same temperature as the temperature at which the III / V ratio is relatively lowered. It is a manufacturing method.
FIG. 1 is a conceptual diagram illustrating a method of manufacturing a high-intensity light emitting diode according to the present invention in the order of steps. Hereinafter, each step will be described in more detail.

図1の工程101において、成長用単結晶基板としてn型GaAs基板2を準備し洗浄した後MOCVDのリアクターに入れる。   In step 101 of FIG. 1, an n-type GaAs substrate 2 is prepared as a growth single crystal substrate, cleaned, and then placed in a MOCVD reactor.

次に、工程102において、n型GaAs基板2の第一主表面側上に、有機金属気相成長法(MOCVD法)により、AlGaInPよりなる4元発光層3を、エピタキシャル成長させ5μmほど形成させる。この4元発光層3は、各々(AlGa1−xIn1−yP(0<x,y<1)よりなり、n型クラッド層、活性層、p型クラッド層をこの順で形成する。Next, in step 102, the quaternary light emitting layer 3 made of AlGaInP is epitaxially grown on the first main surface side of the n-type GaAs substrate 2 by metal organic vapor phase epitaxy (MOCVD) to form about 5 μm. The quaternary light emitting layer 3 is made of (Al x Ga 1-x ) y In 1-y P (0 <x, y <1), and an n-type cladding layer, an active layer, and a p-type cladding layer are arranged in this order. Form with.

これら各層のエピタキシャル成長で使用するAl、Ga、In(インジウム)、P(リン)の各成分源となる原料ガスとして、Al源ガス(例えば、トリメチルアルミニウム(TMAl)、トリエチルアルミニウム(TEAl))、Ga源ガス(例えば、トリメチルガリウム(TMGa)、トリエチルガリウム(TEGa))、In源ガス(例えば、トリメチルインジウム(TMIn)、トリエチルインジウム(TEIn))、P源ガス(例えば、トリメチルリン(TMP)、トリエチルリン(TEP)、ホスフィン(PH))などが挙げられる。As source gases used as component sources of Al, Ga, In (indium), and P (phosphorus) used in the epitaxial growth of these layers, an Al source gas (for example, trimethylaluminum (TMAl), triethylaluminum (TEAl)), Ga Source gas (for example, trimethylgallium (TMGa), triethylgallium (TEGa)), In source gas (for example, trimethylindium (TMIn), triethylindium (TEIn)), P source gas (for example, trimethylphosphorus (TMP), triethyl) Phosphorus (TEP), phosphine (PH 3 )) and the like.

次に、工程103において、4元発光層3の上に、第一の電流拡散層を形成する。電流拡散層4は、GaPまたはGaAsP窓層とすることが好ましい。以下、電流拡散層4として、GaP窓層を例に挙げ、説明する。   Next, in Step 103, a first current diffusion layer is formed on the quaternary light emitting layer 3. The current spreading layer 4 is preferably a GaP or GaAsP window layer. Hereinafter, the GaP window layer will be described as an example of the current spreading layer 4.

p型GaPからなる接続層6をMOCVD法により数μmの厚さでヘテロエピタキシャル成長させる。そして、基板をHVPEのリアクター内に入れ、Znをドープし、接続層6の上にp型GaPの電流拡散層4をホモエピタキシャル成長させ、p型GaP窓層を30〜200μm厚で形成させる。   The connection layer 6 made of p-type GaP is heteroepitaxially grown to a thickness of several μm by the MOCVD method. Then, the substrate is placed in an HVPE reactor, doped with Zn, and the p-type GaP current diffusion layer 4 is homoepitaxially grown on the connection layer 6 to form a p-type GaP window layer with a thickness of 30 to 200 μm.

ここでHVPE法について、具体的には、容器内にてIII族元素であるGaを所定の温度に加熱保持しながら、そのGa上に塩化水素を導入することにより、下記(1)式の反応によりGaClを生成させ、キャリアガスであるHガスとともに基板上に供給する。なお、成長温度は、例えば600℃以上800℃以下に設定する。
Ga(g)+HCl(g)→GaCl(g)+1/2H(g)・・・(1)
Here, with respect to the HVPE method, specifically, the reaction of the following formula (1) is performed by introducing hydrogen chloride onto the Ga while maintaining the group III element Ga at a predetermined temperature in the container. Then, GaCl is generated and supplied onto the substrate together with H 2 gas which is a carrier gas. The growth temperature is set to 600 ° C. or higher and 800 ° C. or lower, for example.
Ga (g) + HCl (g) → GaCl (g) + 1 / 2H 2 (g) (1)

また、V族元素であるPは、PHをキャリアガスであるHとともに基板上に供給し、p型ドーパントであるZnは、DMZn(ジメチルZn)の形で供給する。GaClはPHとの反応性に優れ、下記(2)式の反応により、効率よく電流拡散層を成長させることができる。
GaCl(g)+PH(g)→GaP(s)+HCl(g)+H(g)・・・(2)
Further, P, which is a group V element, supplies PH 3 together with H 2 which is a carrier gas onto the substrate, and Zn, which is a p-type dopant, is supplied in the form of DMZn (dimethyl Zn). GaCl is excellent in reactivity with PH 3, and the current diffusion layer can be efficiently grown by the reaction of the following formula (2).
GaCl (g) + PH 3 (g) → GaP (s) + HCl (g) + H 2 (g) (2)

次に、工程104において、GaAs基板の第二主表面側を研磨して周辺のノジュールを除去した後、GaAs基板を除去するため、エッチングを行う。エッチング液として、例えば、硫酸/過酸化水素混合液を用いることができる。   Next, in step 104, the second main surface side of the GaAs substrate is polished to remove peripheral nodules, and then etching is performed to remove the GaAs substrate. As an etchant, for example, a sulfuric acid / hydrogen peroxide mixture can be used.

次に、工程105a、工程105bにおいて、前記GaAs基板を除去した面に第二の電流拡散層5を前述のHVPE法を用い、エピタキシャル成長により形成する。なお、この電流拡散層5は、n型GaP窓層、又はn型GaAsP窓層であることが好ましい。工程105aでは当初III/V比を3以上、より好ましくは3より高くし、高III/V比の第二の電流拡散層5aを数μm形成する。一方、工程105bではIII/V比を相対的に低くなるように変化させ、低III/V比の第二の電流拡散層5bを形成する。
このように、エピタキシャル成長当初のIII/V比を3以上、より好ましくは3より高くすることで、III族原料の不足から生じるエピタキシャル膜の破壊を効果的に防止できる。
Next, in Step 105a and Step 105b, the second current diffusion layer 5 is formed on the surface from which the GaAs substrate has been removed by epitaxial growth using the HVPE method described above. The current spreading layer 5 is preferably an n-type GaP window layer or an n-type GaAsP window layer. In step 105a, the initial III / V ratio is set to 3 or more, more preferably higher than 3, and the second current diffusion layer 5a having a high III / V ratio is formed to have a thickness of several μm. On the other hand, in step 105b, the III / V ratio is changed to be relatively low, and the second current spreading layer 5b having a low III / V ratio is formed.
Thus, by making the III / V ratio at the initial stage of epitaxial growth 3 or more, more preferably higher than 3, it is possible to effectively prevent the destruction of the epitaxial film caused by the shortage of the group III material.

ここで、工程105aにおける、III/V比を3以上にする方法は、工程105bの時に比べ、V族原料ガスの供給量を少なくすることで、III/V比を相対的に高くするのが好ましい。こうすることで、III族原料の未反応による無駄をなくすことができる。また、成長初期の反応温度を低温にする場合に、原料が過剰となり、エピタキシャル膜品質が低下するようなこともない。
このとき、工程105aにおける、3以上に設定するIII/V比を、好ましくは5以上とすることができる。該範囲とすることで、より下流に位置する基板においても、エピタキシャル中の成長膜の破壊を効果的に抑えることができる。なお、III/V比は、10000以下であることが望ましい。10000より小さければ、V族元素が不足してエピタキシャル膜品質が低下することを抑制できる。
一方、工程105bにおける、相対的に低く設定するIII/V比を、好ましくは1.0以上、更に好ましくは1.2以上とすることができる。
Here, in the method of setting the III / V ratio to 3 or more in the step 105a, the III / V ratio is relatively increased by reducing the supply amount of the group V source gas compared to the step 105b. preferable. By doing so, waste due to unreacted group III raw materials can be eliminated. Further, when the reaction temperature at the initial stage of growth is lowered, the raw material becomes excessive and the quality of the epitaxial film does not deteriorate.
At this time, the III / V ratio set to 3 or more in the step 105a can be preferably 5 or more. By setting it as this range, the destruction of the growth film during the epitaxial can be effectively suppressed even in the substrate located further downstream. The III / V ratio is desirably 10,000 or less. If it is smaller than 10,000, it can suppress that the V group element runs short and the quality of the epitaxial film deteriorates.
On the other hand, the relatively low III / V ratio in step 105b can be set to 1.0 or more, more preferably 1.2 or more.

さらに、工程105aにおける成長開始温度は、工程105bの成長温度に昇温する途中の低温域である550℃〜700℃、III/V比を5以上にする場合は550℃〜730℃の範囲内の温度とし、その後工程105bの成長温度と同じ温度まで昇温させる。
このように、550℃〜700℃、III/V比を5以上にする場合は550℃〜730℃といった低温域の温度で成長を開始し昇温することで、マイクロ穴欠陥の発生を抑えることができるためである。
Furthermore, the growth start temperature in the step 105a is in the range of 550 ° C. to 700 ° C., which is a low temperature region in the middle of raising the temperature to the growth temperature of the step 105b, and in the range of 550 ° C. to 730 ° C. when the III / V ratio is 5 or more. Then, the temperature is raised to the same temperature as the growth temperature in step 105b.
As described above, when the temperature is increased from 550 ° C. to 700 ° C. and the III / V ratio is 5 or more, the growth is started at a low temperature range of 550 ° C. to 730 ° C. It is because it can do.

最後に、工程106において、基板を切断し、チップに加工して、電極付け等を行い、高輝度発光ダイオードが得られる。
Finally, in step 106, the substrate is cut, processed into chips, and electrodes are attached, so that a high-intensity light emitting diode is obtained.

(実施例1)
前記した本発明の図1の工程に従い、厚さ280μmで外周にオリエンテーションフラット(OF)が形成されたGaAs基板の第一主表面側上に、600〜800℃の環境下、(CHAl、(CHGa、(CHIn、PHを原料ガスとして、MOCVD法を用い、AlGaInPの4元発光層を8μm形成する。その際表層に、MOCVD法を用い、GaP膜を数μm形成する。その上に、HVPE法を用い、第一の電流拡散層としてp型GaP窓層を150μm形成した後、GaAs基板をエッチング除去した。
次に、第二の電流拡散層を、HVPE法により形成する。形成当初の形成開始温度を614℃とし、所定の成長温度である750℃に昇温する途中の低温域の614℃から成長を開始する。また、炉内に導入するn型GaP窓層の原料ガスである塩化水素とホスフィンのモル比を変えることでIII/V比を6.0として基板に原料ガスを供給し、n型GaP窓層を2.5μm形成する。その後、III/V比を1.2〜3.0に変えて、n型GaP窓層を150μm形成した。
Example 1
In the environment of 600 to 800 ° C. on the first main surface side of the GaAs substrate having the thickness of 280 μm and the orientation flat (OF) formed on the outer periphery in accordance with the process of FIG. 1 of the present invention described above, (CH 3 ) 3 Using Al, (CH 3 ) 3 Ga, (CH 3 ) 3 In, and PH 3 as source gases, an MOGa method is used to form an AlGaInP quaternary light-emitting layer having a thickness of 8 μm. At that time, a MOP method is used as the surface layer to form a GaP film of several μm. A p-type GaP window layer having a thickness of 150 μm was formed as a first current diffusion layer using the HVPE method, and then the GaAs substrate was removed by etching.
Next, a second current spreading layer is formed by the HVPE method. The formation start temperature at the beginning of the formation is set to 614 ° C., and the growth is started from 614 ° C. in a low temperature region in the middle of raising the temperature to 750 ° C. which is a predetermined growth temperature. Further, by changing the molar ratio of hydrogen chloride and phosphine, which is a raw material gas for the n-type GaP window layer introduced into the furnace, the raw material gas is supplied to the substrate with a III / V ratio of 6.0, and the n-type GaP window layer Is formed to 2.5 μm. Thereafter, the III / V ratio was changed to 1.2 to 3.0, and an n-type GaP window layer was formed to 150 μm.

前記原料ガスの供給は、図10に示される装置を用いて行った。図10の(a)は装置の断面図であり、(b)は正面図である。サセプタ21の上流から表側に供給される原料ガスは、ザグリ部22に保持された基板24の表側と十分触れ合うことができる。なお、均等に原料ガスが供給されるように、支持軸25は一定速度で回転している。なお、下記の全ての実施例、比較例および実験例においてもこの装置を用いて原料ガスの供給を行った。   The source gas was supplied using an apparatus shown in FIG. (A) of FIG. 10 is sectional drawing of an apparatus, (b) is a front view. The source gas supplied from the upstream side of the susceptor 21 to the front side can sufficiently come into contact with the front side of the substrate 24 held by the counterbore part 22. The support shaft 25 rotates at a constant speed so that the source gas is supplied evenly. In all of the following Examples, Comparative Examples, and Experimental Examples, the raw material gas was supplied using this apparatus.

図2は、実施例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。
また、図6は、実施例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡(VK−9710 キーエンス製)で500倍に拡大したn層界面の観察写真である。それぞれのウェーハのセンター(Center)および外周から5mmの位置2点(OF側(OF)およびOF側の反対側(反OF))のn層界面を観察した。どのウェーハにもマイクロ穴欠陥が観察されておらず欠陥の発生を抑えることができた。
FIG. 2 shows high brightness obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream from the source gas supply port of the n-type GaP window layer in Example 1. It is an observation photograph of the substrate surface of a light emitting diode.
Further, FIG. 6 was obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Example 1. It is the observation photograph of the n layer interface expanded 500 times with the color laser microscope (product made from VK-9710 Keyence) of the board | substrate of a high-intensity light emitting diode. The n-layer interface was observed at two points (OF side (OF) and opposite side of the OF side (anti-OF)) at 5 mm from the center (Center) and the outer periphery of each wafer. No micro-hole defects were observed in any wafer, and the generation of defects could be suppressed.

(比較例1)
前記実施例と同じ方法で、GaAs基板をエッチング除去するまでの工程を行う。
次に、第二の電流拡散層を、HVPE法により形成する。成長温度を750℃で一定に保ち、また、n型GaP窓層の原料ガスの形成当初のIII/V比を6.0として基板に原料ガスを供給し、n型GaP窓層を2.5μm形成する。その後、III/V比を1.2〜3.0に変えて、n型GaP窓層を150μm形成した。
(Comparative Example 1)
The same process as in the previous embodiment is performed until the GaAs substrate is removed by etching.
Next, a second current spreading layer is formed by the HVPE method. The growth temperature is kept constant at 750 ° C., and the source gas is supplied to the substrate at the initial III / V ratio of 6.0 for forming the source gas for the n-type GaP window layer, and the n-type GaP window layer is 2.5 μm. Form. Thereafter, the III / V ratio was changed to 1.2 to 3.0, and an n-type GaP window layer was formed to 150 μm.

図3は、比較例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。
また、図7は、比較例1における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡(VK−9710 キーエンス製)で500倍に拡大したn層界面の観察写真である。なお、(a)上流は、ウェーハのセンター(Center)のみ、(b)中流、(c)下流は、それぞれのウェーハのセンター(Center)および外周から5mmの位置2点(OF側(OF)およびOF側の反対側(反OF))のn層界面を観察した。図7のn層界面の観察写真から、比較例1の界面部分にマイクロ穴欠陥が観察された。
FIG. 3 shows high brightness obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 1. It is an observation photograph of the substrate surface of a light emitting diode.
Further, FIG. 7 was obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 1. It is the observation photograph of the n layer interface expanded 500 times with the color laser microscope (product made from VK-9710 Keyence) of the board | substrate of a high-intensity light emitting diode. Note that (a) upstream is the center of the wafer only (Center), (b) is the middle stream, (c) the downstream is the center (Center) of each wafer and two positions 5 mm from the outer periphery (OF side (OF) and The n layer interface on the opposite side of the OF side (anti-OF) was observed. From the observation photograph of the n-layer interface in FIG. 7, microhole defects were observed at the interface portion of Comparative Example 1.

(比較例2)
前記実施例と同じ方法で、GaAs基板をエッチング除去するまでの工程を行う。
次に、第二の電流拡散層を、気相成長法により形成する。成長温度を750℃で一定に保ち、n型GaP窓層の原料ガスのIII/V比を3.0で一定に保ちながら、n型GaP窓層を150μm形成した。
(Comparative Example 2)
The same process as in the previous embodiment is performed until the GaAs substrate is removed by etching.
Next, a second current diffusion layer is formed by a vapor deposition method. While maintaining the growth temperature constant at 750 ° C. and maintaining the III / V ratio of the source gas of the n-type GaP window layer constant at 3.0, the n-type GaP window layer was formed to 150 μm.

図4は、比較例2における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。
また、図8は、比較例2における、n型GaP窓層の原料ガスの供給口からみて上流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡(VK−9710 キーエンス製)で500倍に拡大したn層界面の観察写真である。なお、それぞれのウェーハのセンター(Center)および外周から5mmの位置2点(OF側(OF)およびOF側の反対側(反OF))のn層界面を観察した。図8のn層界面の観察写真から、比較例2の界面部分にマイクロ穴欠陥が観察された。
FIG. 4 shows high brightness obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream as viewed from the source gas supply port of the n-type GaP window layer in Comparative Example 2. It is an observation photograph of the substrate surface of a light emitting diode.
8 shows a color laser microscope (VK−) of the substrate of the high-intensity light-emitting diode obtained by forming the n-type GaP film upstream from the source gas supply port of the n-type GaP window layer in Comparative Example 2. 9710 Keyence)) is an observation photograph of the n-layer interface magnified 500 times. It should be noted that the n-layer interface was observed at two points (OF side (OF) and opposite side of the OF side (anti-OF)) 5 mm from the center and the outer periphery of each wafer. From the observation photograph of the n-layer interface in FIG. 8, microhole defects were observed at the interface portion of Comparative Example 2.

(比較例3)
前記実施例と同じ方法で、GaAs基板をエッチング除去するまでの工程を行う。
次に、第二の電流拡散層を、気相成長法により形成する。成長温度を750℃で一定に保ち、n型GaP窓層の原料ガスのIII/V比を1.2で一定に保ちながら、n型GaP窓層を150μm形成した。
(Comparative Example 3)
The same process as in the previous embodiment is performed until the GaAs substrate is removed by etching.
Next, a second current diffusion layer is formed by a vapor deposition method. The n-type GaP window layer was formed to 150 μm while the growth temperature was kept constant at 750 ° C. and the III / V ratio of the source gas of the n-type GaP window layer was kept constant at 1.2.

図5は、比較例3における、n型GaP窓層の原料ガスの供給口からみて(a)上流、(b)中流、(c)下流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板表面の観察写真である。
また、図9は、比較例3における、n型GaP窓層の原料ガスの供給口からみて上流でn型GaP膜を形成して得られた高輝度発光ダイオードの基板のカラーレーザー顕微鏡(VK−9710 キーエンス製)で500倍に拡大したn層界面の観察写真である。なお、ウェーハのセンター(Center)および外周から5mmの位置2点(OF側(OF)およびOF側の反対側(反OF))のn層界面を観察した。図9のn層界面の観察写真から、比較例3の界面部分にマイクロ穴欠陥が観察された。
FIG. 5 shows a high brightness obtained by forming an n-type GaP film at (a) upstream, (b) midstream, and (c) downstream from the source gas supply port of the n-type GaP window layer in Comparative Example 3. It is an observation photograph of the substrate surface of a light emitting diode.
9 shows a color laser microscope (VK−) of a substrate of a high-intensity light-emitting diode obtained by forming an n-type GaP film upstream from the source gas supply port of the n-type GaP window layer in Comparative Example 3. 9710 Keyence)) is an observation photograph of the n-layer interface magnified 500 times. Note that the n-layer interface was observed at two points (OF side (OF) and opposite side of the OF side (anti-OF)) at a position 5 mm from the center and the outer periphery of the wafer. From the observation photograph of the n-layer interface in FIG. 9, microhole defects were observed at the interface portion of Comparative Example 3.

図4、5の基板表面の観察写真からもわかる通り、III/V比が3.0以下かつ基板温度を高温とした場合は下流の基板に成長膜の破壊が見られた。また、III/V比が1.2の場合は下流の基板だけでなく、中流の基板にも成長膜の破壊があった。
4 and 5, when the III / V ratio was 3.0 or less and the substrate temperature was high, the growth film was broken on the downstream substrate. When the III / V ratio was 1.2, the growth film was broken not only on the downstream substrate but also on the midstream substrate.

(実験例)
前記実施例1と同じ方法で、GaAs基板をエッチング除去するまでの工程を行う。
次に、第二の電流拡散層を、気相成長法により形成する。形成当初の形成開始温度を5水準、n型GaP窓層の原料ガスの形成当初のIII/V比を5水準設定し、それぞれを変化させて第二の電流拡散層を形成した。前記形成開始温度は、それぞれ500℃、550℃、700℃、730℃とし、所定の成長温度である750℃に昇温する途中の低温域の温度から成長を開始させた。また、残りの1水準は750℃で一定とした。前記n型GaP窓層の原料ガスの形成当初のIII/V比はそれぞれ1.2、3、6、20、80として基板に原料ガスを供給し、n型GaP窓層を2.5μm形成した。その後、III/V比を1.2〜3.0に変えて、n型GaP窓層を150μm形成した。
(Experimental example)
The same process as in Example 1 is performed until the GaAs substrate is removed by etching.
Next, a second current diffusion layer is formed by a vapor deposition method. The formation start temperature at the beginning of formation was set to 5 levels, the III / V ratio at the beginning of formation of the source gas for the n-type GaP window layer was set to 5 levels, and each was changed to form the second current diffusion layer. The formation start temperatures were 500 ° C., 550 ° C., 700 ° C., and 730 ° C., respectively, and the growth was started from a temperature in the low temperature region while the temperature was raised to 750 ° C., which is a predetermined growth temperature. The remaining one level was constant at 750 ° C. The source gas of the n-type GaP window layer was initially formed with a III / V ratio of 1.2, 3, 6, 20, and 80, respectively, and the source gas was supplied to the substrate to form an n-type GaP window layer of 2.5 μm. . Thereafter, the III / V ratio was changed to 1.2 to 3.0, and an n-type GaP window layer was formed to 150 μm.

なお、上記実験例中、形成開始温度を700℃とした時にn型GaP窓層の原料ガスの形成当初のIII/V比を6とした場合を実施例2、20とした場合を実施例3、80とした場合を実施例4とし、形成開始温度を550℃とした時に原料ガスの形成当初のIII/V比を6とした場合を実施例5、20とした場合を実施例6、80とした場合を実施例7とし、また比較例4(形成開始温度=500℃、形成当初のIII/V比=1.2)、比較例5(形成開始温度=500℃、形成当初のIII/V比=3)、比較例6(形成開始温度=500℃、形成当初のIII/V比=6)、比較例7(形成開始温度=500℃、形成当初のIII/V比=20)、比較例8(形成開始温度=500℃、形成当初のIII/V比=80)、比較例9(形成開始温度=550℃、形成当初のIII/V比=1.2)、実施例8(形成開始温度=550℃、形成当初のIII/V比=3)、比較例10(形成開始温度=700℃、形成当初のIII/V比=1.2)、実施例9(形成開始温度=700℃、形成当初のIII/V比=3)、比較例11(形成開始温度=730℃、形成当初のIII/V比=1.2)、比較例12(形成開始温度=730℃、形成当初のIII/V比=3)、実施例10(形成開始温度=730℃、形成当初のIII/V比=6)、実施例11(形成開始温度=730℃、形成当初のIII/V比=20)、実施例12(形成開始温度=730℃、形成当初のIII/V比=80)、比較例13(750℃一定、形成当初のIII/V比=1.2)、比較例14(750℃一定、形成当初のIII/V比=3)、比較例15(750℃一定、形成当初のIII/V比=6)、比較例16(750℃一定、形成当初のIII/V比=20)、比較例17(750℃一定、形成当初のIII/V比=80))とした。   In the above experimental examples, when the formation start temperature is 700 ° C., the initial III / V ratio of the source gas for forming the n-type GaP window layer is set to 6, and the case where the examples are set to Examples 2 and 20. , 80 is Example 4, and when the formation start temperature is 550 ° C., the initial III / V ratio is 6 and Examples 5 and 20 are Examples 6 and 80. Example 7 and Comparative Example 4 (formation start temperature = 500 ° C., III / V ratio at the beginning of formation = 1.2), Comparative Example 5 (formation start temperature = 500 ° C., III / V at the beginning of formation) V ratio = 3), Comparative Example 6 (formation start temperature = 500 ° C., initial III / V ratio = 6), Comparative Example 7 (formation start temperature = 500 ° C., initial III / V ratio = 20), Comparative example 8 (formation start temperature = 500 ° C., initial III / V ratio = 80), comparative example (Formation start temperature = 550 ° C., III / V ratio at the beginning of formation = 1.2), Example 8 (Formation start temperature = 550 ° C., III / V ratio at the beginning of formation = 3), Comparative Example 10 (Formation start temperature) = 700 ° C, III / V ratio at the beginning of formation = 1.2), Example 9 (formation start temperature = 700 ° C, III / V ratio at the beginning of formation = 3), Comparative Example 11 (formation start temperature = 730 ° C, III / V ratio at the beginning of formation = 1.2), Comparative Example 12 (formation start temperature = 730 ° C., III / V ratio at the beginning of formation = 3), Example 10 (formation start temperature = 730 ° C., III at the beginning of formation) / V ratio = 6), Example 11 (formation start temperature = 730 ° C., initial III / V ratio = 20), Example 12 (formation start temperature = 730 ° C., initial III / V ratio = 80) Comparative Example 13 (constant at 750 ° C., initial III / V ratio = 1.2), Comparative Example 1 (Constant 750 ° C., III / V ratio at the beginning of formation = 3), Comparative Example 15 (Constant 750 ° C., III / V ratio at the beginning of formation = 6), Comparative Example 16 (Constant 750 ° C., III / V ratio at the beginning of formation) = 20) and Comparative Example 17 (constant at 750 ° C, III / V ratio at the beginning of formation = 80)).

表1はそれぞれの水準を用いて第二の電流拡散層を形成したウェーハにおいて接合不良およびマイクロ穴欠陥(直径1μm以上)の個数の結果を示したものである。なお、マイクロ穴欠陥の計数方法は、カラーレーザー顕微鏡(VK−9710キ−エンス製)により500倍に拡大した写真から界面に沿って50μmの範囲で1μm以上の欠陥個数をカウントし、その個数を200倍して1cm当りの個数とし、ウェーハのセンターおよび外周から5mmの位置2点(OF側及びOF側の反対側(反OF側))の計3点の平均値を算出した。   Table 1 shows the results of the number of bonding defects and micro-hole defects (diameter of 1 μm or more) in the wafer in which the second current diffusion layer is formed using each level. The micro hole defect counting method is to count the number of defects of 1 μm or more in the range of 50 μm along the interface from a photograph magnified 500 times with a color laser microscope (manufactured by VK-9710 Keyence). By multiplying by 200, the number per 1 cm was calculated, and the average value of a total of 3 points, 2 points at 5 mm from the center and outer periphery of the wafer (on the opposite side of the OF side and the OF side (anti-OF side)), was calculated.

Figure 0005278323
Figure 0005278323

上記表1の記載中、◎、○は接合不良なし、□は若干の接合不良があるが95%以上良品、△は一部接合不良あり、×はエピタキシャル成長不可を示す。表1から、実施例2−7においては、接合不良がなく、1μm以上のマイクロ穴欠陥は0個/cmであった。一方、形成当初のIII/V比を1.2とした比較例4−11、13においてはエピタキシャル成長できず、その他の比較例(比較例12、14−17)においては一部接合不良が見られ、1μm以上のマイクロ穴欠陥が多数見られた。このことから、第二の電流拡散層形成当初のIII/V比を3以上にした状態で、かつ、後のIII/V比を相対的に低くして成長するときの温度(750℃)に昇温する途中の550〜700℃、III/V比を5以上にする場合は550℃〜730℃といった低温域の温度で成長を開始することで、接合不良を抑えることができ、マイクロ穴欠陥の発生を抑えることができることが明らかとなった。   In the description of Table 1 above, ◎ and ○ indicate no bonding failure, □ indicates a slight bonding failure but good product of 95% or more, Δ indicates a partial bonding failure, and × indicates that epitaxial growth is not possible. From Table 1, in Example 2-7, there was no joining defect and the micro hole defect of 1 micrometer or more was 0 piece / cm. On the other hand, in Comparative Examples 4-11 and 13 in which the initial III / V ratio was 1.2, epitaxial growth could not be performed, and in other Comparative Examples (Comparative Examples 12 and 14-17), partial bonding failure was observed. Many micro hole defects of 1 μm or more were observed. From this, the temperature (750 ° C.) when growing with the III / V ratio at the beginning of the second current diffusion layer formation being 3 or more and the later III / V ratio being relatively low is grown. When the temperature is increased from 550 to 700 ° C. and the III / V ratio is 5 or more, by starting the growth at a low temperature range of 550 ° C. to 730 ° C., it is possible to suppress the bonding failure, and the micro hole defect It became clear that generation | occurrence | production of can be suppressed.

これらの結果の通り、本発明の高輝度発光ダイオードの製造方法によれば、GaAs基板を除去した面に第二の電流拡散層を成長する際に、エピタキシャル中の成長膜の破壊を効果的に防止し、成長初期段階の界面に発生してしまうマイクロ穴欠陥を効果的に抑えることができ、それは、原料ガスの供給口から離れた下流で製造された基板でも同様の効果が得られるため、高品質な高輝度発光ダイオードを製造することができた。   As can be seen from these results, according to the manufacturing method of the high-intensity light-emitting diode of the present invention, when the second current diffusion layer is grown on the surface from which the GaAs substrate is removed, the growth film in the epitaxial layer is effectively destroyed. It is possible to effectively prevent micro-hole defects that occur at the interface at the initial stage of growth, and the same effect can be obtained even with a substrate manufactured downstream from the source gas supply port. High-quality high-intensity light-emitting diodes could be manufactured.

本発明によって、膜破壊がなくなって窓層の両面成長エピタキシャル成長による高品質な高輝度発光ダイオードの生産が多段で安定して生産できるようになり、両面成長の生産性が大幅に向上した。また、界面穴欠陥の発生を抑えることにより、Vf値やライフ特性が向上し、接合不良を抑えることにより、チップ製作工程での接合不良部の除去による歩留低下の抑制と除去工数の低減を実現でき、高輝度発光ダイオードの生産性が飛躍的に向上した。   According to the present invention, the film breakage is eliminated and the production of high-quality high-intensity light-emitting diodes by double-sided growth epitaxial growth of the window layer can be stably produced in multiple stages, and the productivity of double-sided growth is greatly improved. In addition, by suppressing the occurrence of interface hole defects, the Vf value and life characteristics are improved, and by suppressing defective bonding, it is possible to reduce yield reduction and reduce man-hours by removing defective bonding parts in the chip manufacturing process. This has been achieved and the productivity of high-intensity light-emitting diodes has been dramatically improved.

尚、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

Claims (4)

少なくとも、GaAs基板の第一主表面側上に4元発光層をエピタキシャル成長により形成する工程と、該4元発光層上に第一の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、前記GaAs基板を除去する工程と、前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程と、得られた基板をチップに加工する工程、とを行う高輝度発光ダイオードの製造方法において、
前記GaAs基板を除去した面に第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程は、供給する原料ガスの形成当初のIII/V比を3以上にし、その後前記III/V比が相対的に低くなるように変化させ、第二の電流拡散層としてIII−V族化合物半導体をHVPE成長により形成する工程とし、該工程において前記形成当初のIII/V比を3以上にして第二の電流拡散層を形成する時の成長温度を、III/V比を相対的に低くして成長する時の温度よりも、低温域である550℃〜700℃、III/V比を5以上にする場合は550℃〜730℃の範囲内の温度として成長を開始し、その後III/V比を相対的に低くして成長する時の温度と同じ温度まで昇温させることを特徴とする高輝度発光ダイオードの製造方法。
At least a step of forming a quaternary light emitting layer by epitaxial growth on the first main surface side of the GaAs substrate, and forming a III-V group compound semiconductor as a first current diffusion layer on the quaternary light emitting layer by HVPE growth. A step, a step of removing the GaAs substrate, a step of forming a group III-V compound semiconductor as a second current diffusion layer on the surface from which the GaAs substrate has been removed by HVPE growth, and processing the obtained substrate into a chip In the method of manufacturing a high-intensity light emitting diode,
The step of forming a group III-V compound semiconductor as a second current diffusion layer on the surface from which the GaAs substrate has been removed by HVPE growth has an initial III / V ratio of 3 or more, and then III / V ratio is changed so as to be relatively low, and a III-V compound semiconductor is formed as a second current diffusion layer by HVPE growth, and the initial III / V ratio is 3 or more in this step. Thus, the growth temperature when forming the second current diffusion layer is 550 ° C. to 700 ° C., which is a lower temperature range than the temperature when growing with a relatively low III / V ratio, and the III / V ratio. When the temperature is 5 or more, the growth is started at a temperature in the range of 550 ° C. to 730 ° C., and then the temperature is raised to the same temperature as that at the time of growth with a relatively low III / V ratio. High Method for producing a degree-emitting diodes.
前記供給する原料ガスの形成当初のIII/V比を、3より高くし、前記第二の電流拡散層を形成する時の成長温度を、550℃〜700℃の範囲内の温度とすることを特徴とする請求項1に記載の高輝度発光ダイオードの製造方法。   The initial III / V ratio of the source gas to be supplied is made higher than 3, and the growth temperature when forming the second current diffusion layer is set to a temperature within the range of 550 ° C. to 700 ° C. The method for manufacturing a high-intensity light-emitting diode according to claim 1. 前記成長させる第一、第二の電流拡散層を、GaPまたはGaAsP窓層とすることを特徴とする請求項1または請求項2に記載の高輝度発光ダイオードの製造方法。   3. The method for manufacturing a high-intensity light emitting diode according to claim 1, wherein the first and second current diffusion layers to be grown are GaP or GaAsP window layers. 前記形成当初のIII/V比を3以上にする方法を、III/V比を相対的に低くする時よりも、V族原料ガスの供給量を少なくすることにより、III/V比を相対的に高くすることを特徴とする請求項1ないし請求項3のいずれか1項に記載の高輝度発光ダイオードの製造方法。
In the method of setting the initial III / V ratio to 3 or more, the III / V ratio is relatively reduced by reducing the supply amount of the group V source gas than when the III / V ratio is relatively low. The method for manufacturing a high-intensity light-emitting diode according to any one of claims 1 to 3, wherein the manufacturing method is high.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269145A (en) * 1999-03-17 2000-09-29 Sharp Corp Crystal growing method of compound semiconductor and semiconductor light emitting element
JP2003023177A (en) * 2001-07-06 2003-01-24 Sharp Corp Method of manufacturing semiconductor light emitting element
JP2004260109A (en) * 2003-02-27 2004-09-16 Shin Etsu Handotai Co Ltd Method of manufacturing light-emitting element, composite translucent substrate, and light-emitting element
JP2004296707A (en) * 2003-03-26 2004-10-21 Shin Etsu Handotai Co Ltd Light emitting device, method for manufacturing the same and compound translucent substrate
JP2005150664A (en) * 2003-11-19 2005-06-09 Shin Etsu Handotai Co Ltd Light-emitting element and its manufacturing method
JP2005277218A (en) * 2004-03-25 2005-10-06 Shin Etsu Handotai Co Ltd Light-emitting element and its manufacturing method
WO2007088841A1 (en) * 2006-01-31 2007-08-09 Shin-Etsu Handotai Co., Ltd. Light-emitting device and method for manufacturing same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269145A (en) * 1999-03-17 2000-09-29 Sharp Corp Crystal growing method of compound semiconductor and semiconductor light emitting element
JP2003023177A (en) * 2001-07-06 2003-01-24 Sharp Corp Method of manufacturing semiconductor light emitting element
JP2004260109A (en) * 2003-02-27 2004-09-16 Shin Etsu Handotai Co Ltd Method of manufacturing light-emitting element, composite translucent substrate, and light-emitting element
JP2004296707A (en) * 2003-03-26 2004-10-21 Shin Etsu Handotai Co Ltd Light emitting device, method for manufacturing the same and compound translucent substrate
JP2005150664A (en) * 2003-11-19 2005-06-09 Shin Etsu Handotai Co Ltd Light-emitting element and its manufacturing method
JP2005277218A (en) * 2004-03-25 2005-10-06 Shin Etsu Handotai Co Ltd Light-emitting element and its manufacturing method
WO2007088841A1 (en) * 2006-01-31 2007-08-09 Shin-Etsu Handotai Co., Ltd. Light-emitting device and method for manufacturing same

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