JP5267189B2 - Epitaxial wafer manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an epitaxial wafer that improves the uniformity in an in-plane direction of the thickness of an epitaxial layer. <P>SOLUTION: The method includes a model preparing step S1 of measuring the thickness of an epitaxial layer at a plurality of measuring positions arrayed in the in-plane direction of a wafer, opening and closing a gas flow outlet corresponding to the opening and closing member by operating the opening and closing member, modeling the thickness of the wafer in-plane epitaxial layer corresponding to the operation of the opening and closing member, and preparing an epitaxial layer thickness estimation model in the wafer plane; an epitaxial layer forming step S2 of forming the epitaxial layer on the wafer; a real thickness measuring step S3 of measuring the actual thickness of the epitaxial layer in the wafer plane, which is the actual thickness of the epitaxial layer, at a plurality of measuring positions concerning the epitaxial layer formed in the epitaxial layer forming step S2; and an in-wafer-plane epitaxial layer real thickness correcting step S10 of correcting the dispersion of the real thickness of the epitaxial layer in the wafer plane to be a minimum, by manipulating the opening and closing member, based on the wafer in-plane epitaxial layer thickness estimation model which is prepared in the model preparing step S1. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an epitaxial wafer manufacturing method in which an epitaxial layer is formed on a main surface of a semiconductor wafer.

  In the field of semiconductor wafers such as silicon wafers, epitaxial wafers are known in which an epitaxial layer is formed on the main surface of a semiconductor wafer as a substrate. According to the epitaxial wafer, for example, an epitaxial layer of single crystal silicon having an arbitrary thickness and specific resistance is formed on the silicon wafer, so that a high-performance semiconductor device can be manufactured.

A vapor phase growth apparatus is used as an apparatus for obtaining an epitaxial wafer by growing an epitaxial layer on the main surface of a semiconductor wafer. A vapor phase growth apparatus generally includes a chamber (reaction chamber) in which a semiconductor wafer is accommodated, a susceptor rotatably installed in the chamber and supporting the semiconductor wafer, and a source gas (SiH ₄ or the like) or a carrier. A gas supply source for supplying a reaction gas containing at least a gas (such as H ₂ ) into the chamber. According to the vapor phase growth apparatus, the epitaxial layer can be grown on the main surface of the semiconductor wafer accommodated in the chamber by supplying the reaction gas from the gas supply source into the chamber.

  By the way, in the field of semiconductor devices, higher integration is progressing, and finer processing is required. For example, a higher flatness is required for a semiconductor wafer as a device material because of a relationship such as a depth of focus of an exposure apparatus in a photolithography process.

  In order to improve the flatness in the vapor phase growth apparatus, the uniformity in the in-plane direction (hereinafter also referred to as “in-plane uniformity”) of the thickness of the epitaxial layer (hereinafter also referred to as “epi-thickness”) is improved. Is important. As a technique for improving the in-plane uniformity of epi-thickness in a single wafer type vapor phase growth apparatus that processes wafers one by one, the following Patent Document 1 is provided with a rectifying member having a plurality of gas outlets to supply gas. A technique is described in which a reaction gas supplied from a source is rectified by flowing out from a plurality of gas outlets of a rectifying member and supplied into the chamber. The in-plane tendency of the epi thickness by the single wafer type vapor phase growth apparatus has an axisymmetric distribution with the center of the wafer as the axis of symmetry.

JP 2002-249398 A

  However, according to the vapor phase growth apparatus described in Patent Document 1, it may be effective for a specific process condition, but it is an effective means for all the process conditions that are variously changed. I can not say. In particular, in a batch-type vapor phase growth apparatus in which a plurality of wafers are placed on one susceptor for processing, the in-plane tendency of the epitaxial thickness of the wafer is unclear, and the center of the wafer is the axis of symmetry. Therefore, it is more difficult to improve the in-plane uniformity of the epi thickness.

  Therefore, an object of the present invention is to provide an epitaxial wafer manufacturing method that can further improve the uniformity in the in-plane direction with respect to the thickness of the epitaxial layer.

  (1) An epitaxial wafer manufacturing method of the present invention includes a chamber containing a semiconductor wafer, a susceptor installed inside the chamber so that the semiconductor wafer can be placed thereon, and a reaction gas containing at least a source gas or a carrier gas. A gas supply source for supplying gas into the chamber, a plurality of gas outlets for allowing the reaction gas supplied from the gas supply source to flow into the chamber, and a plurality of opening / closing members for opening and closing the gas outlets An epitaxial wafer manufacturing method using a vapor phase growth apparatus for forming an epitaxial layer on a main surface of the semiconductor wafer accommodated in the chamber, the rectifying unit having the rectifying unit, and the rectifier placed on the susceptor Measure the thickness of the epitaxial layer at multiple measurement positions arranged in the in-plane direction of the semiconductor wafer Then, the gas outlet corresponding to the opening / closing member is opened / closed by operating each of the opening / closing members, and the thickness of the epitaxial layer in the wafer surface corresponding to the operation of the opening / closing member is modeled. A model creating step for creating a model; an epitaxial layer forming step for forming the epitaxial layer on the semiconductor wafer; and a plurality of the epitaxial layers formed by the epitaxial layer forming step arranged in an in-plane direction of the semiconductor wafer. The actual thickness measuring step for measuring the actual epi-thickness in the wafer surface, which is the actual thickness of the epitaxial layer at the measurement position, and the opening / closing member are operated based on the epi-thickness epitaxy estimation model created in the model creating step. Variation in the actual epitaxial thickness in the wafer surface Characterized in that it comprises a wafer surface Naijitsu epitaxial thickness correcting step of correcting such a small, and.

  (2) The wafer surface actual epi thickness correction step is calculated by the wafer surface actual epi thickness correction amount calculation step for calculating the wafer surface actual epi thickness correction amount and the wafer surface actual epi thickness correction amount calculation step. Based on the opening / closing pattern selection step of selecting the opening / closing pattern of the gas outlet by the opening / closing member based on the correction amount of the actual epitaxial thickness in the wafer surface, and the opening / closing pattern of the gas outlet selected by the opening / closing pattern selection step And an opening / closing member operating step for operating the opening / closing member.

  (3) The rectifying unit has an internal space divided into a plurality of spaces, a plurality of the gas outlets arranged corresponding to the plurality of spaces, and the reaction gas introduced into the space is It is preferable to be configured to flow out from the gas outlet corresponding to the space.

  (4) In-wafer surface epi-thickness estimation for correcting the wafer-in-plane epi-thickness estimation model created in the model creation step based on the wafer-in-plane actual epi thickness measured in the actual thickness measurement step that has already been performed. It is preferable to further include a model correction step.

  According to the epitaxial wafer manufacturing method of the present invention, the uniformity in the in-plane direction with respect to the thickness of the epitaxial layer can be further improved.

It is a top view which shows typically the vapor phase growth apparatus 1 used for one embodiment of the manufacturing method of the epitaxial wafer of this invention. It is a top view which expands and shows the rectification | straightening part 2 in the vapor phase growth apparatus 1 shown in FIG. FIG. 3 is a side view of the rectifying unit 2 shown in FIG. 2 as viewed from the surface side where the gas outlets 22 are formed, in which (A) shows a state in which all the gas outlets 22 are open, and (B) shows a part of them. It is a figure which shows the state which the gas outflow port 22 closed. It is a flowchart which shows one embodiment of the manufacturing method of the epitaxial wafer of this invention. It is a figure which shows the example which numbered [1]-[20] to the 20 gas outflow ports 22 in the rectification | straightening part 2. FIG. It is a graph which shows distribution of the in-plane direction about epi thickness obtained in the state which opened all the gas outflow ports 22 fully. It is a graph which shows distribution of the in-plane direction about epi thickness obtained in the state where a part of gas outlets 22 were closed.

  Hereinafter, an embodiment of a method for producing an epitaxial wafer of the present invention will be described with reference to the drawings. First, a vapor phase growth apparatus used in one embodiment of the epitaxial wafer manufacturing method of the present invention will be described.

  FIG. 1 is a plan view schematically showing a vapor phase growth apparatus 1 used in an embodiment of a method for producing an epitaxial wafer of the present invention. FIG. 2 is an enlarged plan view showing the rectifying unit 2 in the vapor phase growth apparatus 1 shown in FIG. 3 is a side view of the rectifying unit 2 shown in FIG. 2 as viewed from the side on which the gas outlets 22 are formed. FIG. 3A is a diagram showing a state in which all the gas outlets 22 are open. These are figures which show the state in which some gas outflow ports 22 were closed.

  The vapor phase growth apparatus 1 of this embodiment is an apparatus for producing an epitaxial wafer by forming an epitaxial layer (vapor phase growth) on the main surface of a semiconductor wafer W such as a silicon wafer. As shown in FIGS. 1 to 3, the vapor phase growth apparatus 1 includes a chamber 12, a susceptor 13, a gas supply source 14, a rectifying unit 2, and the like. According to the vapor phase growth apparatus 1 of this embodiment, the reaction gas G introduced from the gas supply source 14 is supplied to the inside of the chamber 12 through the rectifying unit 2, so that the semiconductor housed in the chamber 12 is accommodated. An epitaxial layer can be formed on the main surface of the wafer W.

The chamber 12 is also called a reaction chamber or a reaction vessel, and houses a susceptor 13, a semiconductor wafer W on which an epitaxial layer is formed, and the like.
The susceptor 13 is rotatably installed inside the chamber 12 and has a plurality of recesses (not shown) that accommodate the semiconductor wafer W. The susceptor 13 is configured such that a plurality of (for example, eight) semiconductor wafers W can be placed in the recess. On the mounting surface of the susceptor 13, a plurality of semiconductor wafers W are arranged and arranged at predetermined intervals along the rotation direction of the susceptor 13. Accordingly, by rotating the susceptor 13, the plurality of semiconductor wafers W revolve around the center of the susceptor 13 as the center of rotation, and an epitaxial layer is formed on each main surface of the revolving semiconductor wafers W.

The gas supply source 14 supplies a reaction gas containing at least a source gas or a carrier gas into the chamber 12 via the rectifying unit 2. Examples of the source gas include SiH ₄ , SiCl ₄ , SiHCl ₃ , and SiH ₂ Cl ₂ . As the carrier gas, such as H ₂ and the like. A reaction gas composed of a raw material gas, a carrier gas, and the like is supplied into the chamber 2 through the supply pipe 16 and the rectification unit 2 in a mixed gas state.

  The rectification unit 2 is disposed above the outside of the chamber 12, and when the reaction gas introduced through the supply pipe 16 is supplied to the inside of the chamber 12, the rectification unit 2 rectifies the reaction gas and then above the semiconductor wafer W. This is the part that flows into the space. The rectifying unit 2 includes a plurality of gas outlets 22 that allow the reaction gas supplied from the gas supply source 14 to flow out into the chamber 12, and a plurality of opening and closing members 23 that open and close the gas outlet 22.

More specifically, as shown in FIGS. 2 and 3, the rectifying unit 2 has an internal space partitioned into a plurality of spaces. The rectifying unit 2 is provided with a plurality (40 in this embodiment) of gas outlets 22. 2 and 3, only 20 of the 40 gas outlets 22 are shown for the sake of simplicity.
The plurality of gas outlets 22 are arranged at the same position in the height direction in the rectifying unit 2 and arranged at equal intervals in the width direction.

The rectifying unit 2 includes a partition member 25 that partitions the internal space into a plurality of spaces (hereinafter also referred to as “divided spaces”) 26. In this embodiment, five partition members 25 are provided, and therefore six divided spaces 26 are formed in the internal space of the rectifying unit 2.
The plurality of gas outlets 22 are arranged corresponding to the plurality of divided spaces 26. In this embodiment, the 40 gas outlets 22 correspond to each of the six divided spaces 26, and are 6, 6, 8, 8, 6, and 6 from the side of one outer wall 24. Arranged for each.

  The supply pipe 16 can adjust the supply amount of the reaction gas independently for each divided space 26. Therefore, the total flow rate of the reaction gas from the gas outlet 22 corresponding to each divided space 26 can be changed for each divided space 26.

  The reaction gas introduced into each divided space 26 flows out from each gas outlet 22 corresponding to each divided space 26. For example, in the divided space 26 having the three gas outlets 22, when the three gas outlets 22 are completely open, the reaction gas flows out from the three gas outlets 22 evenly. When two gas outlets 22 are fully open and one gas outlet 22 is completely closed, the flow rate is larger than that when three gas outlets 22 are fully open. The reaction gas flows out uniformly from the individual gas outlets 22. When the three gas outlets 22 are completely closed, the reaction gas does not flow out from the corresponding divided space 26.

  The opening / closing member 23 is provided corresponding to each gas outlet 22 and opens and closes the corresponding gas outlet 22. As shown in FIG. 3 (B), when the opening / closing member 23 is positioned above, the corresponding gas outlet 22 is opened. On the other hand, when the opening / closing member 23 is positioned below, the corresponding gas outlet 22 is closed.

  The opening / closing member 23 may have a configuration in which the gas outlet 22 is opened / closed alternatively or completely closed. Further, the opening / closing member 23 may have a configuration that allows the degree of opening (opening degree) of the gas outlet 22 to be adjusted steplessly or stepwise (for example, opening with a degree of opening of 70%). The opening / closing member 23 can adjust the opening / closing of the gas outlet 22 (including the adjustment of the degree of opening) during the vapor phase growth process.

  Next, one embodiment of the method for producing an epitaxial wafer of the present invention will be described with reference to FIG. FIG. 4 is a flowchart showing an embodiment of the method for producing an epitaxial wafer of the present invention. The manufacturing method of the epitaxial wafer of this embodiment is a method of manufacturing an epitaxial wafer using the vapor phase growth apparatus 1 described above.

  As shown in FIG. 4, the epitaxial wafer manufacturing method of this embodiment includes the following steps S1 to S3, S10 (S11 to S13), S21 and S2 '.

(S1) Model Creation Step The gas outlet 22 corresponding to the opening / closing member 23 is opened / closed by operating each of the opening / closing members 23, and the thickness of the epitaxial layer in the wafer surface is modeled to create an epitaxial thickness estimation model in the wafer surface. .

  Here, the thickness of the epitaxial layer is measured at a plurality of measurement positions arranged in the in-plane direction of the semiconductor wafer W placed on the susceptor 13.

  “A plurality of measurement positions arranged in the in-plane direction” refers to an arrangement position on a straight line CL (see FIG. 1) passing through the center of the wafer W in the same direction as the flow direction of the reaction gas G. When a plurality of wafers W are placed on one susceptor 13 as in the vapor phase growth apparatus 1 of this embodiment, the wafer W is placed on the susceptor 13 most upstream in the flow direction of the reaction gas G. The arrangement position is determined in the arranged state.

  Here, the thickness of the epitaxial layer is unlikely to vary because it passes through the same locus with respect to the center of the susceptor 13 in the direction orthogonal to the flow direction of the reaction gas G. Therefore, if the thickness of the epitaxial layer is evaluated at the measurement position in the same direction (parallel direction) as the flow direction of the reaction gas G, the uniformity of the epitaxial layer thickness in the in-plane direction (in-plane uniformity) over the entire surface of the wafer W. )

  In the present embodiment, the measurement positions P1 to P7 are epitaxial corresponding to the boundaries (the outer wall 24 or the partition member 25) of the six divided spaces 26 (T1 to T6) (see FIG. 3A) in the rectifying unit 2. It becomes the position of the layer. The thickness of the epitaxial layer is measured using, for example, the FTIR method (Fourier transform infrared spectroscopy).

(S2) Epitaxial Layer Formation Step By supplying the reactive gas G from the gas supply source 14 into the chamber 12, an epitaxial layer is formed on the main surface of the semiconductor wafer W accommodated in the chamber 12. Specifically, the reaction gas G is introduced from the gas supply source 14 into the divided spaces 26 in the rectification unit 2 via the supply pipe 16, rectified in the rectification unit 2, and then supplied into the chamber 12.

(S3) Actual thickness measurement step The epitaxial layer formed in the epitaxial layer formation step S2 is measured at the plurality of measurement positions P1 to P7 arranged in the in-plane direction of the semiconductor wafer W. Is also measured). As described above, in the case of the batch-type vapor phase growth apparatus 1, the actual thickness of the epitaxial layer (wafer surface) with the wafer W disposed on the most upstream side in the flow direction of the reaction gas G on the susceptor 13. Measure the intrinsic epi thickness). The actual epitaxial thickness in the wafer plane is measured by, for example, an epitaxial wafer obtained by growing an epitaxial layer on the main surface of a low specific resistance semiconductor wafer using the FTIR method.

(S10) Actual in-wafer epi-epi thickness correction step By operating the opening / closing member 23 based on the wafer in-plane epi-thickness estimation model created in the model creation step S1, the in-wafer in-plane epi measurement is performed in the actual thickness measurement step S3. Modify to minimize thickness variation.

The wafer in-plane actual epitaxial thickness correction step S10 is preferably performed when it is considered that the conditions of the vapor phase growth process have changed greatly, such as after the components of the chamber 12 are cleaned.
The wafer in-plane actual epi thickness correction step S10 includes the following in-wafer in-plane actual epi thickness correction amount calculation step S11, open / close pattern selection step S12, and open / close member operation step S13.

(S11) In-wafer in-plane actual epi-thickness correction amount calculation step The in-wafer in-plane actual epi-thickness correction amount calculation step is calculated so that the variation in the in-wafer in-plane actual epi thickness is minimized.

(S12) Opening / Closing Pattern Selection Step Based on the correction amount of the wafer surface actual epi-thickness correction amount calculation step S11, the opening / closing pattern of the gas outlet 22 by the opening / closing member 23 is selected. The opening / closing pattern of the gas outlet 22 is selected based on the wafer in-plane epitaxial thickness estimation model created in the model creation step S1.

(S13) Opening / closing member operation step The opening / closing member 23 is operated based on the opening / closing pattern of the gas outlet 22 selected in the opening / closing pattern selection step S12. The opening / closing member operating step S13 is performed before the next epitaxial layer forming step S2 ′.
The opening / closing member 23 may alternatively be opened / closed as to whether the gas outlet 22 is completely opened or completely closed. Further, the opening / closing member 23 may adjust the opening degree (opening degree) of the gas outlet 22 steplessly or stepwise (for example, opening with a degree of opening of 70%). The opening / closing member 23 may adjust the opening / closing of the gas outlet 22 (including adjusting the degree of opening) during the vapor phase growth process.
The operation of the opening / closing member 23 can be mechanically performed in conjunction with the opening / closing pattern of the gas outlet 22 selected in the opening / closing pattern selection step S12, or can be performed by an operator's operation.

(S21) Wafer In-plane Epi Thickness Estimation Model Correction Step The wafer in-plane epi thickness estimation model created in the model creation step S1 is based on the wafer in-plane epi thickness measured in the actual thickness measurement step S3 already performed. to correct.

(S2 ′) Epitaxial Layer Formation Step After the wafer in-plane epitaxial thickness estimation model correction step S21, the next epitaxial layer formation step S2 ′ is performed. Prior to the epitaxial layer forming step S2 ′, maintenance such as cleaning of the components of the chamber 12 and changes in the conditions of the vapor phase growth process (change of reaction gas, change of atmospheric gas, change of diameter of the semiconductor wafer W, etc.) And so on.

According to the epitaxial wafer manufacturing method of the present embodiment, the following effects can be obtained.
In the present embodiment, the wafer surface that is corrected so that the variation in the actual epi-thickness in the wafer surface is minimized by operating the opening / closing member 23 based on the in-plane epi-thickness estimation model created in the model creation step S1. A solid epi thickness correction step S10 is provided. Therefore, the uniformity in the in-plane direction with respect to the thickness of the epitaxial layer can be improved. Therefore, an epitaxial wafer having excellent flatness and excellent in-plane distribution of specific resistance can be obtained.

In particular, in the batch type vapor phase growth apparatus 1 that performs processing by mounting a plurality of semiconductor wafers W on one susceptor 13 as shown in FIG. 1, the in-plane direction of the thickness of the epitaxial layer in the wafer This tendency is unclear and does not have an axially symmetric distribution with the center of the wafer as the axis of symmetry. This is because the distribution of the thickness of the epitaxial layer differs depending on the mounting position of the wafer W on the susceptor 13 in the direction toward the rotation center of the susceptor 13 and the rotation direction (circumferential direction) of the susceptor 13.
On the other hand, according to the present embodiment, by adopting a process that can extract the optimum condition based on the relationship between the degree of opening / closing of the gas outlet 22 and the thickness distribution of the epitaxial layer in the direction toward the rotation center of the susceptor 13. The thickness distribution of the epitaxial layer in the direction toward the rotation center of the susceptor 13 can be improved. Therefore, the in-plane uniformity of the thickness of the epitaxial layer can be improved.

  Factors that reduce the flatness of the epitaxial wafer include causes derived from the substrate, such as non-uniformity in the thickness of a semiconductor wafer (such as a silicon wafer) and low polishing accuracy, and vapor phase growth. And factors derived from the process. However, in actual production, the factor that lowers the flatness is often derived from the vapor phase growth process. Therefore, it is important to improve the flatness of the epitaxial wafer to improve the vapor phase growth process. .

Although one embodiment of the epitaxial wafer manufacturing method of the present invention has been described above, the present invention is not limited to the above-described embodiment.
For example, the measurement position for measuring the thickness of the epitaxial layer in the model creation step S1 and the measurement position for measuring the actual thickness of the epitaxial layer (actual epi-thickness in the wafer surface) in the actual thickness measurement step S3 are as follows: There is no particular limitation.
The opening / closing member operating step S13 can also be performed during the epitaxial layer forming step S2.

In the vapor phase growth apparatus 1, the number of the gas outlet 22, the opening / closing member 23, the partition member 25, the divided space 26, and the like is not limited to the number in the above embodiment.
The surface of the rectifying unit 2 on which the gas outlet 22 is provided may be curved along the circumferential direction of the susceptor 13. The rectifying unit 2 may be provided with a rectifying plate.
The vapor phase growth apparatus is not limited to a batch type apparatus, and may be a single wafer type apparatus. Further, the vapor phase growth apparatus may be an apparatus in which a reactive gas is supplied from the side with respect to the main surface of the semiconductor wafer. The semiconductor wafer is not limited to a silicon wafer.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to these.

  The vapor phase growth apparatus 1 described above was used as the vapor phase growth apparatus. The number of gas outlets 22 and opening / closing members 23 is 40.

  First, an epitaxial layer was formed on the main surface of the silicon wafer with all (40) gas outlets 22 fully opened. Experiments are performed to change the flow rate ratio of the reactive gas G flowing out from the gas outlet 22 for each divided space 26, and the flow rate of the reactive gas in each divided space where the distribution in the in-plane direction with respect to the thickness of the epitaxial layer is minimized. The ratio was determined.

  Next, in a state in which the reaction gas G is caused to flow out from the gas outlets 22 located in the respective divided spaces 26 at the flow rate ratio obtained as described above, the gas outlets 22 by the open / close members 23 based on the experimental design method. By performing the opening / closing operation, the distribution in the in-plane direction with respect to the thickness of the epitaxial layer was changed. By analyzing the results of this experiment, the influence of the opening / closing pattern of the gas outlet 22 by each opening / closing member 23 on the distribution in the in-plane direction with respect to the thickness of the epitaxial layer was estimated.

  Specifically, the thickness of the epitaxial layer at each measurement position P1 to P7 was measured. Regarding the thickness of the epitaxial layer, the thickness of the epitaxial layer in the wafer surface was modeled in a state where all the gas outlets 22 were fully opened, and an epitaxial thickness estimation model in the wafer surface was created.

Next, the opening / closing pattern of the gas outlet 22 by the opening / closing member 23 for making the distribution in the in-plane direction about the thickness of the epitaxial layer uniform was calculated using the created wafer in-plane epitaxial thickness estimation model.
The influence of the opening / closing pattern of the gas outlet 22 by the opening / closing member 23 on the thickness of the epitaxial layer can be obtained, for example, as follows.

  In FIG. 5, about the rectification | straightening part 2 which has 40 gas outflow ports 22, 20 gas flows between one edge part (outer wall 24 side) and center parts among 40 gas outflow ports 22. An example is shown in which the outlet 22 (that is, the gas outlet 22 located in the divided space 26 (T1 to T3)) is numbered in ascending order [1] to [20] from one end side. Note that the degree of opening and closing of the gas outlet 22 is not necessarily symmetric with respect to the central portion of the rectifying unit 2 (the central line of the flow of the reaction gas G), and may be asymmetrical. In many cases, the in-plane uniformity of the thickness of the epitaxial layer is optimized when the degree of opening and closing of the gas outlet 22 is asymmetric.

  In the following [Table 1], only the sign of the influence on the thickness of the epitaxial layer at each measurement position P1 to P7 by completely closing the corresponding gas outlet 22 by the opening / closing member 23 is shown. Specifically, “− (minus)” means that the thickness of the epitaxial layer is reduced by closing the gas outlet 22, and “+ (plus)” is epitaxial by closing the gas outlet 22. It means that the thickness of the layer is increased.

  Under the conditions of the example, by closing the gas outlet [2], the thickness of any epitaxial layer is shifted to the negative side, and by closing the gas outlet [15], the thickness of any epitaxial layer is The result of shifting to the positive side was obtained. Regarding the other gas outlets, not only the tendency in one direction but also by appropriately combining the opening and closing of the plurality of gas outlets, the thickness of any epitaxial layer can be minimized within the wafer surface. Adjusted.

Actually, a database is created from numerical data of the wafer in-plane epi-thickness estimation model, and by using this database, it is possible to extract conditions that make the in-plane distribution of the epitaxial layer thickness uniform. it can. Specifically, when an epitaxial layer is grown to a thickness of 30 μm using a 6-inch semiconductor wafer, the thickness of the epitaxial layer obtained with all the gas outlets 22 fully opened is in the in-plane direction. While the distribution is 2.84% (see FIG. 7), the plane of the thickness of the epitaxial layer obtained with [2], [3] and [15] of the gas outlet 22 closed. The inward distribution is 1.20% (see FIG. 6).
Further, the distribution in the in-plane direction with respect to the thickness of the epitaxial layer is improved to 0.82% by adjusting the flow rate ratio of the reaction gas in a state where the opening / closing pattern of the gas outlet 22 by the opening / closing member 23 is fixed. I was able to.

DESCRIPTION OF SYMBOLS 1 Vapor growth apparatus 2 Rectification part 12 Chamber 13 Susceptor 14 Gas supply source 22 Gas outlet 23 Opening / closing member 25 Partition member 26 Divided space (space)
S1 Model creation step S2, S2 'Epitaxial layer formation step S3 Actual thickness measurement step S10 Wafer surface actual epi thickness correction step S11 Wafer surface actual epi thickness correction amount calculation step S12 Open / close pattern selection step S13 Open / close member operation step S21 Wafer surface epi Thickness estimation model correction process W Semiconductor wafer

Claims (1)

A gas supply for supplying a reaction gas containing at least a source gas or a carrier gas into the chamber, a chamber containing the semiconductor wafer, a susceptor installed inside the chamber so that a plurality of the semiconductor wafers can be placed And a rectifying unit having a plurality of gas outlets for allowing the reaction gas supplied from the gas supply source to flow into the chamber, and a plurality of opening and closing members for opening and closing the gas outlets. An epitaxial wafer manufacturing method using a vapor phase growth apparatus for forming an epitaxial layer on the main surface of the semiconductor wafer accommodated in the semiconductor wafer,
A plurality of semiconductor wafers arranged on the susceptor at a predetermined interval along the rotation direction of the susceptor and arranged in a direction toward the rotation center of the susceptor and on a straight line passing through the center of the semiconductor wafer. In the measurement position, all the gas outlets are fully opened by operating the opening / closing member, the thickness of the epitaxial layer in the wafer surface is measured, and further, the gas outlets are opened from the state where all the gas outlets are fully opened. By operating the member and closing only one of the gas outlets to determine the effect on the thickness of the epitaxial layer, modeling is performed on the plurality of gas outlets, and the wafer in-plane epitaxy is determined. A model creation process for creating a thickness estimation model;
An epitaxial layer forming step of forming the epitaxial layer on the semiconductor wafer;
An actual thickness measuring step of measuring an actual epi-thickness in a wafer surface that is an actual thickness of the epitaxial layer at the plurality of measurement positions with respect to the epitaxial layer formed by the epitaxial layer forming step;
By operating the opening / closing member based on the wafer surface epi-thickness estimation model created by the model creation step, the gas outlet corresponding to the opening / closing member is opened and closed, and the wafer surface actual epi-thickness In-wafer in-plane actual epi-thickness correction process for correction so as to minimize the variation,
Wafer-plane epi-thickness estimation model correction step for correcting the wafer-plane epi-thickness estimation model created in the model creation step based on the wafer-plane actual epi-thickness measured in the actual thickness measurement step that has already been performed And comprising
The wafer surface actual epi thickness correction step is
A wafer surface actual epi thickness correction amount calculating step for calculating the wafer surface actual epi thickness correction amount; and
An opening / closing pattern selection step of selecting an opening / closing pattern of the gas outlet by the opening / closing member based on the correction amount of the wafer surface actual epi thickness correction amount calculated by the wafer surface actual epi thickness correction amount calculation step;
An opening / closing member operating step for operating the opening / closing member based on the opening / closing pattern of the gas outlet selected by the opening / closing pattern selection step;
With
The rectifying unit has an internal space partitioned into a plurality of spaces, a plurality of the gas outlets arranged corresponding to the plurality of spaces, and the reaction gas introduced into the space corresponds to the space An epitaxial wafer manufacturing method characterized by being configured to flow out from the gas outlet.

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