JP5237683B2 - Video signal transmission device, reception device, and video transmission device - Google Patents

Description

  The present invention relates to a video signal transmission device, a reception device, and a video transmission device, and more particularly to a technique for multiplexing and transmitting a plurality of digital video signals.

  2. Description of the Related Art Conventionally, for example, a device described in Non-Patent Document 1 is known as a video transmission device that transmits a large-capacity video signal. This video transmission apparatus transmits a plurality of uncompressed digital high-definition signals using an IP network which is a bidirectional communication path.

  In such a video transmission device, a video signal is transmitted by synchronizing a video clock between a transmission-side device (transmission device) and a reception-side device (reception device) in a bidirectional communication path. ing. Non-Patent Document 2 describes an outline of video clock synchronization technology and experimental results in a bidirectional communication path.

Mochida, 1 outside, "Uncompressed HDTV video multiplex transmission technology in 10 Gigabit network" i-Visto Gateway XG "", NTT Technical Journal, February 2005, 2005 vol. 17 No. 2, p. 47-49 Shimizu, 3 others, “Joint Experiment on Multi-point Synchronous Transmission of Uncompressed HDTV Video by i-Visto”, NTT Technical Journal, March 2005, 2005 vol. 17 No. 3, p. 85-88

  According to the video clock synchronization technique of Non-Patent Document 2, the receiving device monitors the data amount of the video frame buffer provided in the device itself, and detects the frequency shift of the video clock. To control. In other words, this video clock synchronization technique can be applied to a bidirectional communication path, but is applied to a unidirectional communication path (a unidirectional communication path through which a video signal is transmitted from a transmission device to a reception device). There was a problem that could not.

  Accordingly, in order to solve the above-described problem, an object of the present invention is to operate a receiver for a long time by reproducing a video clock of a transmitter when transmitting a plurality of video signals using a unidirectional communication path. It is another object of the present invention to provide a transmission device, a reception device, and a video transmission device that can transmit a stable video signal.

In order to achieve the above object, a first aspect of the present invention provides a transmission apparatus for multiplexing and transmitting uncompressed digital video signals input from a plurality of video devices to a reception apparatus via a unidirectional communication path. , a video clock generation unit for generating an image clock as a reference of signal processing on the plurality of digital video signals, said plurality of said plurality of digital video signal generated-out based on the video clock in the video equipment On the other hand, for each system corresponding to each of the plurality of digital video signals , based on the video clock, the data amount of one frame or one line in the digital video signal is divided into video data of a predetermined size divisible by an integer, wherein generating a video signal packet including video data, a multiplexing unit for multiplexing a transmission frame including the video signal packet, the For example, the receiving apparatus, from the signal of the received transmission frame, thereby reproducing the video clock for signal processing, characterized in that.

According to a second aspect of the present invention, in the transmission device according to the first aspect, the multiplexing unit divides the video data into the predetermined size video data based on the video clock for each system of the digital video signal. A signal data dividing unit, a video signal packet generating unit for generating a video signal packet including the video data divided by the video signal data dividing unit based on the video clock, and a transmission frame header indicating a head of the transmission frame. A transmission frame header generation unit that generates the video signal packet for each system of digital video signals generated by the video signal packet generation unit, the transmission frame header generated by the transmission frame header generation unit, A packet combining unit that generates a transmission frame including the combined video signal packet. And wherein the door.

Further, the invention of claim 3 is the transmission device according to claim 1 , further comprising the video clock input, and synchronized with the video clock from the relationship between the size of the video data and the size of the video signal packet. A transmission clock generating unit that generates a first transmission clock and generates a second transmission clock synchronized with the video clock based on a relationship between the size of the video data and the transmission frame; and the multiplexing unit includes the video The digital video signal is divided into video data of a predetermined size using a clock, a video signal packet including the video data is generated using the first transmission clock, and the second transmission clock is used. And multiplexing to a transmission frame including the video signal packet .

  According to a fourth aspect of the present invention, in the transmission device according to any one of the first to third aspects, the digital video signal is an HD-SDI signal.

According to a fifth aspect of the present invention , each digital video signal is generated in a plurality of video devices based on a video clock serving as a reference for digital video signal processing, and each system corresponding to each of the plurality of digital video signals is generated. Further, the data amount of one frame or one line in the digital video signal is divided into video data of a predetermined size that is divisible by an integer, a video signal packet including the video data is generated, and multiplexed into a transmission frame including the video signal packet. and, from said transmitting apparatus for transmitting a signal of a transmission frame in synchronization with the video clock, a receiver for receiving a signal of the transmission frame via a unidirectional communication path from the signal of the transmission frame and the reception, the A video clock reproduction unit for reproducing a video clock, and a video clock reproduced by the video clock reproduction unit. Based on the click, the signal transmission the received frame, and a separation unit for separating a video signal packet for each line of the digital video signal included in the transmission frame, based on the video clock, the separation The video data of the predetermined size included in the video signal packet separated by the unit is reproduced, and a plurality of original digital video signals before being multiplexed by the transmission device are generated.

  The invention according to claim 6 is the receiving apparatus according to claim 5, wherein the transmitting apparatus receives the clock signal used as a reference when the transmitting apparatus multiplexes a plurality of digital video signals to generate a transmission frame. A reception interface unit for reproducing from a frame signal, wherein the video clock reproduction unit divides the clock signal reproduced by the reception interface unit and reproduces the video clock by a PLL (Phase Locked Loop); To do.

  The invention according to claim 7 is the receiving apparatus according to claim 5 or 6, wherein the digital video signal is an HD-SDI signal.

  The invention of claim 8 is provided with the transmitter according to any one of claims 1 to 4 and the receiver according to any one of claims 5 to 7. This is a featured video transmission apparatus.

  As described above, according to the present invention, when a plurality of video signals are transmitted using a unidirectional communication path, the receiving device reproduces the video clock of the transmitting device. As a result, all signal processing units in the transmission device and the reception device operate in synchronization with the video clock of the transmission device. Therefore, even if the transmission device and the reception device are operated for a long time, video data underflow and overflow do not occur, so that a stable video signal can be transmitted.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
[Video transmission equipment]
First, the video transmission apparatus will be described. FIG. 1 is a diagram illustrating an overall configuration of a video transmission apparatus including a transmission apparatus and a reception apparatus according to an embodiment of the present invention. The video transmission device 1 is a video transmission system that transmits a plurality of digital video signals (hereinafter referred to as “video signals”) using a unidirectional communication path, and includes a transmission device 2 and a reception device 3. The transmission device 2 and the reception device 3 are connected by a transmission path 4 that is a unidirectional communication path.

  The transmission device 2 multiplexes a plurality of video signals based on the video clock generated by the own device, and constitutes a transmission frame. Then, the transmission signal composed of the transmission frame is transmitted to the receiving device 3 through the transmission path 4. Here, when the transmission apparatus 2 constructs a transmission frame, the transmission apparatus 2 has a size that can divide the data amount (bit number, byte number) of one frame in the video signal or the data amount (bit number, byte number) of one line by an integer. Based on the reference, the video signal is divided. By configuring a transmission frame based on such a size, the reception device 3 can reproduce the video clock used by the transmission device 2. That is, in the transmission device 2 and the reception device 3, signal processing can be performed based on the same video clock. Details will be described later.

  The reception device 3 receives the transmission signal transmitted from the transmission device 2, reproduces a clock synchronized with the video clock used in the transmission device 2, and generates a plurality of original video signals from the received transmission signal. .

  The transmission path 4 is a unidirectional communication path through which a plurality of video signals are transmitted as transmission signals from the transmission apparatus 2 to the reception apparatus 3. For example, a wireless transmission line or an optical fiber transmission line.

[Transmitter]
Next, the transmission device 2 shown in FIG. 1 will be described. FIG. 2 is a block diagram showing a configuration of the transmission apparatus 2 according to the embodiment of the present invention. The transmission device 2 includes a video clock generation unit 21, an HDTV synchronization signal generation unit 22, an HDTV interface unit (HDTV I / F) 23-1 to 23-6, a transmission clock generation unit 24, a multiplexing unit 25, and a transmission interface unit ( Tx I / F) 26.

  The video clock generator 21 generates a video clock signal that serves as a reference clock for video signal processing in the video transmission device 1. For example, the high vision 1080 50i standard generates a 74.25 MHz signal as a video clock, and the 1080 59.94i standard generates a 74.25 / 1.001 MHz signal as a video clock. This video clock signal is output to the HDTV synchronization signal generator 22, the transmission clock generator 24, and the multiplexer 25.

  The HDTV sync signal generator 22 receives the video clock signal generated by the video clock generator 21 and generates a sync signal (HDTV sync signal) for processing a high-definition video signal based on the video clock. This synchronization signal is a positive / negative bipolar ternary signal standardized by BTA S-001B in the Radio Industries Association (ARIB), and is output to the HDTV interface units 23-1 to 23-6.

  The HDTV interface units 23-1 to 23-6 input / output signals to / from the video devices 5-1 to 5-6 and output the input video signals to the multiplexing unit 25. Specifically, the synchronization signal generated by the HDTV synchronization signal generator 22 is input and output to the video devices 5-1 to 5-6, respectively. Also, video signals are input from the video devices 5-1 to 5-6 and output to the multiplexing unit 25, respectively. The HDTV interface units 23-1 to 23-6 are required as many as the number of video signals multiplexed in the multiplexing unit 25. In the example of FIG.

  Here, the video devices 5-1 to 5-6 are, for example, high-vision cameras, which receive a synchronization signal from the HDTV interface units 23-1 to 23-6 of the transmission device 2, and based on the synchronization signal, the transmission device A clock synchronized with the video clock signal generated by the second video clock generator 21 is generated inside the video equipment. The video devices 5-1 to 5-6 use the synchronized clock and operate the video signal processing circuit inside the video device to synchronize with the video clock signal generated by the video clock generation unit 21 of the transmission device 2. The generated video signal (HDTV video signal) is generated. This video signal is, for example, an HDTV serial digital signal (HD-SDI signal) standardized by SMPTE 292M, and is output to the HDTV interface units 23-1 to 23-6 of the transmission device 2.

  The transmission clock generator 24 receives the video clock signal generated by the video clock generator 21 and generates a transmission clock signal synchronized with the synchronization signal generated by the HDTV synchronization signal generator 22 based on the video clock. This transmission clock signal is a signal serving as a reference of a transmission signal obtained by multiplexing a plurality of video signals transmitted from the transmission device 2, and is output to the multiplexing unit 25 and the transmission interface unit 26, and has a frequency necessary for signal processing. Used as a clock signal. Details of the transmission clock generator 24 will be described later.

  The multiplexing unit 25 receives a video signal from the HDTV interface units 23-1 to 23-6, a video clock signal from the video clock generation unit 21, and a transmission clock signal from the transmission clock generation unit 24. Multiple input video signals are multiplexed according to the signal format. The multiplexed video signal is output to the transmission interface unit 26 as a transmission frame signal. The embodiment of the present invention is characterized in that the transmission frame signal generated by the multiplexing unit 25 has a signal format that allows the reception device 3 to reproduce the video clock. Details of the multiplexing unit 25 will be described later.

  The transmission interface unit 26 receives a transmission frame signal from the multiplexing unit 25 and a transmission clock signal from the transmission clock generation unit 24, respectively, and performs processing for converting the signal into a format suitable for the transmission signal, for example, parallel / serial conversion Then, processing such as signal amplification is performed, converted into an electric / optical signal or a radio wave signal, and transmitted as a transmission signal to the receiver 3 via the transmission line 4.

[Transmission frame]
Next, the transmission frame will be described. FIG. 3 is a diagram for explaining a configuration example of a transmission frame when the video signal is an HD-SDI signal. The transmission frame signal shown in FIG. 3 is a signal generated by multiplexing six video signals by the multiplexing unit 25 of the transmission apparatus 2 shown in FIG. The transmission frame signal is composed of a plurality of transmission frames, and the transmission frame is composed of a plurality of sets each including a transmission frame header and six video signal packets (video signal packets). The transmission frame header is composed of data for detecting frame synchronization of the transmission frame, and is periodically inserted into the transmission frame signal. The video signal packet is data obtained by dividing the video signal into packets. That is, the packet 1 of the video signal 1, the packet 2 of the video signal 1, and the like are data obtained by dividing the video signal from the HDTV interface unit 23-1 into packets set in advance. Similarly, packets 1 and 2 of the video signals 2 to 6 are data obtained by dividing the video signals from the HDTV interface units 23-2 to 23-6 into packets set in advance.

[Video signal packet]
Next, the video signal packet will be described. FIG. 4 is a diagram for explaining a configuration example of a video signal packet. This video signal packet corresponds to the video signal packet in the transmission frame shown in FIG. 3, and includes a packet header, video data, and parity. The packet header consists of data for detecting the synchronization of video signal packets. The video data is data obtained by dividing a video signal by a predetermined size. Since it is necessary to reproduce the video clock in the receiving device 3, the size is such that the data amount of one frame in the video signal or the data amount of one line in the video signal is exactly divisible by an integer, that is, video If the data amount of one frame or one line in the signal is divisible by an integer, the size of the division result may be used.

  FIG. 5A and FIG. 5B are diagrams showing examples of the size of video data necessary for reproducing the video clock in the receiving device 3. FIG. 5A shows an example in which the division size of the video data is in units of one line. Specifically, when the size of the video data constituting the video signal packet is in units of one line, in the 1080 50i standard, the size is 5280 words (one word is 10 bits), that is, 52800 bits. Further, in the case of the standard of 1080 59.94i, the size is 4400 words, that is, 44000 bits.

  On the other hand, FIG. 5B shows an example in which the division size of the video data is set to 1/10 unit of one line. Specifically, when the size of the video data constituting the video signal packet is 1/10 unit of one line, in the case of 1080 50i standard, the size is 528 words, that is, 5280 bits. In the case of the standard of 1080 59.94i, the size is 440 words, that is, 4400 bits.

  As shown in FIGS. 5A and 5B, the multiplexing unit 25 divides the input video signal into video data having a size in which the data amount of one frame or one line is exactly divisible by an integer, A transmission frame including a video signal packet including video data of that size is generated.

(Multiple part)
Next, the multiplexing unit 25 of the transmission device 2 illustrated in FIG. 2 will be described. FIG. 6 is a block diagram illustrating a configuration of the multiplexing unit 25. The multiplexing unit 25 includes video signal data division units 251-1 to 251-6, error correction code parity generation units 252-1 to 252-6, packet header generation units 253-1 to 253-6, and video signal packet generation units. 254-1 to 254-6, a transmission frame header generation unit 255, and a packet synthesis unit 256. Also, the video signal data division units 251-1 to 251-6, the error correction code parity generation units 252-1 to 252-6, the packet header generation units 253-1 to 253-6, and the video signal packet generation units 254-1 to 251-2. 254-6 constitute first to sixth signal processing systems, respectively. These signal processing systems are the same signal processing system corresponding to the number of video signals to be multiplexed. FIG. 6 shows an example in which six video signals are multiplexed. Here, in order to correct the transmission path error, parity for error correction is added to the packet, but the parity for error correction may not be present.

  With such a configuration, the multiplexing unit 25 inputs video signals from the HDTV interface units 23-1 to 23-6, receives a video clock from the video clock generation unit 21, and receives a transmission clock from the transmission clock generation unit 24. However, for each video signal, a video signal packet is generated by dividing the video signal into video data of a preset size (size in which the amount of data of one frame or one line of the input video signal is exactly divisible by an integer). Then, the generated video signal packet is synthesized to generate a transmission frame. Hereinafter, the first signal processing system will be specifically described.

  The video signal data dividing unit 251-1 receives the video signal from the HDTV interface unit 23-1, and divides the input video signal into video data of a preset size. The divided video data is output to the error correction code parity generation unit 252-1 and the video signal packet generation unit 254-1.

  The error correction code parity generation unit 252-1 receives the video data divided from the video signal data division unit 251-1 and generates parity for performing error correction on the video data. The generated parity is output to the video signal packet generation unit 254-1.

  The packet header generating unit 253-1 generates packet synchronization detection data (information indicating the head of the video signal packet) of the video signal packet as a packet header. The generated packet header is output to the video signal packet generation unit 254-1 and used to detect the video signal packet in the receiving device 3.

  The video signal packet generator 254-1 receives the video data divided from the video signal data divider 251-1, the parity from the error correction code parity generator 252-1, and the packet header from the packet header generator 253-1. These are input and combined to generate the video signal packet shown in FIG. The generated video signal packet is output to the packet combining unit 256. Although the first signal processing system has been described above, the same applies to the second to sixth signal processing systems.

  The transmission frame header generation unit 255 generates frame synchronization detection data (information indicating the beginning of the transmission frame) of the transmission frame as the transmission frame header. The generated transmission frame header is output to the packet combining unit 256 and used for detecting the transmission frame in the reception device 3.

  The packet synthesizer 256 receives video signal packets from the video signal packet generators 254-1 to 254-6 of the first to sixth signal processing systems, and receives a transmission frame header from the transmission frame header generator 255, The video signal packet and transmission frame header of each system are multiplexed and combined to generate the transmission frame shown in FIG. 3, and output it as a transmission frame signal. The video signal packets input from the video signal packet generators 254-1 to 254-6 of the first to sixth signal processing systems are all the same size.

  FIG. 7A shows the video signal packet generators 254-1 to 254 shown in FIG. 6 when each signal processing unit such as the HDTV interface unit 23-1 in the transmission apparatus 2 operates in synchronization with the video clock. It is a figure which shows the structural example of the video signal packet produced | generated by -6. This video signal packet has a total data amount of 53,100 bits when the packet header is 100 bits, the video signal division size (video data) is 52,800 bits (for one video line), and the error correction parity is 200 bits. An example is shown. That is, the video signal data division units 251-1 to 251-6 divide the video signal into video data of 52800 bit size, and the error correction code parity generation units 252-1 to 252-6 divide the video signal into the divided video data. On the other hand, 200-bit parity for error correction is generated, and the packet header generation units 253-1 to 253-6 generate 100-bit packet headers. The video signal packet generators 254-1 to 254-6 combine the video data, the parity, and the packet header to generate the video signal packet shown in FIG.

  FIG. 7B shows a transmission frame generated by the packet combining unit 256 shown in FIG. 6 when each signal processing unit such as the HDTV interface unit 23-1 in the transmission device 2 operates in synchronization with the video clock. It is a figure which shows the example of a structure. This transmission frame shows an example in which the total data amount is 319200 bits when the transmission frame header is 600 bits and each video signal packet is 53100 bits. That is, the transmission frame header generation unit 255 generates a 600-bit transmission frame header, and the packet synthesis unit 256 includes the video signal packets from the video signal packet generation units 254-1 to 254-6 and the transmission frame header generation unit. The transmission frame header from 255 is multiplexed and combined to generate the transmission frame shown in FIG.

  FIG. 8 shows a system diagram of the system clock with respect to the clock frequency used in the multiplexing unit 25 of the transmission apparatus 2 shown in FIG. Hereinafter, the video signal data division unit 251 (video signal data division) of the multiplexing unit 25 in the case of the configuration example of the video signal packet shown in FIG. 7A and the configuration example of the transmission frame shown in FIG. Used in the video signal packet generating unit 254 (meaning each unit of the video signal packet generating units 254-1 to 254-6) and the packet synthesizing unit 256. The clock frequency will be described.

  The video signal data dividing unit 251 inputs a video clock signal having a frequency of 74.25 MHz from the video clock generating unit 21. That is, the clock frequency used in the video signal data dividing unit 251 is the same as the video clock frequency 74.25 MHz.

  Therefore, the video signal data dividing unit 251 divides the video signal into video data having a preset 52800 bit size by using a clock frequency of 74.25 MHz of the video clock.

The video signal packet generator 254 receives from the transmission clock generator 24 a transmission clock signal having a frequency of 74.671875 MHz obtained by multiplying the video clock from the video clock generator 21 by 177/176. The clock frequency of the video signal packet generation unit 254 is based on the relationship between the video data size 52800 bits, which is the video signal division size, and the video signal packet size 53100 bits, and the video clock frequency × video signal packet size / video signal. Calculated by the division size. In particular,
74.25 MHz × 53100/52800 = 74.25 MHz × 177/176
= 74.671875 MHz
It is. Here, 74.25 MHz is the frequency of the video clock when the video signal data is a 20-bit parallel signal in the 1080 50i standard. The size of the video signal packet is the total size of the video signal division size, the packet header size, and the error correction parity size.

  Therefore, the video signal packet generation unit 254, when the video signal division size (video data size) corresponds to the frequency of the video clock, the clock frequency corresponding to the size of the video signal packet, that is, the clock of frequency 74.6671875 MHz. Is used to synthesize video data and the like to generate a video signal packet.

The packet synthesizer 256 receives from the transmission clock generator 24 a transmission clock signal having a frequency of 448.875 MHz obtained by multiplying the video clock from the video clock generator 21 by 133/22. The clock frequency of the packet synthesizer 256 is determined from the relationship between the video data size of 52800 bits, which is the division size of the video signal, and the multiplexed transmission frame size of 319200 bits, the video clock frequency × multiplexed transmission frame size / video. It is calculated by the division size of the signal. In particular,
74.25 MHz × 319200/52800 = 74.25 MHz × 133/22
= 448.875 MHz
It is. Here, the multiplexed transmission frame size is a size calculated by video signal packet size × multiplex number + transmission frame header size.

  Therefore, when the division size (video data size) of the video signal corresponds to the frequency of the video clock, the packet synthesis unit 256 uses a clock frequency corresponding to the size of the transmission frame, that is, a clock having a frequency of 448.875 MHz. The video signal packets are multiplexed and combined to generate a transmission frame.

The transmission interface unit 26 receives a clock signal having a frequency of 448.875 MHz obtained by multiplying the video clock from the video clock generation unit 21 by 133/22 from the transmission clock generation unit 24. The clock frequency of the transmission interface unit 26 is the bit length × 20 bits from the relationship between the bit length of 20 bits of the parallel signal when converting the parallel signal to the serial signal and the clock frequency of 448.875 MHz in the packet synthesis unit 256 of the multiplexing unit 25. It is calculated by the clock frequency in the packet combining unit 256. In particular,
20 × 448.875 MHz = 8.9775 GHz
It is.

  Therefore, the transmission interface unit 26 uses a transmission clock having the same frequency of 448.875 MHz as the multiplexing unit 25, performs parallel-serial conversion on the transmission frame signal, which is a parallel signal from the multiplexing unit 25, and converts the converted serial signal into a transmission signal. Send as.

  As described above, according to the transmission device 2 according to the embodiment of the present invention, the HDTV interface units 23-1 to 23-6 receive the synchronization signal generated based on the video clock from the HDTV synchronization signal generation unit 22. And interface processing. The multiplexing unit 25 receives the video clock signal from the video clock generation unit 21 and the transmission clock signal generated by multiplying the video clock from the transmission clock generation unit 24, respectively, and performs multiplexing processing. In addition, the transmission interface unit 26 receives the transmission clock generated by multiplying the video clock from the transmission clock generation unit 24 and performs interface processing. Thereby, these signal processing units can operate in synchronization with the video clock generated by the video clock generation unit 21. In addition, the transmission device 2 can transmit a transmission signal synchronized with the video clock.

  Thereby, the receiving device 3 reproduces the video clock (video clock of the transmitting device 2) by receiving the transmission signal synchronized with the video clock transmitted by the transmitting device 2 via the transmission path 4. Can do. That is, all signal processing units in the transmission device 2 and the reception device 3 operate in synchronization with the video clock of the transmission device 2. Therefore, even if the transmission device 2 and the reception device 3 are operated for a long time, video data underflow and overflow do not occur, so that a stable video signal can be transmitted.

[Receiver]
Next, the receiving apparatus 3 shown in FIG. 1 will be described. FIG. 9 is a block diagram showing a configuration of the receiving device 3 according to the embodiment of the present invention. The receiving device 3 includes a reception interface unit (Rx I / F) 31, a video clock reproduction unit 32, a separation unit 33, error correction / HD-SDI frame processing units 34-1 to 34-6, and an HD-SDI transmission interface unit. (HD-SDI Tx I / F) 35-1 to 35-6. The following description is based on the video signal packet size shown in FIG. 7A, the transmission frame size shown in FIG. 7B, and the frequency and multiplication rate shown in FIG.

  The reception interface unit 31 receives a transmission signal (electrical / optical signal or radio wave format signal) synchronized with the video clock from the transmission device 2 via the transmission path 4 and performs clock recovery. Specifically, a clock recovery process is performed using a CDR (Clock Data Recovery) circuit or the like to generate a recovered clock signal having a frequency of 448.875 MHz. The reception interface unit 31 performs synchronization processing on the received transmission signal and performs serial / parallel conversion processing and the like. The reproduction clock signal generated in this way is output to the video clock reproduction unit 32, and the signal subjected to the synchronization processing, the serial / parallel conversion processing, and the like is sent to the separation unit 33 as a video signal synchronized with the reproduction clock signal. Is output.

  The video clock reproduction unit 32 receives a reproduction clock signal having a frequency of 448.875 MHz from the reception interface unit 31, divides this reproduction clock signal by 22/133 by a frequency dividing circuit, and has the same frequency as the video clock of 74.25 MHz. The clock signal is generated. Then, a stable clock signal is generated by a PLL using a VCXO (Voltage Control Xtal) or the like. The clock signal output from the PLL is synchronized with the transmission signal transmitted by the transmission device 2. That is, it is synchronized with the video clock which is the reference of the transmission device 2. Thereby, the video clock signal can be reproduced. Alternatively, the recovered clock signal may be directly input to Xtal without separating the recovered clock signal to generate a stable 74.25 MHz clock.

  The video clock reproduction unit 32 multiplies the clock signal from the PLL by 133/22, generates a clock signal having a frequency of 488.875 MHz, and outputs the clock signal to the separation unit 33. Also, the clock signal from the PLL is multiplied by 177/176 to generate a clock signal having a frequency of 74.671875 MHz and output to the error correction / HD-SDI frame processing units 34-1 to 34-6. Also, a clock signal having a frequency of 74.25 MHz from the PLL is output to the HD-SDI transmission interface units 35-1 to 35-6.

  The separation unit 33 receives the video signal from the reception interface unit 31, receives the clock signal having a frequency of 488.875 MHz from the video clock reproduction unit 32, and synthesizes the transmission frame header performed by the multiplexing unit 25 of the transmission device 2. The reverse process of the process to perform is performed. Further, the transmission frame header of the transmission frame and the packet header of the video signal packet are detected and divided into signals for each system, and the video signal is separated. Here, the video signal is separated into the same number (six) of signals as multiplexed by the multiplexing unit 25. The separated video signals are output to the error correction / HD-SDI frame processing units 34-1 to 34-6, respectively.

  The error correction / HD-SDI frame processing unit 34-1 receives the video signal of the first signal processing system among the six video signals separated by the separation unit 33, and receives the frequency 74. A clock signal of 671875 MHz is input, and the transmission path error is corrected using the error correction parity (the parity of the video signal packet) generated by the error correction code parity generation unit 252-1 of the transmission apparatus 2. Then, a video signal (signal frame) that is an HD-SDI signal is processed by reversing the video data, error correction parity, and packet header synthesis processing performed by the video signal packet generation unit 254-1 of the transmission device 2. ). The reproduced signal frame is output to the HD-SDI transmission interface unit 35-1. The same applies to the error correction / HD-SDI frame processing units 34-2 to 34-6.

  The HD-SDI transmission interface unit 35-1 receives a signal frame from the error correction / HD-SDI frame processing unit 34-1, and receives a clock signal having a frequency of 74.25 MHz from the video clock reproduction unit 32. After performing the conversion process or the like, a video signal in a prescribed format (in this example, an HD-SDI signal) is output. The same applies to the HD-SDI transmission interface units 35-2 to 35-6.

  As described above, according to the reception device 3 according to the embodiment of the present invention, the reception interface unit 31 regenerates the clock signal from the received transmission signal, and the video clock reproduction unit 32 transmits the signal using the frequency divider and the PLL. A signal synchronized with the signal, that is, a signal synchronized with the video clock signal of the transmission apparatus 2 is reproduced. Then, the video clock reproduction unit 32 generates a clock signal by multiplying the reproduced video clock signal by a preset magnification, and the clock signal (a clock synchronized with the video clock of the transmission device 2). Signal) is supplied to the signal processing units of the separation unit 33, error correction / HD-SDI frame processing units 34-1 to 34-6, and HD-SDI transmission interface units 35-1 to 35-6. Accordingly, each signal processing unit of the receiving device 3 can operate in synchronization with the video clock, and thus can operate in synchronization with each signal processing unit of the transmission device 2. Therefore, even if the transmission device 2 and the reception device 3 are operated for a long time, video data underflow and overflow do not occur, so that a stable video signal can be transmitted.

  The present invention has been described above with the embodiment raised, but the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the technical idea thereof. In the embodiment, the signal processing is performed by six systems in the transmission device 2 and the reception device 3, but the present invention does not limit the number of systems.

  In the embodiment, the multiplexing unit 25 of the transmission device 2 is configured such that the video signal 1 packet 1, the video signal 2 packet 1,..., The video signal 6 packet 1, video, as shown in FIG. The transmission frame is generated by multiplexing the packet 1 of the signal 1, the packet 2 of the video signal 2,..., The packet 2 of the video signal 6, and so on. It is not limited. For example, video signal 1 packet 1, video signal 1 packet 2, ..., video signal 1 packet 6, video signal 2 packet 1, video signal 2 packet 2, ..., video signal 2 packet A transmission frame may be generated by multiplexing in the order of 6,. That is, as illustrated in FIG. 3, the multiplexing unit 25 may generate a transmission frame by multiplexing each packet in the order of the video signals 1 to 6, or 6 in the order of the video signals 1 to 6. A transmission frame may be generated by multiplexing each packet.

  In the embodiment, the packet header generation units 253-1 to 253-6 of the multiplexing unit 25 in the transmission device 2 generate packet headers, and the video signal packet generation units 254-1 to 254-6 include packet headers. Is generated, and the separation unit 33 of the reception device 3 detects the packet header included in the video signal packet and separates it into video signals for each system. 25 may not include the video signal packet generation unit 254. In this case, the video signal packet generation units 254-1 to 254-6 of the transmission device 2 generate video signal packets that do not include a packet header, and the separation unit 33 of the reception device 3 includes a transmission frame header included in the transmission frame. Thus, the head of the transmission frame is detected, a predetermined bit length is counted from the head, video signal packets are divided for each system, and separated into video signals for each system.

  In the above embodiment, the video signal is described as an HD-SDI signal. However, the present invention is not limited to this signal, and can be applied to other signals.

1 is a diagram illustrating an overall configuration of a video transmission apparatus including a transmission apparatus and a reception apparatus according to an embodiment of the present invention. It is a block diagram which shows the transmitter by embodiment of this invention. It is a figure explaining the structural example of the transmission frame in case a video signal is a HD-SDI signal. It is a figure explaining the structural example of a video signal packet. (A) is a figure which shows the example which made the division size of video data the unit of 1 line. (B) is a diagram illustrating an example in which the division size of video data is set to 1/10 unit of one line. It is a block diagram which shows the structure of the multiplexing part of a transmitter. (A) is a figure which shows the structural example of a video signal packet in case each signal processing part of a transmission apparatus operate | moves synchronizing with a video clock. (B) is a figure which shows the structural example of a transmission frame. It is a systematic diagram of the system clock which a transmitter uses. It is a block diagram which shows the structure of the receiver by embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Video transmission apparatus 2 Transmission apparatus 3 Reception apparatus 4 Transmission path 5 Video equipment 21 Video clock generation part 22 HDTV synchronous signal generation part 23 HDTV interface part 24 Transmission clock generation part 25 Multiplexing part 26 Transmission interface part 31 Reception interface part 32 Video clock Playback unit 33 Separation unit 34 Error correction / HD-SDI frame processing unit 35 HD-SDI transmission interface unit 251 Video signal data division unit 252 Error correction code parity generation unit 253 Packet header generation unit 254 Video signal packet generation unit 255 Transmission frame header Generation unit 256 Packet synthesis unit

Claims (8)

In a transmission device that multiplexes and transmits each uncompressed digital video signal input from a plurality of video devices to a reception device via a unidirectional communication path,
A video clock generating unit that generates a video clock serving as a signal processing reference for the plurality of digital video signals;
Wherein the plurality of said plurality of digital video signal generated-out based on the video clock in the video equipment, each system corresponding to each of the plurality of digital video signals, on the basis of the video clock, the digital image A multiplexing unit that divides the data amount of one frame or one line in the signal into video data of a predetermined size that is divisible by an integer, generates a video signal packet including the video data, and multiplexes the video signal packet into a transmission frame including the video signal packet; With
A transmitting apparatus, wherein the receiving apparatus reproduces a video clock for signal processing from a signal of a received transmission frame. The transmission apparatus according to claim 1,
The multiplexing unit is
A video signal data dividing unit that divides the digital video signal into video data of the predetermined size based on the video clock for each system of the digital video signal;
A video signal packet generator that generates a video signal packet including video data divided by the video signal data divider based on the video clock;
A transmission frame header generation unit that generates a transmission frame header indicating the beginning of the transmission frame;
A transmission including the transmission frame header generated by the transmission frame header generation unit and the combined video signal packet by combining the video signal packets for each system of the digital video signal generated by the video signal packet generation unit A packet synthesis unit for generating a frame;
A transmission device comprising: The transmission apparatus according to claim 1 ,
Further, the video clock is input, and a first transmission clock synchronized with the video clock is generated from the relationship between the size of the video data and the size of the video signal packet, and the size of the video data and the transmission frame From the relationship, a transmission clock generation unit that generates a second transmission clock synchronized with the video clock,
The multiplexing unit is
The digital clock signal is divided into video data of the predetermined size using the video clock, the video signal packet including the video data is generated using the first transmission clock, and the second transmission clock And a transmission frame including the video signal packet . In the transmission device according to any one of claims 1 to 3,
A transmission apparatus characterized in that the digital video signal is an HD-SDI signal. Each digital video signal is generated in a plurality of video devices based on a video clock serving as a reference for digital video signal processing, and one frame in the digital video signal is generated for each system corresponding to each of the plurality of digital video signals. Alternatively, the data amount of one line is divided into video data of a predetermined size divisible by an integer, a video signal packet including the video data is generated, multiplexed in a transmission frame including the video signal packet, and transmitted in synchronization with the video clock A receiving device that receives a signal of the transmission frame from a transmitting device that transmits a signal of a frame via a unidirectional communication path ,
A video clock recovery unit for recovering the video clock from the received transmission frame signal;
A separation unit that separates the received transmission frame signal into video signal packets for each system of digital video signals included in the transmission frame, based on the video clock reproduced by the video clock reproduction unit;
Based on the video clock, reproduce the video data of the predetermined size included in the video signal packet separated by the separation unit, and generate a plurality of original digital video signals before the transmission device multiplexes. A receiving device. The receiving device according to claim 5,
A reception interface unit that reproduces a clock signal, which is a reference when the transmission device generates a transmission frame by multiplexing a plurality of digital video signals, from the signal of the received transmission frame;
The receiving apparatus according to claim 1, wherein the video clock reproduction unit divides the clock signal reproduced by the reception interface unit and reproduces the video clock by a PLL (Phase Locked Loop). The receiving device according to claim 5 or 6,
A receiving apparatus, wherein the digital video signal is an HD-SDI signal.   A video transmission apparatus comprising: the transmission apparatus according to any one of claims 1 to 4; and the reception apparatus according to any one of claims 5 to 7.