JP2008193405A - Transmission system, transmission side apparatus, reception side apparatus, their operation method, and digital broadcasting system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a relatively inexpensive transmission system capable of allowing the phases of clocks to be coincident at a reception side by utilizing a system for transmitting data and its clock information with one line between a transmission side apparatus and a reception side apparatus. <P>SOLUTION: The data transmission side apparatus 110 includes: a phase comparing circuit 114 for comparing the phases between a data clock and a transmission clock; and a phase marker inserting circuit 111 for inserting phase marker data a3 into a region, other than the transmission section of the data to be transmitted to a serial transmission line 120, at a timing for allowing the phase difference between the data clock and the transmission clock to be within a prescribed range. The data reception side apparatus 130 includes calibration means (phase comparators 131, LPF 132, VCXO 133) for calibrating the phase of the data clock to be reproduced, in response to the timing of the insertion point of the received phase marker data a3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transmission system, a transmission-side device, a reception-side device, an operation method thereof, and a digital broadcasting system, and particularly to a transmission system that transmits clock information together with data transmission and a circuit configuration thereof.

  The terrestrial digital broadcasting system is a clock synchronization system that transmits data and a clock. An example of this is shown in FIG.

  FIG. 4 is a signal connection diagram between devices in the conventional terrestrial digital broadcasting system. In the terrestrial digital broadcasting system shown in the figure, a data transmission side device is provided on the transmission side, and a data reception side device is provided on the reception side.

  Among them, the data transmission side device forms an 8-bit TS (transport stream) signal in which 204-byte fixed-length packets are continuous as a stream obtained by multiplexing a plurality of compression-coded video signals, audio signals, and data. An ASI (Asynchronous Serial Interface) transmitter 9 that converts parallel data into serial data having a transmission rate of 270 Mbps, and a cable that transmits the TS signal using an 8.127 MHz clock or 10 MHz clock that is a data clock of the TS signal; Has a clock driver 10 that transmits by another cable (coaxial cable).

  On the other hand, the data receiving side device converts the serial data from the ASI transmitter 9 into 8-bit parallel data and receives the ASI receiver 11, the clock receiver 12 that receives the clock from the clock driver 10, and the clock receiver 12. It has a PLL (Phase Locked Loop) circuit 13 that inputs an output signal and outputs a data clock of 8.127 MHz or 10 MHz.

  In the configuration shown in FIG. 4, the data is in the form of TS (Transport Stream) packets, and is transmitted between the data transmission side device and the data reception side device by an asynchronous serial interface called DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface). Transmitted between both devices. The clock (270 MHz) on DVB-ASI is reproduced by the data receiving side device using the data change point. In the terrestrial digital broadcasting system, in addition to transmitting the TS data by DVB-ASI, the cable for transmitting the TS data of the 8.127 MHz clock or 10 MHz clock is different from the cable for transmitting the TS data (coaxial cable). ).

As prior art documents related to the present invention, there are the following.
JP 2000-253275 A JP 2001-103502 A Japanese Patent Laid-Open No. 08-1226029 Japanese Patent Laid-Open No. 11-004204

  However, in the above-described conventional digital terrestrial broadcasting system, when the distance between the data transmission side and the reception side is long, it is difficult to transmit these two signals with different cables due to cost problems or the like. There is. In such a case, generally, the following two methods are currently used.

  (1) In the first method, data and clock information are multiplexed and transmitted by a single cable. This method will be described with reference to FIG.

  FIG. 5 is a block diagram for explaining signal processing in a system in which data and a clock are transmitted through one signal line.

  In FIG. 5, a data transmission side apparatus having a data / clock multiplexing circuit 14 and an E / O (electric / optical) conversion circuit 15 connected to the output side of the data transmission side apparatus are provided on the transmission side. The output side of the E / O conversion circuit 15 is connected to an optical line. On the receiving side, an O / E (optical / electrical) conversion circuit 16 connected to the optical line and a data / clock restoration / separation circuit 17 connected to the output side of the O / E conversion circuit 16 are provided. A data receiving device.

  The data / clock multiplexing circuit 14 multiplexes the parallel or serial data and the data clock of 8.127 MHz or 10 MHz, and transmits the multiplexed data via the DVB-ASI interface.

  The E / O conversion circuit 15 converts the transmission data supplied from the data / clock multiplexing circuit 14 from an electric signal to an optical signal and transmits it through an optical line. The O / E conversion circuit 16 converts the data from the E / O conversion circuit 15 from an optical signal to an electrical signal via an optical line, and supplies the transmission data to the data / clock restoration / separation circuit 17.

  The data / clock restoration / separation circuit 17 receives the transmission data from the O / E conversion circuit 16 and separates it into parallel or serial data and an 8.127 MHz or 10 MHz data clock for restoration.

  In the configuration shown in FIG. 5, the data and the clock information signal are transmitted through one signal line by multiplexing.

  (2) In the second method, both the data transmission side device and the reception side device have the same frequency using GPS (Global Positioning System), and no clock signal is transmitted between the two devices. This method will be described with reference to FIG.

  FIG. 6 shows a system diagram when only data is transmitted using GPS. FIG. 6 illustrates a method in which clock transmission is not performed by using a clock from a conventional GPS.

  In FIG. 6, a data transmission side device having a GPS unit 18 and an ASI transmitter 19 and an E / O conversion circuit 20 are provided on the transmission side, and an O / E conversion circuit 21 and an ASI receiver 22 are provided on the reception side. And a data receiving device having a GPS unit 23 are provided.

  In the data transmission side device, the GPS unit 18 receives a radio wave from a GPS satellite and generates a 10 MHz data clock based on the GPS time signal. The ASI transmitter 19 transmits parallel or serial data to the E / O conversion circuit 20 through the DVB-ASI interface.

  The E / O conversion circuit 20 converts the electrical signal supplied from the ASI transmitter 19 into an optical signal and transmits it through an optical line. The O / E conversion circuit 21 converts the optical signal from the E / O conversion circuit 15 into an electrical signal via an optical line, and supplies the electrical signal to the data reception side device.

  In the data receiving device, the GPS unit 23 receives radio waves from GPS satellites and generates a 10 MHz data clock based on the GPS time signal. The ASI receiver 22 receives the electrical signal from the O / E conversion circuit 21 and converts it into parallel or serial data.

  However, the method (1) for multiplexing and transmitting data and clock has the following problems. This point will be described with reference to FIGS.

  FIG. 7 is a block diagram showing details of (1).

  In FIG. 7, the data transmission side device includes a K28.5 insertion circuit 24, a clock counter 25, a data selector 26, a parallel / serial conversion circuit 27, a transmission clock generation, as a detailed configuration in the data / clock multiplexing circuit 14 shown in FIG. A circuit 28 and a serial / parallel conversion circuit 29 are provided.

  The K28.5 insertion circuit 24 inserts K28.5, which is a special character code, as stuffing data in addition to the data transmission area on the serial transmission path, and supplies the K28.5 to the data selector 26.

  The clock counter 25 counts the clock of the data on the transmission side and supplies the count value to the data selector 26 as clock information (frequency information).

  The data selector 26 selects one of parallel data to be transmitted, K28.5 from the K28.5 insertion circuit 24, and a counter value (clock information) from the clock counter 25, and the serial / parallel conversion circuit 29. Send to.

  The parallel / serial conversion circuit 27 converts the data, K28.5, and clock information output from the serial / parallel conversion circuit 29 into serial data based on the transmission clock from the transmission clock generation circuit 28, DVB-ASI, etc. On the serial transmission line. In the example of FIG. 8, the data is transmitted on the serial transmission path in a format such as K28.5, clock information, and data.

  The data transmission side device includes a serial / parallel conversion circuit 29, a demultiplexer 30, a variable frequency oscillator 31, a counter value comparison circuit 32, and a frequency counter 33.

  The serial / parallel conversion circuit 29 converts serial data into parallel data and outputs the parallel data to the demultiplexer 30.

  The demultiplexer 30 separates the data and its clock information from the converted parallel data, outputs the data, and supplies the clock information to the counter value comparison circuit 32.

  The counter value comparison circuit 32 compares the count value of the transmission side clock, which is clock information, with the count value from the frequency counter 33, and outputs a difference signal between the counter values to the variable frequency oscillator 31.

  The variable frequency oscillator 31 variably controls the oscillation frequency of the clock that it oscillates so that the difference between both counter values from the counter value comparison circuit 32 becomes zero, and outputs it as a reproduction clock. Feedback is provided to the counter value comparison circuit 32 via the counter 33.

  The frequency counter 33 counts the frequency of the reproduction clock variably controlled from the variable frequency oscillator 31 and supplies the count value to the counter value comparison circuit 32.

  Therefore, in the method (1), as shown in FIG. 8, a counter value for counting the clock on the transmitting side is transmitted at a predetermined frequency, and the counter value and its own clock are counted on the receiving side. Only control that makes progress with the counter value the same can be performed. For this reason, even if frequency information can be sent as clock information, even phase information cannot be transmitted. That is, phase information cannot be sent because transmission jitter exists on the line.

  For this reason, in the method (1), that is, a method in which data and clock information are multiplexed and transmitted over one line, the processing time between a plurality of receiving side devices is a maximum of one clock when the power of the device is turned off / on. This is a shift and becomes an obstacle when performing SFN (single frequency network) or when switching between multiple lines without interruption. A configuration example in such a case is shown in FIG.

  In FIG. 8, two systems of transmission apparatuses 1 and 2 (34 and 35), transmission paths 1 and 2 (36 and 37), reception apparatuses 1 and 2 (38 and 39), and a system selection apparatus 40 are provided. The transmission devices 1 and 2 (34 and 35) input the same data and its clock in parallel, respectively, convert them into serial data as described above, and receive them via the transmission lines 1 and 2 (36 and 37). Transmit individually to devices 1, 2 (38, 39). Each receiving device 1, 2 (38, 39) converts the transmitted serial data into parallel data as described above, separates the data into its clock and outputs it to the system selection device 40. The system selection device 40 selects and outputs either of the outputs (data output 1 and clock output 1, data output 2 and clock output 2) from the receiving devices 1 and 2 (38, 39) of both systems. . At this time, as shown in the figure, the frequency between the clock output 1 and the clock output 2 matches, but the phase does not match. For this reason, line switching cannot be performed seamlessly.

  On the other hand, in the method (2) using the GPS, there are cases where the installation cost of the GPS is high and radio waves from the GPS satellites cannot be received due to lightning strikes or the like.

  The present invention solves the above-mentioned problem, and uses the method of transmitting data and its clock information on one line between the transmission side device and the reception side device, and matches the clock phase on the reception side. It is an object of the present invention to provide a transmission system that can perform communication at a relatively low cost.

  In order to achieve the above object, a transmission system according to the present invention includes a transmission-side device that transmits data on a serial transmission line, and a reception-side device that receives the data via the serial transmission line. The transmission side device includes phase comparison means for comparing phases of the clock of the data and the transmission clock of the serial transmission path asynchronous with the clock, and a phase difference between the clock and the transmission clock is within a predetermined range. Phase information insertion means for inserting clock phase information into an area other than the transmission section of data to be sent out on the serial transmission path at a timing that becomes inside, and the receiving side device receives the clock phase information together with the data. Receiving means for receiving and calibrating the phase of the clock according to the timing corresponding to the insertion point of the received clock phase information And having a positive means.

  In the present invention, the serial transmission path may be based on an asynchronous serial interface transmission system. The asynchronous serial interface transmission method may be a DVB-ASI transmission method. The phase information insertion unit may insert the clock phase information at a timing at which phases of the data clock and the transmission clock match. The calibration means includes an oscillator that oscillates a clock, and a control means that controls the oscillation frequency of the oscillator so that the rising point of the clock coincides with the insertion point of the received clock phase information. Also good.

  An operation method of a transmission system according to the present invention is an operation method of a transmission system including a transmission-side device that transmits data on a serial transmission line and a reception-side device that receives the data via the serial transmission line. The transmission side device compares the phase of the data clock and the transmission clock of the serial transmission path asynchronous with the clock, and the phase difference between the clock and the transmission clock falls within a predetermined range. The clock phase information is inserted into an area other than the transmission section of the data to be transmitted on the serial transmission path, and the receiving side apparatus receives the clock phase information together with the data, and inserts the received clock phase information. The clock phase is calibrated in accordance with the timing corresponding to the point.

  The transmission-side apparatus according to the present invention sends data on a serial transmission line, and comprises a phase comparison means for comparing the phase of the clock of the data and the transmission clock of the serial transmission line asynchronous with the clock. And phase information insertion means for inserting clock phase information into a region other than a transmission interval of data transmitted on the serial transmission path at a timing at which a phase difference between the clock and the transmission clock falls within a predetermined range. Features.

  The operation method of the transmission side device according to the present invention is to send data on a serial transmission line, and compares the phase of the clock of the data and the transmission clock of the serial transmission line asynchronous with the clock, The clock phase information is inserted into an area other than a transmission section of data transmitted on the serial transmission path at a timing when a phase difference between the clock and the transmission clock falls within a predetermined range.

  The receiving-side device according to the present invention receives data from the transmitting-side device via a serial transmission path, and the serial transmission path is asynchronous with the clock of the data and the clock from the transmitting-side apparatus. Receiving means for receiving, together with the data, clock phase information inserted in an area other than the transmission section of the data transmitted on the serial transmission path at a timing when the phase difference from the transmission clock falls within a predetermined range. And phase calibrating means for calibrating the phase of the clock in accordance with the timing corresponding to the insertion point of the clock phase information.

  The operation method of the receiving apparatus according to the present invention is to receive data from the transmitting apparatus via a serial transmission line, and the clock of the data and the clock thereof are asynchronous from the transmitting apparatus. When the phase difference from the transmission clock of the serial transmission path falls within a predetermined range, the clock phase information inserted in the area other than the transmission section of the data transmitted on the serial transmission path is received together with the data and received. The clock phase is calibrated in accordance with the timing corresponding to the insertion point of the clock phase information.

  The digital broadcasting system according to the present invention is characterized by using any of the above transmission systems.

  According to the present invention, a transmission system that can match the phase of a clock on the receiving side is compared by using a method of transmitting data and its clock information on one line between the transmitting side device and the receiving side device. Can be provided inexpensively.

  Next, a transmission system, a transmission side device, a reception side device, an operation method thereof, and a digital broadcasting system according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an overall configuration of a transmission system used in a digital terrestrial broadcasting system according to an embodiment of the present invention. The transmission system shown in the figure multiplexes the TS signal data and its clock information in which 204-byte fixed-length packets are continuous as a stream obtained by multiplexing the plurality of compression-encoded video signals, audio signals, and data. In this way, a transmission method using one line is applied.

  Specifically, a data transmission side device 110 is provided on the transmission side, and a data reception side device 130 connected to the data transmission side device 110 via the serial transmission path 120 on the reception side. As the serial transmission path 120, a transmission system using an asynchronous serial interface is used. In this embodiment, the above-described DVB-ASI interface having a transmission rate of 270 Mbps is used as the asynchronous serial interface. The serial transmission line 120 can also be applied to the circuit configuration (E / O conversion circuit, O / E conversion circuit) using the optical line described above.

  The data transmission side device 110 performs a phase comparison between the data clock of the TS signal and the transmission clock on the serial transmission line 120 asynchronous with the data clock (which constitutes the phase comparison means of the present invention), and its circuit. A circuit for detecting a phase coincidence point of both clocks from the result and inserting a phase marker (calibration marker) which is clock phase information with low jitter at that timing (which constitutes the phase information insertion means of the present invention). . The phase marker is composed of a specific control code (for example, 10-bit serial data) determined in advance in this transmission system.

  As a specific configuration example, as shown in FIG. 1A, a phase marker insertion circuit 111, a data selector 112, a parallel-serial conversion circuit 113, a main part of the phase information insertion means of the present invention, It has a phase comparison circuit 114 and a transmission clock generation circuit 115 which constitute the main part of the phase comparison means of the invention. In addition, although not shown in FIG. 1A, a K28.5 insertion circuit for inserting K28.5, which is a special character code, is included as stuffing data, as in FIG. 7 described above.

  The phase marker insertion circuit 111 sends data other than user data in synchronization with the rising edge (see below) of the pulse signal that constitutes the control signal from the phase comparison circuit 114, from the L level to the H level. Marker data is generated, and the phase marker data is supplied to the data selector 2.

  The data selector 112 selects either 8-bit data (32.5 Mbps) input from the outside as data constituting the above-described TS packet or the phase marker data from the phase marker insertion circuit 1, and a parallel-serial conversion circuit 113.

  The transmission clock generation circuit 115 generates a 27 MHz transmission clock and supplies it to the parallel-serial conversion circuit 113 and the phase comparison circuit 114.

  The parallel-serial conversion circuit 113 converts the parallel data output from the data selector 112 into 10-bit serial data in accordance with the 27 MHz transmission clock from the transmission clock generation circuit 115 and sends it to the serial transmission path 120.

  At this time, as shown in FIG. 1A, the data a1, the special character code K28.5 stuffing data a2, and the phase marker data a3 are cut off on the serial transmission path 120. It is sent continuously without. Among these, as shown in FIG. 1B, the data a1 is synchronized with the user data a11 to be transmitted and the synchronization that is sent to synchronize the transmitting side and the receiving side when the user data a11 is not present. Data for use a12. The phase marker data a3 is inserted in an area other than the user data a11 in order to avoid interference with the user data a11 on DVB-ASI.

  The phase comparison circuit 114 compares the phase of the 10 MHz data clock input from the outside as the clock signal of the TS signal with the 27 MHz transmission clock generated by the transmission clock generation circuit 115, and the phase difference between the two is determined in advance. When within the specified range, at that timing, the logic level of the control signal (control pulse) output to the phase marker insertion circuit 111 is raised from the L level to the H level.

  The data receiving side device 130 receives the serial data transmitted from the data transmitting side device 110, converts it into parallel data by a serial / parallel conversion circuit (not shown), and demultiplexes (not shown) the data, The clock information is separated. The serial-parallel conversion circuit and the demultiplexer are the same as those in FIG.

  In the present embodiment, a circuit (which constitutes the calibration means of the present invention) that receives the phase marker a3 and controls the phase of its own clock oscillator is added to the data receiving side device 130. A specific configuration example of this circuit is shown in FIG.

  As shown in FIG. 2B, the data receiving side device 130 includes a phase comparator 131, an LPF (low pass filter) 132, and a VCXO (Voltage Controlled Xtal Oscillator) that is a clock oscillator of the data receiving side device 130. 133. With this configuration, the data receiving side device 130 controls the oscillation of the VCXO 133 so that the rising edge of the phase marker a3 and the rising edge of the clock of the phase marker a3 coincide with each other, and matches the frequency and phase of the reproduction (restoration) clock. .

  More specifically, the phase comparator 131 compares the phases of the rising edge of the phase marker a3 and the rising edge of the clock output oscillated by the VCXO 133, and supplies the phase difference signal to the LPF 132.

  The LPF 132 cuts off the high frequency component of the difference signal from the phase comparator 131 and turns it into a direct current, and supplies the corresponding voltage to the VCXO 133.

  The VCXO 133 outputs a clock whose own oscillation frequency (free-running frequency) is changed according to a given voltage, and raises or lowers the frequency of the clock output according to the voltage from the LPF 132. That is, the oscillation frequency of the clock output is variably controlled so that the phase difference from the phase comparator 131 becomes substantially zero. For example, if the phase of the rising edge of the clock output is ahead of the rising edge of the phase marker, the clock output oscillation frequency is lowered to delay the phase, while the rising edge of the clock output is delayed from the rising edge of the phase marker. If the phase is delayed, the oscillation frequency of the clock output is increased to advance the phase. By doing so, not only the frequency of the data clock but also the phase is synchronized, that is, the clock including the phase information in addition to the frequency information can be restored (reproduced). The restored clock is output to the outside as a data clock and fed back to the phase comparator 131.

  Next, the operation of this embodiment will be described.

  FIG. 2 explains the output timing by the phase comparison circuit of the data transmission side device 110.

  As shown in the figure, the data transmission side device 110 has a timing at which the phase difference between the rising edge of the 27 MHz transmission clock and the rising edge of the 10 MHz data clock becomes smaller than a predetermined range (example in the figure). The phase marker a3 is transmitted to the serial transmission line 120 at the timing T1 when the phase difference becomes zero within the allowable error range (that is, the timing at which the phases of the data clock and the transmission clock substantially coincide). Is inserted in a region other than (region composed of 10-bit serial data a4 transmitted every 27 MHz transmission clock).

  Here, in the data transmission side apparatus 110, the data is normally converted from parallel to serial data and transmitted to the serial transmission path 120. However, even if there is no data to be transmitted on the transmission path 120, the data transmission side apparatus 110 In order to synchronize 110 and the data receiving side device 130, synchronization data always flows. Therefore, there is a case where the data to be transmitted is kept waiting until the transmission of the synchronization data is completed, and is transmitted with a jitter of one transmission clock (37 nsec) of 27 MHz at the maximum.

  Therefore, as shown in FIG. 2, the phase marker a3 is generated at the timing when the phases of the data clock and the transmission clock coincide with each other, and the phase marker a3 is transmitted to the serial transmission line 120 with priority over the user data a11. Then, phase information can be transmitted without jitter.

  FIG. 3 illustrates the timing for calibrating the phase and frequency of the clock by the data receiving side device 130. As shown in the figure, the data receiving side device 130 periodically sets the rising point of the recovered clock so as to match the timing T2 corresponding to the insertion point of the phase marker a3 intermittently sent from the data transmitting side device 110. The phase of the recovered clock becomes a fixed phase.

  In this way, in this embodiment, the data transmission side device 110 compares the phase of the data clock with the asynchronous clock of DVB-ASI, and at the timing T1 at which transmission can be performed with low jitter, for clock phase calibration. The phase marker is inserted and sent out on the serial transmission line 120. That is, using DVB-ASI, a phase marker that is phase information of the data clock signal is also transmitted together with the data. Then, the data receiving side device 130 performs data clock phase alignment based on the phase marker.

  That is, in the present embodiment, the data transmission side device 110 is provided with a phase comparison circuit 114 that compares the phases of the data clock (10 MHz) and the asynchronous transmission clock (27 MHz) with the phase difference between the two in advance. A phase marker insertion circuit 111 for inserting the phase marker data a3 into the data area (area other than the user data transmission section) to be transmitted to the data receiving side device 130 at the timing T1 when it is within the determined range. It is configured. Further, the data receiving side device 130 controls the phase of the VCXO 133 at the transmission timing T2 of the phase marker data a3 and calibrates the phase and frequency of the data clock to be reproduced (restored) (phase comparator 131, LPF 132). Is provided. For this reason, the following effects can be produced.

  The first effect is that two signals of data and clock can be transmitted with one cable, so that the line use efficiency is good. The reason is that it does not interfere with user data because an area other than user data on DVB-ASI is used.

  The second effect is that not only the frequency information of the clock signal but also the phase information can be transmitted, so it is possible to suppress fluctuations in the signal processing time at the receiving device, and transmission is performed over multiple lines, and the lines are switched seamlessly It can be performed. This is because the transmission timing of clock information transmission is managed.

  In addition, since the clock signal information including the phase information can be transmitted together with the data with a single cable, the O / O device can be operated from a simple E / O device while maintaining the baseband signal of the clock required for the terrestrial digital broadcasting system. Long-distance transmission to the E device is also possible, which has the advantage that the line cost can be reduced.

  Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment as a representative example, and those skilled in the art will understand the contents of the claims. Based on the above, various modifications and changes can be made without departing from the scope of the present invention. These modified examples and modified examples also belong to the scope of the right of the present invention.

  For example, the hardware configuration of the above transmission system is not particularly limited, and any configuration can be applied as long as the functions (means) of each unit described above can be realized. For example, any of those constituted by independent circuits (IC or the like) for each function of each unit or those integrally constituted by one or a plurality of circuits (IC or the like) can be applied.

  Moreover, you may implement | achieve at least one part of the function of each said part by the process of the computer (CPU) which used the program. In this case, such a program and a computer-readable recording medium for recording the program are included in the scope of the present invention. In this case, when the above functions are realized in cooperation with other software such as an operating system, those programs are also included.

  The present invention can be applied not only to a terrestrial digital transmission / broadcasting system but also to a transmission system such as an in-rack data transmission system and an inter-room transmission system.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the whole structure of the transmission system used for the terrestrial digital broadcasting system which concerns on embodiment of this invention, (a) is a block diagram which shows the structure of a data transmission side apparatus, (b) is a data reception side apparatus. It is a block diagram which shows a structure. It is a timing chart explaining the output timing of the phase comparison circuit of the transmission system concerning an embodiment of the invention. It is a timing chart explaining the timing which calibrates the phase and frequency of the data receiving side apparatus of the transmission system which concerns on embodiment of this invention. It is an inter-device signal connection diagram in the conventional terrestrial digital broadcasting system. It is a block diagram of the system which multiplexes and transmits the data and clock information of a prior art example. It is a block diagram of a system that uses a conventional GPS to synchronize on the data transmission side and data reception side and does not transmit a clock signal. It is a block diagram which shows the detail of the system which multiplexes and transmits the data and clock of a prior art example. It is a figure explaining the problem of the system of multiplexing and sending the data and clock of a prior art example.

Explanation of symbols

110 data transmission side device 111 phase marker insertion circuit 112 data selector 113 parallel serial conversion circuit 114 phase comparison circuit 115 transmission clock generation circuit 120 serial transmission path (DVB-ASI)
130 Data receiving side device 131 Phase comparator 132 LPF
133 VCXO

Claims (11)

A transmission side device for sending data on a serial transmission path;
A transmission system comprising a receiving side device for receiving the data via the serial transmission path,
The transmitting device is:
Phase comparison means for comparing the phase of the clock of the data and the transmission clock of the serial transmission path that is asynchronous with the clock;
Phase information insertion means for inserting clock phase information into a region other than a transmission interval of data transmitted on the serial transmission path at a timing at which a phase difference between the clock and the transmission clock falls within a predetermined range;
The receiving side device
Receiving means for receiving the clock phase information together with the data;
A transmission system comprising calibration means for calibrating the phase of the clock in accordance with the timing corresponding to the insertion point of the received clock phase information.   The transmission system according to claim 1, wherein the serial transmission path is an asynchronous serial interface transmission system.   The transmission system according to claim 2, wherein the asynchronous serial interface transmission method is a DVB-ASI transmission method.   4. The transmission system according to claim 1, wherein the phase information insertion unit inserts the clock phase information at a timing at which phases of the data clock and the transmission clock coincide with each other. The calibration means includes
An oscillator that oscillates the clock;
5. The control device according to claim 1, further comprising a control unit configured to control an oscillation frequency of the oscillator so that a rising point of the clock coincides with an insertion point of the received clock phase information. The transmission system according to item. A transmission side device for sending data on a serial transmission path;
An operation method of a transmission system comprising a receiving side device that receives the data via the serial transmission path,
The transmission side device compares the phase of the clock of the data and the transmission clock of the serial transmission path that is asynchronous with the clock, and the timing at which the phase difference between the clock and the transmission clock is within a predetermined range, Insert clock phase information into an area other than the transmission section of the data sent on the serial transmission path,
The transmission side device receives the clock phase information together with the data, and calibrates the phase of the clock in accordance with a timing corresponding to an insertion point of the received clock phase information. How it works. A transmission side device for sending data on a serial transmission line,
Phase comparison means for comparing the phase of the clock of the data and the transmission clock of the serial transmission path that is asynchronous with the clock;
Phase information insertion means for inserting clock phase information into a region other than a transmission interval of data transmitted on the serial transmission path at a timing when a phase difference between the clock and the transmission clock falls within a predetermined range. A transmitting side device. An operation method of a transmission side device for sending data on a serial transmission line,
Compare the phase of the clock of the data and the transmission clock of the serial transmission path asynchronous with the clock,
Operation of a transmitting apparatus, wherein clock phase information is inserted into an area other than a transmission section of data transmitted on the serial transmission path at a timing at which a phase difference between the clock and the transmission clock falls within a predetermined range Method. A receiving device that receives data from a transmitting device via a serial transmission path,
From the transmission side device, the phase difference between the clock of the data and the transmission clock of the serial transmission path that is asynchronous with the clock is within a predetermined range, and other than the transmission section of the data transmitted on the serial transmission path Receiving means for receiving the clock phase information inserted in the region together with the data;
And a phase calibration means for calibrating the phase of the clock in accordance with the timing corresponding to the insertion point of the received clock phase information. An operation method of a reception side device for receiving data from a transmission side device via a serial transmission path,
From the transmission side device, the phase difference between the clock of the data and the transmission clock of the serial transmission path that is asynchronous with the clock is within a predetermined range, and other than the transmission section of the data transmitted on the serial transmission path Receiving the clock phase information inserted in the region together with the data;
A method for operating a receiving apparatus, wherein the phase of the clock is calibrated in accordance with a timing corresponding to an insertion point of the received clock phase information.   A digital broadcasting system using the transmission system according to any one of claims 1 to 5.

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