JP5225812B2 - OFDM demodulation apparatus, OFDM demodulation method, program, and computer-readable recording medium - Google Patents

Description

  The present invention relates to a receiving apparatus and a receiving method for a signal transmitted by a digital transmission method, and more particularly, an orthogonal frequency division multiplexing (hereinafter, abbreviated as OFDM) that can efficiently transmit a video signal and an audio signal. The present invention relates to a demodulation device, a program, and a computer-readable recording medium.

  In terrestrial digital broadcasting, a multicarrier OFDM modulation / demodulation method is known as a modulation method suitable for overcoming ghost interference (fading, multipath) by buildings. The OFDM modulation / demodulation method is a digital modulation / demodulation method in which a large number (about 256 to 1024) of sub-carriers are provided in one channel band and video signals and audio signals can be efficiently transmitted. A baseband (BB) signal in which all the carriers are OFDM-modulated by an inverse fast Fourier transform (IFFT) is generated.

  According to Non-Patent Document 1, a pilot signal called SP (Scattered Pilot) is periodically inserted into sub-carriers once every 12 carriers in the carrier direction and once every 4 symbols in the symbol direction as a time axis unit. Has been. The pilot signal has a predetermined phase and amplitude, and is used for estimation of synchronization and transmission path transmission measurement.

  In order to maintain good reception, it is necessary to accurately measure an error between the operation clock frequency of the reference broadcasting station and the operation clock frequency of the receiver and feed it back to the reception system. For example, as a conventional technique, Patent Document 1 discloses one configuration example for detecting and correcting a frequency error in an OFDM signal receiver.

  An OFDM signal receiver described in Patent Document 1 includes an antenna that receives an OFDM signal from a transmitter, a frequency converter that converts a frequency of an RF signal received by the antenna into a baseband signal, and a sine wave in the frequency converter. A local oscillator for supplying a local oscillation signal, a sampler for sampling a received baseband signal, a frequency error & timing error estimator for detecting a frequency offset and a timing offset using an output signal of the sampler, And a fast Fourier transformer that converts the time-domain signal output from the sampler into a frequency-domain signal. The frequency error & timing error estimator transmits the pilot symbol using the signal output from the sampler. The frequency error and timing error are determined by the signal obtained by the sliding correlation operation between the received signal and the received signal. Out to.

The OFDM signal receiver described in Patent Document 1 supplies the carrier frequency error information output from the frequency error & timing error estimator to the local oscillator, and controls the local oscillator (that is, the oscillation frequency of the reproduced carrier signal). The carrier frequency is synchronized and the sampling timing is synchronized.
JP 2000-341236 A (released on December 8, 2000) "Transmission method for digital terrestrial television broadcasting ARIB STDB31 version 1.5", the radio industry, the first edition on May 31, 2001, revised version 1.5 on July 29, 2003

  Incidentally, the above-described local oscillator is generally constituted by a PLL circuit. As PLL circuits, there are those constituted only by analog circuits, those constituted only by digital circuits, and those constituted by analog circuits and digital circuits. Alternatively, a PLL circuit composed of an analog circuit and a digital circuit, which is adjusted for each manufacturing process and made into a hard macro, is used.

  However, in the above conventional configuration, when correcting the frequency error, the frequency of the PLL circuit itself (local oscillator) (that is, the oscillation frequency of the reproduced carrier signal) is finely adjusted during operation. It is necessary to prepare. For this reason, a problem arises in that a corresponding PLL circuit is searched for every change in the manufacturing process, and if there is no PLL circuit, it must be newly created. In addition, among the PLL circuits composed only of digital circuits, those with particularly high resolution can be used for correcting the frequency error, but problems such as an increase in circuit scale and power consumption may occur. There is sex.

  The present invention has been made in view of the above-described problems, and its object is to receive a frequency error that can be corrected only by a logic unit regardless of an analog hard macro that needs to be adjusted for each manufacturing process. An apparatus, a receiving method, an OFDM demodulator, a control program, and a computer-readable recording medium are provided.

  A receiving apparatus according to the present invention includes a receiving unit that receives an analog signal obtained by analogizing a first sample series signal sampled at a first sampling timing based on a reference signal of a first frequency oscillator; Sampling means for sampling a signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal, and the first frequency oscillator A frequency error detecting means for detecting a frequency error between the reference signal of the second frequency oscillator and the reference signal of the second frequency oscillator, and sampling for generating sampling timing error information for specifying the first sampling timing from the frequency error From the timing error information generating means and the second sample series signal, Serial is characterized in that it comprises a sampling value predicting means for predicting a sampling value in the first sampling timing specified by the sampling timing error information.

  According to the above configuration, the receiving apparatus according to the present invention receives an analog signal obtained by analogizing the first sample series signal sampled at the first sampling timing based on the reference signal of the first frequency oscillator. The second sample series signal is generated by sampling at the second sampling timing based on the reference signal of the second frequency oscillator different from the first frequency oscillator.

  That is, the receiving device receives and samples an analog signal superimposed on, for example, a broadcast wave. The analog signal to be received is not limited to the one superimposed on the broadcast wave, and may be an analog signal transmitted through a wireless or wired communication network, or from another device provided integrally. The read analog signal may be used and is not particularly limited. The analog signal is obtained by analogizing the first sample series signal sampled at the first sampling timing based on the reference signal of the first frequency oscillator. On the other hand, the receiving apparatus receives the analog signal, performs sampling at the second sampling timing based on the reference signal of the second frequency oscillator, and generates a second sample series signal. Here, the second sampling timing based on the reference signal of the second frequency oscillator may be configured to sample one data for each period of the reference signal of the second frequency oscillator, A configuration for sampling (that is, a configuration for oversampling) may be used. Or the structure which samples 1 data for every several periods of a reference signal may be sufficient.

  Further, according to the above configuration, the frequency error detecting means detects a frequency error between the reference signal of the first frequency oscillator and the reference signal of the second frequency oscillator. The first frequency oscillator and the second frequency oscillator are different frequency oscillators independent from each other, and the second sample series signal includes a clock (for example, baseband) based on the reference signal of the first frequency oscillator. A frequency error that is an error between the clock of the transmission device that generates the signal) and a clock based on the reference signal of the second frequency oscillator is included, and the frequency error detecting means is configured to detect this. There is no particular limitation as long as it is present. Note that this may be included in an ADC that converts an analog signal into a digital signal.

  Further, according to the above configuration, the sampling timing error information generating means generates sampling timing error information for specifying the first sampling timing from the frequency error. As described above, since the second sample series signal generated in the receiving apparatus includes a frequency error, the first sampling timing does not match the second sampling timing, but based on the received analog signal. In order to accurately reproduce the first sampling series signal in the receiving apparatus, the sampling data at the true sampling timing, that is, the first sampling timing is necessary. Therefore, the sampling timing error information generating means generates sampling timing error information for specifying the first sampling timing. As the sampling timing error information, for example, there are a fractional delay amount and an integer delay amount representing a deviation of the true sampling timing from the reference sampling timing in the second sampling timing.

  According to the above configuration, the sampling value prediction means predicts the sampling value at the first sampling timing specified by the sampling timing error information from the second sample series signal. The sampling value prediction means interpolates the data at the true sampling timing using the second sample series signal by various digital filters such as a Lagrange filter and a Farrow filter.

  As a result, the receiving device can obtain sampling data at the true sampling timing, that is, the timing sampled when the signal is transmitted. Therefore, by repeating the above-described processing, the frequency error can be converged to 0 or near 0, and the frequency error can be corrected. In addition, in the receiving apparatus, for example, the frequency error can be corrected only by the logic unit without controlling the operation clock frequency by controlling the PLL circuit or the like. Therefore, it is not necessary to use a hard macro analog PLL circuit that is required in the configuration for controlling the operation clock frequency, so that adjustment for each manufacturing process does not occur, process dependency can be eliminated, and reception It becomes possible to improve the productivity of the apparatus.

  In addition, the reception method according to the present invention receives an analog signal obtained by analogizing the first sample series signal sampled at the first sampling timing based on the reference signal of the first frequency oscillator. A sampling step of sampling the received analog signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal; A frequency error detecting step for detecting a frequency error between the reference signal of the first frequency oscillator and the reference signal of the second frequency oscillator; and a sampling timing for specifying the first sampling timing from the frequency error A sampling timing error information generation step for generating error information; From the second sample sequence signal, it is characterized in that it contains a sampling value prediction step of predicting a sampling value in the first sampling timing specified by the sampling timing error information.

  According to said structure, there exists an effect similar to the receiver which concerns on this invention.

  In the receiving apparatus according to the present invention, it is preferable that the second sample series signal input to the sampling value prediction means is in an oversampling state with respect to a reference signal of the second frequency oscillator.

  As a result, even when the entire Nyquist region is not the fractional delay frequency region, the sampling data at the first sampling timing can be accurately interpolated over the entire desired frequency region.

  The receiving apparatus according to the present invention converts the second sample series signal obtained by the sampling means into an oversampling state with respect to a reference signal of the second frequency oscillator, and also converts an oversampling state. The second sampling sequence signal converted into the second sampling sequence signal may further include an oversampling unit that inputs the sampling prediction unit.

  The sampling means converts the second sample series signal into an oversampling state with respect to the reference signal of the second frequency oscillator, and converts the second sample series into the oversampling state. The signal may be input to the sampling prediction unit.

  Further, an OFDM demodulator according to the present invention is an OFDM demodulator comprising the above receiver, and an orthogonal demodulator that orthogonally demodulates a sample sequence signal composed of a prediction value obtained by the sampling value predictor; FFT calculation means for converting the demodulated signal obtained by the orthogonal demodulation means into a frequency domain signal including a data signal and a pilot signal by FFT calculation, and the sampling timing error information generating means includes the sampling timing If the first sampling timing specified by the error information exceeds the predictable range of the sampling value prediction means, a reference used as a reference when generating the sampling timing error information at the second sampling timing Sampling timing is The first sampling timing specified with shifting so as not to exceed the predicted range by ring timing error information, is characterized by shifting the start position of the FFT calculation to offset the shift.

  According to the above configuration, when the first sampling timing specified by the sampling timing error information exceeds a predetermined sampling timing range (predictable range of the sampling value prediction means), that is, for example, by a fractional delay amount When the specified interpolation point exceeds the area that can be accurately interpolated depending on the filter characteristics, the reference sampling timing that is used as a reference when calculating the fractional delay amount is shifted by, for example, one period of the sampling clock. The interpolation point specified by the fractional delay amount calculated based on the later reference sampling timing is within the range of the area that can be accurately interpolated depending on the filter characteristics, and according to the shifted reference sampling timing. , FFT operation Only one period of the start position, for example the sampling clock shifts.

  As a result, the interpolation process can always be performed at the optimum sampling timing, and at the same time, the circuit in which the region that can be accurately interpolated is limited depending on the filter characteristics, that is, the fractional delay amount is set to a finite value can be used. The frequency error can be corrected while reducing the scale. In addition, the FFT window always starts at the same timing with respect to the true sampling timing corresponding to the interpolation point, so that the sampling timing can be corrected without much.

  Further, in the OFDM demodulator according to the present invention, the frequency error detecting means is configured to calculate the frequency error from the phase rotation amount in the time axis direction of the phase of the pilot signal included in the frequency domain signal obtained by the FFT calculating means. Is preferably detected.

  According to the above configuration, the frequency error detection means converts, for example, a digital broadcast wave signal on the time axis including the frequency error into a signal on the frequency axis by applying FFT to the frequency axis, and is converted onto the frequency axis. The SP signal is extracted from the signal in the OFDM demodulation process. Then, it is observed in the symbol direction, the phase rotation amount in symbol units is obtained, the FFT window shift amount in one symbol is calculated from the phase rotation amount in symbol units, and the calculated FFT window shift amount in one symbol The frequency error is calculated from

  Thereby, since the frequency error can be detected from the pilot signal, the frequency error of the OFDM modulated wave can be easily calculated.

  Note that a plurality of pilot signals may be used when obtaining the frequency error, and the frequency error may be calculated from a value based on the integration of each phase of the plurality of pilot signals. Or the structure which calculates | requires the phase difference of a certain two pilot signals, performs it with respect to several pilot signals, and calculates a frequency error from the value based on those integrals may be sufficient.

  Further, the predetermined range may be a frequency range constituted by a single band or a frequency range (group) constituted by a plurality of bands.

  Further, in the OFDM device according to the present invention, the frequency error detection means is a pilot signal whose amplitude is larger than a predetermined threshold among pilot signals included in the frequency domain signal obtained by the FFT operation means. Preferably used to detect the frequency error.

  According to said structure, it becomes possible to detect a frequency error more correctly.

  In the OFDM apparatus according to the present invention, the frequency error detection means is a frequency domain signal obtained by the FFT computation means among pilot signals included in the frequency domain signal obtained by the FFT computation means. Therefore, it is preferable to detect the frequency error using a pilot signal extracted from a signal having a frequency within a predetermined range.

  According to said structure, it becomes possible to detect a frequency error more correctly.

  In the OFDM apparatus according to the present invention, the frequency error detection means includes a pilot signal that is not affected by an interference wave or spurious noise among pilot signals included in the frequency domain signal obtained by the FFT calculation means. It is preferable to detect the frequency error by using.

  According to said structure, it becomes possible to detect a frequency error more correctly.

  The receiving apparatus may be realized by a computer. In this case, a receiving program for realizing the receiving apparatus in the computer by operating the computer as each of the above means and a computer-readable recording medium on which the receiving program is recorded also fall within the scope of the present invention.

  The OFDM demodulator may be realized by a computer. In this case, a demodulation program for realizing the OFDM demodulator in the computer by operating the computer as each of the above means and a computer-readable recording medium recording the demodulation program are also included in the scope of the present invention.

  A receiving apparatus according to the present invention includes a receiving unit that receives an analog signal obtained by analogizing a first sample series signal sampled at a first sampling timing based on a reference signal of a first frequency oscillator; Sampling means for sampling a signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal, and the first frequency oscillator A frequency error detecting means for detecting a frequency error between the reference signal of the second frequency oscillator and the reference signal of the second frequency oscillator, and sampling for generating sampling timing error information for specifying the first sampling timing from the frequency error From the timing error information generating means and the second sample series signal, It is characterized containers that includes a sampling value predicting means for predicting a sampling value in the first sampling timing specified by serial sampling timing error information.

  In addition, the reception method according to the present invention receives an analog signal obtained by analogizing the first sample series signal sampled at the first sampling timing based on the reference signal of the first frequency oscillator. A sampling step of sampling the received analog signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal; A frequency error detecting step for detecting a frequency error between the reference signal of the first frequency oscillator and the reference signal of the second frequency oscillator; and a sampling timing for specifying the first sampling timing from the frequency error A sampling timing error information generation step for generating error information; From the second sample sequence signal, it is characterized in that it contains a sampling value prediction step of predicting a sampling value in the first sampling timing specified by the sampling timing error information.

  Therefore, in the receiving apparatus according to the present invention, since the analog signal received from the outside can be interpolated with data at the true sampling timing, that is, when the signal is transmitted, in the receiving apparatus, It is possible to correct a frequency error included in the sampled signal.

  In addition, since the frequency error can be corrected only by the logic unit, the dependency of the manufacturing process can be eliminated, and the productivity of the receiving apparatus can be improved.

[Embodiment 1]
(Outline of OFDM demodulator 100)
The OFDM demodulator 100 according to the first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a configuration of an OFDM demodulator 100 according to the present invention.

  An OFDM demodulator 100 includes an analog-to-digital converter (ADC, sampling means, oversampling means) 101, a sampling receiver (oversampling means) 102, a frequency error correction part (sampling value prediction means) 103, and an orthogonal demodulation generator. Section (orthogonal demodulation means) 104, fast Fourier transform operation section (FFT section, FFT operation means) 105, frequency error detection section (frequency error detection means) 106, sampling correction control section (sampling timing error information generation means) 107, a waveform equalization unit 108, an error correction unit 109, a frequency oscillator 110, and a phase-locked loop circuit (PLL) 111. The OFDM demodulator 100 is connected to a tuner (reception unit) 10.

  The tuner 10 receives a digital broadcast wave from a broadcast station via an antenna, frequency-converts an RF (high frequency) signal, and supplies the obtained analog IF (intermediate frequency) signal to the ADC 101.

  The frequency oscillator 110 generates a clock signal and supplies it to the PLL 111. The PLL 111 generates an operation clock signal based on the clock signal from the frequency oscillator and supplies it to each unit of the OFDM demodulator 100. Each unit of the OFDM demodulator 100 operates based on an operation clock from the PLL 111.

  The ADC 101 samples (digitizes) the IF signal and supplies the obtained digital IF signal to the sampling receiver 102. The sampling receiving unit 102 performs a predetermined filter process on the digital IF signal, and supplies the filtered digital IF signal to the frequency error error correction unit 103. Examples of the filtering process performed by the sampling receiver 102 include a filtering process that removes unnecessary bands. Note that the sampling receiver 102 may be omitted if filter processing is unnecessary.

  Based on the frequency error correction information from the sampling correction control unit 107, the frequency error correction unit 103 determines a certain amount of frequency error in the digital IF signal (hereinafter, “digital IF signal” is simply referred to as “IF signal”). Remove and correct. Here, the sampling correction control unit 107 calculates a sampling timing error used for correcting the sampling timing based on the frequency error detected by the frequency error detection unit 106, and supplies the sampling timing error information to the frequency error correction unit 103. The frequency error correction unit 103 supplies the corrected IF signal to the orthogonal demodulation generation unit 104.

  The quadrature demodulation generation unit 104 performs quadrature demodulation on the corrected IF signal using a carrier signal having a set carrier frequency, and a base composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). A band OFDM signal is generated and supplied to the FFT unit 105. The FFT unit 105 performs fast Fourier transform (FFT operation) on the baseband OFDM signal, converts the baseband OFDM signal into a frequency domain complex signal including a data signal and a pilot signal, and supplies the complex signal to the waveform equalization unit 108. Note that the FFT unit 105 is configured to be able to adjust the start time of the FFT operation, as will be described later.

  The waveform equalization unit 108 performs waveform equalization on the data signal obtained by the FFT unit 105, removes the influence of fading and the like, and supplies the result to the error correction unit 109. The error correction unit 109 performs error correction using an error correction code or the like included in the restored transmission bit string.

  The OFDM demodulator 100 according to the present embodiment is characterized in that the frequency error is corrected by the frequency error correction unit 103 and the FFT unit 105. The frequency error correction is repeatedly performed in the OFDM demodulation process, and the frequency error detection unit 106 detects a corrected frequency error in which a certain amount of frequency error is removed from the demodulated signal. Based on the frequency error correction information generated by the sampling correction control unit 107, the frequency error correction unit 103 and the FFT unit 105 correct the frequency error. Then, by repeating a series of operations for correcting the frequency error, the frequency error at the time of output of the frequency error correction unit 103 can be made close to 0 or close to 0.

  Note that the frequency error correction unit 103, the frequency error detection unit 106, and the sampling correction control unit 107 form the reception unit 1 (reception device). In the present embodiment, the receiving unit 1 is integrally provided in the OFDM demodulator 100, but may be provided in other devices that receive digital data transmitted from the outside regardless of wired or wireless. It may be configured as an independent device, and is not particularly limited.

(Fractional delay filter)
The OFDM demodulator 100 corrects the frequency error by interpolating the sampling data using a fractional delay (interpolation) filter. Examples of the fractional delay filter include a Lagrange interpolation filter, a Farrow filter, and a modified Farrow filter. For details of the fractional delay filter, see, for example, “Chapter 7. Resampling Filters” of “Multirate Signal Processing for Communication Systems” (Fredric Harris, 2004, Prentice Hall).

  If input sample data is {x (0), x (1),..., X (n−1), x (n), x (n + 1),. When the nth sampling value x (n) is input to the filter, N + 1 sampling values {x (n−N), x (n−N + 1),. x (n-1), x (n)} are stored. Then, the fractional delay filter performs N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n) input before the given delay amount D. −1), x (n)}, a sampling value x (n−D) that is D-delayed with respect to the sampling value x (n) currently input is calculated by interpolation processing. Here, the delay amount D may be an integer or a fraction. Interpolation processing when the delay amount D is an integer is called integer delay processing, and interpolation processing when the delay amount D is a fraction is called fractional delay processing. FIG. 2 shows a fourth-order fractional delay filter immediately after x (4) is input. When D = 1 + 1/3 is given as a delay amount, as shown in FIG. 2, the fractional delay filter has five sampling values {x (0), x (1), x From (2), x (3), x (4)}, a fractional delay process is performed to calculate x (4-D) = x (2 + 2/3).

(Lagrange interpolation filter)
The Lagrange interpolation filter will be described with reference to FIG. FIG. 3 is a diagram illustrating a configuration of an FIR (Finite Impulse Response) filter. The coefficients of the FIR filter shown in FIG.

This FIR filter is an interpolation filter for obtaining a value at an interpolation point n-D corresponding to the delay amount D from discretized data in integer time held in a register, and is generally called a Lagrange interpolation filter. The Lagrange interpolation filter is effective even when the delay amount D is a fraction, and a fractional delay filter can be realized. In the Lagrange interpolation filter, when the target point to be interpolated changes with time, it is necessary to calculate the filter coefficient by the calculation of Formula 1 each time. However, since one coefficient per N multipliers are required, N ² multipliers across FIR filter is required. The transfer function (Z function) of this FIR filter is expressed by Equation 2.

  Further, the frequency characteristic of the FIR filter is expressed by Equation 3. Further, the theoretical value Dint of the delay amount in the output signal (hereinafter simply referred to as “delay amount Dint”) is expressed by Equation 4 using the phase component Θ of Equation 3.

  The filter characteristics of this FIR filter, that is, the Lagrange interpolation filter will be described with reference to FIG. FIG. 4 is a diagram showing filter characteristics when the delay amount D is changed in a Lagrange interpolation filter of N = 7, (a) is a diagram showing amplitude frequency characteristics, and (b) is expressed by Equation 4. It is a figure which shows the calculated delay amount Dint, (c) is a figure which shows the signal noise power ratio (SNR) which considered both the amplitude and the phase. In FIG. 4, the horizontal axis represents a normalized frequency obtained by normalizing the frequency f by the sampling frequency Fs. Also, the vertical axis in FIG. 4A is decibel (dB), and the vertical axis in FIG. 4B is the sampling period Ts.

  In FIG. 4A, the frequency component with | H | = 0 dB is output as it is without being attenuated in strength. Further, it can be seen from FIG. 4B that the delay amount Dint obtained from the output signal matches the set value D.

  The frequency region where | H | = 0 dB in FIG. 4A and Dint≈D in FIG. 4B is a frequency region that can be subjected to fractional delay processing in this Lagrange interpolation filter (hereinafter, fractional delay frequency region). Called). Increasing N increases the fractional delay frequency region, but also increases the circuit scale.

(Farrow Structure)
Hereinafter, the Farrow type fractional delay filter and the modified Farrow type fractional delay filter will be described. FIG. 5 is a diagram illustrating a configuration of a Farrow-type fractional delay filter. As shown in FIG. 5, the Farrow-type fractional delay filter is obtained by Honer combining a plurality of N-order FIR filters. Here, considering the determinants defined by Equations 5 to 7, the FIR filter constituting the Farrow fractional delay filter shown in FIG. 5 is defined by C _n (z) shown in Equation 8. That is, the n-th column vector q _n (k) of the coefficient matrix Q of Expression 6 (Expression 7) corresponds to the filter coefficient of the FIR filter C _n (z).

  As with the Lagrange interpolation filter, the Farrow type fractional delay filter can also be interpolated with an arbitrary delay amount D. However, in the Farrow type fractional delay filter, the multiplications for the delay amount D are all N-1. Therefore, the Farrow type fractional delay filter can be configured with a smaller circuit scale than the Lagrange interpolation filter.

  The filter characteristics of the Farrow type fractional delay filter will be described with reference to FIG. 6A and 6B are diagrams illustrating filter characteristics when the delay amount D is changed in a Narrowed Farrow type fractional delay filter, where FIG. 6A is a diagram illustrating amplitude frequency characteristics, and FIG. 4 is a diagram showing a delay amount Dint calculated by No. 4, and (c) is a diagram showing a signal noise power ratio (SNR) in consideration of both amplitude and phase. FIG. The vertical and horizontal axes in FIG. 6 are the same as those in FIG. Similar to FIG. 4, the frequency component (f≈−0.2 Fs to +0.2 Fs) in which | H | = 0 dB in FIG. 6A is output as it is without being attenuated in intensity. Further, it can be seen from FIG. 6B that the delay amount Dint obtained from the output signal matches the set value D.

  The order of the filter coefficients differs depending on what is important when applying the present invention to an actual system, and is not particularly limited. For example, when emphasizing the actual interpolation timing, the frequency region where Dint≈D in FIG. 6B is considered in the frequency region where fractional delay processing is possible with this Farrow type fractional delay filter. There is also a method of studying with an SNR considering the amplitude and phase in total. For example, the required CNR (Carrier to Noise Ratio) when the modulation method is QPSK slightly changes depending on the coding rate, but is around 4 dB. In this case, the calculation error of SNR ≧ 20 dB can be ignored. Therefore, in the filter having the characteristics of FIG. 6, it is possible to secure a calculation error of SNR ≧ 20 dB in the frequency band component of f = −0.3 Fs to +0.3 Fs from FIG. On the other hand, the required CN of 64QAM varies slightly depending on the coding rate, but is around 20 dB. In this case, since the calculation accuracy of SNR≈20 dB affects the required CN, a calculation accuracy of 30 dB or 40 dB or more is required. From FIG. 6C, it is possible to secure a calculation error of SNR ≧ 40 dB in the frequency band component of f = −0.2 Fs to +0.2 Fs. Thus, if parameters such as the modulation method and coding rate are determined, the required calculation accuracy is determined. The filter order N can be determined by comparing the required calculation accuracy with the calculation accuracy of the filter.

  A modified Farrow type fractional delay filter is a modified Farrow type fractional delay filter. Here, when the matrix T and the matrix Q ′ are defined by Equations 9 and 10, respectively, a combination of a plurality of FIR filters defined by C′n (z) of Equation 11 as shown in FIG. This is called a Farrow type fractional delay filter. That is, the Farrow-type fractional delay filter and the modified Farrow-type fractional delay filter are both configured as shown in FIG.

  The Farrow-type fractional delay filter and the modified Farrow-type fractional delay filter differ in the way of setting interpolation points, but share the function of fractional delay processing. The delay amount D given to the Farrow filter is round (N / 2) −1/2 <D <round (N / 2) +1/2 (where round (N / 2) −1/2 <D <round (N / 2) +1/2) in consideration of the number of stages of the shift register in FIG. x) is set within the range of the rounded value of x). That is, it is set within a range of ± 1/2 centering on round (N / 2). On the other hand, the delay amount D ′ applied to the modified Farrow filter is set within a range of ± 1/2 centering on 0. That is, the delay amount D ′ is set within a range of −1/2 <D ′ <+ 1/2. Thus, the delay amount setting method is different. However, when the delay amount D and the delay amount D ′ satisfy the relationship D ′ = D−round (N / 2), the interpolation processing for the Farrow type delay amount D is performed for the modified Farrow type delay amount D ′. It corresponds to processing.

  In the following description, when a Lagrange interpolation filter or a Farrow type fractional delay filter is used, the delay amount D is input to the filter. When a modified Farrow type fractional delay filter is used, a delay is applied to the filter. Assume that the quantity D ′ is entered. The Lagrange interpolation filter or Farrow type fractional delay filter can be interpolated even when a delay amount D outside the range of round (N / 2) -1/2 to round (N / 2) +1/2 is given. is there. That is, the delay amount D may be set, for example, within a range of ± 1/2 sampling points centered around round (N / 2) +1 or round (N / 2) −1. Alternatively, it may be set in the range of round (N / 2) to round (N / 2) +1. Similarly, the fractional delay amount D ′ of the Farrow type fractional delay filter may be set in the range of 0 <D ′ <+ 1 or −1 <D ′ <0.

  Similar to the Lagrange interpolation filter, the frequency region where | H | = 0 dB in FIG. 6A and Dint≈D in FIG. 6B is the frequency region that can be subjected to fractional delay processing with this Farrow type fractional delay filter. Become. Further, the fractional delay frequency region is proportional to the circuit scale.

  Note that the N = 7 Lagrange interpolation filter shown in FIG. 4 and the Farrow-type fractional delay filter shown in FIG. 6 can ensure a wide fractional delay frequency region by the fractional delay process of D = 3 to 4. Thus, in the case of a Farrow type fractional delay filter, the Nth order fractional delay filter is modified by fractional delay processing in the range of round (N / 2) -1/2 to -round (N / 2) +1/2. In the case of a Farrow type fractional delay filter, a wide fractional delay frequency region can be secured by fractional delay processing of D = -1 / 2 to +1/2.

(Frequency error correction)
As described above, in the OFDM demodulator 100 according to the present invention, the frequency error is corrected by the frequency error correction unit 103 and the FFT unit 105.

  The frequency error detection unit 106 uses the carrier frequency of the digital broadcast wave (that is, the sampling frequency in OFDM modulation on the transmission side) and the operation clock frequency supplied from the PLL 111 in the OFDM demodulator 100 (that is, in OFDM demodulation on the reception side). A frequency error α with respect to the sampling frequency) is detected and supplied to the sampling correction control unit 107. Here, the digital signal obtained by OFDM modulation on the transmission side corresponds to the first sample series signal sampled at the first sampling timing in the claims. And the digital signal (digital signal generated by the ADC 101) subject to OFDM demodulation on the receiving side corresponds to the second sample series signal generated by sampling at the second sampling timing in the claims. To do.

  The sampling correction control unit 107 calculates a sampling timing error as information for correcting the frequency error from the frequency error α, and supplies the fractional part to the frequency error correction unit 103. The sampling timing error is the difference between the sampling timing when sampling the digital broadcast wave received by the OFDM demodulator 100 and the true sampling timing (sampling timing at the time of OFDM modulation at the broadcasting station). The calculation method of the sampling timing error in the sampling correction control unit 107 will be described in more detail as follows.

  In the OFDM demodulator 100, assuming that the receiving side sampling frequency is F's, the true sampling frequency is Fs, and the true sampling clock period is Ts, the receiving side sampling clock period T's is expressed by Equation 12 using the frequency error α.

  Further, the sampling timing error δTs per clock cycle (deviation of the true sampling clock cycle Ts with respect to the receiving-side sampling clock cycle T ′s) is expressed by Equation 13.

  For example, when the MT's time has passed in the OFDM demodulator 100, the total error is M times δTs shown in Equation 13. Therefore, if the sampling timing error MδTs (in seconds) is corrected with a fractional delay filter that operates at the receiving-side sampling frequency F ′s, it is possible to extract a value at the true sampling timing.

  The sampling correction control unit 107 calculates the sampling timing error not in units of seconds but in units of reception side sampling clock cycles. That is, the sampling correction control unit 107 calculates the sampling timing error Δ from the frequency error α according to Equation 14.

  Then, the sampling correction control unit 107 decomposes the calculated sampling timing error Δ into an integer part Δint and a fractional part (fractional part) Δfrac (Δ = Δint + Δfrac). Then, the fractional part Δfrac of the sampling timing error Δ is given to the frequency error correction unit 103 as sampling timing error information, and the integer part Δint of the sampling timing error Δ is given to the FFT unit 105 as sampling timing error information.

  When the frequency error correction unit 103 receives the sampling timing error information Δfrac, the frequency error correction unit 103 executes a fractional delay filter process according to the sampling timing error information Δfrac. For example, when an Nth-order Lagrange filter or Farrow type fractional delay filter is used as the fractional delay filter, D = round (N / 2) −Δfrac is input to the fractional delay filter to obtain a sample value at the true sampling timing. . When an Nth-order modified Farrow-type fractional delay filter is used as the fractional delay filter, D ′ = − Δfrac is input to the fractional delay filter to obtain a sample value at the true sampling timing.

  On the other hand, the FFT unit 105 operates at the reception-side sampling frequency F ′s, and can shift the FFT calculation start time in units of the reception-side sampling clock period T ′s. When the integer part Δint of the sampling timing error information Δ changes, that is, when the sampling timing error MδTs (in seconds) changes by ± T ′s, the FFT calculation start position is shifted by ± T ′s so as to cancel it.

  In this way, by correcting the fractional part Δfrac of the sampling timing error information Δ by the frequency error correction unit 103 and the integer part Δint by the FFT operation unit 105, the entire sampling timing error information Δ can be corrected.

  More specifically, the frequency error correction unit 103 is represented by Equation 15 in the case of a Lagrange filter, Equation 16 in the case of a Farrow type fractional delay filter, and Equation 17 in the case of a modified Farrow type fractional delay filter. The sampling value at the interpolation point corresponding to the delay amount D or D ′ is interpolated. As described above, the Lagrange interpolation filter and the Farrow-type fractional delay filter obtain the D-delayed sampling value x (n−D) by interpolation when the n-th sampling value x (n) is input. Specifically, the Lagrange interpolation filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}. X (n−D) is calculated according to Equation 15. Further, the Farrow type fractional delay filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}, X (n−D) is calculated according to Equation 16. The modified Farrow-type fractional delay filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}. , X (n−D) is calculated according to Equation 17. However, as can be seen from Equation 17, when calculating x (n−D), D ′ = D-round (N / 2) is designated for the modified Farrow type fractional delay filter, not the delay amount D itself. (Input) needs to be done.

  As described above, D = round (N / 2) −Δfrac may be input to the Lagrange filter and the Farrow-type fractional delay filter. On the other hand, D ′ = − Δfrac may be input to the modified Farrow type fractional delay filter. As a result, interpolation can be performed at the same timing within the sampling period T's whether the Lagrange filter or the Farrow type fractional delay filter is used as a fractional delay filter or when the modified Farrow type fractional delay filter is used as a fractional delay filter. it can.

  Since D and D 'are delay amounts, their time axes are set from the present to the past. On the other hand, since the time axis of the timing error information Δ is set from the present to the future, a minus sign is added before Δfrac. When the time axis of D or D ′ is defined from the present to the future in the implementation of the filter, D = round (N / 2) + Δfrac and D ′ = + Δfrac. Thus, when the fractional part Δfrac is input to the fractional delay filter, it is necessary to pay attention to the direction of the time axis in Δfrac, D, and D ′.

  Note that the possible range of the fractional part Δfrac may be −0.5 ≦ Δfrac <+0.5 or 0 ≦ Δfrac <+1. There is no problem in adopting an optimal definition based on the characteristics of the sampling value prediction means used for the implementation and the specifications of the control circuit. The integer part may be defined in accordance with the fractional part Δfrac.

Note that the filter coefficient qn (k) in Expression 16 is the element Q (n, k) of the matrix Q in Expression 7, and Σq _n (k) x (nk) constitutes the Farrow type filter shown in FIG. 5 corresponds to each FIR filter Cn (z), and Σ {D ⁿ (Σq _n (k) x (nk))} corresponds to the Honer method shown in FIG. Further, the filter coefficient q′n (k) of Expression 17 is the element Q ′ (n, k) of the matrix Q ′ of Expression 10.

  In the OFDM demodulator 100 according to the present embodiment, the frequency error correction unit 103 is repeated by repeating the above processing in the frequency error detection unit 106, the sampling correction control unit 107, the frequency error correction unit 103, and the FFT unit 105. The frequency error at the time of output is converged to 0 or near 0.

  The processing outline of the correction of the frequency error in the OFDM demodulator 100 will be described with reference to FIGS. 7 and 8 as follows.

  FIG. 7 is a diagram for explaining a sampling timing error between the sampling timing and the true sampling timing of the OFDM demodulator 100. In the example shown in FIG. 7, the operation clock cycle of the OFDM demodulator 100 is T's, and sampling is performed every T's. However, the sampling clock cycle in the digital baseband processing at the broadcasting station is Ts, and one cycle A state in which an error of δTs occurs is shown every time. Here, if the timing at which the sampling timing of the OFDM demodulator 100 coincides with the true sampling timing is t = 0, the timing error at the time of sampling at t = T ′s is δTs, and the timing error at the time of sampling at t = 2T ′s. Is δTs × 2, and the timing error at the time of sampling at t = 3T ′s is δTs × 3. That is, the timing error at the time of sampling at t = MT ′s is MδTs.

  At this time, the sampling correction control unit 107 uses the frequency error α received from the frequency error detection unit 106 to calculate the sampling timing error Δ = Mα by Equation 14. Then, the fractional part Δfrac of the sampling timing error Δ is supplied to the frequency error correction unit 103, and the integer part Δint of the sampling timing error Δ is supplied to the FFT unit 105. Then, the frequency error correction unit 103 refers to the fractional part Δfrac of the sampling timing error Δ to calculate the sampling value at the true sampling timing, and the FFT unit 105 refers to the integer part Δint of the sampling timing error Δ. Shift the start position of the FFT operation.

  The Lagrange filter calculates an interpolation value at the same interpolation point unless the filter coefficient h (k, D) is changed. On the other hand, in the Farrow type fractional delay filter and the modified Farrow type fractional delay filter, although both the filter coefficients qn (k) and q′n (k) are always fixed, the multiplier (× By changing the value of D), it is possible to dynamically change the point at which interpolation processing is performed.

  FIG. 8 is a diagram showing an image of interpolation processing using a modified Farrow-type fractional delay filter, and FIG. 8A is a diagram showing an image of interpolation processing at a certain sampling timing (t = 4T ′s), and FIG. FIG. 4 is a diagram showing an image of interpolation processing at the next sampling timing (t = 5T ′s) of (a).

  In the example shown in FIG. 8, at time t = 4T's, as shown in (a), the true sampling timing (from the five sampling values X (0) to X (4) stored in the register ( The sampling value X (4-D) = X (2-D ′) at the interpolation point corresponding to the delay amount D ′ is calculated, and stored in the register at time t = 5T ′s as shown in FIG. The sampling value X (5-D) = X (3-D ′) at the true sampling timing is calculated from the five sampling values X (1) to X (5). In the example of the modified Farrow type fractional delay filter illustrated in FIG. 8, the delay amount D ′ = − Δfrac, and the frequency error correction unit 103 performs the calculation of Equation 17.

  As a result, at each sampling timing in the OFDM demodulator 100, data at the true sampling timing (sampling timing at a broadcast station performing OFDM modulation) is sequentially interpolated, so that the frequency error can be corrected.

  The OFDM demodulator according to the present invention may be configured to be connected to a direct conversion type tuner. FIG. 9 is a block diagram showing a configuration of another OFDM demodulator 200 according to the present invention. As shown in FIG. 9, the OFDM demodulator 200 is used by being connected to a direct conversion type tuner 20. The tuner 20 receives a digital broadcast wave from a broadcast station, performs orthogonal demodulation, generates a baseband OFDM signal composed of an I channel signal and a Q channel signal, and supplies the baseband OFDM signal to the OFDM demodulator 200. Each block included in the OFDM demodulator 200 has the same function as the block having the same reference numeral in the OFDM demodulator 100 shown in FIG. 1, and the I channel signal and the Q channel signal from the tuner 20. In contrast, the above-described sampling reception and frequency error correction are performed, and the frequency error is corrected by the same operation as that of the OFDM demodulator 100. Since the I-channel signal and the Q-channel signal are independent signals, the ADC 101, the sampling receiver 102, and the frequency error correction unit 103 mount two identical circuits in parallel for the I-channel signal and the Q-channel signal.

  FIG. 1 shows a configuration example of the present invention in the case of an IF type tuner, and FIG. 9 shows a configuration example of the present invention in the case of a zero IF type tuner. The frequency error correction unit 103 independently corrects the digital IF signal in FIG. 1 and the two I / Q components of the digital BB signal in FIG. However, even in the case of FIG. 1, since the digital BB signal is generated by the digital quadrature detection unit 104, the two I / Q component systems may be independently corrected by the frequency error correction unit 103.

(Oversampling)
The processing and control of the fractional delay filter in the configuration for correcting the frequency error using oversampling will be described. In the OFDM demodulator 100, oversampling is performed in the ADC 101 or the sampling receiver 102.

  In the Lagrange interpolation filter and the Farrow type fractional delay filter, as shown in FIGS. 4 and 6, the entire Nyquist region is not the fractional delay frequency region. If the range of about 80% of the Nyquist region is set to the fractional delay frequency region, the order of the Lagrange interpolation filter or the Farrow type fractional delay filter is N ≧ 200, so that circuit implementation is not practical.

Therefore, a filter that can secure the fractional delay frequency region required according to the application is designed. That is, consider designing a filter capable of fractional delay processing in the range of f = −F _{1/2 to} + F _1/2 , where F ₁ is the desired fractional delay frequency region width. The actual design of OFDM demodulator, the sum of the margin of the carrier frequency error allowed in the frequency band of the OFDM wave is equivalent to F _1.

By the way, it can be seen from FIG. 6B that fractional delay processing is correctly performed in the frequency range of ± 0.2 Fs, and the error is small. Therefore, if the sampling frequency is Fs = 5F ₁ , fractional delay processing is correctly performed in the frequency region of ± F ₁ (= ± 0.2 × 5F ₁ ). That is, when the desired fractional delay frequency region cannot be realized at the reference clock frequency, the sampling frequency is converted into an oversampling state according to the desired fractional delay frequency region, thereby enabling interpolation in the entire desired frequency region. According to the “Multirate Signal Processing for Communication Systems” described above, rate conversion at an integer multiple sampling frequency is a general technique that surpasses digital signal processing. By applying this rate conversion to the OFDM demodulator 100, a wide fractional delay frequency region can be realized by a Farrow type fractional delay filter having a low order N. A configuration in which the sampling rate conversion function and the Farrow type fractional delay filter with a low order N are combined can be easily implemented on a smaller scale than a filter with N ≧ 200.

The sampling frequency is not limited to Fs = 5F _1. For example, from FIG. 6B, when it is necessary to reduce the error, it is necessary to further increase the conversion rate. Conversely, if it is desired to lower the sampling frequency with emphasis on reducing power consumption rather than error, the rate conversion ratio needs to be made smaller.

(Fraction delay processing shift)
FIG. 10 is a block diagram showing a configuration of another OFDM demodulator 300 according to the present invention. The OFDM demodulator 300 includes the same blocks as those of the OFDM demodulator 100 shown in FIG. 1, and each block included in the OFDM demodulator 300 is assigned the same reference numeral in the OFDM demodulator 100 shown in FIG. It has the same basic functions as the block. Hereinafter, operations different from those of the OFDM demodulator 100 of FIG. 1 in each block of the OFDM demodulator 300 will be described.

  The difference from the OFDM demodulator 100 in FIG. 1 is that the sampling clock shift amount is supplied from the sampling correction control unit 107 to the frequency error correction unit 103, and the FFT window shift is also performed from the sampling correction control unit 107 to the FFT unit 105. The amount is in the supply.

  As described above, for example, in the modified Farrow type filter, the delay amount D ′ = − Δfrac (fractional delay amount). If the filter characteristic is the characteristic as shown in FIG. Considering calculation error, when N is an even number, it is set within the range of −1/2 <D ′ <+ 1/2, and when N is an odd number, it is set within the range of 0 <D ′ <1. It is preferable (both upper limit value and lower limit value are in units of the sampling clock period on the receiving side) Therefore, even when the fractional delay amount exceeds the range of a finite value (for example, -1/2 to +1/2), a configuration for correcting the frequency error is required. The finite value range corresponds to the predetermined sampling timing range in the claims.

  Hereinafter, the operation of the OFDM demodulator 300 will be described. The sampling clock shift amount and the FFT window shift amount described above are used when the fractional delay amount exceeds the finite value described above. In the OFDM demodulator 300, the sampling clock shift to the frequency error correction unit 103 is performed. By supplying the amount and the FFT window shift amount to the FFT unit 105 in conjunction with each other, a configuration is realized in which the frequency error is corrected even when the fractional delay amount exceeds a finite value.

  When the time elapsed in the OFDM demodulator 300 is expressed as MT ′s (T ′s is the sampling period in the OFDM demodulator 300) described above, the value of M increases monotonically with the elapse of time if demodulation is continued. However, the area that can be corrected by the fractional delay filter is finite, and when M increases, the sampling timing error Δ = Mα exceeds the finite value described above.

  Here, taking the case of the modified Farrow type fractional delay filter as an example, the delay amount D ′ = − Δfrac is set to −1/2 to +1/2. Therefore, in the OFDM demodulator 300, if D ′ = + − 1/2 as a result of the increase in M, the D ′ is changed to D ′ = − + 1/2 as shown in FIG. FIG. 11 is a diagram illustrating an example of correcting the sampling value. Each row in FIG. 11 represents the timing within the symbol. The time advances in sampling units from the left to the right of each row, and in symbols from the upper row to the lower row. In FIG. 11, a thick arrow indicates the reception side sampling timing based on the operation clock, and a thin arrow indicates the true sampling timing of the broadcast wave. When the frequency error is constant, the true timing shifts at regular intervals with time as shown in FIG. Since it is difficult to display the entire symbol in the sampling clock cycle, only the vicinity of the FFT window position is enlarged and displayed in FIG. At the same time, the FFT window is shifted by 1T ′s in the direction opposite to the change of D ′. This is equivalent to shifting the integer part Δint and the fractional part Δfrac of the sampling timing error Δ by 1T ′s in the opposite direction. The total Δ is unchanged before and after the shift. By this processing, the delay amount D ′ and Δfrac can be set to −1/2 to +1/2. In FIG. 11, the processing is performed at the falling timing of the reception side sampling clock, but conversely, the processing may be performed at the rising timing. In that case, the rising and falling in the figure may be reversed.

  For example, if the state shown in FIG. 8B is D ′ = 2/3, for example, the delay amount D ′ exceeds a finite value (= 1/2), and the interpolation value cannot be calculated with high accuracy. . In the example shown in FIG. 8, a fractional delay amount with n = 0 as the reference sampling timing is set as the delay amount D ′ corresponding to the true sampling timing. However, the interpolation point corresponding to the delay amount D ′ is closer to the sampling timing of n = 1 than the sampling timing of n = 0. That is, instead of using n = 0 as the reference sampling timing, the delay amount D ′ is set to a finite value −1/2 to +1/2 by using the delay amount D ′ using n = 1 as the reference sampling timing. The interpolation value (sampling value at the true sampling timing) can be calculated with high accuracy.

  In updating the reference sampling timing, the sampling timing error Δ (sampling clock unit) calculated for each sampling clock is divided into an integer part Δint and a fractional part Δfrac, and the delay amount D ′ is set as D ′ = − Δfrac. (When D ′ falls within the range of −1 to 0). If D ′ falls within −1/2 to +1/2, for example, the delay amount D ′ may be calculated by subtracting 1/2 from the fractional part of (Δ + 1/2). The sampling correction control unit 107 supplies the delay amount D ′ calculated in this way to the frequency error correction unit 103 as the sampling clock shift amount, and simultaneously calculates the integer part of (Δ + 1/2) calculated at the same time as the FTT window shift amount. To the FTT unit 105. Alternatively, the start timing of the FFT window may be generated in consideration of the shift by the integer part, and the start timing may be supplied to the FFT unit 105.

  The frequency error correction unit 103 (1) latches new data in the modified Farrow type fractional delay filter, (2) acquires the delay amount D ′ from the sampling correction control unit 107, and (3) acquires the acquired delay amount D ′. Is input to the modified Farrow-type fractional delay filter to repeat a series of processes for obtaining a new sampling value for each sampling clock. At the same time, the FFT unit 105 acquires (1) the FFT window shift amount (an integer part of Δ + 1/2) from the sampling correction control unit 107, and (2) the acquired FFT window shift amount is the same as the previously acquired FFT window shift amount. When the number is increased or decreased by ± 1 (and only in that case), a series of processes of shifting the FFT calculation start position by ± T ′s is repeated for each sampling clock. Or you may comprise so that an FFT window may be set and FFT processing may be performed according to the FFT window start timing which the frequency error correction | amendment part 103 supplies.

  As a result, the fractional delay amount does not always exceed a finite value, and D ′ falls within the range of −1/2 to +1/2. As shown in FIG. 11, the FFT window always starts at the same timing with respect to the sampling clock. That is, the sampling timing error due to the frequency error can be corrected in an infinite time without being restricted by the interpolation point range (that is, the fractional delay range restriction).

(Interpolation processing in oversampled state)
Further, as described above, when the fractional delay process is performed in the oversampled state, the fractional delay frequency region is effectively widened as described above. Here, however, the fractional delay frequency region exceeds four times the FFT standard sampling clock frequency Fs. Consider the case of sampling and performing fractional delay processing. Even when fractional delay processing is performed by oversampling, the final timing correction target is to correct the error in the Fs clock. Therefore, in order to perform a fractional delay (D ′ = − 1/2 to +1/2) with respect to the reference sampling clock, an integer delay (D ′ = ± 0, ± 1, ± 2, ± 3) with respect to the oversampling clock ( (Hereinafter referred to as “oversampled integer delay”) and fractional delay fractional delay (D ′ = − 1/2 to +1/2) with respect to the oversampling clock (hereinafter referred to as “oversampled fractional delay”) It becomes.

  In this case, the frequency error correction unit 103 that receives the sampling clock shift amount has a configuration in which a sampling clock shift unit is added. FIG. 12 is a diagram illustrating a specific configuration of the frequency error correction unit 103 corresponding to integer delay processing.

  As shown in FIG. 12, the frequency error correction unit 103 includes integer delay units 1032 and 1033 for oversampled integer delay (D ′ = ± 0, ± 1, ± 2, ± 3), and an oversample fractional delay (D This is a configuration including a fractional delay unit 1031 for '= -1 / 2 to +1/2). The integer delay unit 1032 is an integer delay unit that corrects the frequency error when the frequency deviation is negative, and the integer delay unit 1033 is an integer delay unit that corrects the frequency error when the frequency deviation is positive. That is, when fractional delay processing is performed in the oversampled state, the oversampled integer delay amount is also shifted while the oversampled fractional delay amount is shifted by the configuration shown in FIG.

  Hereinafter, the oversampled integer delay and the oversampled fractional delay in the oversampling state will be described in more detail. When oversampling is not performed (ie, Fs clock), when the fractional delay amount exceeds a finite value, the oversampled fractional delay amount is changed from D ′ = + − 1/2 to D ′ = − + 1/2. At the same time, as described above, it is necessary to shift the disclosure timing of the FFT window in the reverse direction.

  On the other hand, when the oversampling rate conversion ratio is an integer oversampling state, for example, when the oversampling clock is 4 Fs clock, the oversampling delay amount is changed from D ′ = + − 1/2 to D ′ =. By changing to-+ (4-1 / 2), the start timing of the FFT window is shifted in the reverse direction by the Fs clock and one period T's. That is, it is necessary to shift the oversampled integer delay amount in accordance with the oversampling state. However, as shown in FIG. 12, the frequency error correction unit 103 has a total oversample delay amount before and after the fractional delay filter 1031. With the configuration in which the integer delay units 1032 and 1033 that can be selected are provided, the oversampled integer delay amount can be shifted.

  Further, the rate conversion ratio may be a non-integer due to the restriction of the entire baseband processing unit. For example, when 4.5 times oversampling, 4.5 Fs clock oversampled integer delay (D ′ = ± 0, ± 1, ± 2, ± 3) and oversampled fractional delay (D ′ = − 1/2) Timing adjustment is performed in both of (˜ + 1/2).

  However, in this case, care must be taken because the FFT window start timing is shifted in units of the cycle Ts of the FFT reference clock frequency. Therefore, when the oversampling clock is 4.5 Fs clock, the oversampling delay amount is changed from D ′ = + − 1/2 to D ′ = − + (4.5−1 / 2), but the FFT window starts. The timing is shifted in the reverse direction by the same amount as when the Fs clock is 1 cycle Ts, that is, when the oversampling clock is 4Fs clock.

  In the above description, the case where the rate conversion ratio is 4 times and 4.5 times has been described as an example, but the rate conversion ratio is not limited to this. It can be implemented in the same manner at an arbitrary rate conversion ratio according to the calculation accuracy of fractional delay processing and the request for baseband signal processing.

(Frequency error detection)
FIG. 13 is a block diagram showing a configuration of another OFDM demodulator 400 according to the present invention. The OFDM demodulator 400 includes the same blocks as those of the OFDM demodulator 100 shown in FIG. 1, and each block included in the OFDM demodulator 400 is assigned the same reference numeral in the OFDM demodulator 100 shown in FIG. It has the same basic functions as the block. Hereinafter, operations different from those of the OFDM demodulator 100 in FIG. 1 in each block of the OFDM demodulator 400 will be described.

  In the OFDM demodulator 400 of FIG. 13, the frequency error detection unit 106 extracts an SP (Scattered Pilot) signal from the frequency domain complex signal output from the FFT unit 205 in the OFDM demodulation process, and the phase of the SP signal in the time direction is extracted. A frequency error α is obtained from the rotation amount. Here, an example for obtaining the frequency error from the amount of phase rotation will be given.

  If the number of FFT sampling points is N and the guard interval ratio is g, the effective symbol period is N [Ts ′], and the symbol period is (1 + g) N [Ts ′]. The accumulated error δTsym of the sampling timing error after one symbol is expressed by Expression 14 to Expression 18.

  Further, the phase rotation amount ψ (k) of the FFT output carrier k when the FFT window is shifted by τ [Ts ′] is expressed by Equation 19.

  From Equation 18 and Equation 19, the change θ (k) of the phase rotation amount caused by the FFT window shift amount δTsym per symbol having the same meaning as the accumulated error of the sampling timing error after one symbol is obtained by Equation 20. It is done.

  Then, the frequency error α is obtained by the equation 21 from the phase rotation amount of the equation 20.

  That is, in the OFDM demodulator 400, the frequency error detection unit 106 extracts the SP signal from the signal converted into the frequency axis information output from the FFT unit 105, observes the SP signal in the time axis direction, and determines its phase. By converting the rotation amount into a rotation amount per symbol, a frequency error can be detected.

  Furthermore, among the SP signals extracted from the signal in the frequency domain output from the FFT unit 105, those having low phase reliability, more specifically, those corresponding to the following (1) to (3) are used as frequencies. By not using it for error detection, it is possible to improve the accuracy of the frequency error value. The SP signal is (1) the amplitude of the SP signal is small, (2) the center frequency carrier of the FFT output or its vicinity, affected by interference waves, (3) affected by spurious noise, etc. In this case, the reliability of the phase of the SP signal is low because it is strongly influenced by noise or the accuracy of the value is low.

  Whether or not the amplitude of the SP signal is small is determined by directly obtaining the amplitude of the SP or by obtaining the square of the amplitude and comparing it with a predetermined threshold value. Further, whether or not it is the center frequency carrier of the FFT output or the vicinity thereof (frequency within a predetermined range) can be determined by the timing of the FFT output to be used. FIG. 14 is a diagram showing the relationship between the window position shift due to the frequency error and the phase rotation of the carrier of the FFT output. As shown in FIG. 14, the phase rotation of the carrier near the center frequency carrier becomes small. As a result, in the case of the center frequency carrier, the denominator of Formula 21 becomes 0 and the value cannot be obtained, or the value of the numerator of Formula 21 itself becomes small near the center frequency carrier, and the accuracy deteriorates. The degree is lowered. Furthermore, as an example of a method for determining whether or not it is affected by jamming waves or spurious noise, the fluctuation in amplitude is examined in the time axis direction, and it has a constant high amplitude. For example, the configuration may be such that the object is affected by interference or spurious noise. The phase of the SP signal having a constant high amplitude is less reliable because the phase of the disturbing wave or spurious noise is more strongly influenced than the phase change caused by the window position shift.

  Therefore, the frequency error detection unit 106 determines whether the SP signal included in the output from the FFT unit 105 corresponds to the above (1) to (3), and does not correspond to the SP signal, that is, the reliability of the phase. By using a configuration that detects a frequency error using only a SP signal having a high value, the accuracy of the calculated frequency error value can be improved.

  Finally, the guard interval ratio, effective symbol period, and symbol period used in the above description will be briefly described.

  A transmission symbol in the OFDM modulation / demodulation scheme is composed of a guard interval and an effective symbol following the guard interval. When a transmission symbol is expressed on the time axis, a period occupied by a guard interval is called a guard interval period, and a period occupied by an effective symbol is called an effective symbol period. The symbol period occupied by the transmission symbol on the time axis is naturally the sum of the guard interval period and the effective symbol period. The waveform of the transmission symbol in the guard interval period is the same as the waveform at the end of the effective symbol period. The ratio of the guard interval period to the effective symbol period is called a guard interval ratio g. For details, see Non-Patent Document 1.

(Additional notes)
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Finally, each block of the OFDM demodulator 100, 200, 300, 400 may be configured by hardware logic, or may be realized by software using a CPU as follows.

For example, the present invention can be expressed or modified as follows.
1. A set of subcarriers including pilot signals arranged in a predetermined pattern is subjected to orthogonal frequency division multiplex modulation (OFDM) using a clock generated on the basis of a specific frequency transmitter, and the frequency transmitter Is an OFDM demodulator that corrects a frequency error when receiving and demodulating using a clock generated based on another frequency oscillator, and the clock generated based on the frequency transmitter on the OFDM demodulator side A sampling receiver that generates a received sample sequence signal sampled using the sampling error, a sampling correction controller that calculates a fractional delay amount corresponding to true sampling timing from the frequency error information detected by the frequency error detector, and the reception The frequency error is calculated by interpolating the sampling value of the sample series signal with the fractional delay in the previous period. A frequency error correcting unit for generating a corrected correction signal,
An OFDM demodulator characterized by comprising:
The OFDM demodulator according to 2.1, further comprising oversampling means, wherein the oversampling means converts the sampling frequency of the sample sequence according to claim 1 into an oversampling state with respect to a reference clock frequency, An OFDM demodulator characterized in that interpolation processing performs interpolation processing of the oversampled data sequence.
The OFDM receiver according to 3.2 includes an FFT unit (Fast Fourier Transform) that converts a signal of time axis information to a signal of frequency axis information, and an FFT window position control unit that shifts an FFT calculation start position. When the sampling correction control unit calculates a delay amount exceeding a predetermined value, a fractional delay amount shifted by one cycle of the reference sampling clock is output, and the FFT window position control means sets the FFT window position to the reference sampling clock 1. An OFDM receiver characterized in that sampling timing correction can always be processed by simultaneously shifting by a period.
In the OFDM receiver according to 4.1, an FFT unit (Fast Fourier Transform) that converts time axis information into a signal of frequency axis information, and a phase from the pilot signal included in the signal converted into the frequency axis information An OFDM demodulator comprising: a frequency error detection unit that detects the frequency error from the amount of phase rotation in the time axis direction.
5.4 In the OFDM receiver described in 5.4, the pilot signal used for frequency error detection has a small amplitude, a frequency at or near the center frequency of the FFT output, a signal affected by an interference wave, and a spurious signal. An OFDM demodulator characterized by not using one that is affected by noise.

  Note that in each part and each processing step of the OFDM demodulator of the above embodiment, a calculation means such as a CPU executes a program stored in a storage means such as a ROM (Read Only Memory) or a RAM, and a communication such as an interface part. This can be realized by controlling the means. Therefore, various functions and various processes of the OFDM demodulator according to the present embodiment can be realized simply by a computer having these means reading the recording medium storing the program and executing the program. In addition, by recording the program on a removable recording medium, the various functions and various processes described above can be realized on an arbitrary computer.

  As this recording medium, a program medium such as a memory (not shown) such as a ROM may be used for processing by the microcomputer, or a program reader is provided as an external storage device (not shown). It may be a program medium that can be read by inserting a recording medium therein.

  In any case, the stored program is preferably configured to be accessed and executed by the microprocessor. Furthermore, it is preferable that the program is read out, and the read program is downloaded to a program storage area of the microcomputer and the program is executed. It is assumed that this download program is stored in advance in the main unit.

  The program medium is a recording medium configured to be separable from the main body, such as a tape system such as a magnetic tape or a cassette tape, a magnetic disk such as a flexible disk or a hard disk, or a disk such as a CD / MO / MD / DVD. Fixed disk, IC card (including memory card), etc., or semiconductor ROM such as mask ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash ROM, etc. In particular, there are recording media that carry programs.

  In addition, if the system configuration is capable of connecting to a communication network including the Internet, the recording medium is preferably a recording medium that fluidly carries the program so as to download the program from the communication network.

  Further, when the program is downloaded from the communication network as described above, it is preferable that the download program is stored in the main device in advance or installed from another recording medium.

  The present invention can be applied to a receiver that can efficiently transmit a video signal and an audio signal by a digital transmission method, and is particularly suitable for an OFDM demodulator, an OFDM demodulation method, a program, and a computer-readable recording medium. is there. In addition, a device that receives a signal in accordance with the OFDM scheme, for example, a demodulator for a wireless LAN, a demodulator for a PLC (Power Line Communication), 3GPP standard 3.9 generation (LTE: mobile phone standard) The present invention can also be applied to an OFDM demodulator for Long Term Evolution), a fourth generation standard, a demodulator for receiving BS digital broadcast and CS digital broadcast, and a demodulator for cable television.

It is a block diagram which shows the structural example of the OFDM demodulation apparatus which concerns on this invention. It is a figure which shows the interpolation process by a fraction delay filter. It is a figure which shows the structure of a FIR filter. In the Lagrange interpolation filter, it is a figure which shows the filter characteristic at the time of changing an interpolation point, (a) is a figure which shows an amplitude frequency characteristic, (b) shows the actual correction timing Dint which considered the phase characteristic. (C) is a figure which shows SNR which considered both the amplitude and the phase. It is a figure which shows the structure of a Farrow type | mold fractional delay filter. In the Farrow type fractional delay filter, it is a figure which shows the filter characteristic at the time of changing an interpolation point, (a) is a figure which shows an amplitude frequency characteristic, (b) is the actual correction timing which considered the phase characteristic. (C) is a figure which shows SNR which considered both the amplitude and the phase. It is a figure explaining the sampling timing error of the sampling timing of an OFDM demodulator, and a true sampling timing. It is a figure which shows the image of the interpolation process using a deformation | transformation Farrow type | mold fractional delay filter, Comprising: (a) is a figure which shows the image of the interpolation process in a certain sampling timing, (b) is the next sampling timing of (a). It is a figure which shows the image of the interpolation process in. It is a block diagram which shows the structural example of the OFDM demodulation apparatus which concerns on this invention. It is a block diagram which shows the structural example of the OFDM demodulation apparatus which concerns on this invention. It is a figure which shows the example which correct | amends a sampling value. It is a figure which shows the structure of the frequency error correction | amendment part corresponding to an integer delay process. It is a block diagram which shows the structural example of the OFDM demodulation apparatus which concerns on this invention. It is a figure which shows the relationship between the window position shift by a frequency error, and the phase rotation of the carrier of an FFT output.

Explanation of symbols

1 Receiver (Receiver)
10 Tuner (Receiving means)
20 direct conversion type tuner 100 OFDM demodulator 200 OFDM demodulator 300 OFDM demodulator 400 OFDM demodulator 101 ADC (sampling means, oversampling means)
102 Sampling receiver (oversampling means)
103 Frequency error correction unit (sampling value prediction means)
104 Quadrature demodulation generator (orthogonal demodulation means)
105 FFT section (FFT operation means)
106 Frequency error detection unit (frequency error detection means)
107 Sampling correction control unit (sampling timing error information generating means)
108 Waveform Equalizer 209 Error Correction Unit 110 Frequency Transmitter 111 PLL Circuit 1031 Fractional Delay Filter 1032 Sampling Clock Shift Register 1033 Sampling Clock Shift Register

Claims (11)

An OFDM demodulator for demodulating an OFDM signal including a data signal and a pilot signal,
Receiving means for receiving an analog signal obtained by analogizing the first sample series signal sampled at the first sampling timing based on the reference signal of the first frequency oscillator;
Sampling means for sampling a received analog signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal;
Frequency error detecting means for detecting a frequency error between the reference signal of the first frequency oscillator and the reference signal of the second frequency oscillator;
From the frequency error, first sampling error information representing a fractional part of the sampling timing error, which is a difference between the first sampling timing and the second sampling timing, and a second representing an integer part of the sampling timing error Sampling timing error information generating means for generating the sampling timing error information of
Sampling value predicting means for predicting a sampling value at the first sampling timing by performing fractional delay filtering on the second sample series signal according to the first sampling error information;
Orthogonal demodulating means for orthogonally demodulating a sample sequence signal composed of predicted values obtained by the sampling value predicting means;
FFT calculation means for converting the demodulated signal obtained by the quadrature demodulation means into a frequency domain signal including a data signal and a pilot signal by FFT calculation , with reference to the second sampling timing error information An OFDM demodulator comprising: FFT computation means for shifting the FFT computation start position so as to cancel the change in the integer part of the sampling timing error . 2. The OFDM demodulation according to claim 1, wherein the second sample series signal input to the sampling value predicting unit is in an oversampling state with respect to a reference signal of the second frequency oscillator. Equipment . The second sample series signal obtained by the sampling means is converted to an oversampling state with respect to the reference signal of the second frequency oscillator, and the second sample series is converted to an oversampling state. OFDM demodulation apparatus according to signals to claim 1, characterized in further comprising in that, it oversampling means for inputting to the sampling value predicting means. The sampling means converts the second sample series signal into an oversampling state with respect to the reference signal of the second frequency oscillator, and converts the second sample series signal converted into the oversampling state. 2. The OFDM demodulator according to claim 1 , wherein the OFDM demodulator is input to the sampling value predicting means. The frequency error detecting means is
2. The OFDM demodulator according to claim 1 , wherein the frequency error is detected from a phase rotation amount in the time axis direction of a phase of a pilot signal included in a frequency domain signal obtained by the FFT operation means. The frequency error detecting means is
Of the pilot signal included in the signal obtained frequency domain by the FFT operation section, claim 1 using a large pilot signal than a threshold amplitude is predetermined, and detects the frequency error The OFDM demodulator according to 1. The frequency error detecting means is
Of the pilot signals included in the frequency domain signal obtained by the FFT computing means, the frequency domain signal obtained by the FFT computing means and extracted from the signal having a frequency within a predetermined range. The OFDM demodulator according to claim 1 , wherein the frequency error is detected using a pilot signal. The frequency error detecting means is
The frequency error is detected using a pilot signal which is not affected by an interference wave or spurious noise among pilot signals included in a frequency domain signal obtained by the FFT operation means. 2. The OFDM demodulator according to 1 . An OFDM demodulation method for demodulating an OFDM signal including a data signal and a pilot signal,
A receiving step of receiving an analog signal obtained by analogizing a first sample series signal sampled at a first sampling timing based on a reference signal of a first frequency oscillator;
A sampling step of sampling the received analog signal at a second sampling timing based on a reference signal of a second frequency oscillator different from the first frequency oscillator to generate a second sample series signal;
A frequency error detecting step of detecting a frequency error between the reference signal of the first frequency oscillator and the reference signal of the second frequency oscillator;
From the frequency error, first sampling error information representing a fractional part of the sampling timing error, which is a difference between the first sampling timing and the second sampling timing, and a second representing an integer part of the sampling timing error A sampling timing error information generating step for generating the sampling timing error information of
A sampling value prediction step of predicting a sampling value at the first sampling timing by performing a fractional delay filtering process according to the first sampling error information on the second sample series signal ;
An orthogonal demodulation step for orthogonally demodulating the sample sequence signal composed of the prediction values obtained in the sampling value prediction step;
An FFT calculation step for converting the demodulated signal obtained in the orthogonal demodulation step into a frequency domain signal including a data signal and a pilot signal by FFT calculation, and refers to the second sampling timing error information. And an FFT calculation step of shifting an FFT calculation start position so as to cancel the change in the integer part of the sampling timing error. A demodulation program for causing a computer to operate as the OFDM demodulator according to any one of claims 1 to 8, wherein the demodulation program causes the computer to function as each means included in the OFDM demodulator. . A computer-readable recording medium on which the demodulation program according to claim 10 is recorded.

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