JP5174363B2 - Display system - Google Patents

Description

  The present invention relates to a hold-type display device such as a liquid crystal display device, an organic EL (Electro Luminescence) display, and an LCOS (Liquid Crystal On Silicon) display, and more particularly to a display device and a display system suitable for displaying moving images.

  When the display devices are classified particularly from the viewpoint of moving image display, they are roughly classified into impulse-type display devices and hold-type display devices. An impulse type display device is a type in which the brightness of a scanned pixel is increased only during a scanned period, such as a cathode ray tube, and the brightness is decreased immediately after scanning. The hold type display device is a liquid crystal display device. In this way, the luminance based on the display data is kept until the next scanning.

In Patent Document 1, one frame period is divided into a first period and a second period, and pixel data to be written to the pixels in the frame period is intensively written in the first period. At this time, the luminance of the entire video is reduced. The writing value for the pixel is set to be twice the value of the image data so that the remaining pixel data is written in the second period only when the doubled value exceeds the displayable range. It is described that a change approaches an impulse type display device and improves the visibility of a moving image.
In Patent Document 2, a frame memory unit stores an input video signal for one frame, and a frame rate conversion signal generator generates a frame of a video signal from a clock signal, a horizontal synchronization signal, and a vertical synchronization signal synchronized with the input video signal. A clock signal, a horizontal synchronization signal, and a vertical synchronization signal converted at a conversion rate of 3 times or more are generated, and the video signal switching unit switches the output signal of the frame memory unit and the black level fixed video signal. It is described that switching is performed on the basis of a switching signal output from, and the display period of one frame of video is arbitrarily shortened.

  Similarly, Patent Document 3 discloses a liquid crystal display device having a frequency conversion circuit 11 that outputs each input frame four times at a rate of four times, and a liquid crystal display element 15 that displays each frame output 2N times. In the conversion frame, the luminance level of every other conversion frame of each conversion frame is converted to a level lower than the luminance level of every other conversion frame by the luminance control circuit, and supplied to the liquid crystal display element, It is described that motion blur of a moving image that occurs when each original frame is switched is reduced.

  Hereinafter, in the present specification, such a driving method is referred to as n-times speed impulse driving.

JP 2004-240317 A JP 2002-215111 A Japanese Patent Laid-Open No. 2004-317928

  In the display device having the n-times speed impulse drive described in Patent Document 1, it is necessary to perform n-time drawing, that is, rewrite output display data within one frame time of input display data. An n-times speed increasing means for increasing the display data n times is required. However, a frame memory is required for n-times speed increase. That is, a display device provided with an n-fold speed impulse drive increases the cost for the frame memory as compared with a normal display device. In Patent Document 1, since the first period data and the second period data are generated inside the display device, the first period data and the second period data are generated outside the display device and sequentially displayed. No consideration is given to the fact that the data in the first period and the data in the second period cannot be discriminated when the data is input to.

  An object of the present invention is to provide a display device in which the circuit scale is reduced by providing an n-times speed increasing circuit outside the display device.

  Another object of the present invention is to provide a display device capable of discriminating each of n fields within one frame period when an n-times speed increasing circuit is provided outside the display device.

  In Patent Documents 2 and 3, a switching signal is generated to discriminate a doubled frame, but delay due to writing to and reading from the frame memory is not considered.

  An object of the present invention is to provide a display device that can accurately determine a field period within one frame period.

The display system of the present invention includes a display panel in which a plurality of pixels are arranged, a first drive circuit that outputs a display signal corresponding to display data to the pixel, and a pixel for selecting the pixel that is to receive the display signal. a display device and a second driving circuit for outputting a selection signal to the pixel, first a synchronization signal to enter into the display device, the signal generating apparatus having a function of generating a first display data When, wherein the display device, the reception and the first display data, the first synchronizing signal indicating a break for each frame of the first display data as an input, conforming to predetermined data conversion rule The second display data obtained by data conversion of the first display data by the data conversion circuit and the second synchronization signal indicating a frame-by-frame separation of the second display data are used. Display data of 2 The data conversion circuit includes: n (n is an integer of 2 or more) data conversion rules; and a selection circuit that selects one data conversion rule from the n data conversion rules. Sequentially switches and selects the n data conversion rules from the first data conversion rule to the nth data conversion rule, and the switching of the data conversion rules is performed using the first synchronization signal. The selection circuit identifies each of the n frames of the first display data in order to select one data conversion rule from the n data conversion rules. An identification signal generation circuit for generating an identification signal to be transmitted, wherein the identification signal generation circuit is configured such that a frame having the same content as the immediately preceding frame is repeatedly input to the first display data, or It is detected whether or not switching of frames occurs due to the input of a frame having the content, and when the same frame is repeatedly input, the identification signal is sequentially transmitted in synchronization with the first synchronization signal. And when the frame is switched, the identification signal is reset, and the signal generator includes a signal generation circuit for generating third display data, and the first display data Is display data obtained by multiplying the frame frequency of the third display data by n, and the signal generator includes an n-times speed increasing circuit for generating the first display data from the third display data. The n-fold speed increasing circuit outputs the third display data n times during one frame period of the third display data, thereby converting the third display data into the first display data. In other words, at least one data conversion rule among the n data conversion rules is converted so as to display a brightness brighter than the first display data, and at least one of the n data conversion rules is displayed. The data conversion rule is perceived by performing data conversion so as to display a luminance lower than that of the first display data, and displaying the n second display data obtained by the n data conversion in series. The n data conversion rules are adjusted in advance so that the luminance corresponds to the luminance perceived by directly displaying the third display data for one frame period of the third display data. It is a display system.

The display system of the present invention further includes a signal generator having a function of generating the first synchronization signal input to the display device and the first display data, and the signal generator includes a third The first display data is generated based on the third display data and the direction of movement between frames from the third display data. And the display data having the frame frequency doubled by alternately selecting the third display data and the fourth display data, and based on the first synchronization signal, the first display data Is the third display data or the fourth display data, the selection circuit is selected based on the determination result, and the data conversion result for the same display data is the fourth display data. It may be converted to a bright or equal brightness compared to.

  According to the present invention, in a hold-type display device and a display system using the display device, the display characteristics of the impulse-type display device are realized by applying n-fold speed impulse-type driving, and good display with less moving image blurring is achieved. Quality can be obtained. Furthermore, according to the present invention, the display device and the display system can be provided at a lower cost than when the n-times speed impulse driving is performed on the display device.

  That is, according to the present invention, the circuit scale of the display device can be reduced by providing the n-times speed increasing circuit outside the display device.

  In addition, according to the present invention, even when the n-times speed increasing circuit is provided outside the display device, the display device can determine each of the n field periods within one frame period.

  Further, according to the present invention, since the field period is identified in consideration of the delay associated with the double speed, the display device can accurately determine the field period within one frame period.

  Subsequently, the configuration method of the display device and the display system of the present invention will be described with examples.

  First, the n-fold speed impulse driving performed in the present invention will be described with reference to FIGS. 1, 2, and 3. FIG.

  Subsequently, two configuration examples of a display device equipped with n-times speed impulse drive will be described with reference to FIG. 4 and respective problems will be described.

  Next, a first embodiment of the present invention that solves the above problems will be described with reference to FIGS.

  In the first embodiment, an n-times speed increasing circuit is arranged on the signal generator side in order to realize n-times speed impulse driving at a low cost, and a display device configured to output a synchronization signal from the signal generator to the display device, and Provide a display system.

  Next, a second embodiment of the present invention that solves the above problems will be described with reference to FIGS.

  In the second embodiment, a display device and a display system configured to provide a frame repetition detection circuit in a display device are provided.

  In the following description of the n-times speed impulse drive, the case of n = 2 will be described, but the value of n is not limited to 2 and may be a larger value.

  FIG. 1 shows a concept of a processing procedure for n-times speed impulse driving. As described above, this is an example of n = 2. The horizontal axis shows the passage of time.

  FIG. 1A shows input display data. Video data sampled every other frame period is sequentially input. One frame period is, for example, 16.6 ms for video data of an NTSC standard television signal. At this time, the frame frequency is 60 Hz.

  Next, the frame frequency of the input display data is multiplied by n.

  FIG. 1B shows n-fold speed display data obtained by speeding up the frame frequency of the input display data shown in FIG. For example, when the input display data is an NTSC signal and n = 2, the frame frequency of the n-times speed display data is 120 Hz. The same input display data is repeatedly output twice during the time of one frame period of the input display data. At this time, the display data update interval is a 1 / n frame period.

  Lastly, the n-speed display data is subjected to data conversion for impulse driving and displayed on the display panel.

  FIG. 1C shows an example of display of n-times speed impulse drive. Data conversion is performed on the n-times speed display data shown in FIG. 1B to generate and display a first field signal and a second field signal. The first field signal is displayed brighter than the original input display data, and the second field signal is displayed darker than the original input display data. At this time, when the first field and the second field are temporally integrated, the luminance is reduced by changing the display characteristics by controlling so that the luminance corresponding to the original input display data is perceived.

  FIG. 1D is another example of display of n-times speed impulse drive. The n-times speed display data shown in FIG. 1B is converted, and a first field signal and a second field signal are generated and displayed. The first field signal is displayed darker than the original input display data, and the second field signal is displayed brighter than the original input display data, so that the display characteristic is an impulse type. At this time, when the first field and the second field are temporally integrated, the luminance is reduced by changing the display characteristics by controlling so that the luminance corresponding to the original input display data is perceived.

  By controlling the display device according to the above procedure, it becomes possible to realize n-times speed impulse type drive, and even in the hold type display device, impulse type display characteristics are realized, and a good display quality with less moving image blur is achieved. Can be obtained.

  FIG. 2 is a diagram illustrating an example of a relationship (so-called γ characteristic) between the display luminance of the first field and the display luminance of the second field with respect to input display data in the n-fold speed impulse drive.

  The horizontal axis is the gradation of the input display data, and the vertical axis is the display brightness. A solid line 201 is an example in the case of normal driving, and a broken line 203 and an alternate long and short dash line 202 are examples of the display luminance of the first field and the display luminance of the second field in n-times speed impulse type driving, respectively.

  In normal driving, for example, the display luminance for the input display data of gradation Dp is Bp, and the display luminance for the input display data of gradation Dq is Bq. In other gradations, gradation and display luminance are associated with each other as in the example of FIG.

  On the other hand, in the n-times speed impulse drive, for input display data of gradation Dp, the display luminance of the first field is Blp and the display luminance of the second field is Bdp. By displaying the display brightness Blp in the first field period and subsequently displaying the display brightness Bdp in the second field period, it is possible to perceive the display brightness corresponding to the case where the display brightness Bp is displayed over one frame period. Adjust to. For input display data of gradation Dq, the display luminance of the first field is B1q, and the display luminance of the second field is Bdq. By displaying Blq in the first field period and then displaying the display brightness Bdq in the second field period, the display brightness corresponding to the case where the display brightness Bp is displayed over one frame period can be perceived. Keep it. In the other gradations, the display luminance of the first field is associated with the display luminance of the second field as in the example of FIG.

  In the above example, the description has been given of the configuration of the n-times speed impulse drive in which the first field is a bright field for relatively bright display and the second field is a dark field for relatively dark display. The second field may be a dark field and the second field may be a bright field.

  FIG. 3A is a graph showing an example of a change in input display data for a certain pixel of the display device. The horizontal axis indicates the frame (that is, time), and the vertical axis indicates the gradation.

  FIG. 3A shows an example of input display data having gradation Dp in the (i−1) -th frame and the i-th frame and gradation Dq in the (i + 1) th frame and the (i + 2) th frame.

  With respect to such input display data, the conventional display device is driven to display the display luminance Bp corresponding to the gradation Dp in the (i−1) th frame and the (i) th frame, and is scaled in the (i + 1) th frame and the (i + 2) th frame. It is driven to display the display brightness Bq corresponding to the tone Dq.

  Next, an example of n-times speed impulse drive will be described.

  3 (b), 3 (c), and 3 (d) show the processing of the display device and the display system when n-times impulse drive is performed on the input display data of FIG. 3 (a). It is a graph which shows a mode.

  FIG. 3B is an example of the n-fold speed-up display data when the input display data shown in FIG. The horizontal axis indicates the frame (that is, time) as in FIG. 3A, and the vertical axis indicates the gradation. The n-fold speed-up display data corresponds to the same input display data output repeatedly n times during the time of one frame period of the input display data.

  FIG. 3C shows a change in display luminance when the display device is driven by output display data obtained by performing data conversion processing for impulse-type driving on the n-fold speed display data shown in FIG. It is a figure which shows the example of a mode. The horizontal axis indicates the frame (that is, time) as in FIG. 3A, and the vertical axis indicates the display function.

  FIG. 3C shows a configuration example in which the first field is a bright field for relatively bright display, and the second field is a dark field for relatively dark display. This corresponds to the example of FIG.

  With respect to the n-fold speed-up display data shown in FIG. 3B, the display brightness Blp corresponding to the gradation Dp is displayed in the i-th frame and the first field of the i-th frame. In the second field of the 1st frame and the i-th frame, the display luminance Bdp corresponding to the gradation Dp is displayed. Further, the display is driven to display the display luminance B1q corresponding to the gradation Dq in the first field of the (i + 1) th frame and the (i + 2) th frame, and the display corresponding to the gradation Dq in the second field of the (i + 1) th frame and the (i + 2) th frame. Drive to display luminance Bdq.

  FIG. 3 (d) is different from FIG. 3 (c) showing a change in display luminance of the display device after the data conversion processing is performed on the n-times speed display data shown in FIG. 3 (b). It is a figure which shows the example of a structure. The horizontal axis indicates the frame (that is, time) as in FIG. 3A, and the vertical axis indicates the display function.

  FIG. 3D shows a configuration example in which the first field is a dark field for relatively dark display and the second field is a light field for relatively bright display. This corresponds to the example of FIG.

  For the n-times speed display data shown in FIG. 3B, the display is driven to display the display luminance Bdp corresponding to the gradation Dp in the i-th frame and the first field of the i-th frame. In the second field of the 1st frame and the i-th frame, the display luminance Blp corresponding to the gradation Dp is displayed. Further, the display is driven to display the display luminance Bdq corresponding to the gradation Dq in the first field of the (i + 1) th frame and the (i + 2) th frame, and the display corresponding to the gradation Dq is displayed in the second field of the (i + 1) th frame and the (i + 2) th frame. Drive to display the brightness B1q.

  As shown in FIGS. 3C and 3D, in the configuration of the n-fold speed impulse drive, there are a plurality of variations in which display characteristics are different depending on the order of the bright field and the dark field.

  The outline of the n-fold speed impulse drive in the display device and the display system of the present invention has been described above. Subsequently, two configuration examples of a display device and a display system equipped with an n-times speed impulse drive will be described with reference to FIG. 4 and respective problems will be described.

  FIG. 4A is a diagram illustrating a configuration example of a display device and a display system for realizing n-times speed impulse driving. Although FIG. 4 shows an example of a liquid crystal display device as a display device, a display device using another display principle may be used.

  The display system is, for example, a television body, a PC body, a mobile phone body, or the like.

  The display system includes a signal generation device 4100 and a display device 4000.

  The signal generator 4100 is, for example, a signal processing circuit group in a television receiver or a video recording / reproducing device, or a graphic processing circuit group in a PC or a mobile phone. The signal generator 4100 includes a signal generator circuit 4110 that generates input display data 4112 to be output to the display device 4000 and an input control signal group 4111.

  The display device 4000 includes an n-fold speed increasing circuit 4010, a data conversion circuit 4030, a timing generation circuit 4050, a frame memory 4020, a parameter holding circuit 4040, a data line driving circuit 4060, a scanning line driving circuit 4070, a liquid crystal A display panel 4080 and a reference voltage generation circuit 4090 are provided.

  The display device 4000 has a function of receiving input display data 4112 and input of an input control signal group 4111, and driving the liquid crystal display panel 4080 by applying n-fold speed impulse driving to the input display data 4112 and the input control signal group 4111. .

  The input control signal group 4111 includes, for example, a vertical synchronization signal that defines one frame period (a period for displaying one screen), a horizontal synchronization signal that defines one horizontal scanning period (a period for displaying one line), and display data It consists of a data valid period signal that defines the valid period, a reference clock signal synchronized with display data, and the like.

  The input display data 4112 and the input control signal group 4111 are transferred from the signal generator 4100 to the display device 4000. Various electrical signal levels such as LVDS level, CMOS level, and LVTTL level can be used for this transfer. In the display system, when the signal generating device 4100 and the display device 4000 are arranged far away from each other, it is desirable to use a method that can transmit over a long distance with less noise for this transfer.

  The n-times speed increasing circuit 4010 is a circuit that generates n-times speed-up display data 4012 obtained by multiplying the frame frequency of the input display data 4112 by n times.

  More specifically, the n-times speed increasing circuit 4010 sequentially stores the input display data 4112 input in the frame memory 4020. On the other hand, when reading the stored data for one frame period, the data is read within a time period obtained by dividing one frame period into n. Further, by performing the read operation n times in one frame period, n times the frame frequency can be realized.

  The input display data read out for the first time is used as the n-times speed-up display data for the first field, and the input display data read out for the second time is used as the n-times speed-up display data for the second field.

  4021 is write data to the frame memory 4020, and 4022 is read data from the frame memory 4020.

  The n-times speed increasing circuit 4010 generates a field identification signal 4013 and an n-times speed control signal group 4011.

  The field identification signal 4013 is synchronized with the n-fold speed-up display data 4012. Whether the n-fold speed-up display data 4012 is the n-fold speed-up display data for the first field or the n-fold speed-up display for the second field. Used to identify data. That is, the field identification signal 4013 is synchronized with the display data read clock from the frame memory 4020.

  The n-times speed control signal group 4011 includes, for example, an n-times speed vertical synchronization signal that defines one field period, an n-times speed horizontal synchronization signal that defines one horizontal scanning period, and n-times speed display data that defines an effective period of n-times speed display data. It is composed of an effective period signal and an n-times speed clock signal synchronized with the n-times speed display data.

  The frame memory 4020 is a storage element having a capacity capable of storing display data for at least one frame, and performs a process of writing input display data and a process of reading n-fold display data.

  As the frame memory 4020, for example, various DRAMs (Dynamic Random Access Memory) can be used.

  The data conversion circuit 4030 is a circuit for generating field conversion data 4032 for performing the n-times speed impulse driving, and receives the n-times speed display data 4012 output from the n-times speed circuit 4010 as an input, The n-times speed display data 4012 is converted into field conversion data 4032 for each field according to a predetermined data conversion rule.

  Here, the data conversion rule is input to the data conversion circuit 4030 as n field conversion parameters 4041 and 4042.

  The data conversion circuit 4030 identifies the field by the field identification signal 4013 and selects a parameter for each field.

  The first field conversion parameter 4041 defines the data conversion rule for the first field.

  The second field conversion parameter 4042 defines the data conversion rule for the second field.

  When one frame is divided into two or more fields by n-times impulse driving, it is preferable to prepare n-th field conversion parameters for each field.

  The data conversion rule considers the influence of the number of frame divisions n, the environmental temperature of the display device, the temperature of the liquid crystal display panel, the reference voltage setting amount, the length of one frame period, the length of each field period, etc. Appropriately determined so that a good display quality can be obtained without generating false contours or color shifts.

  The data conversion rule may be defined by an arithmetic expression using the various conditions as parameters, or by referring to a lookup table using the various conditions as an index.

  Further, the data conversion circuit 4030 adjusts the timing so that the n-times speed control signal group 4011 input from the n-times speed increasing circuit 4010 is synchronized with the field conversion data 4032 and outputs it as a field conversion data control signal group 4031.

  The timing generation circuit 4050 receives the field conversion data control signal group 4031 and the field conversion data 4032 output from the data conversion circuit 4030 as inputs. From the field conversion data control signal group 4031 and the field conversion data 4032, a data line driving circuit control signal group 4051 for controlling the data line driving circuit 4060, output display data 4052, a scanning line driving circuit 4070 And a scanning line driving circuit control signal group 4053 for controlling.

  The parameter holding circuit 4040 is a circuit that holds various setting parameters including field conversion parameters 4041 and 4042 used in the data conversion circuit 4030. Also, it has a function of reading the various setting parameters from an external storage circuit (not shown).

  The parameter holding circuit 4040 includes a storage element group such as a register file and various RAMs (Random Access Memory), and a control circuit for the storage circuit.

  A storage circuit (not shown) is a circuit used for storing the various setting parameters. For example, various non-volatile memories such as ROM (Read-Only Memory) and EEPROM (Electrically Erasable Programmable ROM) flash memory can be used.

  The data line driver circuit control signal group 4051 includes, for example, an output timing signal that defines the output timing of the gradation voltage based on the output display data 4052, an AC signal that determines the polarity of the source voltage, a clock signal that is synchronized with the display data, and the like. Configure.

  The scanning line drive circuit control signal group 4053 is composed of, for example, a shift signal that defines the scanning period of one line, a vertical start signal that defines the scanning start of the first line, and the like.

  Reference numeral 4090 denotes a reference voltage generation circuit, and 4091 denotes a reference voltage.

  The data line driver circuit 4060 generates a potential corresponding to the number of display gradations from the reference voltage 4091, selects a one-level potential corresponding to the output display data 4052, and applies it as a data voltage to the liquid crystal display panel 4080. . Reference numeral 4061 denotes a data voltage generated by the data line driving circuit.

  4070 is a scanning line driving circuit, and 4071 is a scanning line selection signal.

  The scanning line driver circuit 4070 generates a scanning line selection signal 4071 based on the scanning line driver circuit control signal group 4053 and outputs the scanning line selection signal 4071 to the scanning lines of the liquid crystal display panel 4080.

  Reference numeral 4080 is a liquid crystal display panel, and 4081 is a schematic diagram of one pixel of the liquid crystal display panel. One pixel 4081 of the liquid crystal display panel 4080 includes a TFT (Thin Film Transistor) including a source electrode, a gate electrode, and a drain electrode, a liquid crystal layer, and a counter electrode. A TFT switching operation is performed by applying a scanning signal to the gate electrode. When the TFT is open, the data voltage is written to the drain electrode connected to one of the liquid crystal layers via the source electrode, and to the drain electrode in the closed state. The written voltage is retained. The drain electrode voltage is Vd, and the counter electrode voltage is VCOM. The liquid crystal layer changes the polarization direction based on the potential difference between the drain electrode voltage Vd and the counter electrode voltage VCOM, and through the polarizing plates disposed above and below the liquid crystal layer, the amount of transmitted light from the backlight disposed on the back surface can be reduced. Change and perform gradation display.

  The configuration example of the display system for realizing the n-fold speed impulse drive has been described above with reference to FIG. However, in the case of the configuration of FIG. 4A, there is a problem that the n-times speed increasing circuit 4010 and the frame memory 4020 are required on the display device 4000 side, which increases the cost of the display device 4000.

  On the other hand, FIG.4 (b) is a figure which shows another structural example of the display system for implement | achieving n-times-speed impulse type drive.

  Compared with the configuration of FIG. 4A, the n-times speed increasing circuit 4510 and the frame memory 4520 that were on the display device 4500 side are arranged on the signal generator 4600 side, and the signal generator 4600 is transferred to the display device 4500 with n-times speed. The difference is that the digitized display data 4512 and the n-times speed control signal group 4511 are transmitted. The n-times speed display data 4512 is the same display data.

  Since the other points are the same as the configuration of FIG. 4A, description of each part is omitted.

  In general, a signal generator needs to perform complex signal processing such as various format conversions (image resolution conversion, interlace-progressive conversion) and image correction processing (edge enhancement, color correction), and so on. It is equipped with a high-performance signal processing circuit. Therefore, it can be said that the cost that is increased by mounting the n-times speed increasing circuit and the frame memory on the signal generation device side is smaller than the cost that is increased by mounting them on the display device side. That is, if the n-times speed increasing circuit and the frame memory are arranged on the signal generator side, the entire display system can be realized at a lower cost.

  However, in the case of the configuration of FIG. 4B, the display device 4500 side receives the n-fold speed-up display data 4512 and the n-fold speed control signal group 4511 instead of the input display data 4612 and the input control signal 4611. The device 4500 side cannot identify the frame break of the original input display data 4612. That is, the switching between the first field and the second field cannot be synchronized with the frame delimiter, and the data conversion result by the data conversion circuit 4530 is either in FIG. 3C or FIG. There is a problem that it cannot be arbitrarily controlled. That is, in one state, the first field is a bright field and the second field is a dark field as shown in FIG. 3C. In another state, as shown in FIG. In addition, a situation in which the first field becomes a dark field and the second field becomes a light field may occur at random, resulting in a situation in which control cannot be performed. In such a case, since the display characteristics are different between the case of FIG. 3C and the case of FIG. 3D, the displayed video is the state of the display system even though the input display data 4612 is the same. There arises a problem that it fluctuates randomly under the influence of (for example, power-on timing).

  Further, the input display data 4612 itself varies depending on the operation of the signal generator 4600 and the like. For example, there are fluctuations caused by switching of the reception channel and video source of the television receiver, and fluctuations due to irregular display such as fast forward reproduction and rewind reproduction in the video recording / reproducing apparatus. Each time such an operation is performed, the display characteristic of the display system is randomly switched to either FIG. 3C or FIG.

  From the viewpoint of display stability, it is preferable to configure the display system so that the display device can arbitrarily control the display characteristics. That is, it is necessary to identify a frame delimiter of input display data and to synchronize field switching.

  Heretofore, the two configuration examples of the display device and the display system equipped with the n-times speed impulse drive and the respective problems have been described.

  Next, a display device and a display system of the present invention for solving the above problems will be described with reference to FIGS.

  FIG. 5 is a diagram illustrating a configuration example of a display system and a display device 5000 to which an embodiment of the present invention is applied in order to realize the n-fold speed impulse drive while solving the above-described problem.

  4A is different from the configuration of FIG. 4A in that the n-times speed increasing circuit 5010 and the frame memory 5020 that are present on the display device side 5000 are disposed on the signal generator 5100 side. Further, the difference is that the n-fold speed-up display data 5012, the n-fold speed control signal group 5011, and the input control signal 5111 are transmitted from the signal generator 5100 to the display device 5000. In addition, a field identification signal for identifying frame switching of the input display data 5112 is not generated by the n-times speed-up circuit 5010 and input to the data conversion circuit 5030, but instead of the original input control signal 5111. A difference is that a field identification signal generation circuit 5200 for generating an identification signal 5013 is provided and a field identification signal 5013 is generated from the input control signal 5111.

  Since the other points are the same as the configuration of FIG. 4A, description of each part is omitted.

  4B differs from the configuration of FIG. 4B in that the input control signal 5111 of the original input display data 5112 is input from the signal generator 5100 to the display device 5000.

  As described above, from the viewpoint of display stability, the display device 5000 is preferably configured to be able to arbitrarily control the display characteristics in the n-times speed impulse drive. For this purpose, the frame delimiter of the input display data 5112 is identified. For this identification, it is simple and effective to use the input display signal 5111 of the input display data 5112. For example, an input vertical synchronization signal that is one of the input control signal groups 5111 is a signal that defines one frame period of the input display data 5112 and is therefore suitable for identifying frame switching of the input display data 5112. .

  If a field identification signal 5013 is generated by the field identification signal generation circuit 5200 based on the input vertical synchronization signal and used for field identification, it is possible to solve the problem that the display characteristics of the display system fluctuate randomly and to be stable. Display can be performed.

  Note that another signal of the input control signal group 5111 may be used instead of the input vertical synchronization signal.

  The configuration example of the display device and the display system to which the embodiment of the present invention is applied has been described above with reference to FIG.

  6 is a diagram illustrating an operation example of the display device and the display system to which the embodiment of the present invention is applied, and is an example of a timing chart of operations of the display device and the display system device illustrated in FIG.

  The horizontal axis in FIG. 6 indicates time.

  First, the input display data 5112 and the input control signal group 5111 are output from the signal generation circuit 5110.

  In the example of FIG. 6, the input vertical synchronization signal 601 that is one of the input control signal groups 5111 and the input display data 5112 are illustrated. The input vertical synchronization signal 601 is a signal defining one frame period, and an event is generated in synchronization with the switching of the frame of the input display data 5112.

  In FIG. 6, symbol D (i) indicates input display data of the i-th frame. Similarly, for example, D (i + 1) indicates input display data of the (i + 1) th frame.

  The input display data 5112 includes data for each frame in units of one frame period. . . D (i), D (i + 1), D (i + 2). . . Are input sequentially.

  Next, the n-times speed increasing process is performed by the n-times speed increasing circuit 5010.

  In the example of FIG. 6, the n-times vertical control signal 611 that is one of the n-times speed control signal group 5011 generated by the n-times speed increasing circuit 5010, the n-times speed display data 5012, and the field identification signal generation circuit 5200 are input. A field identification signal 5013 generated from the vertical synchronization signal 601 is shown. The n × speed vertical synchronization signal 611 is a signal that defines one field period of the n × speed display data 5012, and an event is generated in synchronization with the field switching of the n × speed display data 5012.

  As illustrated in FIG. 6, a delay due to the n-fold speed increase process may occur between the input vertical synchronization signal 601 and the input display data 5112, the n-fold speed vertical synchronization signal 611 and the n-fold speed display data 5012. It is common. After the event of the input vertical synchronization signal 601 occurs, the first field period starts from the time when the first event of the n-times vertical synchronization signal 611 occurs. This delay is caused, for example, by the n-multiplication circuit 5010 by the frame memory. This is caused by the difference between the timing for writing display data to the 5020 and the timing for reading. The n-multiplying circuit 5010 can read the display data for 1 / n frames from the frame memory 5020 following the timing when the display data for 1 / n frames is written to the frame memory 5020. Therefore, the n-multiplying circuit 5010 can start reading display data from the frame memory 5020 in a period shorter than one frame period after writing display data to the frame memory 5020.

  A field identification signal generation circuit 5200 generates a field identification signal 5013 from the input vertical synchronization signal 601. The field identification signal 5013 is used to determine the field. In this embodiment, an example in which one frame is divided into two fields of a first field and a second field is shown. Therefore, the field identification signal 613 includes, for example, a signal level (Low) indicating the first field, It can be constituted by a signal that toggles two values of the signal level (High) indicating the second field for each field period.

  The field identification signal 5013 when n = 2 is generated by the following procedure, for example.

  First, a field identification preparation signal 612 that inverts Low and High in synchronization with the n-times vertical synchronization signal 611 is provided. Further, the field identification preparation signal 612 is configured to be always set to High in synchronization with the input vertical synchronization signal 601. Subsequently, the field identification signal 5013 latches the field identification preparation signal 612 in synchronization with the n-times vertical synchronization signal 6111 so that it becomes Low in the first field and High in the second field as shown in FIG. It can be configured as follows.

  With such a configuration, the input control signal group 5111 and the input display data 5112 fluctuate due to some factor (for example, channel switching if the display system is a TV, fast forward / rewind operation if the video recording / reproducing device, etc.). Therefore, even if the field identification signal 5013 and the field identification preparation signal 612 are indefinite or abnormal values and the field identification cannot be normally performed, if the input of the input vertical synchronization signal 601 is accepted, Since the normal field identification operation can be started again from the field, the operation stability of the display device is improved.

  As described above, the method for generating the field identification signal 5013 in the field identification signal generation circuit 5200 has been described with reference to one configuration example using the input vertical synchronization signal 601, but the method for generating the field identification signal of the present invention is not limited thereto. It is not a thing.

  Subsequently, the data conversion circuit 5030 performs a data conversion process on the n-times speed display data 5012.

  The data conversion circuit 5030 receives the field identification signal 5013 output from the field identification signal generation circuit 5200 and the n-fold speed-up display data 5012 output from the n-fold speed-up circuit 5010 as inputs. The data conversion circuit 5030 identifies the first field and the second field based on the field identification signal 5013, and when the n-times speed display data is the first field (that is, the field identification signal 5013 is Low). Is converted) based on the first field conversion parameter 5041, and the n-fold speed-up display data is the second field (that is, the field identification signal 5013 is High). Performs data conversion based on the second field conversion parameter 5042.

  Here, since an example of n-times speed impulse drive in the case of n = 2 has been described, the field identification signal is a binary toggle signal, but when n is 3 or more, the field identification signal is Preferably, this is realized by a counter value for counting the number of fields.

  In FIG. 6, a field conversion vertical synchronization signal 621 which is one of the field conversion control signal groups 5031 generated by the data conversion circuit 5030 and field conversion data 5032 are shown. The field conversion vertical synchronization signal 621 is a signal that defines one field period of the field conversion data 5032.

  In FIG. 6, symbol Fl (i) indicates data obtained by performing bright field data conversion on the n-times speed display data of the i-th frame. Similarly, for example, Fl (i + 1) indicates data obtained by performing data conversion for the bright field on the n-fold speed-up display data of the (i + 1) th frame. On the other hand, in FIG. 6, symbol Fd (i) indicates data obtained by performing data conversion for dark field on the n-times speed display data of the i-th frame. Similarly, for example, Fd (i + 1) indicates data obtained by performing data conversion for the dark field on the n-fold speed-up display data of the (i + 1) th frame.

  Although FIG. 6 shows an example in which the first field is a bright field and the second field is a dark field, the first field is a dark field and the second field is a bright field. It is good.

  Finally, the timing generation circuit 5050 generates output display data 5052 (not shown in FIG. 6) from the field conversion data 5032.

  The timing generation circuit 5050 generates an output control signal 5051 group from the field conversion control signal group 5031 generated by the data conversion circuit 5030.

  As shown in FIG. 6, a delay due to data conversion processing generally occurs between the n-times vertical sync signal 611 and the n-times speed display data 5012, the field vertical sync signal 621, and the field conversion data 5032. Is.

  By configuring the display device as described above, it is possible to realize the n-times speed impulse drive as shown in FIG. 1 and to obtain a good image quality with reduced moving image blur in a moving image.

  Subsequently, a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 7 is a diagram illustrating a configuration example of a display system and a display device to which an embodiment of the present invention is applied in order to realize n-times impulse drive while solving the above-described problem.

  Compared with the configuration of FIG. 4A, a field repetition detection circuit 7210 is provided on the display device 7000 side instead of inputting the control signal 7111 of the original input display data 7112 from the signal generator 7100 to the display device 7000. The point is different. Another difference is that the n-times speed display data 7012 and the n-times speed control signal group 7011 are transmitted from the signal generator 7100 to the display device 7000. Since the other points are the same as the configuration of FIG. 4A, description of each part is omitted. In the configuration of FIG. 4B described above, it has already been described that the problem is that the switching of the frame of the original input display data 7112 cannot be identified. The configuration of FIG. 7 provides a means for solving this problem.

  In the example of FIG. 7, a field repeat detection circuit 7210 is provided in the display device 7000. The field repetition detection circuit 7210 receives the n-times speed display data 7012 and the n-times speed control signal group 7011 and detects the repetition of the field of the n-times speed display data 7012. If the same content field is repeated, it is originally input. The display data 7112 is identified as the same frame, and when there is no repetition of the same content field, it is identified that the frame has been switched, and the identification result is output as a field identification signal 7013.

  FIG. 8 is a diagram illustrating a configuration example of the field repetition detection circuit 7210.

  The field repetition detection circuit 7210 includes a field feature quantity extraction circuit 810, a field feature quantity divergence calculation circuit 830, a field repetition identification circuit 840, and a memory 820.

  The field feature amount extraction circuit 810 extracts a feature amount 811 indicating the feature of each field of the n-times speed display data 7012. The feature amount 811 is an index indicating the feature of the video data. For example, the average luminance level, the maximum luminance level, the minimum luminance level, the luminance distribution histogram, the frequency spectrum distribution, the data hash value, the cyclic redundancy code of the data, the video data Reduced images can be used. A vector obtained by combining a plurality of these may be used as the feature amount. The data amount of the feature amount is preferably smaller than the data amount of one field of the n-times speed display data.

  The memory 820 has a function of writing the feature quantity 811 of the current field extracted by the feature quantity extraction circuit 810 and reading the feature quantity 821 of the previous field. The memory 820 has a memory capacity sufficient to hold the feature amount for at least one field period. Here, as described above, since the data amount of the feature amount is smaller than the data amount for one field, the memory 820 can be realized with a smaller capacity than the frame memory, and the cost can be reduced.

  As the memory 820, for example, various DRAMs (Dynamic Random Access Memory) can be used.

  The field feature quantity divergence calculation circuit 830 is a circuit that compares and calculates the feature quantity 811 of the current field and the feature quantity 821 of the previous field, and calculates the divergence degree 831 of the two fields. For example, the difference value between the feature values of the two fields can be set as the divergence 831 between the two fields. Alternatively, when the feature quantity is a vector having a plurality of dimensions, for example, the cosine value of the angle formed by the feature quantity vector of the current field and the feature quantity vector of the previous field is set as the degree of divergence 831 between the two fields. Can do.

  The field repetition identification circuit 840 determines whether the two fields match, i.e., the same field is repeated, or the two fields do not match, i.e., the original frame, based on the degree of divergence 831 of the field feature quantity. Identifies whether has been switched. For example, when the degree of divergence 831 is smaller than a predetermined threshold, the two fields are identified as being repeated, or when the degree of divergence 831 is larger than the predetermined threshold, the original frame is identified as being switched. can do. Thereby, the field identification signal 7013 can be generated.

  Upon receiving this field identification signal 7013, the data conversion circuit 7030 shown in FIG. 7 can perform data conversion by selecting appropriate field parameters in a timely manner.

  Note that the operations of the display device and the display system shown in FIG. 7 are the same as those in the example of the timing chart shown in FIG. In FIG. 6, the field identification signal 7013 corresponds to the field identification signal 613.

  The configuration example of the display device to which the embodiment of the present invention is applied has been described above.

  By configuring the display device and the display system as described above, it is possible to realize an n-times speed impulse drive as shown in FIG. 1 and to obtain a good image quality with reduced moving image blur in a moving image.

  Next, an example in which the present technology is applied to a signal generation device including a frame rate conversion device will be described with reference to FIGS. 2, 5, 6, 9, and 10. The frame rate conversion device is a device that generates a video signal between frames using a motion vector or the like from a video signal between frames, as described in, for example, Japanese Patent Laid-Open No. 2003-333540. By applying the disclosed technique, motion judder can be reduced in the case of PAL-NTSC conversion as described in JP-A-2003-333540. Further, for example, by performing 60 Hz-120 Hz conversion, it is possible to improve the motion blur. When converting to 60Hz-120Hz, as shown in FIG. 9 (a), it is shown in FIG. 9 (b) from input display data consisting of 60Hz indicated by i-1, i, i + 1,. Generates 120 Hz double speed display data indicated by i-1, i-0.5, i, i + 0.5,. Hereinafter, in FIGS. 9 (a) and 9 (b), i-1, 1, i + 1, and display data in which the attached numerals are integers are referred to as real frame display data, i-0.5, i + 0.5, and so on. The display data indicated by a small number is called interpolation frame display data. In the actual frame display data, the same display data is assumed to be the same in the frames having the same attached numbers in (a) and (b).

  It can be assumed that the signal generator including the above frame rate converter is included in the n-times speed increasing circuit 5010 in FIG.

  In this case, the input display data and the double speed display data when generating the interpolated frame display data of the (i + 0.5) th frame using the real frame display data of the (i) th frame and the real frame display data of the (i + 1) th frame. As shown in FIG. 10, the actual frame video display start position is delayed by one frame period as shown in FIG. In this case, in the display system shown in FIG. 5, when the signal level of the field identification signal 5013 is Low, it can be said that the frame is interpolated frame display data.

  The data conversion circuit 5030 receives the field identification signal 5013 output from the field identification signal generation circuit 5200 and the double speed display data 5012 output from the double speed circuit 5010 as inputs. The data conversion circuit 5030 identifies the actual frame and the interpolation frame based on the field identification signal 5013, and the double-speed display data is actual frame display data (that is, the field identification signal 5013 is High). ) Is converted as much as possible in the bright field characteristic 203 in FIG. 2, and when the double speed display data is interpolation frame display data (that is, when the field identification signal 5013 is Low), Data conversion is performed as much as possible in the dark field characteristics 202 in FIG.

  As described above, in this embodiment, conversion is performed so that the actual frame display data becomes a bright frame and the interpolation frame display data becomes a dark frame. Since the interpolated frame display data is generated from the actual frame display data, the accuracy of the interpolated frame display data is reduced in principle compared to the actual frame display data equivalent to the input frame display data. On the other hand, as described in the first embodiment, the impulse-type driving method of the present invention observes the averaged luminance with respect to n frames (in this embodiment, n = 2). By making the low interpolation frame display data a dark field, even when accurate interpolation is not performed, image distortion accompanying it can be suppressed, and further, impulse conversion taking into account the direction of movement of the line of sight is made, It is possible to reduce the so-called pseudo contour which becomes a problem in the impulse response.

  The present invention can be used for a television display device.

It is a figure explaining the concept of the n times speed impulse type drive of the present invention. It is a figure which shows the example of matching with the gradation and display luminance in the n times speed impulse type drive of this invention. It is a graph which shows the example of the mode of a change of the display brightness at the time of implementing input display data in the n times speed impulse type drive of the present invention, and the above-mentioned input display data by n times speed impulse driving. It is a figure which shows the structural example of the display apparatus and display system provided with the n times speed impulse type drive of this invention. It is a figure which shows the structural example of the display apparatus and display system in 1st Example of this invention. It is a figure which shows the operation example of the display apparatus and display system in 1st Example of this invention. It is a figure which shows the structural example of the display apparatus and display system in 2nd Example of this invention. It is a figure which shows the structural example of the field repetition detection circuit of the display apparatus in the 2nd Example of this invention. It is a figure explaining the concept of the double speed impulse type drive in the 3rd Example of this invention. It is a figure which shows the operation example of the display apparatus and display system in 3rd Example of this invention.

Explanation of symbols

4112,4612,5112,7112… Input display data, 4111,4611,5111,7111,… Input control signal group, 4010,4510,5010,7010… N-times speed increasing circuit, 4011,4511,5011,7011… n-times speed control Signal group, 4012, 4512, 5012, 7012… n-speed display data, 4021, 4521, 5021, 7021… Write data, 4022, 4522, 5022, 7022… Read data, 4013, 5013, 7013… Field identification signal, 4030 , 4530,5030,7030… Data conversion circuit, 4032,4532,5032,7032… Field conversion data, 4041,4242,4541,4542,5041,5042,7041,7042… Field conversion parameters, 4050,4550,5050,7050 … Timing generation circuit, 4051,4551,5051,7051… Data line drive circuit control signal group, 4052,4552,5052,7052… Output display data, 4070,4570,5070,7070… Scan line drive circuit, 4080,4580, 5080,7080… Liquid crystal display panel, 4081, 4581, 508, 7081… Liquid crystal display panel pixels, 4060, 4560, 5060, 7060… Data line drive circuit, 4061, 4561, 5061, 7061 Data voltage, 4070, 4570, 5070, 7070… Scan line drive circuit, 4071, 4571, 5071, 7071… Scan line selection signal, 4090, 4590, 5090, 7090… Reference voltage generation circuit, 4091, 4591, 5091, 709, … Reference voltage, 4020, 4520, 5020, 7020… Frame memory, 4021, 4521, 5021, 7021… Write data, 4022, 4522, 5022, 7022… Read data, 4040, 4540, 5040, 7040… Setting parameter holding circuit, 4041,4042,4541,4542,5041,5042,7041,7042… Various setting parameters, 5200… Field identification signal generation circuit, 7210… Field repetition detection circuit, 810… Field feature extraction circuit, 811,821… Feature, 830… Field feature quantity divergence calculation circuit, 831 ... Deviation degree, 840 ... Field repetition identification circuit

Claims (1)

A display panel in which a plurality of pixels are arranged, a first drive circuit that outputs a display signal corresponding to display data to the pixel, and a selection signal for selecting a pixel that is to receive the display signal is output to the pixel A display device comprising: a second drive circuit that:
Wherein it comprises a first synchronization signal to enter the display device, a signal generator having a function of generating a first display data, and
The display device includes a first display data, receiving the first synchronization signal indicating a break for each frame of the first display data as input, the data conversion circuit in accordance with the predetermined data conversion rule The second display data is obtained by using the second display data obtained by data conversion of the first display data, and a second synchronization signal indicating a break for each frame of the second display data. Display
The data conversion circuit includes n (n is an integer of 2 or more) data conversion rules, and a selection circuit that selects one data conversion rule from the n data conversion rules.
The selection circuit sequentially switches and selects the n data conversion rules from the first data conversion rule to the nth data conversion rule;
The switching of the data conversion rule is performed in synchronization with the first display data using the first synchronization signal,
The selection circuit generates an identification signal generating an identification signal for identifying each of the n frames of the first display data in order to select one data conversion rule from the n data conversion rules. With
In the identification signal generation circuit, the first display data can be switched between frames when the same content as the previous frame is repeatedly input or when a frame having a different content from the previous frame is input. When the same frame is repeatedly input, the identification signal is sequentially updated in synchronization with the first synchronization signal, and when frame switching occurs, It has a function to reset the identification signal,
The signal generation device includes a signal generation circuit for generating third display data,
The first display data is display data obtained by multiplying the frame frequency of the third display data by n,
The signal generator includes an n-times speed increasing circuit for generating the first display data from the third display data,
The n-times speed increasing circuit converts the third display data into the first display data by outputting the third display data n times during one frame period of the third display data. ,
At least one data conversion rule among the n data conversion rules performs data conversion so as to display brightness brighter than the first display data.
At least one data conversion rule among the n data conversion rules performs data conversion so as to display a luminance lower than that of the first display data.
The luminance perceived by displaying the n second display data obtained by the n data conversion in a series is directly calculated from the third display data for one frame period of the third display data. A display system in which the n data conversion rules are adjusted in advance so as to correspond to luminance perceived by display.

Images