JP2004317928A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of reducing a moving blur of a moving picture with simple circuit constitution by adding an improving circuit for a movement blur of a moving picture which occurs when the moving picture is displayed. <P>SOLUTION: In the liquid crystal display device having a frequency converting circuit 11 which outputs input frames four times each at a four-fold speed, and a liquid crystal display element 15 which displays frames outputted 2N times each, a luminance control circuit 14 converts luminance levels of alternate converted frames to levels lower than the remaining alternate converted frames and supplies the frames to the liquid crystal display element 15 to reduce a movement blue of the moving picture which occurs when each original frame is switched. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to a liquid crystal display device that displays a moving image, and more particularly to a liquid crystal display device that suppresses motion blur of a displayed moving image.
[0002]
[Prior art]
As an image display device, an impulse-type display device that performs image display by a CRT or the like that continuously emits light only for the afterglow time of the phosphor, and an image display by a liquid crystal that maintains the display of the previous frame until new writing is performed are performed. And a hold type display device.
In recent years, the cost of the latter liquid crystal display device, which is a hold type display device, has been reduced, and the liquid crystal display device has been generally used as a display device such as a computer display or a home TV.
In addition, the resolution of liquid crystal projectors has been increasing, and ultra-high-definition liquid crystal projectors having a resolution several times higher than that of HD television have emerged.
Under such circumstances, there is a movement to realize a conventional film projection system with an ultra-high definition liquid crystal projector.
In this ultra-high-definition liquid crystal projector, 24P (progressive) input video data (signal) is converted into, for example, quadrupled 96P output video data, thereby driving the liquid crystal display element to reduce the flicker of the displayed video. Has been reduced.
[0003]
FIG. 7 shows a liquid crystal display device 70 of the first conventional example.
As shown in the figure, the liquid crystal display device 70 includes a frequency conversion circuit 71 and a liquid crystal display element 72.
The 24P input video data is input to the frequency conversion circuit 71, for example, is multiplied by 4, and is output as 96P output video data. The 96P output video data is supplied to the liquid crystal display element 72 to display a video.
The operation of the liquid crystal display device 70 will be described with reference to FIG.
In the liquid crystal display device 70 of the first conventional example shown in FIG. 7, the input video data is multiplied by, for example, 4 by the frequency conversion circuit 71, and the 24P input video data (A, B, C,. ) Is converted to 96P output video data (A0, A1, A2, A3, B0, B1,...) And supplied to the liquid crystal display element 72 for display.
Here, the 24P video data A is read four times with a clock multiplied by 4, and 96P video data A0, A1, A2, and A3 are displayed. A0, A1, A2, and A3 have the same contents, and the larger the number on the time axis, the slower the time.
[0004]
In FIG. 8, since the 24P input video (A, B, C) frame is written in a memory (not shown) and read in the next frame, the readout frame of the 96P output video quadrupled is one frame for the 24P input video. It is displayed with a delay of one minute.
In this case, the moving image displayed on the liquid crystal display device 70 includes the afterimage of the previous frame (A3) and the current frame (B0) at the switching of A to B of the 24P video (A, B, C) frame of the input video data. Interfere with each other, and the moving part of the displayed moving image is observed as blurred motion blur, which is evaluated as having poor display quality.
[0005]
As a liquid crystal display device for improving the motion blur of a moving image, there is, for example, a device described in Patent Document 1, which will be described below as a second conventional liquid crystal display device 100 with reference to FIGS.
A liquid crystal display device 100 of a second conventional example of the liquid crystal panel two-split display shown in FIG. 9 has a pixel array 101a, 101b, a gate line driving circuit 102, an image signal processing circuit 103, a data line constituting a two-split display liquid crystal panel. It is composed of drive circuits 104a and 104b and a clock generation circuit 105.
[0006]
The display portion of the liquid crystal panel is divided into two pixel arrays 101a and 101b at the center of the panel. The pixel array 101a has 240 gate lines Y1 to Y240 and 640 data lines X1 to X640 (not shown) forming a first data line group, as shown in the configuration diagram of the pixel array in FIG. Pixel cells are arranged in a matrix at these intersections.
On the other hand, the pixel array 101b has the remaining 240 gate lines Y241 to Y480 and 640 data lines X1 to X640 (not shown) forming a second data line group. Are located.
[0007]
Here, the first data line group writes data to the pixel cells in the pixel array 101a, and the second data line group writes data to the pixel cells in the pixel array 101b. It consists of two data lines.
The gate line driving circuit 102 selects a predetermined gate line out of the 480 gate lines Y1 to Y480, and simultaneously selects two gate lines out of the gate lines Y1 to Y480. .
The image signal processing circuit 103 is a circuit that converts image information supplied from the outside into a signal that can be displayed on a liquid crystal panel, and supplies the signal to the data line driving circuits 104a and 104b.
[0008]
The data line driving circuits 104a and 104b are provided for each of the pixel arrays 101a and 101b. One data line driving circuit 104a outputs a signal for setting each pixel cell connected to a selected gate line in the pixel array 101a to a predetermined state based on image display information input from the image signal processing circuit 103. Supply.
The other data line driving circuit 104b supplies a signal for setting each selected pixel cell in the pixel array 101b to a predetermined state.
[0009]
The clock generation circuit 105 controls the gate line driving circuit 102 and the data line driving circuits 104a and 104b by supplying the generated control signals to the circuits.
Specifically, a control signal for selecting one gate line for each of the pixel arrays 101a and 101b in order to display an image on the liquid crystal panel during one period of a period for displaying one image is transmitted. It is supplied to the drive circuit 102.
Then, control signals for simultaneously supplying an image signal for displaying an image to the first data line group and the second data line group are supplied to the data line driving circuits 104a and 104b, respectively.
[0010]
Further, in another period of the same one frame period, a control signal for reselecting the gate line once selected for each of the pixel arrays 101a and 101b is supplied to the gate line driving circuit 102.
Then, a control signal having a predetermined potential and simultaneously supplying a non-image signal different from an image signal to the first and second data line groups is supplied to the data line driving circuits 104a and 104b.
[0011]
In the above-described liquid crystal display device, in one frame period, in addition to writing to a pixel cell according to a normal image signal, writing is further performed according to a non-image signal. This non-image signal is a signal for displaying a blanking image.
The blanking image is an image in which the entire screen has the same gradation, and a black level voltage is written once during normal rewriting for each frame.
[0012]
FIG. 11 is a diagram showing a timing chart related to the gate line. The gate lines Y1 to Y480 have their timing slightly shifted, and are sequentially activated in one frame period to write an image signal to a pixel cell. One frame cycle is completed by raising all 480 gate lines and writing image signals to the pixel cells.
[0013]
At this time, the gate line Y is restarted with a delay of 1/2 frame period from the start for writing the image signal, and a potential for displaying black is supplied to each pixel cell via the data line X. As a result, each pixel cell enters a black display state.
That is, each gate line Y goes high twice in different periods in one frame cycle, and the pixel cells display image data for a certain period of time in the first selection, and the pixel cells are forcibly blackened in the second selection. By displaying, blanking is achieved.
In this manner, by performing image display and black display in one frame period, it is possible to reduce the motion blur between frame moving images that occurs uniquely in the liquid crystal display device.
[0014]
[Patent Document 1]
JP-A-11-109921 (Fig. 1-3)
[0015]
[Problems to be solved by the invention]
By combining the first conventional example, which is a high-definition liquid crystal display apparatus for displaying a film image, with the second conventional example, a liquid crystal display device capable of suppressing motion blur can be configured, but has the following problems.
In order to manufacture the liquid crystal display device 100 of the second conventional example, which can reduce and suppress the motion blur of a moving image and display with a two-segment liquid crystal panel, the liquid crystal panel is designed from a two-segment liquid crystal panel, and a liquid crystal panel is manufactured. It is necessary to incorporate a related circuit for improving image blur, which causes a problem that the configuration of the liquid crystal display device becomes very complicated and the cost is considerably increased.
[0016]
In view of the above, the present invention has been made in view of the above problem, and a motion blur correction circuit having a simple configuration is added to a liquid crystal display device later to provide a motion blur characteristic of a moving image peculiar to a hold type liquid crystal display device. It is an object of the present invention to provide a liquid crystal display device capable of suppressing and suppressing the reduction.
[0017]
[Means for Solving the Problems]
To solve the above problems,
The present invention
Each frame of the input video signal is converted at a quadruple rate and output four times, and an input synchronization signal which is input in synchronization with each frame of the video signal is converted in the same manner as described above. An output frequency conversion circuit 11,
A liquid crystal display device 15 that displays an image corresponding to the output moving image signal of each converted frame,
A luminance control circuit 14 that is supplied with the input synchronization signal and the converted output synchronization signal and outputs a luminance level coefficient indicating a luminance level corresponding to the moving image signal of each of the converted frames;
The moving image signal of each of the converted frames and the corresponding luminance level coefficient are supplied, and the moving image signal of each of the converted frames is converted into a luminance level corresponding to the luminance level coefficient and output to the liquid crystal display element. And an arithmetic circuit 13.
The liquid crystal display device is characterized in that the output luminance level coefficient is set to be smaller than that of the remaining converted frames for every other converted frame among the converted frames. .
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the liquid crystal display device of the present invention will be described below with reference to the drawings.
<Example>
FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a block diagram of a frequency conversion circuit applied to the liquid crystal display device of the present invention.
FIG. 3 is a block diagram of a brightness control circuit applied to the liquid crystal display device of the present invention.
FIG. 4 is a diagram showing a timing chart of input / output signals of the liquid crystal display device of this embodiment.
FIG. 5 is a diagram showing a timing chart of input / output signals of the frequency conversion circuit of the liquid crystal display device of the present embodiment.
FIG. 6 is a diagram showing a timing chart of the luminance control circuit of the liquid crystal display device of the present embodiment.
[0019]
First, the configuration of the liquid crystal display device will be described with reference to FIGS.
The liquid crystal display device 1 according to this embodiment shown in FIG. 1 includes a frequency conversion circuit (timing generator) 11, an arithmetic circuit 13, a brightness control circuit 14, a liquid crystal display element 15, and a CPU 16.
As shown in FIG. 2, the frequency conversion circuit 11 includes frame memories (dual-port type memories) 31 and 32, a PLL (Phase Lock Loop) circuit 33, and a synchronization signal generation circuit 34. The circuit 14 includes a coefficient table 51, a frame counter 52, and a selector 53, as shown in FIG.
[0020]
Next, the operation of the liquid crystal display device of this embodiment will be described.
The frequency conversion circuit 11 according to the present embodiment will be described.
The frequency conversion circuit 11 is supplied with an input synchronization signal (H-SYNC, V-SYNC) input from the outside and 24P (progressive) input video data, and synchronizes with the input synchronization signal to generate a synchronization signal described later. The write clock having a predetermined frequency generated by the generation circuit 34 is multiplied by 4 to generate and output a read clock.
The frequency conversion circuit 11 simultaneously multiplies the input synchronization signal by 4 using the read clock to generate and output output synchronization signals (horizontal synchronization signal (HD) and vertical synchronization signal (VD)) and also converts the input video data. In synchronization with the output synchronizing signal, output video data is generated and output at a rate four times that of the input video data.
[0021]
The input video data, the write clock, and the read clock from a PLL circuit 33 described later are supplied to frame memories (dual-port type memories) 31 and 32 shown in FIG. Thus, output video data having a conversion frame at a rate four times as high is generated.
[0022]
Of the input video data (for example, A, B, C,...), Input data A and C of odd frames are alternately written to the frame memory 31, and input data B of even frames are alternately written to the frame memory 32.
Then, since the image data is read four times at the next frame at a quadruple rate, the output video data (for example, A0, A1, A2, A3, B0, B1,...) Are input video data (A, B) as shown in FIG. , C,...) Are displayed with a delay of one frame.
[0023]
The PLL circuit 33 is supplied with a write clock of a predetermined frequency generated by the synchronization signal generation circuit 34 in synchronization with the input synchronization signal, and generates and outputs a read clock obtained by multiplying the write clock by four.
Further, the synchronizing signal generating circuit 34 is supplied with the input synchronizing signals (H-SYNC, V-SYNC) and the read clock, and outputs the output synchronizing signals (HD, VD) at a rate four times the input synchronizing signal. Generate
[0024]
The synchronization signal generation circuit 34 has a synchronization counter (not shown) that counts in synchronization with the supplied read clock, and as shown in the timing chart of FIG. 5, ends the synchronization part of the input synchronization signal (V-SYNC). Is detected, or when the count value reaches four converted frames of the output video data, the count value of a synchronous counter (not shown) is cleared.
[0025]
By doing so, when the write clock is quadrupled by the PLL circuit 33, the synchronizing signal generation circuit 34, as shown in FIG. 5, has a rate four times the input synchronizing signal (H-SYNC, V-SYNC). The output synchronization signals (HD, VD) are generated and output.
[0026]
Next, the brightness control circuit 14 of the present embodiment will be described.
The luminance control circuit 14 is supplied with an input synchronizing signal (V-SYNC), an output synchronizing signal (VD) converted by the frequency conversion circuit 11 at a rate four times the input synchronizing signal, and the read clock, and 13, four luminance level coefficient data (luminance level coefficients 100%, 50%, 100%, 50) for controlling the respective luminance levels of the four output video data output from the frequency conversion circuit 11 and indicating the luminance level values. % Coefficient data).
[0027]
The luminance level coefficient differs for each frame, and the luminance level coefficient of the moving image signal of every other frame is set to 100% as it is, and the luminance level coefficient of the moving image signal of the remaining frame is changed by the observer. The luminance level coefficient is set to, for example, 50% in order to reduce the visibility of the motion of the moving image of the frame with respect to the frame having the luminance level of 100% and reduce the motion blur.
[0028]
The coefficient table 51 shown in FIG. 3 stores luminance level coefficient data (luminance level coefficients 100%, 50%, 100%, and 50%) corresponding to four output frames quadrupled by the frequency conversion circuit 11, respectively. It is generated and stored based on a control signal supplied from the CPU 16.
[0029]
Further, the frame counter 52 is supplied with the read clock, the output synchronization signal (VD), and the input synchronization signal (V-SYNC) quadrupled by the PLL circuit 33 in the frequency conversion circuit 11, and supplies the input synchronization signal and The count values (0, 1, 2, 3) synchronized with the respective output synchronization signals (VD) converted at the quadruple rate are output to selectors 53 described later.
[0030]
The frame counter 52 is a synchronous counter that counts in synchronization with the read clock quadrupled by the PLL circuit 33.
As shown in the timing chart of FIG. 6, the frame counter 52 counts up the frame count value from 0 to 3 by the output synchronization signal (VD) after the frame rate conversion by the frequency conversion circuit 11, and The count value is reset to 0 by the input synchronization signal (V-SYNC) before the frame rate conversion. If a circuit format for directly counting the output synchronization signal (VD) is used, there is no need for a read clock.
[0031]
The selector 53 receives the four luminance level coefficients of the coefficient table 51 and supplies the four luminance level coefficients of the coefficient table 51 based on the count value (0 to 3) of the frame counter 52. The data (coefficients 1 to 4) correspond to the count value, the coefficient 1 corresponds to the count value 0, and the coefficient 1 (luminance level coefficient 100%) corresponds to the count value 1. 50%),... Each luminance level coefficient data is selected and output.
[0032]
The coefficient table 51 is constituted by a register (not shown) so as to store luminance level coefficient data for four output frames to be multiplied, and has a storage area for four equal to the multiplication factor. I have.
This register is readable and writable by a read / write control signal from an externally provided CPU 16, and is configured so that brightness level coefficient data can be written and set as necessary.
[0033]
Next, the arithmetic circuit 13 of this embodiment will be described.
The arithmetic circuit 13 includes output video data of each converted frame output from the frequency conversion circuit 11 and a luminance level coefficient (coefficient data) of each converted frame output from the luminance control circuit 14. ) Are supplied.
[0034]
In response to these two signals, the arithmetic circuit 13 converts the luminance level of the moving image signal of each of the converted frames into a frame having a different luminance level every other corresponding to the luminance level coefficient, and outputs the frame. I do.
Then, the moving image signal of each of the converted frames having the converted luminance level is supplied to the liquid crystal display element 15 and displayed as a corresponding moving image.
[0035]
Next, a description will be given of a mechanism for reducing the motion blur when the frame of the output video data is switched from the previous A3 frame to the next new B0 frame in the hold-type liquid crystal display device of the present embodiment.
First, when no control is performed on the luminance level value of the frame, as shown in FIG. 8, the moving image of both frames including the moving image of the previous A3 frame and the moving image of the next new B0 frame is switched. The observer visually recognizes the image at the same time, and the moving part of the moving image is visually recognized by the observer as a motion blur of the moving image due to the both visual recognitions.
[0036]
On the other hand, assuming that the luminance level of the moving image of the previous A3 frame shown in FIG. 4 is, for example, 50% and the luminance level of the next B0 frame is 100%, the next B0 switched to the moving image of the previous A3 frame. The observer visually recognizes both frames together with the moving image of the frame.
As a result, the luminance level of the previous A3 frame is set to 50%, which is low, so that the motion of the moving image of the previous A3 frame is difficult for the observer to visually recognize, and the moving image of the next B0 frame, whose luminance level is 100%, is high. The observer visually recognizes the movement of the image, and thus the movement of the moving image portion of the moving A3 frame becomes difficult to recognize, the movement of the moving image of the next B0 frame becomes difficult to recognize, and the overlapping of the movement becomes difficult to recognize. Motion blur of a moving image is reduced.
[0037]
On the other hand, the motion blur of the moving image is reduced in the same manner as before even when the relationship between the luminance levels is reversed and the moving image luminance level of the previous A3 frame is set to 100% and the next B0 frame is set to 50%. .
However, in this case, the observer visually recognizes both the moving image of the previous A3 frame and the next B0 frame that has been switched, but the luminance level of the moving image of the subsequent B0 frame is as low as 50%. The motion of the B0 frame is difficult for the observer to visually recognize, the observer more visually recognizes the motion of the moving image of the preceding A3 frame, and the motion of the moving image portion of the moving B0 frame has a low luminance level and is difficult to visually recognize. The observer visually recognizes the motion of the moving image of the previous A3 frame, the motion does not overlap, and the motion blur of the moving image is reduced.
[0038]
Therefore, the present embodiment suppresses flicker by outputting and displaying each frame of the input moving image signal four times at a quadruple rate, and makes the overlapping of the motion with the previous frame at the time of frame switching inconspicuous. This can improve the motion blur of the image.
[0039]
In the present embodiment, the brightness level of every other frame among the frames output and displayed four times is set in consideration of the reduction of motion blur and the light utilization rate. Is converted to a level of 50% lower than the luminance level of the remaining frames, but is not necessarily limited to this.
If the brightness level is lowered to a level of 25%, the light utilization rate will be reduced, but the motion blur will be more difficult to see at 25% level frames than at 50% level. , Is further suppressed. Of course, the response speed of the liquid crystal element is also involved.
The luminance level of the frame of the output video data A1 can be set irrespective of the frame of A3. However, when the luminance level of the frame of A1 is set to 50% and the luminance level of the frame of A3 is aligned, the flicker frequency becomes higher, and the flicker frequency becomes higher. This is advantageous in terms of reduction.
[0040]
As described above, in the liquid crystal display device of the present embodiment, a signal processing circuit (arithmetic circuit and luminance control circuit) having a simple frame rate is added later to the liquid crystal display device having no motion blur correction device for moving images. The addition can reduce the motion blur of the moving image without increasing the cost.
In addition, since the motion blur improvement circuit is processed in units of frames and can be performed irrespective of the configuration of the liquid crystal display device, the liquid crystal display device constituting the liquid crystal display device of this embodiment may be any type of liquid crystal panel. Applicable range can be widened.
[0041]
【The invention's effect】
As described above, according to the liquid crystal display device of the present invention, the brightness level of every other conversion frame among the conversion frames output and displayed is set to be higher than the brightness level of the remaining conversion frames by the brightness control circuit. Is converted to a low level and supplied to the liquid crystal display element, so that the motion blur of a moving image generated when each input frame is switched can be reduced with a simple circuit without increasing the cost.
[0042]
According to the liquid crystal display device of the present invention, a signal processing circuit (arithmetic circuit and luminance control circuit) of a simple frame rate is added to a liquid crystal display device without a motion blur correction device for a moving image. Motion blur can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a block configuration of an embodiment of a liquid crystal display device of the present invention.
FIG. 2 is a diagram showing a block configuration of a frequency conversion circuit of an embodiment of the liquid crystal display device of the present invention.
FIG. 3 is a diagram showing a block configuration of a brightness control circuit of the embodiment of the liquid crystal display device of the present invention.
FIG. 4 is a diagram showing a timing chart of input / output signals of the embodiment of the liquid crystal display device of the present invention.
FIG. 5 is a diagram showing a timing chart of input / output signals of the frequency conversion circuit of the embodiment of the liquid crystal display device of the present invention.
FIG. 6 is a diagram showing a timing chart of a brightness control circuit of the embodiment of the liquid crystal display device of the present invention.
FIG. 7 is a diagram showing a block configuration of a liquid crystal display device of a first conventional example.
FIG. 8 is an operation explanatory diagram of the liquid crystal display device of the first conventional example.
FIG. 9 is a diagram showing a block configuration of a liquid crystal display device of a second conventional example for displaying on a two-split liquid crystal panel.
FIG. 10 is a diagram showing a configuration of a pixel array of a liquid crystal display device of a second conventional example of the liquid crystal panel two-split display shown in FIG.
11 is a diagram showing a timing chart regarding gate lines of the liquid crystal display device of the second conventional example shown in FIG.
[Explanation of symbols]
1. Liquid crystal display device 11 of the present invention Frequency conversion circuit (timing generator)
13 arithmetic circuit 14 brightness control circuit 15 liquid crystal display element (liquid crystal display device)
31 Frame memory A (dual port type memory)
32 frame memory B (dual port type memory)
33 PLL circuit 34 Synchronous signal generation circuit 51 Coefficient table (register)
52 frame counter (synchronous counter)
53 Selector A, B, C 24P input video A0-A3, B0-B3, C0-C3 96P output video

Claims (1)

Each frame of the input video signal is converted at a quadruple rate and output four times, and an input synchronization signal which is input in synchronization with each frame of the video signal is converted in the same manner as described above. A frequency conversion circuit for outputting,
A liquid crystal display device having a liquid crystal display element that displays an image corresponding to the output moving image signal of each conversion frame,
A luminance control circuit that is supplied with the input synchronization signal and the converted output synchronization signal and outputs a luminance level coefficient indicating a luminance level corresponding to the moving image signal of each of the converted frames,
The moving image signal of each of the converted frames and the corresponding luminance level coefficient are supplied, and the moving image signal of each of the converted frames is converted into a luminance level corresponding to the luminance level coefficient and output to the liquid crystal display element. And an arithmetic circuit,
The liquid crystal display device according to claim 1, wherein the output luminance level coefficient is set to be smaller than every other converted frame among the converted frames and output.

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