JP5173021B2 - System and method for mitigating delay in a data detector feedback loop - Google Patents

Description

  The present invention relates to a system and method for transferring information, and more particularly to a system and method for reducing the effects of delay in data detection processing.

  Various products, such as hard disk drives, typically utilize read channel devices that provide the ability to obtain information from the media in one format and provide it to the recipient in a digital data format. Such read channel devices include an analog-to-digital converter with a data detector circuit implemented such that data dependencies can be used to process received information. For example, the information supplied from the data detector is used to identify the sampling point of the analog-to-digital converter. Referring to FIG. 1, an exemplary read channel device 100 is illustrated that utilizes previously detected information to control a sampling process associated with later received information. The read channel device 100 receives an analog input 103 that is processed using a continuous time filter 105. The filter output 107 is fed to an analog-to-digital converter 110 that converts the analog input 103 to a digital input 115 and is filtered using a digital finite impulse response filter 120. The filter output 122 is provided to a data detector 125 that processes the filter digital output 122 to provide a determination representing the data output 127. If the error rate is sufficiently low, the data output 127 reflects the data originally supplied to the storage medium from which the data input 103 was extracted.

  In addition, the filter digital output 122 is provided to a delay element 160 that operates to reflect the delay caused by delaying the digital filter output 122 and passing through the data detector. The output of the delay element 160 is substantially the filtered output of the analog to digital converter 110. An output 127 from the data detector 125 is supplied to the equivalent target filter 130. The output of the equivalent target filter 130 is substantially what the analog-to-digital converter 110 filter output would have been if there were no channel defects. The difference between what is to be received (ie, the output of the equivalent target filter 130) and what is received (ie, the output of the delay block 160) is sent out using the summation circuit 135. The output of the summing circuit 135 is an error signal 137. Further, the slope detection circuit 140 receives the output 127 and specifies the slope signal 142. The timing error detection circuit 145 combines the slope signal 142 and the error signal 137 to calculate a phase error adjustment value reflected by the timing error signal 147. The timing error signal 147 is filtered by the loop filter 150, and the filtered value is supplied to the phase mixer circuit 155. A phase mixer circuit 155 receives the output of the loop filter 150 and provides a signal that controls the sampling phase of the analog-to-digital converter 110.

  Although feedback of information from the data detector 125 to the analog-to-digital converter 110 provides more accurate data detection processing, a predetermined level of delay is caused by the feedback loop. As the density of storage applications continues to increase, the delay caused by the feedback loop can become very large, which can degrade the error rate performance of the read channel device. Further, feedback loop delay can be a gating factor for the development of high data density and / or low signal to noise ratio storage applications.

  Thus, for at least the reasons described above, there is a need in the art for advanced systems and methods for performing data detection processes.

  The present invention relates to a system and method for transferring information, and more particularly to a system and method for reducing the effects of delay in data detection processing.

  Various embodiments of the present invention provide a data acquisition system. The data acquisition system includes an analog-to-digital converter, a data detector, an error determination circuit, a first feedback loop, and a second feedback loop. The analog to digital converter operates to receive the analog signal and provide a first digital signal corresponding to the analog signal at a first sampling instant. The data detector performs a data detection process on the first digital signal and operates to provide a corrected data signal (corrected data signal), and the error determination circuit converts the corrected data signal to a derivative of the first digital signal. To identify the first error indication. The first feedback loop receives the first error indication and causes the analog to digital converter to provide a second digital signal corresponding to the analog signal at a second sampling instant. The second sampling instant is adjusted to reflect the first error indication. The second feedback loop receives the first error indication, adjusts the derivative of the first digital signal, and applies the second to the error determination circuit based at least in part on the adjusted derivative of the first digital signal. The error display of is specified.

  In one illustration of the above example, the second feedback loop includes a first digital signal for generating a derivative of the first digital signal to compensate for the first error indication during the temporary period. Includes an interpolator to interpolate. In some cases, the second feedback loop further includes a summation element and a delay element. Both the summation element and the delay element receive the first error indication, and the summation element operates to subtract the first error indication from the delayed version of the first error indication. In this case, the output of the summing element is used to control the amount of time interpolated by the interpolator. The delay added by the delay element corresponds to the time period required for the first error indication to be reflected in the first feedback loop. This period may be a temporary period. By using a delay, the derivative of the first digital signal corresponds to the second digital signal after a temporary period. Accordingly, the temporary correction signal is used for a period from when the first error indication is available until the second digital signal is available.

  In various examples of the above embodiments, the error determination circuit includes an equivalent target filter that equalizes the modified data signal. In this case, the error determination circuit includes a summing element that provides the difference between the derivative of the first digital signal and the equivalent corrected data signal. The first error indication corresponds to the difference. In other cases of the above embodiment, the error determination circuit includes an equivalent target filter that is equivalent to the modified data signal. The error determination circuit further includes a summation element and a slope detection circuit. The summing element provides a difference between the derivative of the first digital signal and the equivalent corrected data signal, and the slope detection circuit identifies the slope signal based at least in part on the corrected data signal. In yet another example of the above embodiment, the first error indication includes a phase error indication and a frequency error indication. In this example, the sum of the phase error display and the frequency error display is used as the first error display in the first feedback loop, and the phase error display is used as the first error display in the second feedback loop.

  Another embodiment of the present invention provides a method for reducing delay in an error corrected data acquisition system. The method includes performing an analog-to-digital conversion at a sampling instant to generate a digital sample and performing data detection on the digital sample to generate a detection output. The detected output is compared to digital samples to identify phase errors. During the temporary period, the digital samples are adjusted to produce adjusted digital samples reflecting the phase error. After a temporary period, the sampling instant is adjusted to reflect the phase error.

  This summary only provides an overview of some embodiments of the invention. Numerous other objects, configurations, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

  A further understanding of the various embodiments of the present invention may be realized by reference to the drawings described in the remainder of the specification. In the drawings, like reference numerals are used throughout several drawings to refer to similar components. In one example, a lowercase subscript is associated with a reference sign to indicate one of a plurality of similar members. Where reference is made to an existing subscript without reference to a reference sign, all such similar members shall be referred to.

FIG. 1 illustrates a prior art read channel device. FIG. 2 is a diagram illustrating a data acquisition device including error feedback delay reduction according to various embodiments of the present invention. FIG. 3 is a flowchart illustrating a method for delay reduction error correction according to an embodiment of the present invention. FIG. 4 is a diagram illustrating another data acquisition device including error feedback delay reduction according to various embodiments of the present invention. FIG. 5 is a diagram illustrating a storage system including a delay reduction data acquisition system according to various embodiments of the present invention. FIG. 6 is a diagram illustrating a communication system including a delay reduction data acquisition system according to one or more embodiments of the present invention.

  The present invention relates to a system and method for transferring information, and more particularly to a system and method for reducing the effects of delay in data detection processing.

  Various embodiments of the present invention provide for delay reduction in application of error correction feedback information in a data acquisition system. Delay reduction is achieved through the use of a temporary feedback loop that allows temporary integration of the error correction feedback loop but does not necessarily interfere with the outer error correction feedback loop. In some examples of the above embodiments, the data acquisition system is a read channel device designed to reconstruct information received from a storage medium or data transfer channel. Those skilled in the art will recognize, based on the disclosure provided herein, various data acquisition and other systems that can benefit from the incorporation of an error correction system that includes a temporary feedback loop in accordance with embodiments of the present invention. It should be.

  In one embodiment of the invention, a timing loop is used to detect data embedded in the incoming analog signal. The timing loop includes an analog-to-digital converter, a data detector, and an external error feedback loop. In addition, the timing loop includes a temporary feedback loop that allows error correction information to be used prior to when it would have been available after passing through the external error feedback path. The temporary feedback loop includes a signal interpolator that allows to predict the signal that will be available from the outer error feedback loop once the error correction information has been fully processed. When error correction is completely processed and considered in the outer error feedback loop, the temporary feedback loop invalidates any previous corrections based on the error. Such an embodiment of the present invention reduces the delay in capturing error correction information in future operations. Such a reduction in error correction delay allows an increase in loop stability and a corresponding reduction in bit error rate. In addition, by allowing error correction information to be processed through an outer feedback loop, sampling by an analog-to-digital converter that receives an analog input signal can be performed later without the delay caused by the outer feedback loop. Can be adjusted in time.

  Referring to FIG. 2, a data acquisition device 200 including error feedback delay reduction according to various embodiments of the present invention is shown. Data acquisition device 200 receives input 203. Input 203 may be any analog data signal that carries information to be converted from the analog domain to the digital domain. In one implementation of the present invention, input 203 is an analog representation of data that has been derived from and previously written to the magnetic storage medium. Alternatively, input 203 is an analog representation of data that was previously extracted over a channel, such as, for example, a wireless data transmission channel. Those skilled in the art will recognize a variety of input signals that can be processed using a data acquisition device according to embodiments of the present invention based on the disclosure provided herein. Input 203 is provided to continuous time filter 205 which provides filter output 207 to analog-to-digital converter 210. The continuous time filter 205 may be any continuous time filter known in the art, or may be replaced with some other filter that can prepare the input 203 for sampling by the analog to digital converter 210. . Those skilled in the art will recognize various filters that can be used to prepare the input 203 for sampling by the analog-to-digital converter 210 based on the disclosure provided herein. The analog-to-digital converter 210 may be any circuit that can convert an analog electrical signal into its digital representation. Thus, for example, analog-to-digital converter 210 may be, but is not limited to, a static range flash analog-to-digital converter or a dynamic range analog-to-digital converter, as is well known in the art. Those of ordinary skill in the art will recognize a variety of analog-to-digital converters that can be used in connection with different embodiments of the present invention based on the disclosure provided herein.

  The analog to digital converter 210 converts the filter output 207 into a digital input 215. Digital input 215 is filtered by a digital finite impulse response (DFIR) filter 220 as is well known in the art. Digital finite impulse response filter 220 provides filtered digital output 222 to data detector 225. Data detector 225 may be any detector known in the art that is capable of receiving a potentially corrupted data stream and correcting one or more errors in the data stream. Thus, the data detector 225 is, but is not limited to, a Viterbi data detector that can provide both soft and hard outputs, and a maximum recursive data detector that can provide both soft and hard outputs. be able to. Those skilled in the art will recognize a variety of data detectors that may be used in connection with embodiments of the present invention based on the disclosure provided herein. The data detector 225 operates to detect and correct errors in the filter digital output 222 when compared to the original data from which the input 203 is derived. The data detector 225 ultimately provides an output 227 representing the original data from which the input 203 is derived. In other aspects, the data output 227 represents what should have been received from the analog-to-digital converter 210 if the data detector 225 resolves any errors in the filter digital input 225. This is in contrast to the filtered digital output 222 that represents what is actually received from the analog to digital converter 210.

The output 227 is used to adjust the timing of various sampling and detection processes performed by the data acquisition device 200. Specifically, the output 227 is supplied to an equivalent target filter 230 that supplies the reconstructed output 232 to the summation circuit 235. The reconstructed output 232 is the output 227 after removal of intersymbol interference. In other aspects, the output 232 is substantially what was expected from the data detector 225 (ie, the reconstructed data samples) except for any signal corruption that is not resolved by the data detector 225. The signal collapse is due to electronic noise, a defective medium from which the input 203 is extracted, or the like. Equivalent target filter 230 may be any equivalent filter known in the art, and those skilled in the art will be able to use various equivalent filters that may be used in connection with embodiments of the present invention based on the disclosure provided herein. Should be recognized. In addition, output 227 is provided to a slope detection circuit 240 that identifies a slope signal 242 associated with a given output 227 as is well known in the art. The slope signal 242 indicates where the given output 227 is in the sine wave from which the given output 227 was derived. The slope signal 242 is maximum at the zero crossing of the sine signal and is minimum at the maximum and minimum of the sine signal. The slope signal 242 is used to indicate how much reliability the error signal 237 can be given. The filter digital output 222 is also applied to a delay element 245 that applies (delay by the data detector 225) + (delay by the equivalent target filter 230) − (delay reflecting the delay by the signal interpolator 250) expressed by the following equation: Supplied.
Delay ₂₄₅ = delay ₂₂₅ + delay ₂₃₀ -delay ₂₅₀
In this aspect, an interpolated version of filter digital output 222 (ie, interpolated output 252) is aligned in time with corresponding output 227 after passing through equivalent target filter 230.

  The output of the delay element 245 represents that received from the analog-to-digital converter 210, and the interpolated output 252 provided by the signal interpolator 250 is received from the analog-to-digital converter 210 that is phase shifted based on the output 227. Represents a thing. The output from the signal interpolator 250 is supplied to the summing element 235, which produces the difference between it and the output of the equivalent target filter 250. The error signal 237 and the slope signal 242 are supplied to a timing error detector circuit 270 that combines the error signal 237 and the slope signal 242 to calculate the phase error adjustment reflected in the timing error signal 277. The timing error signal 277 is filtered by the loop filter 275, and the filtered value is supplied to the phase mixer circuit 285. A phase mixer circuit 285 receives the output of the loop filter 275 and provides a feedback signal 287 that controls the sampling phase (ie, ADC sampling instant) of the analog-to-digital converter 210. In this aspect, the data acquisition device 200 can adjust the sampling phase of the analog-to-digital converter 210 based directly on the timing error signal 277.

  In order to reduce the delay involved in correcting the output 227 based on the timing error signal 277 via the above-described feedback loop that returns information to the analog to digital converter 210, a temporary feedback loop 290 (shown in dashed lines) is provided. To be implemented. Temporary feedback loop 290 is capable of ensuring that phase corrected information is prepared and captured in timing error signal 277 faster than existing approaches where connection information is not available until the sampling phase of analog to digital converter 210 is captured. give. In operation, temporary feedback loop 290 receives timing error signal 277 at summing element 260. The output from the summing element 260 is supplied to the coefficient calculation circuit 255. The coefficient calculation circuit 255 supplies the coefficient set 257 to the signal interpolator 250. Coefficient set 257 is used by signal interpolator 250 to phase shift filter digital input 222 by an amount corresponding to timing error signal 277. In this aspect, error signal 237 can be adjusted faster based on previously generated timing error signal 277. In one embodiment of the invention, signal interpolator 250 is a digital finite impulse response (DFIR) filter and coefficient set 257 is a set of taps that drive the digital filter. In one example, the calculation of coefficient set 257 is performed by a look-up table using a derivative of the output of summation element 260 that addresses the look-up table. In another example, coefficient calculation circuit 255 directly calculates coefficient set 257 based on the output of summing element 260. In some cases, the temporary feedback loop 290 is considered a master loop (ie, a loop returning from the signal interpolator 250 through the timing error detection circuit 270 to the signal interpolator 250) and the outer error correction feedback loop is a slave loop (ie, a loop). , A loop returning from the analog-digital converter 210 via the data detector 255 to the analog-digital converter 210 via the timing error detection circuit 270).

Eventually, the corrected error through the temporary feedback loop 290 is reflected in the output of the analog to digital converter 210. Thus, the timing error signal 277 is delayed through the delay element 265 and the output of the delay element 265 is subtracted by the summing element 260 from the undelayed timing error signal. The delay added by delay element 265 is a timing error signal 277 to be translated for use by analog to digital converter 210 and an analog to digital signal to be translated into filter digital signal 222 as shown in the following equation: Reflect the time required for the output of converter 210 delay ₂₆₅ = delay ₂₃₅ + delay ₂₁₀ + delay ₂₂₀ + delay ₂₄₅
In this aspect, the error correction introduced via the temporary feedback loop 290 is invalidated when that same error correction is finally propagated through the phase mixer circuit 285, the analog to digital converter 210, and the DFIR 220. . By invalidating the error signal when the error signal is finally fed back through the slave loop, the error indicated by the timing error signal 277 is not counted twice.

  Those skilled in the art will recognize, based on the disclosure provided herein, various advantageous effects obtained through implementation of a data acquisition system incorporating a temporary feedback loop according to different embodiments of the present invention. is there. For example, loop stability is increased by reducing the feedback delay provided by the temporary feedback loop, while maintaining the slave loop ensures that the sampling instant of the analog-to-digital converter 210 is optimized. .

  Referring to FIG. 3, a flow diagram 300 illustrates a method for error correction with reduced delay according to an embodiment of the present invention. Following the slow diagram 300, analog-to-digital conversion is performed on the received analog signal (block 305). This process results in a digital output corresponding to the analog-to-digital signal at a given sampling instant. The digital output is provided to a data detector where data detection processing is performed (block 310). The output of the data detector represents the output of the analog-to-digital converter after errors resulting from the corrupted input signal have been reduced or eliminated. It is also determined whether the phase error identified in processing the previous bit is already reflected in the sampling instant that drives the analog-to-digital conversion process (block 315). If the phase error has already been captured at the sampling instant, the digital data extracted from the analog-to-digital conversion process is compared with the data extracted from the data detection process (block 325). On the other hand, if the phase error has not yet been captured in the sampling instant, the digital data derived from the analog-to-digital conversion process is interpolated (block 320). In order to reflect the previously specified phase error, the digital data output from the analog-to-digital conversion process is updated by interpolation. If the phase error has not yet been captured in the sampling instant, the interpolated digital data derived from the analog-to-digital conversion process is compared with the data derived from the data detection process (block 325). In either case, the comparison (block 325) is used to calculate the phase error (block 330), which is used to adjust the sampling instant associated with the analog-to-digital conversion process (block 335). The currently calculated phase error is used only for a temporary period in the interpolation process (blocks 315-320) until the currently calculated phase error is captured in the analog-to-digital conversion process (block 305).

  Referring to FIG. 4, a data acquisition device 400 including error feedback delay reduction according to another embodiment of the present invention is shown. The data acquisition device 400 is the same as the data acquisition device 200 except that the construction of the error signal supplied in the external feedback path is different from that in the temporary feedback path. The data acquisition device 400 receives an input 403, which is any analog data signal that carries information to be converted from the analog signal domain to the digital signal domain. In one embodiment of the present invention, input 403 is an analog representation of data that has been drawn from the magnetic storage medium and previously written to the magnetic storage medium. Alternatively, input 403 is an analog representation of data that was previously extracted over a channel, such as a wireless data transmission channel, for example. Those skilled in the art will recognize a variety of input signals that can be processed using a data acquisition device according to embodiments of the present invention based on the disclosure provided herein. Input 403 is provided to a continuous time filter 405 that provides a filter output 407 to an analog-to-digital converter 410. The continuous time filter 405 may be any continuous time filter known in the art, or may be replaced by any other filter that can prepare the input 403 for sampling by the analog to digital converter 410. Those skilled in the art will recognize various filters that can be used to prepare the input 403 for sampling by the analog to digital converter 410 based on the disclosure provided herein. The analog-to-digital converter 410 may be any circuit that can convert an analog electrical signal into its digital representation. Thus, for example, analog-to-digital converter 410 may be, but is not limited to, a static range flash analog-to-digital converter or a dynamic range analog-to-digital converter well known in the art. Those of ordinary skill in the art will recognize a variety of analog-to-digital converters that can be used in connection with different embodiments of the present invention based on the disclosure provided herein.

  The analog to digital converter 410 converts the filter output 407 into a digital input 415. Digital input 415 is filtered by a digital finite impulse response (DFIR) filter 420 as is well known in the art. Digital finite impulse response filter 420 provides filtered digital output 422 to data detector 425. Data detector 425 may be any known detector capable of receiving a potentially corrupted data stream and correcting one or more errors in the data stream. Thus, the data detector 425 is, but is not limited to, a Viterbi data detector that can provide both soft and hard outputs, and a maximum recursive data detector that can provide both soft and hard outputs. be able to. Those skilled in the art will recognize a variety of data detectors that may be used in connection with embodiments of the present invention based on the disclosure provided herein. Data detector 425 operates to detect and correct errors in filter digital output 422 when compared to the original data from which input 403 is derived. The data detector 425 ultimately provides an output 427 representing the original data from which the input 403 is derived. In another aspect, if the data detector 425 resolves any errors in the filter digital input 425, the data output 427 represents what should have been received from the analog to digital converter 410. This is in contrast to the filtered digital output 422 representing what is actually received from the analog to digital converter 410.

Output 427 is used to adjust the timing of various sampling and detection processes performed by data acquisition device 400. Specifically, the output 427 is supplied to an equivalent target filter 430 that supplies the reconstructed output 432 to the summation circuit 435. The reconstructed output 432 is the output 427 after inter-symbol interference is removed. In other aspects, the output 432 is substantially what was expected from the data detector 425 (ie, reconstructed data samples), except for any signal corruption that is not resolved by the data detector 425. Signal decay is electronic noise, defective media from which the input 403 is drawn, and the like. The equivalent target filter 430 may be any equivalent filter known in the art, and those skilled in the art will be able to use various equivalent filters that can be used in connection with embodiments of the present invention based on the disclosure provided herein. Should be recognized. Further, output 427 is provided to a slope detection circuit 440 that identifies a slope signal 442 associated with a given output 427 as is well known in the art. The slope signal 442 indicates where the given output 427 is in the sine wave from which the given output 427 was derived. The slope signal 442 is maximum at the zero crossing of the sine signal and is minimum at the maximum and minimum of the sine signal. Slope signal 442 is used to indicate how much reliability can be given to error signal 437. The filter digital output 422 is also applied to a delay element 445 that applies a delay that reflects (delay by the data detector 225) + (delay by the equivalent target filter 430) − (delay by the signal interpolator 450) as shown by the following equation: Supplied.
Delay ₄₄₅ = delay ₄₂₅ + delay ₄₃₀ -delay ₄₅₀
In this aspect, an interpolated version of filter digital output 422 (ie, interpolated output 452) is aligned in time with corresponding output 427 after passing through equivalent target filter 430.

  The output of the delay element 445 represents that received from the analog-to-digital converter 410, and the interpolated output 452 provided by the signal interpolator 450 is received from the analog-to-digital converter 410 that is phase shifted based on the output 427. Represents a thing. The output from the signal interpolator 450 is supplied to a summing element 435, which produces the difference between it and the output of the equivalent target filter 450. The error signal 437 and the slope signal 442 are supplied to a timing error detector circuit 470 that combines the error signal 437 and the slope signal 442 to calculate a phase error adjustment value reflected in the timing error signal 477. The timing error signal 477 is supplied to the phase correction circuit 480 and the frequency correction circuit 485. The phase error output 482 from the phase correction circuit 480 is added to the frequency error output 487 from the frequency correction circuit 485 using the summation circuit 489. The sum 457 of the frequency error output 487 and the phase error output 482 is supplied to the phase mixer circuit 495. The phase mixer circuit 495 receives the sum 457 and provides a feedback signal 459 that controls the sampling phase (ie, ADC sampling instant) of the analog-to-digital converter 410. In this aspect, the data acquisition device 400 can adjust the sampling phase of the analog-to-digital converter 410 based directly on the timing error signal 477 to minimize energy during the error period.

  A temporary feedback loop 490 (shown in dashed lines) is implemented to reduce the delay involved in correcting the output 427 based on the timing error signal through the feedback loop above returning information to the analog-to-digital converter 410. Is done. Temporary feedback loop 490 ensures that phase corrected information is prepared and captured in timing error signal 477 faster than existing approaches where correction information is not available until it is captured in the sampling phase of analog to digital converter 410. Give ability. In operation, temporary feedback loop 490 receives timing error signal 477 at summing element 460 via phase correction circuit 480. An output from the summation element 460 is supplied to a coefficient calculation circuit 455. The coefficient calculation circuit 455 supplies the coefficient set 458 to the signal interpolator 450. Coefficient set 458 is used by signal interpolator 450 to phase shift filter digital input 422 by an amount corresponding to phase error output 482 derived from timing error signal 477. In this aspect, error signal 437 is quickly adjusted based on previously generated timing error signal 477. In one embodiment of the invention, signal interpolator 450 is a digital finite impulse response (DFIR) filter and coefficient set 458 is a set of taps that drive the digital filter. In one example, the calculation of coefficient set 458 is performed by a lookup table using a derivative of the output of summation element 460 that addresses the lookup table. In another example, coefficient calculation circuit 455 directly calculates coefficient set 458 based on the output of summation element 460. In some cases, the temporary feedback loop 490 is considered a master loop (ie, a loop returning from the signal interpolator 450 via the timing error detection circuit 470 to the signal interpolator 450) and the outer error correction feedback loop is a slave loop (ie. , A loop returning from the analog-digital converter 410 via the data detector 425 to the analog-digital converter 410 via the timing error detection circuit 470).

Eventually, the error corrected through the temporary feedback loop 490 is reflected in the output of the analog to digital converter 410. Accordingly, timing error signal 477 is delayed through delay element 465 and the output of delay element 465 is subtracted by summing element 460 from the undelayed timing error signal. The delay added by delay element 465 is a timing error signal 477 to be translated for use by analog to digital converter 410 and an analog to digital signal to be translated into filter digital signal 422, as shown in the following equation: Reflect the time required for the output of converter 410 delay ₄₆₅ = delay ₄₈₉ + delay ₄₉₅ + delay ₄₁₀ + delay ₄₃₀
In this aspect, the error correction introduced via the temporary feedback loop 490 is invalidated when that same error correction is finally propagated through the phase mixer circuit 495, the analog to digital converter 410, and the DFIR 420. . By invalidating the error signal when the error signal is finally fed back through the slave loop, the error indicated by the timing error signal 477 is not counted twice.

  The error signal 477 includes information regarding various imperfections in the phase shift filtered digital input 422, including false equivalent levels, phase errors and frequency errors. The timing error detection circuit 470 uses the slope signal 442 and the error signal 437 to estimate both phase and frequency error periods included in the timing error signal 477. The phase mixer circuit 495 uses both components to ensure that the analog-to-digital converter 410 is producing optimally sampled digital data. There is a performance advantage that results when the frequency portion of the error signal 477 is not utilized in the master loop due to the different delays of the slave loop compared to the master loop. Thus, in some embodiments of the present invention, there is no steady state phase error at the input of the data detector 425 because no steady state interpolation phase is used in the interpolator. As an example, if the incoming sample has a 1% (1%) frequency offset, the delay difference between the master and slave loops is 40 samples, and the frequency estimate is fed to the master loop, the current Subtraction of the past timing estimate 40T (ie, 40 sample periods) from the timing estimate is performed due to the sum of sum elements 460. This leads to 40 × 1%, ie 40 percent, phase in a single interpolator 450. Since the digital phase lock loop circuit drives the error period energy to be zero, the phase error in the signal interpolator 450 is approximately zero. This means that the phase error at the input of the signal interpolator 450 (and thus at the input of the data detector 425) is 40 percent, which is detrimental to the performance of the data detector 425.

  Those skilled in the art will recognize, based on the disclosure provided herein, various advantageous effects obtained through implementation of a data acquisition system incorporating a temporary feedback loop according to different embodiments of the present invention. is there. For example, maintaining the slave loop ensures that the sampling instant of the analog-to-digital converter 410 is optimized, while loop stability is increased by reducing the feedback delay provided by the temporary feedback loop.

  Referring to FIG. 5, a storage system 500 including a delay reduction data acquisition system according to various embodiments of the present invention is illustrated. For example, the storage system 500 is a hard disk drive. The storage system 500 includes a read channel 510 having a built-in delay reduction data acquisition system. The built-in delay reduction data acquisition system is not limited, but may be any of those described in relation to FIG. 2 and FIG. The storage system 500 includes an interface controller 520, a preamplifier 570, a hard disk controller 566, a motor controller 568, a spindle motor 572, a disk platter 578, and a read / write head 576. Interface controller 520 controls the addressing and timing of data to / from disk platter 578. The data on the disk platter 578 consists of a group of magnetic signals detected by the read / write head assembly 576 when the read / write head assembly 576 is properly positioned on the disk platter 578. In a normal read operation, the read / write head assembly 576 is accurately positioned by the motor controller 568 on the desired data track of the disk platter 578. The motor controller 568 positions the read / write head assembly 576 relative to the disk platter 578 and moves the read / write head assembly 576 to the appropriate data track of the disk platter 578 under the guidance of the hard disk controller 466. 572 is driven. The spindle motor 572 rotates the disk platter 578 at a predetermined rotational speed (RPM).

  Read / write head assembly 578 is positioned adjacent to the appropriate data track, and magnetic signals representing data on disk platter 578 are read by read / write head assembly 576 as disk platter 578 is rotated by spindle motor 572. Detected. The detected magnetic signal is supplied as a continuous instantaneous analog signal representing magnetic data on the disk platter 578. This instantaneous analog signal is transferred from read / write head assembly 576 to read channel module 564 via preamplifier 570. Preamplifier 570 is operable to adjust the instantaneous analog signal accessed from disk platter 578. Further, the preamplifier 570 can operate to adjust data from the read channel module 510 that is defined to be written to the disk platter 578. This time, the read channel module 510 decodes and digitizes the received analog signal to regenerate the information originally written to the disk platter 578. This data is supplied to the receiving circuit as read data 503. The write operation is substantially the reverse of the previous read operation, and write data 501 is provided to the read channel module 510. This data is encoded and written to the disk platter 578.

  FIG. 6 is a diagram illustrating a communication system 600 including a receiver 620 having a delay reduction data acquisition system in accordance with one or more embodiments of the present invention. Communication system 600 includes a transmitter that operates to transmit encoded information via transfer media 630 as is well known in the art. The encoded data is received from transfer medium 630 by receiver 620. The receiver 620 incorporates a delay reduction data acquisition system. The captured delay reduction data acquisition system is not limited, but may be any of those described with reference to FIGS.

  In conclusion, the present invention provides novel systems, devices, methods and configurations for analog-to-digital conversion. While detailed descriptions of one or more embodiments of the invention have been given above, various changes, modifications and equivalents will become apparent to those skilled in the art without departing from the spirit of the invention. Accordingly, the above description should not be taken as limiting the scope of the invention, which is defined by the following claims.

Claims (20)

A data acquisition system, the circuit of which is
An analog-to-digital converter operable to receive an analog signal and provide a first digital signal corresponding to the analog signal at a first sampling instant;
A data detector operable to perform a data detection process on the first digital signal and to provide a modified data signal (modified data signal);
An error determination circuit operable to compare the modified data signal with a derivative of the first digital signal to identify a first error indication;
A first feedback loop that receives the first error indication and causes the analog-to-digital converter to supply a second digital signal corresponding to the analog signal at a second sampling instant, the second sampling loop; A first feedback loop that is adjusted to reflect the first error indication; and a second feedback loop that receives the first error indication and adjusts a derivative of the first digital signal A system comprising a second feedback loop that causes the error determination circuit to identify a second error indication based at least in part on a derivative of the adjusted first digital signal.   The system of claim 1, wherein the second feedback loop includes an interpolator that operates to interpolate the first digital signal in time to compensate for the first error indication during a temporary period; The system, wherein the interpolator provides a derivative of the first digital signal.   3. The system of claim 2, wherein the second feedback loop further includes a summation element and a delay element, both the summation element and the delay element receiving the first error indication, wherein the summation element is the first summation element. A system that operates to subtract the first error indication from a delayed version of the error indication.   4. The system of claim 3, wherein the summing element output is used to control the amount of time interpolated by the interpolator.   4. The system of claim 3, wherein the delay added by the delay element corresponds to a time period required for the first error indication to be reflected in the first feedback loop.   The system of claim 2, wherein a derivative of the first digital signal corresponds to the second digital signal after the temporary period.   4. The system of claim 3, wherein the temporary period reflects a period from when the first error indication is available until the second digital signal is available.   2. The system of claim 1, wherein the error determination circuit includes an equivalent target filter that equalizes the corrected data signal, the error determination circuit being a difference between the derivative of the first digital signal and the equivalent corrected data signal. The first error indication corresponds to the difference.   2. The system of claim 1, wherein the error determination circuit includes an equivalent target filter that is equivalent to the modified data signal, the error determination circuit being a difference between a derivative of the first digital signal and the equivalent corrected data signal. The error determination circuit includes a slope detection circuit that identifies a slope signal based at least in part on the modified data signal, the error determination circuit based on the difference and the slope signal at least in part. A system including a timing error detection circuit that generates a first error indication.   2. The system of claim 1, wherein the first error indication includes a phase error indication and a frequency error indication, and the sum of the phase error indication and the frequency error indication is the first error indication in the first feedback loop. And the phase error indication is used as the first error indication in the second feedback loop. A method for reducing delay performed in the data acquisition system of claim 1 , comprising:
Performing an analog-to-digital conversion at the first sampling instant to generate the first digital signal ;
Performing a data detection on the first digital signal to produce the modified data signal,
Comparing the modified data signal with the first digital signal to identify a phase error;
Adjusting the first digital signal to generate an adjusted digital signal reflecting the phase error during a temporary period; and after the temporary period, adjusting the first digital signal to reflect the phase error . Adjusting the sampling instant of the method. 12. The method of claim 11, further comprising:
A method comprising receiving an analog input signal, the analog input signal comprising a data stream contained therein. 12. The method of claim 11, wherein comparing the modified data signal with the first digital signal comprises comparing the modified data signal with the adjusted digital signal during the temporary period; and the modified data signal comprises comparing directly with said first digital signal, the method later. The method of claim 11, wherein the analog - digital conversion first analog - a digital conversion before Symbol step of adjusting the first digital signal, and supplies the second sampling instant, said data detection The first data detection, the correction data signal is a first correction data signal , the phase error is a first phase error, the temporary period is a first temporary period, and the adjustment The digital signal is a first adjusted digital signal , and the method further comprises:
Second analog at the second sampling instant to generate the second digital signal - performing a digital conversion,
Performing a second data detection on the second digital signal to generate a second correction data signals,
Comparing the second modified data signal with the second digital signal to identify a second phase error;
During the second transient period, the second step of adjusting the second digital signal to produce a second adjustment digital signal reflecting the phase error, and after the second transient period Adjusting the second sampling instant to reflect the second phase error.   15. The method of claim 14, wherein the first temporary period precedes the second temporary period and a non-zero period is inserted between the first temporary period and the second temporary period. The way it is. 15. The method of claim 14, wherein comparing the second modified data signal with the second digital signal comprises converting the second modified data signal to the second adjusted digital during the second temporary period. step of comparing signals, and the step of comparing the correction data signal of the second direct adjustment digital signal of the second after a temporary period of the second method. A data processing system,
A data receiving device for extracting an analog signal from a medium, the data receiving device comprising:
An analog-to-digital converter that operates to receive the analog signal and provide a first digital signal corresponding to the analog signal at a first sampling instant;
A data detector that operates to perform a data detection process on the first digital signal to provide a modified data signal;
An error determination circuit operable to compare the modified data signal with a derivative of the first digital signal to identify a first error indication;
A first feedback loop that receives the first error indication and causes an analog-to-digital converter to provide a second digital signal corresponding to the analog signal at a second sampling instant, the second sampling instant; A first feedback loop adjusted to reflect the first error indication; and receiving the first error indication and adjusting a derivative of the first digital signal to determine the error determination circuit. A data processing system including a second feedback loop that operates to determine a second error indication based at least in part on the adjusted derivative of the first digital signal.   18. The data processing system of claim 17, wherein the second feedback loop includes an interpolator, a summation element, and a delay element, and the derivative of the first digital signal displays the first error indication during a temporary period. Corresponding to the first digital signal interpolated in time to compensate, both the summing element and the delay element receive the first error indication, and the summing element is the first error indication Is processed to subtract from the delayed version of the first error indication, and the output of the summing element is used to control the amount of time interpolated by the interpolator.   18. The data processing system of claim 17, wherein the data receiving device is a wireless receiver and the medium is a wireless transmission medium.   18. The data processing system according to claim 17, wherein the data processing system is a hard disk drive system and the medium is a magnetic storage medium.

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