JP2912323B1 - Digital data receiver - Google Patents

Abstract

Kind Code: A1 In a transmission system capable of simultaneously using a plurality of types of transmission schemes combining a plurality of modulation schemes and error correction schemes and performing multiplex transmission, a required C / N ratio is obtained at a low C / N reception.
The data transmitted by the high N transmission method has interfered with the data transmitted by the low C / N transmission method. SOLUTION: For each of the transmission systems, means 820 for detecting whether reception is impossible or difficult, or error correction is likely to be impossible, and the means for detecting When it is detected that there is a possibility of being in an impossible state, a packet of the detected transmission method is set to a null packet, or a signal of the packet of the detected transmission method is set to the impossible state. The configuration is such that at least means 821 for replacing each of the signals with no influence on the packets of the other transmission schemes in which the possibility is not detected is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for receiving digital data multiplexed and transmitted by mutually different transmission systems (determined by a modulation system and an error correction system). The present invention relates to a digital data receiving apparatus configured to prevent mutual influence upon deterioration of a transmission state.

[0002]

2. Description of the Related Art In digital broadcasting, for example, in the conventional digital transmission, it is common to select one type from several types of transmission systems and provide it for transmission. However, in the case of a transmission line having a high rarity like a repeater of a broadcasting satellite, a case where one repeater is operated simultaneously by a plurality of broadcasters may be considered. In this case, it is desirable that each operator can freely select a transmission method that has an error tolerance for a desired low reception C / N (carrier-to-noise ratio). This is because, when digital data (services) sent from each carrier is transmitted in a transmission system desired by each carrier, for example, each data is compressed on a time axis, multiplexed and transmitted ( (Time-division multiplex transmission). At this time, considering that the MPEG system is used, a TS (Transport Stream) packet sent from each carrier has a PID (Package) depending on the contents of the service.
et Identification: 1 called packet identification information
A 3-bit identification flag is added. By using this identifier, the receiving end can extract only the packet of the service desired by the receiver and decode information such as video and audio.

[0003]

As described above, the service transmitted from each broadcaster to the viewer is transmitted by a transmission method having an error tolerance desired by each broadcaster. In this case, depending on the degree of deterioration of the transmission state,
Data transmitted by a certain transmission method may be transmitted normally, but data transmitted by another transmission method may become unusable due to a too high bit error rate. At this time, even if it is unavoidable that the transmitted data becomes unusable, the PID information in the unusable packet also causes a bit error, so that there is a certain probability that the PID information in the unusable packet becomes unusable. In some cases, the PID matches the PID used in a normally transmitted packet. In this case, as a result, interference (interference between data) is given to services transmitted in normally transmitted packets.

An object of the present invention is to provide a digital data receiving apparatus in which interference between data multiplex-transmitted by such different transmission methods is suppressed.

[0005]

In order to achieve the above object, a digital data receiving apparatus according to the present invention comprises: a receiving apparatus for receiving digital data multiplex-transmitted by mutually different transmission methods; Means for detecting whether reception is impossible or difficult, or error correction is impossible for each of them, and the possibility that the state is impossible by the means for detecting When it is detected that the packet of the detected transmission method is a null packet, or the signal of the packet of the detected transmission method is not detected as another transmission method in which the possibility of being in the impossible state is not detected. At least means for replacing each of the signals with a signal that does not affect the packet.

In the digital data receiving apparatus according to the present invention, the detecting means is a bit error rate estimating means or an error correction impossible detecting means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments of the present invention with reference to the accompanying drawings. As described above, in the present invention, a plurality of transmission schemes combining any modulation scheme and error correction scheme are used at the same time, and in a multiplexed transmission system, the transmission state of each transmission scheme is detected and unusable. By replacing a packet with a bit error rate with a null packet or a signal that does not affect normally transmitted packets, data with a reduced bit error rate is transmitted by another transmission method. To prevent data transmitted using a low error resilience transmission scheme from interfering with data transmitted using a high error resilience transmission scheme by preventing packets from being misrecognized as packets that have been rejected. ing.

Hereinafter, the present invention will be described with reference to specific examples. The embodiment shown here is a transmission system which is being developed for satellite digital broadcasting by a BS (broadcast satellite). First, the configuration of a multiplexed signal handled in this transmission scheme will be described. FIG. 1 shows an example of a frame configuration of the multiplexed signal (for BS broadcasting).

In this system, video, audio, and various digital data are multiplexed in accordance with the MPEG2 system to generate a TS packet of 188 bytes. As shown in FIG. 1, the TS packet includes a Reed-Solomon code (RS (204, 1) in the subsequent 16 bytes.
A parity check byte (101) consisting of 88)) is added, and 49 packets of such a configuration are combined to form one frame. Here, each position occupied by the packet in the frame is called a slot.
Here, the 49th slot is a dummy slot inserted in advance to create a BPSK burst section to be inserted to reinforce carrier regeneration. Although a 1-byte packet synchronization code (47 in hexadecimal) is originally written in the first Byte of each TS packet, in this embodiment, when a frame is formed, the first frame is further added to this portion. 2 as the synchronization signal w1 (102)
Byte (16bit), TMCC (Transmission and Multi)
plexing Configuration Control; transmission multiplexing configuration control)
8 bytes (64 bytes) as a control signal called a signal (103)
bit) and a second frame synchronization signal w2 (or w2
3) 2 bytes (16 bits) as (104), totaling 12 bytes
(96 bit) is overwritten.

Here, for example, a case may be considered in which only one TS packet in one frame is transmitted by a certain modulation method. In this case, a superframe is configured by treating eight frames as one unit in order to perform code mixing (interleaving) of a sufficient depth (depth of 8 or more) to extract the capability of the error correction code. And interleaving is done in this. At this time, it is necessary to identify the position of the first frame in the superframe. If the second frame synchronization signal (104) is w2, it is identified as the first frame in the superframe, and if w3, it is identified as another frame. doing.

[0011] In each slot, a transmission system desired by the carrier occupying the slot is specified. For example,
As shown in FIG. 1, designation is made such that the first eight slots are transmitted by the transmission method 1 and the second half 40 slots are transmitted by the transmission method 2. Information on the correspondence between each slot position and the transmission method is described in the TMCC signal. However, the content of the TMCC signal indicates the frame configuration one superframe later, and therefore, when the transmission method is switched, the content of the TMCC signal is changed, for example, two superframes before.

FIG. 2 shows an example of the configuration of a modulated wave for BS broadcasting generated from a multiplexed signal having this frame structure (a frame structure transmitted by the transmission method 1 and the transmission method 2). As shown in FIG. 2, the first frame synchronization signal W1 (32 symbols) (2
01), TMCC signal (128 symbols) (202),
And the second frame synchronization signal W2 (or W3) (3
A total of 192 symbols (2 symbols) (203) are modulated by two-phase shift keying (BPSK) as a header and multiplexed. Here, the number of these symbols is the TMCC of FIG.
The reason why the number of bits (64 bits) of the portion corresponding to the signal is doubled is that these are subjected to convolutional coding at a coding rate of 1/2, and the same number of redundant bits as the original data amount are added. It depends.

Following these headers, the main signal (service data) for 8 slots is multiplexed using the transmission system 1 and the 40 slots for the main signal (service data) using the transmission system 2. It should be noted that the modulated signal 192 used for transmitting the main signal is included in the main signal section.
Four random BPSK modulated waves (carrier regeneration enhancement symbols) are inserted into the symbols. This B
The carrier reproduction up to a low C / N is enabled by the PSK modulation wave.

By using the modulated wave for BS broadcasting having such a configuration, the BS receiver captures the frame synchronization signal, demodulates and decodes the TMCC signal portion, and detects the transmission system of the subsequent main signal portion. In order to start demodulation and decoding corresponding to the detected transmission system, even if the transmission system is changed, the transmission system of each slot can be dynamically switched in units of a superframe.

FIGS. 3 and 4 show examples of the first half and the second half, respectively, of the digital modulation circuit for generating the modulated wave for the BS broadcast. In FIG. 3, each of a plurality of video signals, audio signals, and data services is
Frame structure consisting of 49 slots at 01 (see FIG. 1)
Are multiplexed and output. In this example, 44 packets are transmitted as high-quality information (hereinafter, referred to as HQ) using a trellis-coded 8-phase PSK (TC8PSK) modulation method, and two packets are error-corrected by a convolutional code having a coding rate of 1/2. Coding and quadrature phase shift keying (QPS
K) A modulation scheme that combines the modulation scheme (hereinafter, QPS)
In this case, the information is transmitted as highly reliable information (hereinafter, referred to as LQ) using the (K + 1/2) modulation method. Assuming that one slot is allocated to one packet, in the frame configuration (49 slots) written in the multiplexing apparatus 301 surrounded by a broken line, 44 slots for HQ and 2 slots for LQ as shown in the figure. Respectively.

Assuming that all data is transmitted by the TC8PSK modulation method having high frequency use efficiency,
48 slots of data can be transmitted in one frame period, but as shown in this example, two packets of QPSK
When transmitted by the +1/2 modulation method, the efficiency is TC8P
Since this is half of the SK modulation method, data that cannot be transmitted in one frame is generated for two slots. Therefore, in this example, the same number of actually transmitted packets (dummy packets) as the number of slots transmitted by the QPSK + 1/2 modulation method are inserted so that the number of slots per frame is constant regardless of the modulation method. ing.

The HQ and LQ information is for transmitting services such as video and audio. Apart from this, a frame synchronization signal indicating the beginning of a frame and a TMCC signal are also output from the multiplexer 301. The control signal generation circuit 302 uses these signals to determine whether the data stream currently output from the multiplexer 301 is HQ, LQ, or a dummy packet that is discarded without being transmitted. Recognize and generate a control signal for instructing whether to drive or stop the circuits of each unit described below.

The signal of the slot assigned to the HQ is first input to a parallel / serial conversion circuit 304 via a byte interleaver 303, and is converted from an 8-bit stream to a 2-bit stream by the parallel / serial conversion circuit. (In the drawings, the numbers written on the connection lines connecting the blocks represent the number of bits of data.) Further, an error correction code is added by the trellis encoder 305 to convert the data into 3-bit encoded data. From this 3-bit encoded data, 8PSK mapper 30
6 are converted to signals (8 bits each) representing signal points I and Q. The 8PSK mapper at this time is shown in FIG.
Shown in

FIG. 5A shows that, for example, when the input 3-bit signal is (010), the output is I = −90,
Q = + 90 is output, and is generally constituted by a ROM in many cases. Similarly to the slot signal assigned to the HQ, the signal of the slot assigned to the LQ is first input to the parallel / serial conversion circuit 307 via the byte interleaver 303, and this parallel / serial conversion circuit Is converted from an 8-bit stream to a 1-bit stream. Further, an error correction code is added by the convolution encoder 308, and 2bi
Converted to encoded data of t. From the 2-bit encoded data, signal points I and Q are obtained using a QPSK mapper 309.
(8 bits each). The QPSK mapper is shown in FIG.

2By written at the beginning of each slot
te (16-bit) synchronization signal W1 and 8-byte TMCC signal, 2-byte (16-bit) synchronization signal W2 or W3 (W2 is written in the first frame of the superframe, and W3 is written in other cases) Then, in order to obtain higher reliability, a convolutional code having a coding rate of 1/2 is added and transmitted), as in the case of HQ and LQ, after passing through the byte interleaver 303, and by the parallel / serial conversion circuit 310. After being converted from 8 bits to 1 bit signals, an error correction code is added by a convolutional encoder 311, and a BPSK mapper 3
The signal is converted into a signal (8 bits each) representing the signal points I and Q using the signal 12. The BPSK mapper is shown in FIG.

The I / Q signals corresponding to the HQ, LQ, synchronization and TMCC signals obtained as described above are interlocked with the changeover switches 313-1 and 313 using the control signal generated by the control signal generation circuit 302. -2 to sequentially switch to obtain time-division multiplexed I and Q signals. As shown in FIG. 4, these I signal and Q signal are route roll-off filters 414-1 and 414-2, D / A converter 4
15-1, 415-2, low-pass filter 416-1,
After passing through 416-2, the signal is orthogonally modulated by an orthogonal modulator 417, and an unnecessary wave is removed by a bandpass filter 418 to obtain a time-division multiplexed modulated wave as shown in FIG. In the above, it is also possible to update the content of the TMCC signal with the previous superframe and change the next frame to a frame with a different slot number distribution.

Next, the circuit configuration of the demodulation system will be described. FIGS. 7 and 8 show, for example, a digital demodulation circuit required for signal demodulation when a TMCC signal is time-division multiplexed and transmitted using the above-described digital modulation circuit (see FIGS. 3 and 4). 1 shows an example of a circuit configuration of the first half and an example of a circuit configuration of the latter half, respectively.

In FIG. 7, the input time-division multiplex modulation wave (see FIG. 6) is first subjected to a band-pass filter 701 to remove unnecessary wave components. Then, after being converted into baseband I and Q signals in a quadrature demodulator 702, harmonic components are removed by low-pass filters 703-1 and 703-2, and digital signals are converted by A / D converters 704-1 and 704-2. (Here, both I and Q are 8 bits), and further, inter-symbol interference is removed by digital roll-off filters 705-1 and 705-2. At this time, a frame synchronization signal is output from the TMCC signal detection circuit 806 shown in FIG. 8 and a signal of a modulation method indicating 8PSK is output for the BPSK and other periods in the TMCC period, and is added to the phase error detection circuit 707. ing. That is, the phase error detection circuit 707 outputs a phase error signal corresponding to 8PSK at this time, and performs carrier reproduction via the loop filter 710.

Next, the obtained I signal and Q signal are subjected to 8PSK demapping using an 8PSK demapper 708 having a phase shift of n × π / 4 (n = 0, 1, ‥‥ 7,). (Hard decision), and the matched filters 1 to 8 (709-1 to 709-) for comparing this output with frame synchronization.
When the correlation value is obtained in 8), positive or negative equally spaced correlation pulse trains are obtained at the output. The details of this part are shown in FIG.
Shown in

Here, first, the input I signal and Q signal are divided into eight phases by a BPSK demapper 901 having a phase shift of n × π / 4 (n = 0, 1, ‥‥, 7). Is used to perform BPSK demapping. A shift register 902 of 20 bits is prepared for each of the eight output signals. The shift register 902 performs serial / parallel conversion, and a frame synchronization signal detection gate 903 captures a frame synchronization signal. At this time, if the reproduced carrier is near the correct frequency, a frame synchronization signal can be detected from at least one of the eight gates 903. Therefore, the OR of all the detection gate outputs is ORed by the OR gate 904, and if the output of the OR gate is frame-synchronous, they are false-synchronized by the rear / front protection circuit 905 utilizing the fact that they occur in the frame period. Remove the pulses and extract only the correct frame sync pulse.

Using the extracted frame synchronization pulse, the synchronization section symbol averaging circuit 906 performs symbol averaging. At this time, since the code sequence of the synchronization symbol is a known value, if the incoming synchronization code is 1, 18
By averaging the symbols after giving a phase shift of 0 ° or 0 ° if 0, only the symbol of BPSK code “0” is output to the output of the averaging circuit 906. By passing this through the area determination ROM 907, the BPS
The code “0” of K is m × π / 4 (m =
0, 1, 2, 3,..., 7), it is known that demodulation is performed with a phase shift of 0, 1, 2, 3,..., 7). Signal and Q signal can be obtained. Viterbi decoding is performed by the Viterbi decoder 909 for only the TMCC period of the absolutely phased signal, the output signal is stored in a FIFO 910 for one superframe, and the RS (64,48) decoder 91 stores the stored signal.
TMC by performing RS (64, 48) decoding at 1
Obtain the C signal.

From this information, it is possible to know the modulation method of the currently received modulated wave, and based on the result, the phase error detection circuit 707 shown in FIG. QPSK when receiving PSK, and 8 when receiving 8PSK
Switching is performed by giving an appropriate phase to that of PSK. In the block 806 shown in FIG.
On the basis of the value of the C signal and the frame synchronization signal pulse (both refer to FIG. 9), the control signal generation circuit 810 generates digital roll-off filters 705-1 and 705.
-2 activates the trellis decoder 812 when the HQ signal is generated, activates the Viterbi decoder 813 when the LQ signal is generated, activates the synchronization pattern generation circuit 815 or the TMCC signal during the other periods. A gate signal for driving the selection switch 817 for selecting a signal to be generated is generated.

The selection switch 817 is obtained by the above signal processing.
Can output multiplexed data having the frame structure used on the modulation side. Up to this point, a general configuration for generating and demodulating this type of time division multiplex modulation wave has been described.

However, as described above, at the time of low C / N reception, the data of the HQ portion may have a bit error rate that is almost unusable.
It is conceivable that the ID information (packet identification information) is transformed into LQ PID information due to a bit error, which hinders the decoding of LQ data. Therefore, in the receiving apparatus of the present invention, the bit error rate detection and threshold determination circuit 820
Monitors the error rate of the HQ data, and when a bit error rate exceeding a predetermined threshold is detected, a circuit 821 for inserting a null packet into the HQ portion of the multiplexed data of the reconstructed frame is provided. By providing
It is possible to prevent degraded HQ data from interfering with LQ data.

FIG. 10 shows a configuration example of the bit error rate detection and threshold value judgment circuit 820 used here. In FIG. 10, the signal supplied to this circuit is a synchronously demodulated complex signal on the I and Q planes. When this is trellis-decoded by the trellis decoder 1001, decoded data of 2 bits per symbol period is obtained. This data can be obtained with almost no error in a normal reception C / N. Further, even when the C / N is deteriorated, the data has a reduced bit error rate to some extent. When the same trellis coding as performed on the transmission side is performed again on this data by the trellis encoder 1002, coded data of 3 bits to which redundancy for error correction is added is obtained. On the other hand, when the signal supplied to this circuit is decoded by the 8PSK hard decision decoder 1003, as shown in FIG.
000 to 11 for each of the areas separated by dotted lines
One 3-bit decoded output is output.

The 3-bit data is transmitted to the trellis encoder 1
Although the bit error rate after the 3-bit data of 002 output is trellis-decoded is suppressed, but is not error-corrected at all, if both are compared by the code comparator 1004, An approximate value of the transmission error rate of 8PSK before decoding is obtained. This is counter 1005
By comparing with the threshold value in the comparator 1006, it is possible to detect whether or not the bit error rate has deteriorated to a predetermined threshold value or more.

In FIG. 8, the block indicated by 822 replaces the synchronization code (47 hexadecimal) embedded in the first byte of each TS packet with TMCC on the transmitting side. This is a circuit that replaces the synchronization code with a synchronous code. The output of the circuit 822 is supplied to a demultiplexing / demultiplexing device 823, and a plurality of video signals, audio signals, and data service signals are respectively processed by signal processing reverse to that of the multiplexing device 301 (see FIG. 3) on the time division multiplexed modulated wave generation side. Is separated into Of the separated signals, the signal into which a null packet is inserted, of course, loses the information, but prevents this from adversely affecting the service of the normally transmitted packet (this book). Object of the invention).

In the above-described generation and demodulation system of the time division multiplex modulation wave, transmission of the modulation wave of two layers by TC8PSK and QPSK + 1/2 has been described as an example, but the number of layers can be expanded to more. In this case, a plurality of bit error rate detection and threshold value judgment circuits of the same type as shown in FIG. 10 are provided for all the layers except the transmission method with the strongest error resilience, and a null signal is output by these output signals. Try to insert packets. Alternatively, the bit error rate detection circuit may be an error correction undetectable detection circuit instead.

In the above, when the bit error rate of the HQ data exceeds a predetermined threshold, the packet of the HQ data is replaced with a null packet.
In this case, the signal of the HQ data packet that exceeds the threshold value may be replaced with a signal that does not affect other HQ or LQ data packets whose bit error rate does not exceed a predetermined threshold.

[0035]

According to the present invention, in a transmission system in which a plurality of types of transmission schemes combining a plurality of modulation schemes and error correction schemes can be used at the same time and multiplex transmission can be performed,
At the time of receiving N, it is possible to avoid that data transmitted by the transmission method having a high required C / N interferes with data transmitted by a transmission method having a low required C / N.

[Brief description of the drawings]

FIG. 1 shows an example of a frame configuration of a multiplexed signal for BS broadcasting.

FIG. 2 shows a configuration example of a modulated wave for BS broadcasting.

FIG. 3 illustrates an example of a circuit configuration of a digital modulation circuit that generates a modulated wave for BS broadcasting.

FIG. 4 illustrates an example of a circuit configuration of a digital modulation circuit that generates a modulated wave for BS broadcasting.

FIG. 5 shows how each signal is output in each of the 8PSK, QPSK, and BPSK mappers in FIG.
(B) and (c).

FIG. 6 shows a data configuration of a time division multiplex modulation wave.

FIG. 7 shows an example of a circuit configuration of a digital demodulation circuit for demodulating a transmitted time-division multiplex modulation wave.

FIG. 8 shows an example of a circuit configuration of a digital demodulation circuit for demodulating a transmitted time-division multiplex modulation wave.

9 shows a specific circuit configuration of a portion including an 8PSK demapper and a matched filter in FIG. 7, and a frame synchronization signal and TMCC signal detection circuit in FIG. 8;

FIG. 10 shows a configuration example of a bit error rate detection and threshold value determination circuit.

11 is a diagram illustrating a decoding operation of the 8PSK hard decision decoder in FIG.

[Explanation of symbols]

 301 Multiplexer 302 Control signal generation circuit 303 Byte interleaver 304 8bit / 2bit parallel / serial converter 305 Trellis encoder 306 8PSK mapper 307,310 8bit / 1bit parallel / serial converter 308,311 Convolutional encoder 309 QPSK mapper 312 BPSK mapper 313-1, 313-2 Changeover switches (interlocking) 414-1, 414-2 Root roll-off filters 415-1, 415-2 D / A converters 416-1, 416-2 Low-pass filter 417 Quadrature modulator 418 Band Pass filter 701 Band pass filter 702 Quadrature demodulator 703-1, 703-2 Low pass filter 704-1, 704-2 A / D converter 705-1, 705-2 Digital roll-off filter 707 Phase error detection Path 708 8PSK demapper 709-1 to 709-8 Matched filter 710 Loop filter 806 TMCC signal detection circuit 810 Control signal generation circuit 812 Trellis decoder 813 Viterbi decoder 814-1 2bit / 8bit Parallel / serial conversion circuit 814-2 1bit / 8bit Parallel / serial conversion circuit 815 Synchronization pattern generation circuit 817 Selection switch 820 Bit error rate detection and threshold judgment circuit 821 Circuit for inserting null in HQ portion 822 Circuit for replacing TMCC signal with 47 in hexadecimal 823 Demultiplexer 901 BPSK Demapper 902 Shift register 903 Frame synchronization signal detection gate 904 OR gate 905 Back / front protection circuit 906 Synchronization section symbol averaging circuit 907 Area determination ROM 908 Phase rotation ROM 909 Viterbi Coder 910 FIFO 911 RS (64,48) decoder 1001 trellis decoder 1002 trellis encoder 1003 8PSK hard decision decoder 1004 code comparator 1005 counter 1006 comparator

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kyoichi Saito 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tomohiro Saito 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Fumiaki Minematsu 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-4-74046 (JP, A) Hei 9-507358 (JP, A) Technical Report of the Institute of Television Engineers of Japan, Vol. 22, pp. 11-16, BCS'96-14 (Mar. 1996), Hisakazu Kato, Akira Hashimoto "Application of hierarchical transmission to 12GHz band ISDB satellite" (58) Fields investigated (Int. Cl. ⁶ , DB name) ) H04L 1/00 H04J 3/00 H04L 29/04

Claims (2)

(57) [Claims] 1. A receiving apparatus for receiving digital data multiplex-transmitted by mutually different transmission schemes, wherein reception is impossible or difficult for each of the transmission schemes, or error correction is impossible. Means for detecting whether or not there is a possibility that the transmission method may be changed, and when it is detected by the detecting means that the possibility of the impossible state is detected, a packet of the detected transmission method is converted into a null packet, or The apparatus further comprises at least means for replacing a signal of the detected transmission scheme packet with a signal that does not affect a packet of another transmission scheme in which the possibility of the impossible state is not detected. Digital data receiving device. 2. The digital data receiving apparatus according to claim 1, wherein said detecting means is a bit error rate estimating means or an error correction impossible detecting means.