JP5160304B2 - Product operation device including variable resistance variable resistance element, product-sum operation device, neural network including these devices in each neuron element, and product operation method - Google Patents

Description

  The present invention relates to a product operation device including a resistance change type variable resistance element capable of storing information by changing an electrical resistance by applying an electrical stress, a product-sum operation device, and the device for each neuron. The present invention relates to a neural network provided in an element, a product operation method, and the like.

  Currently, so-called Neumann computers have made great progress and are used in various situations around the world. However, these Neumann computers are very poor at processing that humans can easily perform (real-time human face recognition, etc.) due to the characteristics of the processing method itself.

  In contrast, a neural network, which is an arithmetic processing model that imitates the information processing mode of the brain, has been studied.

  As a model of a neuron element (hereinafter referred to as “neuron”) that constitutes a neural network, a multiplication value obtained by weighting output values of a plurality of other units with a synaptic load value is input to a unit corresponding to a neuron, A value obtained by further nonlinearly transforming the input value is used as an output value (internal state value).

  In other words, in a general neural network, desired processing is realized by product-sum operation and nonlinear transformation between units and between units.

  As a neural network architecture using this neuron model (neural network model), so far, associative memories that combine units that perform product-sum operations and hierarchically connect units that also perform product-sum operations A pattern recognition model has been proposed.

  Here, aiming at the practical use of neural networks, it is necessary to execute the product-sum operation more efficiently, especially in terms of execution speed and power consumption. Becomes prominent.

  Various inventions relating to the neuron model and the neural network architecture for executing the product-sum operation as described above have been proposed, and a method for constructing a hierarchical neurocomputer by performing the product-sum operation has also been proposed. (For example, see Patent Documents 1 and 2). FIG. 14A shows a configuration of a product-sum operation apparatus 1000 using a PWM (Pulse Width Modulation) signal.

Each switch 1012 of the current sources 1012 to 1032 of each switched current source (SCS) related to the current Ii corresponding to each PWM input signal having a pulse width Ti (i = 1, 2, 3,...). When 1032... Is turned on, the current Ii flows through the data line 1001 to the capacitor C1004 for the time Ti. The charge amount Qout and the terminal voltage Vout stored in the capacitor C1004 are respectively
Qout = ΣIiTi
Vout = Qout / C = ΣIiTi / C
It is written.

  In this way, the addition result of the PWM signals (IiTi) weighted by the respective current amounts of the current sources 1012 to 1032... Is obtained as the charge amount Qout or the terminal voltage Vout of the capacitor 1004. The terminal voltage Vout is converted into a PWM signal having a pulse width Tout by comparing with a reference ramp voltage Vref that changes linearly as shown in FIG.

  Next, an arithmetic processing step using the product-sum arithmetic circuit unit 3000 will be described. FIG. 15 shows a block diagram of a processing block for implementing the product-sum operation method in Patent Documents 1 and 2.

  The product-sum calculation method in Patent Documents 1 and 2 includes a calculation unit 3006 including a plurality of calculation blocks 1000a, 1000b, 1000c,..., An input value (calculation value) holding block 3001 that holds a calculation value Xi, A load value (operation value) holding block 3004 for holding the operation value Wi, and a switching block (1) for inputting the operation value Xi and the operation value Wi to the operation block corresponding to the label i of the operation value Xi. 3003 and a switching block (2) 3005.

  In Patent Document 1, it is assumed that the calculated value Xi is input as a PWM (Pulse Width Modulation) signal. Note that i of the calculation value Xi and the operand value Wi are subscripts indicating different X and W, respectively, and take 1, 2, 3,... Natural numbers.

  FIG. 16 shows an analog arithmetic circuit 2000 in which one arithmetic block is composed of analog circuits. As illustrated in FIG. 16, the analog arithmetic circuit 2000 in Patent Document 1 includes an analog multiplier 2001, a capacitor 2002, and an output buffer 2003.

  The analog multiplier 2000 includes the product-sum operation apparatus 1000 shown in FIG.

  FIG. 17 shows an input value holding block 3001 configured with an analog memory circuit. Here, it is assumed that the analog memory circuit includes a capacitor 2002 and an output buffer 2003.

  As shown in FIG. 15, a plurality of calculation values Xi are held in the input holding block 3001. The input holding block 3001 includes a capacitor 2002 and an output buffer 2003, and holds the calculated value Xi as a voltage value accumulated in the capacitor 2002.

  Subsequently, the label i included in the operation value Xi is input to the switching block (1) 3003, the switching block (1) 3003 performs switching according to the label i, and the operation value Xi output from the input holding block 3001 is used. It inputs into the calculation block corresponding to the label i.

  On the other hand, the plurality of operand values Wi output from the load holding block 3004 are respectively input to predetermined calculation blocks. Here, in Patent Document 1, similarly to the operation value Xi, the operation value Wi is switched in the switching block (2) 3005 according to the label i included in the operation value Xi, and is determined by the label i. Input to a predetermined calculation block. By executing the above processing, the calculated value Xi and the calculated value Wi are input to a predetermined calculation block.

  Subsequently, a calculation process performed in the predetermined calculation block to which both the calculation value Xi and the calculation value Wi are input will be described. Note that the arithmetic processing is not executed in the arithmetic block to which the arithmetic value Xi is not input.

  In the arithmetic block in FIG. 16 (the arithmetic block in the analog multiplier 2001), the analog multiplier 2001 calculates Xi × Wi for the arithmetic value Xi and the operand value Wi. Note that the calculation value and the value to be calculated input to each calculation block may be the same or different for each calculation.

  Subsequently, the multiplication result of Xi × Wi is expressed by the amount of charge and is additionally accumulated in the capacitor 2002. Here, in Patent Document 1, it is assumed that the multiplication result by the analog multiplier 2001 is output as an amount of charge.

  By repeating the above processing, the accumulated value of the multiplication results of a plurality of Xi and Wi is held in the capacitor 2002, and when the predetermined accumulation is completed, the accumulated value is output via the output buffer 2003. Here, Xi is a PWM signal, and Wi is a pulse train having a certain period or a voltage pulse.

  Next, a case where the product-sum operation apparatus 1000 is applied to a neural network will be described. A commonly described neural network model is shown in FIG. FIG. 19 shows the configuration of an arithmetic processing block when the product-sum operation method described in FIG. 15 is applied to the neural network.

  First, as shown in FIG. 18, as a model of neuron elements in the neural network, the sum of values obtained by weighting the output values of the plurality of neuron elements in the previous stage with the synapse load is obtained. It is common to decide.

The neuron element circuit (unit) described in Patent Literature 1 uses the arithmetic processing block described in FIG. 16 as a neuron element model. That is, the operation value Xi described in FIG. 16 corresponds to the output value of the preceding neuron element, and the operation value Wi corresponds to the synapse load value, and determines the internal state value of the neuron element. Subsequently, as shown in FIG. 20, the accumulated value calculated in each operation block is input to a function processing block 4001A that performs predetermined function processing. The function processing block 4001A may perform nonlinear function processing or linear function processing according to the purpose.
Japanese Patent Laying-Open No. 2005-122465 (published on May 12, 2005) Japanese Patent Laying-Open No. 2005-122466 (published on May 12, 2005) Liu, SQ et al. “Electric-pulse-induced reversible resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000

  However, the product-sum operation apparatus 1000 has the following problems. FIG. 21 shows a circuit configuration of the switched current source (SCS) described in FIG.

  A conventional switched current source (SCS) uses a complementary metal-oxide semiconductor (CMOS) inverter circuit for a switch portion and a metal-oxide semiconductor (MOS) transistor for a constant current source.

  For this reason, there is a problem that the configuration becomes complicated and the occupied area of the product-sum operation apparatus 1000 becomes large.

  Note that a transistor having a channel length of about 2 μm is usually used as the constant current source transistor without depending on the design rule in order to improve analog performance. As a result, the size of the unit element of the switched current source (SCS) is about several μm to several tens of μm.

  Further, as shown in FIG. 14A, in order to simultaneously input a plurality of calculated values / operated values to the product-sum calculation apparatus 1000, it is necessary to provide a plurality of switched current sources (SCS). Therefore, there is a problem that the occupied area further increases.

  The present invention has been made in view of the above-described conventional problems, and an object thereof is to simplify the configuration of a product operation device and a product-sum operation device, and to calculate a product operation device for the area of the entire circuit including these devices, and An object of the present invention is to provide a product operation device and product-sum operation device capable of reducing the area occupied by the product-sum operation device, a neural network including these devices in each neuron element, a product operation method, and the like.

  In order to solve the above-mentioned problem, the product operation device of the present invention is a product operation device that outputs a result of a product operation by inputting a multiplicand and a multiplier, and is reversible by applying a voltage pulse. A variable resistance element having variable resistance and having at least two terminals, and a first input signal corresponding to a multiplicand is applied to one of the two terminals of the variable resistance variable resistance element. , And a second input signal corresponding to the multiplier multiplied by the multiplicand is input to the other terminal, so that an output value corresponding to the result of the product operation of the multiplicand and the multiplier is output. It is characterized by being composed.

  In order to solve the above-described problem, the product calculation method of the present invention includes a variable resistance variable resistance element having a resistance variable variable resistance element having at least two terminals, the electrical resistance of which is reversibly changed by applying a voltage pulse. And a multiplier, and a product operation method executed by a product operation device that outputs the result of these product operations, wherein a multiplicand is applied to one of the two terminals of the variable resistance variable resistance element. A first signal input step of inputting a first input signal corresponding to the second input signal, a second signal input step of inputting a second input signal corresponding to a multiplier multiplied by the multiplicand to the other terminal of the two terminals, And an operation result output step of outputting an output value corresponding to a result of product operation of the multiplicand and the multiplier.

  According to the above configuration, the first input signal corresponding to the multiplicand is input to one terminal of the variable resistance variable resistance element having at least two terminals, and the multiplier corresponding to the multiplier multiplied by the multiplicand is input to the other terminal. By inputting two input signals, an output value corresponding to the result of product operation of the multiplicand and the multiplier is output.

  According to the method, the first signal input step of inputting the first input signal corresponding to the multiplicand to one terminal of the variable resistance variable resistance element having at least two terminals, and the other of the two terminals. A second signal input step for inputting a second input signal corresponding to the multiplier to be multiplied by the multiplicand to the terminal of the output, and an operation result output step for outputting an output value corresponding to the result of the product operation of the multiplicand and the multiplier Are executed.

  The major point in the above configuration or method is to use the physical characteristic that the electrical resistance is reversibly changed by applying a voltage pulse in the variable resistance variable resistance element.

  That is, if the correspondence between the result of the multiplicand, multiplier, and product operation and the first signal, the second signal, and the output value (current value, etc.) of the variable resistance variable resistance element is determined in advance, the product operation is performed. It is possible to execute.

  Thereby, a signal corresponding to the multiplicand is input from one terminal, and a signal corresponding to the multiplier to be multiplied by the multiplicand is input from the other terminal, so that an output corresponding to the result of the product operation of the multiplicand and the multiplier There is no need to configure a product operation device that outputs a value as a switched current source (SCS) having a constant current source and a switch circuit as in the prior art.

Thus, for example, when the design rule is 0.1 μm, the basic element size of the product operation device of the present invention is 0.04 μm ² , and the element area is about two to three digits compared to the above-described conventional technology. Can be reduced.

  Here, the “voltage pulse” means a predetermined amplitude value (voltage value with the maximum absolute value: hereinafter referred to as “pulse voltage” or “pulse voltage value”) and a predetermined pulse width (hereinafter referred to as “voltage pulse width”). NRZ (None-Return-to-Zero) and RZ (Return-to-Zero) signals as well as PWM (Pulse Width Modulation) signals. The “voltage pulse” includes a single voltage pulse in one cycle unit and a “voltage pulse train” having a predetermined frequency (hereinafter referred to as “pulse frequency”).

  The “resistance variable resistance element” is an element whose electric resistance reversibly changes when a voltage pulse is applied. In recent years, the “variable resistance variable resistance element” is expected to be applied as a next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of a flash memory. Examples of the “resistance variable variable resistance element” include RRAM (Resistance RAM) and PCRAM (Phase Change RAM) as described in Non-Patent Document 1.

  Examples of the first signal include a PWM (Pulse Width Modulation) signal. Examples of the second signal include a voltage pulse train having a predetermined cycle (predetermined frequency) and a voltage pulse.

  As described above, it is possible to provide a product operation device that can simplify the configuration of the product operation device and reduce the area occupied by the product operation device with respect to the area of the entire circuit including these devices.

  In the product operation device of the present invention, in addition to the above configuration, the first input signal and the second input signal are voltage pulses, the voltage pulse width of the first input signal, and the pulse of the second input signal. The output value may be controlled according to the frequency.

  The “resistance variable variable resistance element” can control the current flowing through the element in accordance with the number of voltage pulses applied at a predetermined time interval. Therefore, the product of the magnitude of the voltage pulse width of the first input signal corresponding to the multiplicand input to one terminal of the element and the pulse frequency of the second input signal corresponding to the multiplier input to the other terminal of the element. The value of the current flowing through the element is determined according to the number of times voltage pulses are applied to the element. That is, the correspondence between the result of the multiplicand, multiplier, and product operation and the voltage pulse width of the first signal, the pulse frequency of the second signal, and the number of times of voltage pulse application (current value) to the variable resistance variable resistance element Is determined in advance, the product operation can be executed.

  In the product operation device of the present invention, in addition to the above configuration, the first input signal and the second input signal are voltage pulses, the voltage pulse width of the first input signal, and the pulse of the second input signal. The output value may be controlled by voltage.

  The “resistance variable variable resistance element” can control the current flowing through the element according to the voltage pulse width (or the application time of the predetermined pulse voltage) and the pulse voltage value. Therefore, the product of the magnitude of the voltage pulse width of the first input signal corresponding to the multiplicand input to one terminal of the element and the pulse voltage of the second input signal corresponding to the multiplier input to the other terminal of the element. The current value flowing through the element is determined according to the voltage pulse width and pulse voltage value to the element obtained as follows. That is, the result of the multiplicand, the multiplier, and the product operation, the voltage pulse width of the first signal, the pulse voltage of the second signal, and the voltage pulse width and pulse voltage value (current value) to the variable resistance variable resistance element If the correspondence relationship is determined in advance, the product operation can be executed.

  In the product operation device of the present invention, in addition to the above-described configuration, the variable resistance variable resistance element is configured to output the result of the product calculation by inputting the first input signal and the second input signal to the variable resistance variable resistor. It is memorized by the change of the electric resistance of the element.

  Here, a problem different from the above-described problems of the prior art described in Patent Documents 1 and 2 will be described. In the prior art, each of the switched current sources (SCS) does not have a function of recording or erasing information, so that each output value (result of product operation) of each switched current source (SCS) There is a problem that cannot be reused.

  However, as described above, the “variable resistance variable resistance element” can control the current flowing through the element according to the number of application of the voltage pulse, and the current flowing through the element according to the voltage pulse width and the pulse voltage value. Can be controlled.

  In other words, in the “resistance variable variable resistance element”, the electric resistance of the element changes according to the number of voltage pulse applications or according to the voltage pulse width and the pulse voltage value.

  In other words, the “resistance variable variable resistance element” stores the result of the product operation by the input of the first input signal and the second input signal by the change in electric resistance of the variable resistance variable resistance element. This makes it possible to store the result of the product operation by the product operation device (resistance variable variable resistance element) itself of the present invention.

  In addition to the above configuration, the product calculation device of the present invention can erase the product calculation result stored by the change in the electrical resistance by applying a predetermined voltage pulse to the variable resistance variable resistance element. It has become.

  For example, when the variable resistance variable resistance element is operated in a bipolar manner, it is memorized by the change in the electrical resistance by reapplying a voltage pulse having the same time and voltage as the pulse at the time of writing but having a different polarity. The result of the product operation can be deleted. Further, when the variable resistance variable resistance element is monopolarly operated, the product operation result stored by the change in the electrical resistance can be erased by reapplying a pulse having the same polarity and a long time. it can.

  In addition, the product-sum operation apparatus of the present invention includes at least one product operation apparatus, and each set output from the product operation apparatus in response to input of a plurality of sets of the first signal and the second signal. The second output value corresponding to the accumulated value of the output values may be output.

  Here, in the conventional sum-of-products operation device, an example of adopting a configuration in which a plurality of sets of inputs are given to a single switched current source (SCS) and sequentially stored in a capacitor unless reduction in processing speed is considered. There is also.

  However, the switched current source includes a switch circuit and a constant current source, and the element size is considerably larger than that of the product operation device configured by the single variable resistance variable resistance element of the present invention.

  Therefore, even when the product-sum operation device of the present invention is configured to sequentially input the multiple product inputs to a single product operation device and store them in the capacitor, the product-sum operation using the conventional single switched current source is performed. Compared with the devices, the area occupied by the product operation device with respect to the area of the entire circuit including these devices can be reduced.

  According to the product-sum operation apparatus of the present invention, in addition to the above configuration, the variable resistance variable resistance element includes the product operation for each set by inputting the plurality of sets of the first input signal and the second input signal. Is stored by the change in electric resistance of the variable resistance variable resistance element.

  As described above, the “variable resistance variable resistance element” can control the current flowing through the element according to the number of voltage pulse application, and can control the current flowing through the element according to the voltage pulse width and the pulse voltage value. .

  In other words, in the “resistance variable variable resistance element”, the electric resistance of the element changes according to the number of voltage pulse applications or according to the voltage pulse width and the pulse voltage value.

  That is, the “variable resistance variable resistance element” means that the variable resistance variable resistance element is a cumulative result of the product operation for each set by inputting the plurality of sets of the first input signal and the second input signal. The data is stored by changing the electric resistance of the variable resistance variable resistance element. As a result, it is possible to store the accumulated result of the product operation by the product-sum operation device (resistance variable variable resistance element) itself of the present invention.

  In addition to the above configuration, the product-sum operation apparatus of the present invention applies a predetermined voltage pulse to the variable resistance variable resistance element based on the accumulated result of the product operation stored by the change in electrical resistance. Therefore, it can be erased.

  For example, when the variable resistance variable resistance element is operated in a bipolar manner, a voltage pulse having the same time and voltage as the pulse at the time of writing and having a different polarity is applied again to store the change in the electric resistance. The result of the product operation can be deleted. Further, when the variable resistance variable resistance element is monopolarly operated, the product operation result stored by the change in the electrical resistance can be erased by reapplying a pulse having the same polarity and a long time. it can.

  In addition to the above configuration, the product-sum operation apparatus of the present invention includes a plurality of the product operation apparatuses, and a second output corresponding to an accumulated value of output values output from each of the plurality of product operation apparatuses. It may be configured to output a value.

  According to the above, since writing to and reading from a plurality of product operation devices can be performed at the same time, compared to the case where the product-sum operation device is configured with a single variable resistance variable resistance element, The processing speed for writing and reading is increased.

  In addition to the above-described configuration, the product-sum operation apparatus according to the present invention includes a third output corresponding to a cumulative value of output values output from each of a predetermined number of product operation apparatuses among the plurality of product operation apparatuses. It may be configured to output a value.

  According to the above configuration, the third output value (partial sum) corresponding to the accumulated value of the output values output from each of the predetermined number of product operation devices is output, that is, partial product-sum operation (partial sum). Can be calculated).

  In addition to the above configuration, the product-sum operation apparatus of the present invention further includes a storage unit that stores a cumulative value of output values output from each of a predetermined number of product operation apparatuses among the plurality of product operation apparatuses. It is preferable.

  According to the above, a plurality of product operation devices are divided into a plurality of block parts by appropriately providing a storage unit, and a predetermined number of product operation devices among the plurality of product operation devices are provided for each block part. The cumulative value of the output value output from each of the above can be stored. Moreover, since the accumulated result of the product operation can be immediately extracted as long as it is recorded in the storage unit, the partial sum calculation process stored in the storage unit for each block portion is accelerated.

  In addition to the above configuration, the neural network of the present invention has a plurality of neuron elements, and each of the values weighted by the synaptic load values for the output values of a predetermined number of neuron elements in a specific stage is provided. A neural network in which an internal state value indicating an internal state of the neuron element is determined by inputting to a neuron element of the next stage that is uniquely associated and adjacent to the specific stage. 12. The product-sum operation apparatus according to any one of items 6 to 11, wherein an output value of the neuron element in the specific stage is provided as the multiplicand in the neuron element in the next stage. And the synaptic load value is input as a multiplier to a product-sum operation unit provided in the next-stage neuron element. The internal state value indicating the internal state of the next-stage neuron element is configured to be output from the product-sum operation device provided in the next-stage neuron element as an output value corresponding to the accumulated result of the product operation. Preferably it is.

  According to the above configuration, each neuron element includes the product-sum operation device, and the output value, the synapse load value, and the internal state value of these neuron elements are input to and output from the product-sum operation device. Since the neural network is composed of the multiplicand, the multiplier, and the accumulated result of the product operation of the multiplicand and the multiplier, each of the arithmetic processing blocks for calculating the internal state value for each neuron element in the conventional neural network is reduced. Is possible.

  “Unique correspondence” is a concept including “one-to-one correspondence” and “other-to-one correspondence”.

  More specifically, “one-to-one correspondence” means that one neuron element in the next stage adjacent to the specific stage is a value obtained by weighting the output value of one neuron element in the specific stage with a synaptic load value. This corresponds to the correspondence relationship when the input is made to.

  Further, “corresponding to other 1” means that the sum of values weighted by the synapse load values for the output values of a plurality of neuron elements in a specific stage is one neuron element in the next stage adjacent to the specific stage. This corresponds to the correspondence relationship when the input is made to.

  As described above, according to the present invention, it is possible to realize a product operation device and a product-sum operation device with a small element size and a simplified circuit. Further, the product of the input signal written in the variable resistance variable resistance element or the result of the product-sum operation can be stored, and the total sum or the partial sum can be output as necessary.

  Therefore, the configuration of the product operation device and the product-sum operation device is simplified, and the product operation device and the product operation device capable of reducing the occupied area of the product-sum operation device with respect to the area of the entire circuit including these devices, and the product A sum operation device, a neural network including these devices in each neuron element, a product operation method, and the like can be provided.

  As described above, the product operation device of the present invention is a product operation device that outputs the result of the product operation by inputting the multiplicand and the multiplier, and reversibly operates by applying a voltage pulse. A variable resistance variable resistance element having at least two terminals and having a variable resistance is provided, and a first input signal corresponding to a multiplicand is input to one of the two terminals of the variable resistance variable resistance element. The second input signal corresponding to the multiplier multiplied by the multiplicand is input to the other terminal, so that an output value corresponding to the result of the product operation of the multiplicand and the multiplier is output. It is what.

  In addition, as described above, the product calculation method of the present invention includes a variable resistance variable resistance element having a resistance variable variable resistance element having at least two terminals, the electrical resistance of which is reversibly changed by applying a voltage pulse. A product operation method executed by a product operation device that outputs a result of the product operation by inputting a multiplier, wherein a multiplicand is applied to one of the two terminals of the variable resistance variable resistance element. A first signal input step of inputting a corresponding first input signal; a second signal input step of inputting a second input signal corresponding to a multiplier multiplied by the multiplicand to the other terminal of the two terminals; An operation result output step for outputting an output value corresponding to the result of the product operation of the multiplicand and the multiplier is executed.

  Therefore, it is possible to simplify the configuration of the product operation device and reduce the occupation area of the product operation device relative to the entire circuit area including these devices, the product operation device, and the product-sum operation device. There is an effect that a neural network provided in a neuron element, a product operation method, and the like are provided.

  An embodiment of the present invention will be described below with reference to FIGS.

[Embodiment 1]
First, based on FIG. 1, the structure of the product-sum operation apparatus (product operation apparatus) 10 which is one Embodiment of this invention is demonstrated.

  FIG. 1 is a circuit diagram showing a configuration at the time of writing of a product-sum operation apparatus 10 constituted by a single cell having a resistance variable variable resistance element (product operation apparatus) 1 according to an embodiment of the present invention as a unit cell. FIG.

  The product-sum operation apparatus 10 of this embodiment outputs the result of these product operations by inputting a multiplicand and a multiplier. As shown in FIG. The configuration includes a line 2, a bit line 3, a switching transistor 4, a capacitor (storage unit) 5, and an operational amplifier 6.

  The resistance variable variable resistance element 1 has an electrical resistance that reversibly changes by applying a voltage pulse, and has at least two terminals (one terminal) A and a terminal (the other terminal) B.

  Further, by inputting a first input signal corresponding to the multiplicand to the terminal A of the variable resistance variable resistance element 1 and inputting a second input signal corresponding to the multiplier multiplied by the multiplicand to the terminal B, the multiplicand is obtained. And an output value (current value) corresponding to the result of the product operation of the multiplier.

  A voltage pulse train (second input signal) defined by the pulse frequency Fi is applied to the data line 2.

  A single voltage pulse (first input signal) defined by a pulse width (voltage pulse width) Ti is applied to the bit line 3.

  Here, the “voltage pulse” means a predetermined amplitude value (voltage value with the maximum absolute value: hereinafter referred to as “pulse voltage” or “pulse voltage value”) and a predetermined pulse width (hereinafter referred to as “voltage pulse width or NRZ (None-Return-to-Zero) and RZ (Return-to-Zero) signals, as well as PWM (Pulse Width Modulation) signals. The “voltage pulse” includes a single voltage pulse in one cycle unit and a “voltage pulse train” having a predetermined frequency (hereinafter referred to as “pulse frequency”).

  The switching transistor 4 serves as a switch for making the resistance variable variable resistance element 1 and the capacitor 5 and the operational amplifier 6 conductive or nonconductive. In FIG. 1, “OFF” is described because it is a non-conduction state.

  When the capacitor 5 is in conduction with the switching transistor 4, the information written from the data line 2 and the bit line 3 to the variable resistance variable resistance element 1 is stored as a charge amount as described below. Is.

  The operational amplifier 6 provides feedback by providing a capacitor 5 between the negative input terminal (−) and the output terminal, and constitutes an integration circuit. In this case, a constant bias voltage is applied to Vref.

  As a result, the input to the negative input terminal (−) is virtually grounded by the feedback function of the operational amplifier 6, so that an effect of suppressing potential fluctuation due to the accumulation of charges in the capacitor 5 can be obtained.

  Here, based on FIG. 4, the physical characteristic that the electrical resistance reversibly changes by applying the voltage pulse of the variable resistance variable resistance element 1 will be described.

  FIG. 4 shows a structure of the variable resistance variable resistance element 1 and an equivalent circuit at the time of measurement. For example, as shown in FIG. 4, an RRAM (Resistance RAM: variable resistance variable resistance element) includes an upper electrode (one terminal, the other terminal) 11A, a lower electrode (one terminal, the other terminal) 11B, and The resistor 12 is provided.

  The resistor 12 is made of a metal oxide and has a structure sandwiched between the upper electrode 11A and the lower electrode 11B.

  By applying a pulse voltage to the RRAM, the electric resistance changes, and the resistance value is retained even when the power is turned off, and it works as a nonvolatile memory. Usually, an operation that transitions from a high resistance state to a low resistance state is defined as a “SET (set) operation”, and an operation that transitions from a low resistance state to a high resistance state is defined as a “RESET (reset) operation”.

  A system that applies voltage pulses of the same polarity in both the SET operation and the RESET operation is referred to as a “unipolar switching system (monopolar operation)”, and a system that applies a reverse polarity pulse is referred to as a “bipolar switching system (bipolar operation)”.

  FIG. 5A shows the number of times a pulse voltage (amplitude value 2.6 V) is applied to the resistance variable variable resistance element 1 (PRAM) at 35 nsec intervals (SET pulse frequency), and the resistance variable variable resistance element 1 at that time. Shows the relationship with the current flowing through.

  As shown in FIG. 5A, it can be seen that the current flowing through the resistance variable variable resistance element 1 can be controlled according to the number of SET pulses.

  That is, in the product-sum operation apparatus 10, the first input signal and the second input signal are a single voltage pulse and a voltage pulse train, respectively, and the voltage pulse width of the single voltage pulse and the pulse frequency of the voltage pulse train are It can be configured to control the number of SET pulses (output value) as a calculation result.

  The variable resistance variable resistance element 1 can control the current flowing through the element according to the number of SET pulses. Therefore, the element obtained as the product of the magnitude of the voltage pulse width of the single voltage pulse corresponding to the multiplicand input to the terminal A of the element and the pulse frequency of the voltage pulse train corresponding to the multiplier input to the terminal B of the element The value of the current flowing through the element is determined according to the number of SET pulses to. That is, the correspondence relationship between the result of the multiplicand, the multiplier, and the product operation, the voltage pulse width of the single voltage pulse, the pulse frequency of the voltage pulse train, and the number of SET pulses (current value) to the variable resistance variable resistance element is shown in advance. Once determined, product operations can be performed.

  Next, FIG. 5B shows the voltage pulse width of the pulse voltage applied to the resistance variable variable resistance element 1 (PRAM) (the time when the pulse voltage having an amplitude value of 2.6 V is applied: the unit is ns), and at that time The relationship with the electric current which flows into the resistance change type variable resistance element 1 is shown.

  That is, each of the first input signal and the second input signal is a single pulse, the voltage pulse width of the single voltage pulse of the first input signal, and the pulse voltage value of the single voltage pulse of the second input signal. It is also possible to control the pulse voltage value and the voltage pulse width for the element obtained as a product of

  The variable resistance variable resistance element 1 can control the current flowing through the element according to the voltage pulse width and the pulse voltage value. Therefore, to the element obtained as the product of the magnitude of the voltage pulse width corresponding to the multiplicand input to the terminal B (corresponding to the application time of the voltage pulse) and the pulse voltage value corresponding to the multiplier input to the terminal A The current value flowing through the element is determined according to the voltage pulse width and the pulse voltage value. That is, the correspondence between the result of the multiplicand, multiplier, and product operation, the voltage pulse width, the pulse voltage, and the voltage pulse width and pulse voltage value (current value) to the variable resistance variable resistance element 1 can be determined in advance. For example, a product operation can be executed.

  FIG. 5C shows the relationship between the pulse voltage value when a predetermined pulse voltage is applied to the resistance variable variable resistance element 1 and the current flowing through the resistance variable variable resistance element 1 at that time.

  As shown in FIG. 5 (c), there is no change up to about 0.5V, but with a voltage higher than that, the current flowing through the resistance variable resistance element 1 can be controlled according to the pulse voltage value. I understand that.

  Next, based on FIG. 1 to FIG. 3B, an operation when the product-sum operation apparatus 10 is configured with a single variable resistance variable resistance element 1 will be described.

  FIG. 1 shows a write operation of the product-sum operation apparatus 10. At the time of writing, the resistance change type variable resistance element 1 and the capacitor 5 that stores the operation result are not electrically connected. Yes.

  In such a state, first, voltage pulses are applied to the bit line 3 and the data line 2 connected to the variable resistance variable resistance element 1.

  FIG. 2A is a waveform diagram showing a state of a voltage pulse (pulse width Ti) inputted to the terminal A (bit line) of the resistance variable variable resistance element 1, and FIG. FIG. 2C is a waveform diagram illustrating a state of a voltage pulse (pulse frequency Fi) input to (data line), and FIG. 2C is a waveform diagram illustrating a relationship between a potential difference between terminals A and B and a threshold potential Vth. is there.

  At this time, a single voltage pulse defined by the pulse width = Ti shown in FIG. On the other hand, a voltage pulse train defined by pulse frequency = Fi shown in FIG. 2B is applied to the data line 2.

  FIG. 1 shows a single voltage pulse and a voltage pulse train applied between variable resistance elements. As shown in FIG. 2C, a voltage value equal to or higher than the threshold value represented by the threshold potential Vth is shown. In this case, information represented by conductance σii∝Fi · Ti is written in the resistance variable variable resistance element 1 (conductance σii is the reciprocal of the resistance value Rii of the resistance variable variable resistance element 1. .) The variable resistance variable resistance element 1 has a function of holding the conductance σii as written information (holding the result of product operation of multiplicand and multiplier) even when the power is turned off. Information is never lost.

  In other words, the resistance variable variable resistance element 1 stores the result of product calculation by inputting a single voltage pulse and a voltage pulse train by a change in the electric resistance (corresponding to the conductance σii) of the resistance variable variable resistance element 1. is there.

  Here, a problem different from the above-described problems of the prior art described in Patent Documents 1 and 2 will be described. In the prior art, each of the switched current sources (SCS) does not have a function of recording or erasing information, so that each output value (result of product operation) of each switched current source (SCS) is obtained. There is a problem that it cannot be reused.

  However, as described above, the variable resistance variable resistance element 1 can control the current flowing through the element in accordance with the number of voltage pulse applications (the number of SET pulses), and the element in accordance with the voltage pulse width and the pulse voltage value. The current flowing through the can be controlled.

  In other words, in the variable resistance variable resistance element 1, the electric resistance of the element changes according to the number of voltage pulse applications or according to the voltage pulse width and the pulse voltage value.

  That is, the variable resistance variable resistance element 1 stores the result of product calculation by inputting a single voltage pulse and a voltage pulse train (or pulse voltage) as a change in the electrical resistance of the variable resistance variable resistance element 1. As a result, it is possible to store the result of product calculation by the variable resistance variable resistance element 1 itself.

  Next, as shown in FIGS. 3A and 3B, a read operation of the product-sum operation apparatus 10 will be described. At the time of reading, the variable resistance variable resistance element 1 and the capacitor 5 that accumulates the product calculation result as a charge amount are electrically connected.

  FIG. 3A is a circuit diagram showing a configuration at the time of reading of the product-sum operation apparatus 10 constituted by a single cell having the resistance variable variable resistance element 1 as a unit cell, and FIG. FIG. 11 is a sequence diagram showing the operation of the product-sum operation apparatus 10.

  By fixing the data line 2 to 0 V and applying a voltage pulse defined by the pulse voltage value = Vo and the voltage pulse width = To to the bit line 3, the resistance variable variable resistance element 1 has σii · Vo∝. A current indicated by Fi · Ti · Vo flows, and the capacitor 5 accumulates the charge amount defined by the charge amount Q = σii · Vo · To∝Fi · Ti · Vo · To.

  By alternately repeating the writing and reading described above, the product-sum operation result defined by the charge amount Q = (Σσii) · Vo · To∝ (ΣFi · Ti) · Vo · To is accumulated in the capacitor. It will be.

  Further, as shown in FIGS. 3A and 3B, after the (write → read) process, it is necessary to perform a reset operation to initialize.

  In other words, the product-sum operation apparatus 10 can erase the result of the product operation stored by the change in electrical resistance by applying a predetermined voltage pulse to the resistance variable variable resistance element 1.

  For example, when the variable resistance variable resistance element 1 is operated in a bipolar manner, a voltage pulse having the same time (pulse width) and voltage (pulse voltage value) as that at the time of writing is applied again with a different polarity. Thus, the result of the product operation stored by the change in electrical resistance can be erased. When the variable resistance variable resistance element 1 is monopolarly operated, a voltage pulse having the same polarity and a long time (pulse width) is applied again, so that the product operation result stored by the change in the electrical resistance is obtained. Can be erased.

In the present embodiment, the size of the variable resistance variable resistance element 1 is a size indicated by 4F2 (F: design rule). For example, when the design rule is 0.1 μm, the basic element size of the product-sum calculation apparatus 10 is 0.04 μm ² , which is about 2 to 3 digits in comparison with the conventional technique shown in FIG. The area can be reduced. In the prior art, there are a plurality of switched current sources, and thus a product-sum operation device is formed. However, in this embodiment, the element configuration can be configured by a single resistance variable variable resistance element 1. The element size can be reduced.

  As described above, according to the product-sum operation apparatus 10 including the variable resistance variable resistance element 1, the first input signal corresponding to the multiplicand (here, the pulse) is applied to the terminal A of the variable resistance variable resistance element 1. A single voltage pulse signal having a width Ti), and a second input signal (here, a voltage pulse train having a pulse frequency Fi) corresponding to a multiplier multiplied by the multiplicand is input to the terminal B. An output value corresponding to the result of the product operation with the multiplier is output.

  The big point in the above configuration is that the resistance variable variable resistance element 1 uses the physical characteristic that the electrical resistance (or conductance σii) reversibly changes when a voltage pulse is applied.

  That is, if the correspondence relationship between the result of the multiplicand, multiplier, and product operation, the voltage pulse width, the pulse frequency, and the output value (current value, etc.) of the variable resistance variable resistance element 1 is determined in advance, the product operation is performed. It is possible to execute.

  Thereby, a signal corresponding to the multiplicand is input from one terminal, and a signal corresponding to the multiplier to be multiplied by the multiplicand is input from the other terminal, so that an output corresponding to the result of the product operation of the multiplicand and the multiplier There is no need to configure a product operation device that outputs a value as a switched current source (SCS) having a constant current source and a switch circuit as in the prior art.

  Here, the variable resistance variable resistance element 1 is an element whose electric resistance reversibly changes when a voltage pulse is applied. In recent years, the variable resistance variable resistance element 1 is expected to be applied as a next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of a flash memory. Examples of the resistance variable variable resistance element 1 include RRAM (Resistance RAM) and PCRAM (Phase Change RAM) as described in Non-Patent Document 1.

  Examples of the first signal include a PWM (Pulse Width Modulation) signal, and examples of the second signal include a pulse train having a predetermined cycle and a voltage pulse.

  As described above, it is possible to provide the product-sum operation apparatus 10 capable of simplifying the configuration of the product-sum operation apparatus 10 and reducing the occupied area of the product-sum operation apparatus 10 with respect to the area of the entire circuit including these apparatuses. .

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. 6 (a) and 6 (b). Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  FIG. 6A is a circuit diagram showing a configuration and a write operation of the product-sum operation apparatus 10 constituted by a single cell, and FIG. 6B is a circuit diagram showing a read operation. In the second embodiment, the configuration of the product-sum operation apparatus is the same as that of the first embodiment, but FIG. 1, FIG. 2 (a) to FIG. 2 (c) and FIG. 3 (a). -FIG.3 (b) is another operation | movement method.

  That is, in the present embodiment, at least one product-sum operation device 10 is provided, and the output value for each set output from the product-sum operation device 10 by the input of a plurality of sets of single voltage pulses and voltage pulse trains. An output value (second output value) corresponding to the accumulated value may be output.

  Here, in the conventional product-sum operation apparatus, there is an example in which a plurality of sets of inputs are given to a single switched current source and are sequentially stored in a capacitor unless reduction in processing speed is considered.

  However, the switched current source is provided with a switch circuit and a constant current source, and the element size is considerably larger than that of the product calculation device configured by the single variable resistance element 1 of the present embodiment. .

  Therefore, even in the case where a plurality of sets of inputs are given to the product-sum operation apparatus 10 constituted by a single cell of the variable resistance variable resistance element 1 and the capacitors 5 are sequentially stored, the conventional single switched current is used. Compared to a product-sum operation device using a source, the area occupied by the product operation device with respect to the area of the entire circuit including these devices can be reduced.

  In the present embodiment, the configuration itself may be the same as that of the first embodiment, so the operation of the product-sum operation apparatus 10 in the second embodiment will be described below.

  Here, the case where the operation sequence of the first embodiment is changed and the processing steps are further reduced will be described.

  In the write operation shown in FIG. 6A, first, a single voltage pulse defined by a pulse width T1 is applied to the bit line 3, and a voltage pulse train defined by a pulse frequency = F1 is applied to the data line 2. Is applied.

  In this case, information indicated by conductance σ11∝F1 · T1 is written in the variable resistance variable resistance element 1.

  Next, a single voltage pulse defined by a pulse width T2 is applied to the bit line 3, and a voltage pulse train defined by a pulse frequency = F2 is applied to the data line 2.

  In this case, information represented by conductance (σ11 + σ22) ∝ (F1 · T1 + F2 · T2) is written in the variable resistance variable resistance element 1.

  By repeating the same writing process, information represented by Σσii = Σ (Fi · Ti) is finally written in the variable resistance variable resistance element 1.

  That is, in the product-sum operation apparatus 10 according to the present embodiment, the resistance variable variable resistance element 1 is a variable resistance variable variable that is configured to calculate a cumulative result of the product operation for each set by inputting a plurality of sets of single voltage pulses and voltage pulse trains. The data is stored by changing the electric resistance of the resistance element 1.

  As described above, the variable resistance variable resistance element 1 can control the current flowing through the element in accordance with the number of voltage pulses applied, and can control the current flowing in the element in accordance with the voltage pulse width and the pulse voltage value.

  In other words, in the variable resistance variable resistance element 1, the electric resistance of the element changes according to the number of voltage pulse applications or according to the voltage pulse width and the pulse voltage value.

  That is, the variable resistance variable resistance element 1 stores the cumulative result of the product operation for each set by the input of a plurality of sets of single voltage pulses and voltage pulse trains according to the change in electrical resistance of the variable resistance variable resistance element 1. . Thereby, the accumulation result of the product calculation by the product-sum calculation apparatus 10 (resistance variable variable resistance element 1) itself of the present embodiment can be stored.

  Next, in the read operation, as shown in FIG. 6B, the data line 2 is fixed to 0 V, and the voltage pulse defined by the pulse voltage value = Vo and the voltage pulse width = To is applied to the bit line 3. Apply. In this case, a current represented by (Σσii) · Vo = Σ (Fi · Ti) · Vo flows through the resistance variable variable resistance element 1, and a charge amount Q = Σσii · Vo · To∝ΣFi flows through the capacitor 5. The result of the product-sum operation defined by Ti, Vo, and To (accumulated result of the product operation) is accumulated.

  In order to newly perform a product-sum operation process, it is necessary to perform a reset process once after data reading and to initialize it.

  That is, the product-sum operation apparatus 10 of the present embodiment can erase the accumulated result of the product operation stored by the change in the electrical resistance by applying a predetermined voltage pulse to the resistance variable variable resistance element 1. It has become.

  For example, when the variable resistance variable resistance element 1 is operated in a bipolar manner, it is memorized by the change in the electrical resistance by reapplying a voltage pulse having the same time and voltage as the pulse at the time of writing but having a different polarity. The result of the product operation can be deleted. Further, when the variable resistance variable resistance element 1 is operated in a monopolar manner, the result of the product operation stored by the change in the electrical resistance is erased by reapplying a pulse having the same polarity and a long time. Can do.

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first and second embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 and 2 are given the same reference numerals, and explanation thereof is omitted. In the following [Embodiment 4], the same description is omitted.

  In this embodiment, the resistance variable variable resistance element 1 described in the first and second embodiments is used as a unit cell, and an array configuration (matrix arrangement) in which unit cells are arranged at intersections of a plurality of bit lines and data lines. The product-sum operation apparatus 100 will be described.

  FIG. 7A shows a plurality of cells (resistance change type variable resistance element (product operation device) 111, resistance change type variable resistance device (product operation device) 121, resistance, resistance cell, variable resistance element 1. FIG. 2 is a circuit diagram showing a configuration at the time of writing of a product-sum operation device 100 configured by a variable variable resistance element (product operation device) 211, a resistance change type variable resistance element (product operation device) 221. FIG. 7B shows a state of a voltage pulse (pulse width Tj: j is a natural number) input to the terminal A (bit line) of the resistance variable variable resistance element 1 (resistance variable variable resistance element 111). It is a waveform diagram, (c) is a waveform diagram showing the state of the voltage pulse (pulse frequency Fi) input to the terminal B (data line), (d) is the potential difference between the terminals A and B and the threshold value It is a wave form diagram which shows the relationship with the electric potential Vth.

  FIG. 8 shows a plurality of cells (the resistance variable variable resistance element 111, the resistance variable variable resistance element 121, the resistance variable variable resistance element 211, the resistance variable variable resistance, which have the resistance variable variable resistance element 1 as a unit cell. It is a circuit diagram which shows the structure at the time of the reading of the product-sum calculation apparatus comprised by the element 221 ...).

  As shown in FIGS. 7A to 8, the product-sum operation apparatus 100 according to this embodiment includes a plurality of resistance variable variable resistance elements 1 (resistance variable variable resistance element 111, resistance variable variable resistance element 121, Resistance change type variable resistance element 211, resistance change type variable resistance element 221..., And an output value corresponding to a cumulative value of output values output from each of the plurality of resistance change type variable resistance elements 1. The second output value may be output.

  According to the above, since writing to and reading from a plurality of variable resistance variable resistance elements can be processed at the same time, compared with the case where the product-sum calculation apparatus is configured with a single variable resistance variable resistance element, the product calculation The processing speed for writing and reading the accumulated result is increased.

  As shown in FIG. 7A and FIG. 8, the product-sum operation apparatus 100 of this embodiment includes a data line 1i2 (data lines 112, 122..., I is a natural number), a bit line 1j3 (bit lines 113, 123...: J is a natural number), variable resistance variable resistance element (product arithmetic unit) ij 1 (resistance variable variable resistance elements 111, 121, 211, 221...: I, j are natural numbers), switching transistor 1i4 (switching transistors 114, 124 ...: i is a natural number), capacitor 1i5 (capacitor 115, capacitor 125 ...: i is a natural number), operational amplifier 1i6 (op amps 116, 126 ...: i is a natural number), The switching transistor 1j7 (switching transistors 117, 127..., I is a natural number) is configured.

  As shown in FIG. 7A, in the product-sum calculation apparatus 100, a read circuit is connected to the data line 1i2 (data lines 112, 122..., I is a natural number). FIG. 7A shows a write operation. At the time of write, the resistance change type variable resistance element and the capacitor for storing the calculation result are not electrically connected.

  At this time, a single voltage pulse defined by a pulse width = Tj is applied to the bit line 1j3 (bit line 113, bit line 123..., J is a natural number).

  Note that the transistor connected to the bit line 1j3 is in a conductive state. A plurality of pulse voltages defined by the pulse frequency = Fi are applied to the data line 1i2.

FIG. 7A describes the voltage applied between the resistance variable variable resistance elements. When a voltage value equal to or higher than the threshold value represented by the threshold potential Vth is applied, the bit lines 1j3 and Variable resistance element (product calculation device) ij1 selected by the data line 1i2 (resistance variable variable element 111, variable resistance variable element 121, variable resistance variable element 211, variable resistance variable element 211, variable resistance variable element) 221...: I, j are natural numbers), information indicated by conductance σij∝Fi · Tj is written. (The conductance σij is the reciprocal of the element resistance value Rij.)
Note that the variable resistance variable element ij1 has a function of holding data, so that written information does not disappear even when the power is turned off.

  In other words, the resistance variable variable resistance element ij1 stores the result of product operation by inputting a single voltage pulse and a voltage pulse train by a change in the electric resistance (corresponding to the conductance σij) of the resistance variable variable resistance element ij1. is there.

  Here, a problem different from the above-described problems of the prior art described in Patent Documents 1 and 2 will be described. In the prior art, each of the switched current sources (SCS) does not have a function of recording or erasing information, so that each output value (result of product operation) of each switched current source (SCS) is obtained. There is a problem that it cannot be reused.

  However, as described above, the variable resistance variable element ij1 can control the current flowing through the element in accordance with the number of application of voltage pulses (the number of SET pulses), and the element in accordance with the voltage pulse width and the pulse voltage value. The current flowing through the can be controlled.

  In other words, in the resistance variable variable resistance element ij1, the electrical resistance of the element changes according to the number of voltage pulse applications or according to the voltage pulse width and the pulse voltage value.

  That is, the resistance variable variable resistance element ij1 stores the result of product operation by inputting a single voltage pulse and a voltage pulse train (or pulse voltage) by a change in electric resistance of the resistance variable variable resistance element ij1. As a result, it is possible to store the result of product calculation by the variable resistance variable element ij1 itself.

  Next, the read operation of the product-sum operation apparatus 100 will be described with reference to FIG.

  At the time of reading, the variable resistance variable element ij1 and the capacitor 1i5 (capacitor 115, capacitor 125..., I is a natural number) that accumulates the calculation result as a charge amount are in a conductive state. .

  A variable resistance variable resistance element connected on the data line 1i2 by fixing the data line 1i2 to 0V and applying a voltage pulse defined by a pulse voltage value = Vo and a voltage pulse width = To to the bit line 1j3 A current represented by (Σσij) · Vo∝ (ΣFi · Tj) · Vo flows through ij1, and a charge amount Q = (Σσij) · Vo · To∝ (ΣFi · Tj) · Vo · To flows through the capacitor 1i5. The charge amount defined by is accumulated.

  In addition, a method of detecting a current for adding data is also possible. For example, in the present embodiment, the result of product operation of the plurality of variable resistance variable elements ij1 is merely summed, and therefore, in the method of detecting current, it is only necessary to connect the lines and view the current with a resistor. It will be. Since the potential of the common line changes when a resistor is directly connected, an adder circuit using an operational amplifier may be used as in the method using the charge amount Q stored in the capacitor 1i5.

  In order to perform a new sum-of-products operation process after the reading is completed, it is necessary to perform a reset operation and initialize.

  For example, when the variable resistance variable element ij1 is operated in a bipolar manner, a voltage pulse having the same time (pulse width) and voltage (pulse voltage value) as that at the time of writing is applied again with a different polarity. Thus, the result of the product operation stored by the change in electrical resistance can be erased. In addition, when the variable resistance variable element ij1 is monopolarly operated, a voltage pulse having the same polarity and a long time (pulse width) is applied again, so that the product operation result stored by the change in the electrical resistance is obtained. Can be erased.

  In the present embodiment, since writing to and reading from a plurality of cells can be performed simultaneously, the data processing speed is faster than the product-sum operation apparatus 10 of the first and second embodiments. If the information written in the variable resistance variable element ij1 is not to be read, the switching transistor 1j7 (switching transistor 117, switching transistor 127...: J is a natural number) of the bit line 1j3 connected to the cell. ) Is turned off, reading becomes impossible, and as a result, partial product-sum operation is possible.

  As for the element area, the unit cell size is represented by 4F2 (F: design rule) as in the product-sum operation apparatus 10 of the first and second embodiments. However, since it is composed of a plurality of cells, the area of the product-sum operation apparatus 100 as a whole is larger than that of the product-sum operation apparatus 10 of the first and second embodiments.

  As described above, the product-sum operation apparatus 100 according to the present embodiment calculates the accumulated output value output from each of the predetermined number of variable resistance variable elements ij1 from among the variable resistance variable elements ij1. A corresponding output value (third output value) may be output.

  According to the above configuration, the third output value (partial sum) corresponding to the cumulative value of the output values output from each of the predetermined number of variable resistance elements ij1 is output. Calculation (partial sum calculation) is possible.

  In addition to the above-described configuration, the product-sum operation apparatus according to the present invention accumulates output values output from each of a predetermined number of variable resistance variable elements ij1 among the variable resistance variable elements ij1. It is preferable to include a capacitor 1i5 (storage unit) that stores values.

  As described above, by appropriately providing the capacitor 1i5 and the like, the plurality of variable resistance variable elements ij1 are divided into a plurality of block parts, and the variable resistance variable element ij1 is divided into a plurality of block parts. Among these, the cumulative value of the output values output from each of the predetermined number of variable resistance elements ij1 can be stored. Moreover, since the accumulation result of the product operation can be immediately extracted if it is recorded in the capacitor 1i5, the calculation process of the partial sum stored in the capacitor 1i5 is accelerated for each block portion.

[Embodiment 4]
A product-sum operation apparatus 20 according to still another embodiment of the present invention will be described below with reference to FIGS. 9 (a) to 10 (b).

  FIG. 9A is a circuit diagram showing a configuration of a product-sum operation apparatus 20 configured by a single cell using the resistance variable variable resistance element 21 as a unit cell, and FIG. 9B is a resistance variable type. FIG. 9C is a waveform diagram showing a state of a voltage pulse (pulse width Ti) input to the terminal A (bit line) of the variable resistance element 21, and FIG. 9C shows the potential difference between the terminals A and B and the threshold potential Vth. It is a wave form diagram which shows the relationship.

  FIG. 10A shows a configuration of the product-sum operation apparatus 20 and a read operation method using a voltage pulse time (corresponding to a voltage pulse width) and a voltage pulse amplitude (pulse voltage) as a multiplier and a multiplicand, respectively. FIG. 10B is a sequence diagram illustrating a read operation method.

  The product-sum operation apparatus 20 of this embodiment outputs a result of these product operations by inputting a multiplicand and a multiplier. As shown in FIG. 9A, the variable resistance variable resistance element 21, a data line 22, a bit line 23, a switching transistor 24, a capacitor (storage unit) 25, a comparator 26, and a switching transistor 27.

  Unlike the product-sum operation device 10, the capacitor 25 is not connected between the input and output terminals of the comparator 26 (does not constitute a feedback circuit), and a switching transistor 27 is newly provided on the data line 22. This is the point.

  In the present embodiment, as shown in FIG. 9A, a product-sum operation device 20 is configured by a single cell using a single variable resistance element 21 as a unit cell, and a voltage pulse amplitude (Vi: pulse voltage value). ) And voltage pulse time (Ti: equivalent to voltage pulse width) will be described respectively for the multiplier and multiplicand.

  As shown in FIG. 9A, at the time of writing, the resistance variable variable resistance element 21 and the capacitor 25 that accumulates the calculation result as a charge amount are not in conduction.

  First, a voltage pulse is applied to the bit line 23 and the data line 22 connected to the resistance variable variable resistance element 21. At this time, a single voltage pulse defined by voltage pulse amplitude = Vi is applied to the bit line 23.

  The data line 22 is connected to the ground, but normally the switching transistor (select transistor) 27 between the data line 23 and the cell is OFF (high impedance state).

The switching transistor 27 is turned on only during the time when data writing is desired (Ti: equivalent to the voltage pulse width of a single voltage pulse). FIG. 16A shows the voltage applied to the terminals A and B of the variable resistance variable resistance element 21, but when a voltage value equal to or higher than the threshold value represented by the threshold potential Vth is applied, Information indicated by conductance σii∝Ti · Vi is written in the resistance variable variable resistance element 21. (The conductance σii is the reciprocal of the element resistance value Rii.)
The variable resistance variable element 21 has a function of holding data in the same manner as the variable resistance variable element 1 and the like described above, so that written information will not be lost even when the power is turned off. .

  Next, a read operation of the product-sum operation apparatus 20 will be described with reference to FIG. At the time of reading, the resistance variable variable resistance element 21 and the capacitor 25 that accumulates the result of product operation as a charge amount are in a conductive state.

  By fixing the data line 22 to 0V and applying a pulse voltage defined by a pulse voltage value = Vo and a voltage pulse width = To to the bit line 23, the resistance variable variable resistance element 21 has σii · Vo∝. A current indicated by Ti, Vi, and Vo flows, and the capacitor 25 accumulates the charge amount defined by the charge amount Q = σii · Vo · To∝Ti · Vi · Vo · To.

  By alternately repeating the writing and reading described above, the accumulation result of the product operation defined by the charge amount Q = (Σσii) · Vo · To∝ (ΣTi · Vi) · Vo · To is accumulated in the capacitor 25. It will be done.

  As shown in FIG. 17B, after the write / read process, as described above, it is necessary to perform a reset operation and initialize. The element size of the variable resistance variable resistance element 21 in the product-sum operation apparatus 20 of the present embodiment is represented by 4F2 (F: design rule).

  For example, when the design rule is 0.1 μm, the basic element size of the product-sum calculation device 20 is 0.04 μm 2, which is about 2 to 3 digits compared to the prior art shown in FIGS. The element area can be reduced.

  In addition, the operation method using the voltage pulse amplitude and voltage pulse time as a multiplier and a multiplicand is shown in the present embodiment, the processing sequence shown in the second embodiment is changed, and the plurality of cell configurations shown in the third embodiment are used. It is also possible to configure in the same manner as described above.

[Embodiment 5]
A product-sum operation circuit (product operation device, product-sum operation device) 30 according to still another embodiment of the present invention will be described below with reference to FIG.

  The product-sum operation circuit 30 provides a low-power consumption and high-speed product-sum operation circuit by controlling the operation order and operation range of the operand values in the product-sum operation. That is, by sorting the output values in descending order or ascending order, unnecessary potential changes are suppressed, and low power consumption and high speed are realized.

  FIG. 11 is a block diagram showing a configuration of each processing block of the product-sum operation circuit 30 according to the embodiment of the present invention. In the present embodiment, a specific example in the case of using the product-sum operation apparatus 100 in the third embodiment will be described.

  As shown in FIG. 11, the product-sum operation circuit 30 includes an input value holding block (calculated value holding block) 31, a sorting block 32, a switching block (1) 33, a load value holding block (operated value holding block) 34, The switching block (2) 35 and the arithmetic processing block 36 are provided.

  As shown in FIG. 11, the product-sum operation circuit 30 is different from the conventional product-sum operation circuit 3000 shown in FIG. 15 in that the operation processing block 36 can be configured by a single product-sum operation device 100. ing.

  That is, in the prior art, in order to perform a plurality of (n: n is a natural number) product-sum operation processing, a plurality (n) of operation blocks are required. In the product-sum operation circuit 30, an array structure in which the resistance change type variable resistance element 1 is arranged in each of the predetermined regions at positions intersected by the bit lines and the data lines is applied. Multiple product-sum operations. Further, since the unit cell portion of the arithmetic processing block 36 becomes small, the arithmetic processing block 36 can be reduced by about two to three digits as compared with the prior art.

  The input value holding block (calculated value holding block) 31 holds a calculated value (multiplier) Xi.

  The sorting block 32 outputs the calculated values Xi in order of increasing or decreasing values.

  The switching block (1) 33 is for inputting the operation value Xi to a terminal corresponding to the label i of the operation value Xi of the operation processing block 36.

  The load value holding block (calculated value holding block) 34 holds the calculated value (multiplicand) Wi.

  The switching block (2) 35 inputs the operand value Wi to a terminal corresponding to the label i of the operand value Wi of the arithmetic processing block 36.

  Note that i of the calculation value Xi and the value to be calculated Wi are subscripts representing different X and W, respectively, and take 1, 2, 3,... Natural numbers (the same applies hereinafter).

  Next, an operation processing step by the product-sum operation circuit 30 in the present embodiment will be described.

  First, as shown in FIG. 11, the plurality of operation values Xi are held in the input value holding block 31 and further sorted and output by the sorting block 32 in order of increasing or decreasing value.

  Here, in the present embodiment, when there are operation values Xi having the same value, the order of output between the operation values having the same value is arbitrary, but an appropriate order may be set in advance. .

  Subsequently, the label i included in the operation value Xi is input from the sorting block 32 to the switching block (1) 33, and the switching block (1) 33 performs switching according to the label i and is output from the sorting block 32. The calculated value Xi is input to the terminal corresponding to the label i.

  Here, in the present embodiment, the processing executed by the input value holding block 31 and the sorting block 32 described above is realized using an associative memory circuit (not shown).

  This associative memory circuit holds the value of the operation value Xi, the label i of each operation value Xi, and the detection flag.

  The associative memory circuit has a function of comparing the input search value with the stored data and outputting a data whose values match. By utilizing the general function of this associative memory circuit, reading the values and labels one by one in descending order from the calculated value Xi for which no detection flag is set, and setting the detection flag to the read value The processing executed by the input value holding block 31 and the sorting block 32 can be realized.

  That is, it is possible to realize a sorting function by inputting one by one in ascending order from the value corresponding to the maximum value of the operation value Xi to the associative memory circuit and sequentially reading the data with the matching values. (Conversely, it is possible to read out in ascending order of the calculated value Xi).

  In this embodiment, as described above, the functions of the input value holding block 31 and the sorting block 32 are realized by the associative memory circuit. However, the specific circuit configuration is not the main point of the present invention, and the same processing is performed. If possible, other processing configurations may be used.

  On the other hand, the plurality of operand values Wi output from the load value holding block 34 are respectively input to predetermined terminals of the arithmetic processing block 36. Here, in the present embodiment, similarly to the calculation value Xi, the operation value Wi is switched in the switching block (2) 35 according to the label i of the calculation value Xi, and is determined by the label i. It is input to a predetermined terminal.

  Unlike the present embodiment, it is also possible to use a method that is set in advance for the calculation block to which the calculation value Wi is input, without depending on the label i of the calculation value Xi. Further, the value of the operand value Wi input to each terminal may be the same or different for each calculation.

  In the present embodiment, the load value holding block 34 may be configured by a general SRAM (static random access memory) circuit, but other processing configurations may be used as long as similar processing is possible. good. By executing the above processing, the calculated value Xi and the calculated value Wi are input to a predetermined calculation block.

  Since the subsequent processing is the same as that of the third embodiment, description thereof is omitted.

[Embodiment 6]
A neural network 40 according to still another embodiment of the present invention will be described below with reference to FIGS. The configuration other than that described in the present embodiment is the same as that of the fifth embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the fifth embodiment are given the same reference numerals, and explanation thereof is omitted.

  FIG. 12 is a configuration diagram of an operation processing block when the product-sum operation method is applied to the neural network 40 according to the embodiment of the present invention.

  FIG. 13 is a flowchart of each step in the calculation process when the product-sum calculation method is applied to the neural network 40.

  As shown in FIG. 12, the neural network 40 includes a product-sum operation circuit 30A, a product-sum operation circuit 30B, a function processing block 41A, and a function processing block 41B.

  The product-sum operation circuit 30A and the product-sum operation circuit 30B have the same configuration as the product-sum operation circuit 30 described in the fifth embodiment.

  Therefore, in the present embodiment, the product-sum operation circuit 30A, the product-sum operation circuit 30B, and the like are connected via the function processing block 41A, the function processing block 41B, and the like to constitute a neural network. It is different from 5.

  That is, the operation value Xi described in FIG. 11 corresponds to the output value of the previous neuro element, and the operation value Wi corresponds to the synapse load value, which determines the internal state value of the neuron element.

  Next, the operation of the neural network 40 will be described based on the flowchart of FIG.

  In step S1 (hereinafter, “step” is omitted), the output value of each neuron element in the previous stage of the neural network 40 is calculated as the operation value Xi, and the product-sum operation in one neuron element in the next stage is uniquely associated. The value is input to the input value holding block 31A of the circuit 30A, and the process proceeds to S2.

  “Unique correspondence” is a concept including “one-to-one correspondence” and “other-to-one correspondence”.

  More specifically, “one-to-one correspondence” is a correspondence relationship when a value obtained by weighting the output value of one neuron element in the previous stage with a synapse load value is input to one neuron element in the next stage. That is.

  Also, “other-to-one correspondence” is a correspondence relationship when the sum of values weighted by synaptic load values for the output values of a plurality of neuron elements in the previous stage is input to one neuron element in the next stage. That is.

  In S2, the input value holding block 31A passes the input operation value Xi to the sorting block 32A according to the label i, and proceeds to S3.

  “Label i” is information for identifying the output neuron element.

  In S3, the sorting block 32A arranges the operation values Xi in the order of increasing value or decreasing value, and proceeds to S4.

  In S4, the sorting block 32A determines and determines a flag for designating a predetermined storage area in a memory (not shown) in which the operation values Xi arranged in the descending order from S3 are stored in S3. The flag and the label i or the calculated value Xi are transmitted to the switching block (1) 33A, and the process proceeds to S5.

  In S5, the switching block (1) 33A reads the operation value Xi and the label i stored in the memory and inputs them to a predetermined terminal of the operation processing block 36A.

  In parallel with S1 to S5, S6 to S9 proceed.

  In S6, the operation value Wi corresponding to the operation value Xi is input to the load value holding block 34A of one neuron element in the next stage as a synapse load value, and the process proceeds to S7. The operand value Wi is associated with the label i.

  In S7, the load value holding block 34A determines a flag for designating a predetermined storage area in a memory (not shown) in which the operation value Wi is stored, and the process proceeds to S8.

  In S8, the load value holding block 34A receives the label i corresponding to the calculated value Wi from the sorting block 32A, and stores the calculated value Wi and the label i in a predetermined area in the memory based on the determined flag. Proceed to S9.

  In S9, based on the flag determined in S7, the switching block (2) 35A inputs the operand value Wi and the label i held in the memory in S8 to predetermined terminals of the arithmetic processing block 36A, and S10 Proceed to

  In S10, an accumulated value from i = 1 as a result of product operation of the operation value Xi and the operand value Wi to a predetermined number of the preceding neuron elements is calculated and input to the function processing block 41A in the operation processing block 36A. To S11.

  In S11, the accumulated value is function-processed by the function processing block 41A, and the process proceeds to S12.

  In S12, the function processing block 41A inputs the output value after the function processing to the product-sum operation circuit 30B in the subsequent stage (next stage).

  In the neural network 40 of this embodiment, each process from S1 to S12 is repeated.

  As described above, the neural network 40 has a plurality of neuron elements, and each of the values weighted by the synapse load values with respect to the output values of a predetermined number of neuron elements in a specific stage is uniquely supported. A neural network in which an internal state value indicating an internal state of the neuron element is determined by inputting to a neuron element in a next stage adjacent to the specific stage, wherein each neuron element includes the product-sum operation device. An output value of the neuron element in the specific stage is input as a multiplicand to a product-sum operation device provided in the neuron element in the next stage, and the synapse load value is input as the multiplier in the next stage. An internal state value indicating the internal state of the next-stage neuron element is input to the product-sum operation device provided in the neuron element of Miracle is configured to be outputted from the next stage of the product sum operation device provided in the neuron elements as an output value corresponding to the cumulative result of the operation.

  According to the above configuration, each neuron element includes the product-sum operation device, and the output value, the synapse load value, and the internal state value of these neuron elements are input to and output from the product-sum operation device. Since the neural network is composed of the multiplicand, the multiplier, and the accumulated result of the product operation of the multiplicand and the multiplier, each of the arithmetic processing blocks for calculating the internal state value for each neuron element in the conventional neural network is reduced. Is possible.

  As described above, according to the present invention, it is possible to realize a product operation device and a product-sum operation device with a small element size and a simplified circuit. Further, the product of the input signal written in the variable resistance variable resistance element or the result of the product-sum operation can be stored, and the total sum or the partial sum can be output as necessary.

  Therefore, the configuration of the product operation device and the product-sum operation device is simplified, and the product operation device and the product operation device capable of reducing the occupied area of the product-sum operation device with respect to the area of the entire circuit including these devices, and the product A sum operation device, a neural network including these devices in each neuron element, a product operation method, and the like can be provided.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The product-sum operation apparatus of the present invention may input a multiplicand to one terminal of the variable resistance variable resistance element and a multiplier to the other terminal, and use the product of the input signals as an output value.

  A major point of the present invention is to use a variable resistance variable resistance element in the product-sum operation device. A variable resistance variable resistance element is an element whose electrical resistance reversibly changes when a voltage pulse is applied. In recent years, it is a next-generation non-volatile random access memory (NVRAM) that can operate at high speed instead of a flash memory. Application is expected as Access Memory). Examples of the resistance variable variable resistance element include RRAM (Resistance RAM) and PCRAM (Phase Change RAM) as described in Non-Patent Document 1.

  That is, in the product-sum operation apparatus of the present invention, the multiplicand is input to one terminal of the variable resistance variable resistance element, and the multiplier is input to the other terminal, and the product of the input signals is used as the output value.

  In the product-sum operation apparatus according to the present invention, the output value of the input value of the product-sum operation apparatus may be controlled by a voltage pulse width that is a multiplier and a pulse frequency that is a multiplicand.

  In the product-sum operation apparatus of the present invention, the output value of the input value of the product-sum operation apparatus may be controlled by a voltage pulse width that is a multiplier and a pulse voltage that is a multiplicand.

  In the product-sum operation apparatus of the present invention, the element may be formed of a single variable resistance variable resistance element in the product-sum operation apparatus.

  In the product-sum operation apparatus according to the present invention, the element may be formed by a plurality of variable resistance variable resistance elements connected to the row line and the column line in the product-sum operation apparatus.

  The product-sum operation apparatus of the present invention may store the product-sum operation result written in the variable resistance variable resistance element in the product-sum operation apparatus.

  Note that the variable resistance variable resistance element can hold information stored by writing even when the power is turned off and no voltage is applied to the element.

  The product-sum operation apparatus of the present invention may be configured to store the product of the input signals written in the variable resistance variable resistance element designated by each row line and column line in the product-sum operation apparatus.

  In the product-sum operation apparatus of the present invention, the product-sum operation apparatus may be capable of outputting a partial sum of products of input signals written in the variable resistance variable resistance element designated by each row line and column line.

  The neural network of the present invention is a neural network having a plurality of stages of neuron elements, each neuron element including the product-sum operation circuit, and the product-sum operation circuit outputs the output values of the preceding stage neuron elements to a plurality of stages. It is also possible to calculate the internal state as the sum of multiplications by multiplying by the multiplication means the synaptic load as each calculated value.

  The present invention relates to a product operation device including a resistance change type variable resistance element capable of storing information by changing an electrical resistance by applying an electrical stress, a product-sum operation device, and the device for each neuron. The present invention can be applied to a neural network provided in an element, a product calculation method, and the like. Note that the present invention can be applied to any device as long as it is an electronic device and an electrical device that require an arithmetic circuit that performs product operation and product-sum operation.

It is a circuit diagram which shows the structure at the time of writing of the product-sum calculation apparatus comprised by the single cell which makes the resistance change type variable resistance element which is one Embodiment of this invention a unit cell. (A) is a wave form diagram which shows the mode of the voltage pulse (pulse width Ti) input into the terminal A (bit line) of the said resistance change type variable resistance element, (b) is a terminal B (data line). FIG. 6C is a waveform diagram illustrating a state of a voltage pulse (pulse frequency Fi) input to the terminal, and FIG. 5C is a waveform diagram illustrating a relationship between a potential difference between the terminals A and B and a threshold potential Vth. (A) is a circuit diagram which shows the structure at the time of the reading of the product-sum operation apparatus comprised by the single cell which uses the said resistance change type variable resistance element as a unit cell, (b) is the said product-sum operation It is a sequence diagram which shows operation | movement of an apparatus. It is a circuit diagram which shows the structure of the said variable resistance variable resistance element, and the equivalent circuit in the case of an electrical property measurement. (A) is a graph showing the SET pulse frequency dependence of the current value flowing through the resistance variable variable resistance element, and (b) is a graph showing a predetermined pulse voltage of the current value flowing through the resistance variable variable resistance element. It is a graph which shows voltage pulse width (application time of a predetermined pulse voltage) dependence, (c) is a graph which shows pulse voltage dependence. (A) is a circuit diagram which shows the structure and write-in operation | movement of a product-sum operation apparatus comprised by the single cell, (b) is a circuit diagram which shows read-out operation | movement. (Operation method different from FIG. 1, FIG. 2 (a) to FIG. 2 (c) and FIG. 3 (a) and FIG. 3 (b)) (A) is a circuit diagram which shows the structure at the time of writing of the product-sum arithmetic unit comprised by the some cell which unit-cells the said resistance change type variable resistance element, (b) is the said resistance change type It is a wave form diagram which shows the mode of the voltage pulse (pulse width Ti) input into the terminal A (bit line) of a variable resistance element, (c) is the voltage pulse (pulse frequency input into the terminal B (data line). (D) is a waveform diagram showing the relationship between the potential difference between the terminals A and B and the threshold potential Vth. It is a circuit diagram which shows the structure at the time of the reading of the product-sum arithmetic unit comprised by the some cell which uses the said resistance change type variable resistance element as a unit cell. (A) is the circuit diagram which shows the structure of the product-sum arithmetic unit comprised by the said variable resistance variable resistance element as a unit cell, and was comprised by the single cell, (b) is the said variable resistance variable resistance element It is a wave form diagram which shows the mode of the voltage pulse (pulse width Ti) input into the terminal A (bit line), (c) is a wave form diagram which shows the relationship between the electric potential difference between terminal A and B, and threshold potential Vth. is there. (A) is a read-out operation in which the variable resistance variable resistance element is a unit cell and the product-sum operation unit is composed of a single cell, and the voltage pulse width and pulse voltage are used as a multiplier and a multiplicand, respectively. It is a circuit diagram which shows a method, (b) is a sequence diagram which shows the read-out operation method. It is a block diagram which shows the structure of each process block of the product-sum operation circuit which is one Embodiment of this invention. It is a block diagram of the calculation processing block at the time of applying the product-sum calculation method with respect to the neural network which is one Embodiment of this invention. It is a flowchart of each step in the calculation processing when applying the product-sum calculation method to the neural network. (A) is a circuit diagram which shows the structure of the product-sum operation apparatus using the conventional PWM (Pulse Width Modulation: Pulse width modulation) signal, (b) is the terminal voltage Vout and reference in the said product-sum operation apparatus It is a graph which shows the linear relationship of the lamp voltage Vref. It is a block diagram which shows the structure of the product-sum operation circuit in a prior art. FIG. 16 is a circuit diagram showing an analog arithmetic circuit in which one arithmetic block is constituted by an analog circuit in each processing block shown in FIG. 15. FIG. 16 is a circuit diagram in which an input value (calculated value) holding block is configured by an analog circuit in each processing block shown in FIG. 15. It is a figure which shows the structure of the conventional neural network model. It is a block diagram which shows the structure of each calculation processing block at the time of applying the product-sum calculation method with respect to the neural network shown in FIG. It is a graph which shows sigmoid conversion. It is a circuit diagram which shows the more detailed structure of the switched current source in the product-sum calculation apparatus of Fig.14 (a).

Explanation of symbols

1 Variable resistance variable resistance element (product calculation device)
2 Data line 3 Bit line 4 Switching transistor 5 Capacitor (storage unit)
6 operational amplifier 10 product-sum operation device (product operation device)
11A Upper electrode (one terminal, the other terminal)
11B Lower electrode (one terminal, the other terminal)
12 resistors 20 product-sum operation device (product operation device)
21 variable resistance variable resistance element 22 data line 23 bit line 24, 27 switching transistor 25 capacitor (storage unit)
26 Comparator 100 Multiply-sum arithmetic unit (product arithmetic unit)
ij1 (111, 121, 211, 221 ..., i, j are natural numbers) Resistance variable variable resistance element 1i2 (112, 122 ...: i is a natural number) Data line 1j3 (113, 123 ... : J is a natural number) Bit line 1i4 (114, 124 ...: i is a natural number) Switching transistor 1j7 (117, 127 ...: j is a natural number) Switching transistor 1i5 (115, 125 ...: j Is a natural number) Capacitor (storage unit)
1i6 (116, 126..., J is a natural number) Operational amplifier 30, 30A, 30B Product-sum operation circuit (product operation device, product-sum operation device)
31, 31A, 31B Input value holding block (calculation value holding block)
32, 32A, 32B Sorting block 33, 33A, 33B Switching block (1)
34, 34A, 34B Load value holding block (operation value holding block)
35, 35A, 35B Switching block (2)
36, 36A, 36B Arithmetic processing block 40 Neural network 41A, 41B Function processing block A terminal (one terminal)
B terminal (the other terminal)
σii conductance (i is a natural number)
Fi pulse frequency (voltage pulse frequency: i is a natural number)
Q Charge amount (cumulative value of output value)
Ti pulse width (voltage pulse width: i is a natural number)
Vref reference voltage Vth threshold potential Wi operand value (multiplicand: i is a natural number)
Xi operation value (multiplier: i is a natural number)

Claims (13)

A product operation device that outputs a result of these product operations by inputting a multiplicand and a multiplier,
The electric resistance is reversibly changed by applying a voltage pulse, and includes a variable resistance variable resistance element having at least two terminals,
A first input signal corresponding to a multiplicand is input to one of the two terminals of the variable resistance variable resistance element, and a second input signal corresponding to a multiplier multiplied by the multiplicand is input to the other terminal. Thereby, an output value corresponding to the result of the product operation of the multiplicand and the multiplier is configured to be output. The first input signal and the second input signal are voltage pulses;
The product operation device according to claim 1, wherein the output value is controlled by a voltage pulse width of the first input signal and a pulse frequency of the second input signal. The first input signal and the second input signal are voltage pulses;
The product operation device according to claim 1, wherein the output value is controlled by a voltage pulse width of the first input signal and a pulse voltage of the second input signal.   The variable resistance variable resistance element stores a result of the product operation by inputting the first input signal and the second input signal according to a change in electric resistance of the variable resistance variable resistance element. The product operation device according to any one of claims 1 to 3.   The result of the product operation stored by the change in the electrical resistance is erasable by applying a predetermined voltage pulse to the variable resistance variable resistance element. Product operation unit. Comprising at least one product computing device according to any one of claims 1 to 5,
A second output value corresponding to a cumulative value of the output values for each set output from the product operation device is output by inputting the first signal and the second signal of a plurality of sets. A product-sum operation apparatus.   The variable resistance variable resistance element is configured to calculate an accumulation result of the product operation for each set by inputting a plurality of sets of the first input signal and the second input signal, and to change the electrical resistance of the variable resistance variable resistance element. The product-sum operation apparatus according to claim 6, wherein:   The accumulated result of the product operation stored by the change in the electrical resistance can be erased by applying a predetermined voltage pulse to the variable resistance variable resistance element. The product-sum operation apparatus described. A plurality of product operation devices according to any one of claims 1 to 5,
A product-sum operation apparatus configured to output a second output value corresponding to a cumulative value of output values output from each of the plurality of product operation apparatuses.   The third output value corresponding to a cumulative value of output values output from each of a predetermined number of product operation devices among the plurality of product operation devices is output. Item 10. The product-sum operation apparatus according to item 9.   The product-sum operation apparatus according to claim 10, further comprising a storage unit that stores a cumulative value of output values output from each of a predetermined number of product operation apparatuses among the plurality of product operation apparatuses. . Each of the neuron elements in the next stage adjacent to the specific stage has a multi-stage neuron element, and each of the output values of a predetermined number of neuron elements in the specific stage is weighted by the synapse load value uniquely. A neural network in which an internal state value indicating an internal state of the neuron element is determined by inputting to the element,
Each of the neuron elements includes the product-sum operation apparatus according to any one of claims 6 to 11,
The output value of the neuron element in the specific stage is input as a multiplicand to the product-sum operation device provided in the neuron element in the next stage,
The synapse load value is input as a multiplier to a product-sum operation device provided in the next-stage neuron element,
An internal state value indicating an internal state of the next-stage neuron element is configured to be output from a product-sum operation device provided in the next-stage neuron element as an output value corresponding to the accumulation result of the product operation. A neural network characterized by The electrical resistance is reversibly changed by applying a voltage pulse, and a variable resistance variable resistance element having at least two terminals is provided. By inputting a multiplicand and a multiplier, the result of these product operations is obtained. A product operation method executed by a product operation device for outputting,
A first signal input step of inputting a first input signal corresponding to a multiplicand to one of the two terminals of the variable resistance variable resistance element;
A second signal input step of inputting a second input signal corresponding to a multiplier multiplied by the multiplicand to the other terminal of the two terminals;
A product operation method comprising: an operation result output step for outputting an output value corresponding to a product operation result of the multiplicand and the multiplier.

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