JP2007115116A - Neuron element and information processing method using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a so-called soft-computing flexible and adaptable information processor which is highly strong to condition fluctuation, and can follow up any condition by using a neuron element capable of batch processing of multi-dimensional information. <P>SOLUTION: Each of analog information shown by a pulse width of input pulse and a generation time of pulse (delay time from a reference time) is contracted in a designated ratio by applying a weight value, respectively. Each of the resulting weighted two-dimensional inforamtion is connected to compute a composed pulse width and a composed generation delay time, and outputted as an output pulse that is a series of digital signals by applying a weight value thereto. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a neuron element and an information processing method using the same, and more particularly to a neuron element that enables vector processing of multiple information and an information processing method using the same.

  In neuron elements that model information processing performed in the living body, the weight of the input analog signal is multiplied by a weight value, and signal processing is performed to output the sum of all inputs after conversion using a nonlinear threshold function. (For example, refer to Patent Document 1).

As a configuration for realizing these, what is simulated by a digital computer is the mainstream of implementation. Although rare, hardware using analog devices is also known.
JP2004-110421

  In information processing technology using neuron elements, hardware is required for real-time processing of flexible control and pattern recognition similar to living organisms. In particular, there is a strong demand for a system that is compatible with hardware and a digital system that is a mounting technology for information processing by software.

  That is, in an apparatus that requires biologically flexible information processing, analog information processing is desired because the flexibility of information processing is based on processing of analog information that continuously changes. On the other hand, it is desirable to enable consistency with a digital system based on discontinuous binary information, which is widely used for information processing.

  The digital system technology that enables such analog information processing is a technology for reciprocal conflicting properties and has not yet been realized.

  As information input to the neuron element, there is a case where the number of pulses is processed at the research level, but basically, it is a single scalar processing of only the size. That is, the conventional neuron element is based on scalar processing that simply adds a weight value to the magnitude of continuous change, and there is a problem that batch processing of multidimensional information cannot be performed.

  The present invention has been made in view of such problems. First, an input terminal to which the first information and the second information are input as one input signal, and the input terminal are provided corresponding to the input terminal. A synapse for generating multidimensional weighting information by giving weight values to each of two pieces of information, a neuron for generating multidimensional synthetic information by combining the multidimensional weighting information and other multidimensional weighting information, and the multidimensional synthetic information And an output terminal for outputting an output signal corresponding to the above.

  Further, the output signal is a weighted linear function in which a weight value is given to each of the multi-dimensional synthesis information.

  Further, both the first information and the second information are analog information.

  Second, the first information and the second information are input in response to one input pulse, the input terminal is provided corresponding to the input terminal, and a two-dimensional weight value vector is provided for the first information and the second information. Each of the two-dimensional weighting information is generated by synthesizing the two-dimensional weighting information by synthesizing the two-dimensional weighting information by giving a weight value to each of the two-dimensional weighting information. This is solved by providing a neuron to be generated and an output terminal that outputs an output pulse corresponding to the two-dimensional synthesis information.

  Further, both the first information and the second information are analog information.

  Further, the first information is a pulse width of the input pulse, and the second information is a generation delay time of the input pulse.

  The synapse is characterized in that a weight value is given to each of the first information and the second information by a weighting circuit.

  Further, the two-dimensional synthesis information is a synthesis pulse width and a synthesis occurrence delay time.

  Further, the output pulse has a pulse width and a generation time obtained by assigning weight values to the combined pulse width and the combined generation delay time, respectively.

  Third, an information processing method using a neuron element having an input terminal, a synapse, a neuron, and an output terminal, wherein one input pulse having first information and second information is input to the input terminal And performing a first weighting process and a second weighting process for giving weight values based on a two-dimensional weight value vector to the first information and the second information by the synapse, respectively, A step of generating the two-dimensional weighted information by the neuron and the other two-dimensional weighted information to generate two-dimensional composite information composed of composite first information and composite second information; A step of outputting an output pulse corresponding to the two-dimensional synthesis information.

  Further, the first information is a pulse width of the input pulse, and the second information is a generation delay time of the input pulse.

  Further, a third weighting process and a fourth weighting process for assigning weight values to the two-dimensional synthesis information are performed, and output pulses are output.

  According to the present invention, multidimensional information can be collectively processed in a neuron element. Therefore, by using this neuron element, it is possible to realize a flexible information processing apparatus called so-called soft computing, which has robustness against a condition change, and can follow any condition.

  For example, by constructing a neural network using this neuron element, it is possible to adapt to multi-dimensional and diverse processing for optimal and robust machine control, restoration of missing information of speech signals, pattern recognition, etc. .

  In addition, analog information processing having high consistency with digital ICs, digital computers, and interface systems, which are widely used for information processing, and continuous change characteristics can be realized. Therefore, real-time processing is possible, and it is possible to respond with high utility to automatic control and security maintenance of mechanical devices that require high accuracy and high function.

  An embodiment of the present invention will be described in detail with reference to FIGS.

  First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a conceptual diagram showing a neuron element of the present embodiment. The neuron element 1 of the present embodiment includes an input terminal 2, a synapse 3, a neuron 4, and an output terminal 5.

  The neuron element 1 has a plurality of input terminals 2 (21, 22,... 2n) and a plurality of synapses 3 (31, 32,... 3n) corresponding thereto. Input pulses 6 (61, 62,... 6n) are input to the plurality of input terminals 2, respectively.

An input pulse 6i which is i-th information is input to the input terminal 2i. For example, the input terminal 21 receives an input pulse 61 that is first information. The input pulse 61 is a digital pulse signal represented by a binary value of a power supply voltage and a ground potential. On the other hand, the input pulse 61 has first information of analog information and second information of analog information different from the first information. That is, the first information is the pulse width T _s1 of the input pulse 61, and the second information is the generation time of the input pulse 61. More specifically, the generation time is a generation delay time T _d1 from a certain reference time until the input pulse 61 is generated.

The synapse 3i is a two-dimensional synapse that is provided corresponding to each of the input terminals 2i and gives different weight values to the two-dimensional signals (generation delay time T _di and pulse width T _si ). That is, one synapse 31 corresponds to one input terminal 21, but the synapse 31 is generated by a two-dimensional weight value vector (w _d1 , w _s1 ) and a weighting circuit, and the generation delay time T _d1 and the pulse width T _s1. Are given different weight values.

Specifically, the synapse 31 _adds weight values represented by weight value vectors (w _d1 , w _s1 ) to the generation delay time T _d1 and the pulse width T _s1 of the input pulse 61 input from the first input terminal 21. Two-dimensional weighting information (T _d1 w _d1 , T _s1 w _s1 ) is generated by giving each.

  Similarly, two-dimensional weighting information is generated by the synapse 32 for the input pulse 62 that is the second information input from the input terminal 22. Similarly, two-dimensional weighting information is generated, and two-dimensional weighting information is generated by the synapse 3n for the input pulse 6n, which is the nth information input from the input terminal 2n.

The neuron 4 synthesizes two-dimensional weighting information based on each synapse 3 and generates two-dimensional synthesis information. That is, the first to nth weighted pulse widths T _s1 w _{s1 to} T _sn w _sn are combined to generate a combined pulse width T _ss . Also, the first to nth weighted generation delay times T _d1 w _{d1 to} T _dn w _dn are synthesized to generate a synthesis occurrence time (synthesis occurrence delay time: T _ds ).

The neuron 4 further gives weight values to the composite pulse width T _ss and the composite generation delay time T _ds , and outputs an output pulse 7 having the pulse width _Tos and the generation delay time T _od from the reference time as information. Output more.

The input signal of this embodiment is a digital signal (pulse signal) represented by the presence or absence of voltage, but a pulse width capable of expressing a continuous change is used as input information. Then, the analog information represented by the time width (pulse width T _si ) of the input pulse 6i is reduced at a designated ratio, and the analog information is multiplied by a weight value. Specifically, the pulse width _Tsi is weighted by applying a transient electric circuit that realizes an integration operation with a capacitor and a resistor.

As a result, the weighted pulse widths T _si w _si inputted to one neuron 4 are combined with each other (T _ss ). Further, the above-described transient electric circuit is applied to give a weight and output as a pulse width _Tos of the output pulse 7 which is a series of digital signals.

At the same time, the input pulse 6i of the digital signal represented by the binary value of the power supply voltage and the ground potential can be used as input analog information in the same manner as the time width of the start time of the signal. In other words, the analog information represented by the time width (occurrence delay time T _di ) from the time (reference time) determined uniformly throughout the system to the generation of the input pulse 6i is reduced at a specified rate. That is, the generation delay times T _di w _di of the plurality of input pulses 6 obtained by multiplying the analog information by the weight value are combined (T _ds ), and further, the generation delay times T _od of the output pulses 7 as a series of digital signals are given with weights. And Then, the output pulse 7 having the pulse width _Tos is generated with a delay by the time width of the generation delay time _Tod from the reference time. As a result, it is possible to realize a multidimensional neuron element capable of simultaneously processing two pieces of information of the pulse generation time and the pulse width.

  This will be specifically described below.

  First, the two-dimensional synthesis information generated in the neuron 4 is obtained by obtaining the calculation result of the following formula 1 as vector elements of u and v.

ここで、ｕ：合成発生遅れ時間Ｔ_ｄｓ、ｖ：合成パルス幅Ｔ_ｓｓ、ｘ_ｄｉ：ｉ番目の入力端子６ｉに入力された入力パルスの基準時刻からの発生遅れ時間Ｔ_ｄｉ、ｘ_ｓｉ：ｉ番目の入力端子６ｉに入力された入力パルス幅Ｔ_ｓｉである。

Here, u: composite generation delay time _Tds , v: composite pulse width _Tss , _xdi : generation delay time _Tdi , _xsi : i from the reference time of the input pulse input to the i-th input terminal 6i a th input to the input terminal 6i input pulse width T _si.

Further, w _di is a weight value for the generation delay time T _di of the i-th input pulse, and w _si is a weight value for the i-th input pulse T _si .

The weight value is given as a weight value vector (w _di , w _si ) by the synapse 3. The weight value vector (w _di , w _si ) is calculated as N input pulses as shown in Equation 1 to obtain a vector (u, v) as two-dimensional synthesis information.

  Further, the vector (u, v) is calculated by the following expression 2, and the calculation result is obtained as a two-dimensional vector element of f and g.

ここで、ｆ：出力パルス幅の基準時刻からの発生遅れ時間Ｔ_ｏｄ、ｇ：出力パルス幅Ｔ_ｏｓ、ｗ_ｏｄ：合成発生遅れ時間ｕへの重み値、ｗ_ｏｓ：合成パルス幅ｖへの重み値である。すなわち、式２はいわゆるニューロンの出力関数を重み付き線形関数で表現したものである。

Here, f: generation delay time T _od from the reference time of the output pulse width, g: output pulse width _Tos , w _od : weight value to the combined generation delay time u, w _os : weight to the combined pulse width v Value. That is, Expression 2 represents a so-called neuron output function as a weighted linear function.

The neuron 4 generates an output pulse 7 having a pulse width T _os (= g) from the output terminal 5 after the generation delay time T _od (= f) has elapsed from the reference time after the processing of Expression 2. Thereby, vector processing of multiplexed information becomes possible.

  The weighting process by the synapse 3 is performed by an electric circuit that adds a weight value.

FIG. 2 is a circuit diagram showing an example of an electric circuit for adding weight values (w _di , w _si , w _od , w _os ). The operation principle of the circuit will be described by taking as an example a case where the pulse width T _si is T [s] as the input pulse 6i and the magnitude of the pulse is the power supply voltage Vcc [V].

The weighting circuit 10 includes an input terminal 11, a backflow prevention diode switch 13, a first electric resistor 14, a capacitor 15, a switch 16, a second electric resistor 17, a weighted external power supply voltage 18, and an output terminal 19. In the present embodiment, weight values can be added to the generation delay time T _di , the pulse width T _si , the combined generation delay time T _ds , and the combined pulse width T _ss using the illustrated electric circuit.

  The input terminal 11 is connected to, for example, an output terminal of an external IC (not shown) via the input terminal 2 i of the neuron element 1. Between the input terminal 11 and the output terminal 19 of the circuit, a backflow prevention diode switch 13, a first electric resistor 4 having a resistance value R [Ω], and a switch 16 are connected in series. The switch 16 is a transistor such as an FET, and is turned on at the same time as the input pulse 6i ends.

  Further, a capacitor 15 having a capacitance C [F] is connected between these and the GND line. The second electrical resistor 17 has the same resistance value R [Ω] as the first electrical resistor 14. One end of the second electrical resistor 17 is connected to the weighted external power supply voltage 18 (−es [V]).

  During the period of the pulse width T [s] of the input pulse 6i, the switch 16 is off. Therefore, during this time, the signal of the input pulse 6 i is stored in the capacitor 15 via the backflow prevention diode switch 13 and the first electric resistor 14. At this time, the voltage value of the terminal (node n1) on the first electric resistance 14 side of the capacitor 15 is Vcc · T / (CR).

  When the switch 16 is turned on after the period of the pulse width T [s], the electric charge stored in the capacitor 15 flows to the second electric resistance 17. At this time, the backflow prevention diode switch 13 prevents charge from flowing to the input terminal 11 side. One end of the second electrical resistor 17 is connected to the weighted external power supply voltage 18.

  Therefore, when the switch 16 is turned on, the voltage on the terminal side (node n2) connected to the switch 16 of the second electric resistor 17 starts to decrease from the value of the voltage (Vcc · T / (CR)) of the node n1, and eventually becomes 0. It passes through [V] and changes to a negative voltage. When the elapsed time from when the switch 16 is turned on until the node n2 becomes 0 [V] is T ′, the voltage drop based on the discharge of the accumulated charge of the capacitor 15 is (Vcc + es) · T ′ / (CR). Since the drop voltage value is equal to the voltage value Vcc · T / (CR) due to the charge accumulation in the capacitor 15, the equation Vcc · T / (CR) = (Vcc + es) · T ′ / (CR) holds.

  As a result, T ′ = {Vcc / (Vcc + es)} T, which is expressed as a value obtained by adding a weight value represented by Vcc / (Vcc + es) to the value of T.

  The output from the output terminal 19 is converted into a digital signal by shaping the output waveform of the node n2 (see T 'in FIG. 3), and is output as an output pulse 7 from the output terminal 19. For this reason, the comparator 12 for converting the output into a digital signal when the voltage is 0 [V] or higher is connected to the node n2.

  Thus, by using the circuit of FIG. 2, a weight can be given to the pulse width T according to the value of the voltage value es of the weighted external power supply voltage 18.

Having described the pulse width T _si of the input pulse, also generates a delay time T _di from the reference time of the input pulse 6i as described above, the weight value using the circuit of Figure 2 as an element of two-dimensional vector information Can be added. Generating delay time T _di, by passing the IC (e.g., an inverter) that inverts an operation signal of the input pulse 6i, it can be converted to a pulse time interval (pulse width) T _di. Therefore, a weight value can be added to the generation delay time _Tdi by the same operation as described above in a circuit in which an inverter is added in front of the backflow prevention diode switch 3 in FIG.

  In other words, in this embodiment, the weighting circuit 10 separately inputs the pulse signals having the generation delay times and time widths of u and v expressed by Equation 1 to the input terminal 11 of the weighting circuit 10, whereby u, By assigning a weight value to the value of v, it is possible to form an output pulse signal having time delays and time widths of f and g in Equation 2.

  FIG. 3 shows a simulation result in which the two-dimensional information is weighted by the circuit of FIG. In the simulation, the voltage value of the external power supply voltage es is changed under Vcc = 5 [V] and CR = 10 [s], and the weighted pulse width T ′ is measured. FIG. 3A shows the case where es = 10 [V] and T = 3 [s], and FIG. 3B shows the case where es = 15 [V] and T = 2 [s]. Each solid line is an input waveform, and a broken line is an output waveform.

  In each figure, the pulse width T is weighted by the time until the output waveform of the broken line zero-crosses with the input waveform of the solid line (the elapsed time from when the switch 16 is turned on until the node n2 becomes 0 [V]). 'Is. In the case of FIG. 3A, the pulse width T ′ of the simulation result is 1.0 [s], and in FIG. 3B, the pulse width T ′ is 0.5 [s]. This indicates that the theoretical value according to Equation 1 matches the actual voltage waveform.

Although the simulation is a result for only the input pulse width T, as described above, the generation delay time may be weighted by inputting a signal obtained by inverting the input pulse to the input terminal of the circuit of FIG. Therefore, it can be performed weighting of generating a delay time by using this circuit is obvious from the results of FIG. 3, can be weighted concurrently the pulse width T _si and generates delay time T _di of the input pulse 6i .

  The circuit of FIG. 2 can be integrated by externally attaching a capacitor and a resistor to an FPGA (Field Programming Gate Array) or a microcomputer circuit.

  Next, the operation of the neuron element 1 will be described with reference to FIGS. 4 and 5. FIG. 4 is a block diagram showing the neuron element 1, and FIG. 5 is a timing chart of each signal in the configuration of FIG. In FIGS. 4 and 5, each signal is indicated by the same symbol as the corresponding analog information, and the value of the actual analog information is indicated by hatching. In FIG. 5, a timing chart d for synthesizing the generation delay time is shown in the upper part, and a timing chart s for synthesizing the pulse width is shown in the lower part.

  As an example, the neuron element 1 in the case of two input terminals 2 (21, 22) is shown.

First, the composition of the generation delay time will be described. After the reference time signal STD is generated and the first time has elapsed, the first input pulse 61 is input to the input terminal 21. The input pulse 61 is a digital signal having a pulse width T _s1 . The input pulse 61 is input to a signal inverting circuit (digital inverter element) 108, and an inverted signal T _s1 (r) is generated. The output T _s1 (r) of the signal inverting circuit 108 is input to the digital AND circuit 111 together with the reference time signal STD. The AND circuit 111 extracts a pulse signal represented only by the time when the reference time signal STD and the inverted signal T _s1 (r) are generated simultaneously. Thereby, a signal is generated so that the input pulse 61 becomes a pulse having a time width based on the delay time from the generation of the reference time signal STD. As a result, the generation delay time signal _Td1 is obtained.

The generation delay time signal T _d1 is input to the generation delay time weighting circuit 112, and the first weighting process is performed by one two-dimensional synapse 31 corresponding to the input terminal 21. In the first weighting process, a weight value is assigned to the occurrence delay time signal T _{d1 by} the weight value and weighting circuit 112 for the occurrence delay time signal T _d1 in the two-dimensional weight value vector of the synapse 31. The weighting circuit is the circuit shown in FIG. The weighted external power supply voltage es [V] for controlling the weight value is included in this circuit, and a weight value (w _d1 ) corresponding to the weighted external power supply voltage es [V] is given to the generation delay time signal T _d1. The weighted generation delay signal T _d1 w _d1 is output. This signal (pulse) is generated at the falling time of the generation delay time signal _Td1 . That is, the switch 16 shown in the circuit diagram of FIG. 2 is turned on by the fall (end of pulse) of the generation delay time signal _Td1 . As a result, the weighted generation delay signal T _d1 w _d1 is generated immediately after the generation delay time signal T _d1 .

Although not shown in the timing chart of FIG. 5, the second input pulse 62 is input to the input terminal 22 after the second time has elapsed since the generation of the reference time signal STD. The input pulse 62 is a digital signal having a pulse width T _s2 and is processed in the same manner as the input pulse 61. That is, the input pulse 62 is input to the signal inverting circuit, and the generated inverted signal T _s2 (r) and the reference time signal STD are input to the digital AND circuit 111. Thereby, the generation delay time signal _Td2 is obtained.

The generation delay time signal T _d2 is input to the generation delay time weighting circuit 117, and the first weighting process is performed by one two-dimensional synapse 32 corresponding to the input terminal 22. In the first weighting process, a weight value is given to the occurrence delay time signal T _d2 by the weight value and weighting circuit 117 for the occurrence delay time signal T _d2 out of the two-dimensional weight value vector of the synapse 32. The weighting circuit 117 is a circuit shown in FIG. A weight value (w _d2 ) corresponding to the weighted external power supply voltage es [V] is given to the generation delay time signal T _d2 , and a weighted generation delay signal T _d2 w _d2 is output.

Further, this signal (pulse) is generated at the falling time of the first weighted generation delay signal T _d1 w _d1 as shown in FIG. That is, the switch 16 shown in the circuit diagram of FIG. 2 is turned on by the fall of the weighted generation delay signal T _d1 w _d1 (end of pulse). Thus, a weighted generation delay signal T _d2 w _d2 is generated immediately after the generation delay signal T _d1 w _d1 .

Neuron 4 combines the weighted delayed generation signals T _d1 w _d1 and T _d2 w _d2 into a series of consecutive pulse signals. That is, these generation delay signals are input to the digital OR circuit 121 in order to generate a composite generation delay time signal. As a result, a combined generation delay signal T _ds (u in Equation 1) is generated.

Next, pulse width synthesis will be described. The first input pulse 61 is input to the input terminal 21 after the reference time signal STD is generated and the first time has elapsed. Since the pulse width is synthesized, the input pulse 61 (signal having the pulse width T _s1 ) is directly input to the weighting circuit 113, and the second weighting process is performed by one two-dimensional synapse 31 corresponding to the input terminal. In the second weighting process, a weight value is given to the pulse width (signal) T _s1 by the weight value for the pulse width T _s1 and the weighting circuit 113 out of the two-dimensional weight value vector of the synapse 31. The weighting circuit 113 is a circuit shown in FIG. A weight value (w _s1 ) corresponding to the weighted external power supply voltage es [V] is given to the pulse width signal T _s1 , and a weighted pulse width signal T _s1 w _s1 is output. The weighted pulse width signal T _s1 w _s1 is generated at the falling time of the input pulse 61 (T _s1 ).

Similarly, although the second input pulse 62 is omitted in FIG. 5, the reference time signal STD is generated, and is input to the input terminal 22 after the second time has elapsed. The input pulse 62 (signal having a pulse width T _s2 ) is input to the weighting circuit 123 as it is, and the second weighting process is performed on the second input pulse 62. The second weighting process assigns a weight value to the pulse width (signal) T _s2 by using the weight value for the pulse width T _s2 and the weighting circuit 123 among the two-dimensional weight value vectors of the synapse 32. The weighting circuit 123 is a circuit shown in FIG. A weight value (w _s2 ) corresponding to the weighted external power supply voltage es [V] is given to the pulse width signal T _s2 , and a weighted pulse width signal T _s2 w _s2 is output.

Further, as shown in FIG. 5, this signal (pulse) is generated at the falling time of the first weighted pulse width signal T _s1 w _s1 . That is, the switch 16 shown in the circuit diagram of FIG. 2 is turned on by the fall of the weighted pulse width signal T _s1 w _s1 (end of pulse). As a result, the pulse width signal T _s2 w _s2 is generated immediately after the pulse width signal T _s1 w _s1 .

Neuron 4 combines weighted pulse width signals T _s1 w _s1 and T _s2 w _s2 into a series of consecutive pulse signals. That is, these pulse width signals are input to the digital OR circuit 126 in order to generate a composite pulse width. As a result, the composite pulse width signal T _ss (v in Equation 1) is generated.

Next, a third weighting process and a fourth weighting process are performed on the combined generation delay time signal _Tds and the combined pulse width signal _Tss , respectively.

  The output terminal 5 of the neuron element 1 synthesizes a series of weighted pulses and outputs them as one pulse. In the present embodiment, the generation delay time of a series of pulses is also weighted, synthesized, and output.

That is, in order to give a delay time to the output pulse, the weighting circuit 122 performs a third weighting process on the combined generation delay signal _Tds . This weighting circuit 122 is also the circuit shown in FIG. 2, and a weight value (w _od ) corresponding to the weighted external power supply voltage es [V] is given to the composite generation delay time signal T _ds , and the weighted composite generation delay signal T _od (f in Equation 2) is output.

The neuron 4 outputs an output pulse 7 from the output terminal 5 after a predetermined delay time (T _od ) has elapsed. That is, the neuron 4 uses the falling time of the reference time signal STD as the reference time for generating the output pulse 7, and generates a weighted composite generation delay signal _Tod from that time. Then, the operation of the weighting circuit 127 that performs the fourth weighting process is started at the falling time of the composite generation delay signal _Tod . That is, the weighting circuit 127 is also the circuit shown in FIG. 2, and the switch 16 shown in FIG. 2 is turned on by the fall of the composite generation delay signal _Tod , and the weight value (w corresponding to the weighted external power supply voltage es [V] is set. _os ) is _added to the synthesized pulse width signal T _ss and a weighted synthesized pulse width signal T _os (g in Equation 2) is output.

  The block diagram is an example, and the signal inversion circuit 108 and the AND circuit 111 may be included in each of the synapses 31 and 32 in the figure.

As described above, in the present embodiment, the first weighting process and the second weighting process are performed by using one corresponding two-dimensional synapse for each of the generation delay time and the pulse width from the reference time of one input pulse. Then, a third weighting process is performed by combining the generation delay times of the weighted N input pulses to obtain a weighted composite generation delay time (T _od ). Further, a fourth weighting process is performed by combining the pulse widths of the weighted N input pulses to obtain a weighted composite pulse width (T _os ). Thereafter, an output pulse 7 having a pulse width _Tos is output from the output terminal 5 with a generation delay time _Tod from the reference time.

  A neuron element that can simultaneously process vector information represented by two types of information, pulse generation time and pulse width, is multi-dimensional information that is mutually related to control targets and judgment targets, even though they are independent of each other. It can be processed. These two types of information include, for example, simultaneous control of the position and speed of the robot arm, simultaneous control of the speed and acceleration of the car, and judgment of facial expression from changes in the shape of the eyes and mouth. It can greatly contribute to progress.

  An application example of the neuron element 1 is shown as a second embodiment with reference to FIGS.

  In the second embodiment, the same neuron element 1 as that of the first embodiment is applied to a steering driving system 50 for an automobile. Specifically, the steering is automatically operated by the neuron element 1 based on the rotational deviation of the four wheels at the time of automobile slip, and control for improving safety is performed. Hereinafter, the same reference numerals are used for the same components as those in the first embodiment, and detailed descriptions of the same portions as those in the first embodiment are omitted.

  6 and 7 are schematic diagrams showing the system of the second embodiment. FIG. 6 is a main configuration of an automobile to which this system is applied. FIG. 7 is a block diagram of the neuron element 1. .

  The steering driving system 50 is a system that takes out, as a signal, the neuron element 1 that the four wheels rotate differently when slipping by, for example, an ice burn, and takes out the optimum steering operation amount.

  As shown in FIG. 6, a wheel speed detection disk 52 is provided on each of the four axles of the automobile 51. The rotation speed detecting disk 52 is provided with a slit 54, which transmits light from the light emitting lamp 53 through the slit 54 for a predetermined time as the wheel rotates. In addition, a photo sensor 55 that detects light transmitted through the slit 54 is disposed so as to face the light emitting lamp 53.

  Referring to FIG. 7, when there are N inputs, neuron element 1 obtains one output based on them using all different information. That is, the neuron element 1 here corresponds to input of information from the four wheels and has four input terminals 21 to 24.

  Each of the input terminals 21 to 24 has an input pulse 61 in which the presence / absence of light detected by the photosensor 55 according to the rotation speed of the wheel (the time when the light has passed through the slit 54 and the time when the light is shielded) is a digital signal. ~ 64 are input.

  That is, the detection result of the photosensor 55 of the right rear wheel 71 is input to the first input terminal 21 as the input pulse 61, and the detection result of the photosensor 55 of the left rear wheel 72 is input to the second input terminal 22 as the input pulse 62. , The detection result of the photosensor 55 of the right front wheel 73 is input as the input pulse 63 to the third input terminal 23, and the detection result of the photosensor 55 of the left front wheel 74 is input as the input pulse 64 to the fourth input terminal 24. Is input. That is, the input pulses 61 to 64 are rotation speed signals of the respective wheels.

  Further, for example, an engine rotation speed detecting disk 56 for detecting the rotation of the engine is provided. The engine rotation speed detecting disk 56 is also provided with a slit 54, and the photo sensor 57 detects light transmitted through the slit 54. This detection result becomes the timing signal of the entire system, that is, the reference time signal STD of the neuron element 1.

  Further description will be given with reference to FIG.

The first input pulse 61 (pulse width T _s1 ) is inverted by the signal inversion circuit 108 and input to the digital AND circuit 111 together with the reference time signal STD. Thereby, the generation delay time signal _Td1 from the reference time of the input pulse 61 is obtained. The generation delay time signal _Td1 indicates how much the rotational speed signal of the right rear wheel 71 is delayed from the timing signal (reference time) of the entire system.

The generation delay time signal T _d1 is subjected to a first weighting process by the weighting circuit 112 for the generation delay time signal T _d1 of the two-dimensional weight value vector of the synapse 31 and the generation delay time weighting circuit 112. As a result, the weighted generation delay signal T _d1 w _d1 is output. This signal (pulse) is generated at the falling time of the generation delay time signal _Td1 .

Although not shown in the timing chart of FIG. 8, the second input pulse 62 (pulse width T _s2 ) is inverted by the signal inverting circuit 108 and input to the digital AND circuit 111 together with the reference time signal STD. Thereby, the generation delay time signal _Td2 from the reference time of the input pulse 62 is obtained. The generation delay time signal T _d2 is subjected to a first weighting process by the weighting circuit 117 for the generation delay time signal T _d2 of the two-dimensional weight value vector of the synapse 32 and the generation delay time weighting circuit 117.

As a result, the weighted generation delay signal T _d2 w _d2 is output. Further, this signal (pulse) is generated at the falling time of the weighted generation delay time signal T _d1 w _d1 (FIG. 8).

Although not shown in FIG. 8, the third input pulse 63 (pulse width T _s3 ) is inverted by the signal inverting circuit 108 and input to the digital AND circuit 111 together with the reference time signal STD. Thereby, the generation delay time signal _Td3 from the reference time of the input pulse 63 is obtained. The generation delay time signal T _d3 is subjected to a first weighting process by the weighting circuit 119 for the generation delay time signal T _d3 of the two-dimensional weight value vector of the synapse 33 and the generation delay time, and weighted generation A delay signal T _d3 w _d3 is output.

Further, this signal (pulse) is generated at the falling time of the weighted generation delay time signal T _d2 w _d2 (FIG. 8).

Although not shown in FIG. 8, the fourth input pulse 64 (pulse width T _s4 ) is inverted by the signal inversion circuit 108 and input to the digital AND circuit 111 together with the reference time signal STD. Thereby, the generation delay time signal _Td4 from the reference time of the input pulse 63 is obtained. The generation delay time signal T _d4 is subjected to a first weighting process by the weighting circuit 120 for the generation delay time signal T _d4 of the two-dimensional weight value vector of the synapse 34 and the generation delay time signal, and weighted generation A delayed signal T _d4 w _d4 is output.

This signal (pulse) is generated at the falling time of the weighted generation delay time signal T _d3 w _d3 .

The neuron 4 inputs four weighted generation delay signals to the digital OR circuit 121 and generates a combined generation delay signal T _ds (u in Equation 1).

The first input pulse 61 (signal having a pulse width T _s1 ) is input to the input terminal 21 after the first time has elapsed after the generation of the reference time signal STD, and the two-dimensional weight value vector of the synapse 31 is input. Of these, the second weighting process is performed by the weighting value for the pulse width T _s1 signal and the weighting circuit 113. Thereby, the weighted pulse width signal T _s1 w _s1 is generated at the falling time of the input pulse 61 (T _s1 ).

The second input pulse 62 (a signal having a pulse width T _s2 ) is input to the input terminal 22 after the second time has elapsed after the generation of the reference time signal STD, and the pulse of the two-dimensional weight value vector of the synapse 32 is output. A second weighting process is performed by the weight value and the weighting circuit 123 for the width T _s2 signal. As a result, the weighted pulse width signal T _s2 w _s2 as shown in FIG. 8 is generated immediately after the pulse width signal T _s1 w _s1 .

The third input pulse 63 (a signal having a pulse width T _s3 ) is input to the input terminal 23 after the third time has elapsed after the generation of the reference time signal STD, and the pulse of the two-dimensional weight value vector of the synapse 33 is output. A second weighting process is performed by the weighting value and weighting circuit 124 for the width T _s3 signal. As a result, the pulse width signal T _s3 w _s3 weighted as shown in FIG. 8 is generated immediately after the pulse width signal T _s2 w _s2 .

A fourth input pulse 64 (a signal having a pulse width T _s4 ) is input to the input terminal 24 after the fourth time has elapsed after the generation of the reference time signal STD, and the pulse of the two-dimensional weight value vector of the synapse 34 is output. A second weighting process is performed by the weighting value and the weighting circuit 125 for the width T _s4 signal. Thereby, the pulse width signals T _s4 w _s4 weighted as shown in FIG. 8 are generated immediately after the pulse width signals T _s3 w _s3 .

The neuron 4 inputs four weighted pulse width signals to the digital OR circuit 126, and generates a composite pulse width signal T _ss (v in Equation 1).

Thereafter, in order to give a delay time to the output pulse, the weighting circuit 122 performs a third weighting process on the combined generation delay signal _Tds . As a result, a weighted composite generation delay signal T _od (f in Equation 2) is output.

The neuron 4 outputs an output pulse 7 from the output terminal 5 after a predetermined delay time (T _od ) has elapsed. That is, the operation of the weighting circuit 127 that performs the fourth weighting process is started at the falling time of the composite generation delay signal _Tod . As a result, the weighted combined pulse width signal _Tos (g in Equation 2) is output.

An output pulse (generation delay time: T _od , pulse width: T _os ) 7 output from the output terminal 5 is used as a control signal of the control unit 58 of the steering driving system. That is, this output pulse 7 is used to control the rotation of the steering wheel of the automobile with a moderate time delay so as to safely stop drift during slipping.

  A multidimensional neural network can be obtained by configuring a network by connecting a plurality of neuron elements 1 of the present embodiment in parallel to each other in multiple stages. That is, a neural network capable of vector processing of multiple information is realized by configuring a plurality of neuron elements 1 of this embodiment for processing two-dimensional representation vector information with a hierarchical structure, recursive combination, or a combination thereof. To do.

The present invention can be applied to various devices that process signals, such as optimal and robust control of a machine, restoration of missing information of an audio signal, and pattern recognition. In particular, by being incorporated in a device that requires biological processing, it is possible to perform analog information processing having continuous change characteristics even though it is a digital signal processing device. This realizes signal processing that can be processed in real time and that is highly compatible with digital ICs, digital computers, and interface systems that are widely used for information processing. Furthermore, since two pieces of information of the pulse generation time and the pulse width can be processed simultaneously, it can be applied to a multi-dimensional neuron and a neural network composed of a multistage parallel connection thereof.

It is a conceptual diagram of the neuron element of this invention. It is a circuit diagram which shows the weighting circuit of this invention. It is a figure which shows the simulation result by the weighting circuit of this invention. It is a block diagram explaining operation | movement of the neuron element of this invention. It is a timing chart explaining operation | movement of the neuron element of this invention. It is a figure which shows the Example which applied the neuron element of this invention. It is a block diagram explaining operation | movement of the neuron element of this invention. It is a timing chart explaining operation | movement of the neuron element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Neuron element 2, 21, 22, ... 2i, 2n Input terminal 3, 31, 32 ... 3i, 3n Synapse 4 Neuron 5 Output terminal 6, 61, 62 ... 6i, 6n Input pulse 7 Output pulse 10 Weighting circuit 11 Input terminal 12 Comparator 13 Backflow prevention diode switch 14 1st electric resistance 15 Capacitor 16 Switch 17 2nd electric resistance 18 Weighted external power supply voltage 19 Output terminal 50 Steering driving system 51 Car 52 Wheel disc for detecting wheel rotation speed 53 Light emitting lamp 54 Slit 55 57 Photo sensor 56 Engine rotation speed detection disk 58 Control unit 71 Right rear wheel 72 Left rear wheel 73 Right front wheel 74 Left front wheel 108 Signal inversion circuit 111 AND circuit 112, 117, 119, 120, 121, 122 Weighting circuit 113, 123, 124, 125, 126, 127 Weighting circuit STD Reference time generation signal T _d1 , T _d2 ... T _di generation delay time (signal)
T _s1 , T _s2 ·· T _si pulse width (signal)
w _d1 ·· w _di , w _s1 · · w _si , w _od , w _os weight value T _d1 w _d1 · · T _di w _di Weighted occurrence delay time (signal)
T _s1 w _s1 ·· T _si w _si Weighted pulse width (signal)
T _ds synthesis generation delay time (signal)
T _ss composite pulse width (signal)
_Tod output pulse generation delay time (signal)
_Tos output pulse width (signal)

Claims (12)

An input terminal through which the first information and the second information are input as one input signal;
A synapse that is provided corresponding to the input terminal and generates multidimensional weighting information by giving weight values to the first and second information respectively;
A neuron that generates multidimensional synthesis information obtained by synthesizing the multidimensional weighting information and other multidimensional weighting information;
An neuron element comprising: an output terminal that outputs an output signal corresponding to the multidimensional composite information.   The neuron element according to claim 1, wherein the output signal is a weighted linear function in which a weight value is given to each of the multidimensional synthesis information.   2. The neuron element according to claim 1, wherein both the first information and the second information are analog information. An input terminal through which the first information and the second information are input by one input pulse;
A synapse provided corresponding to the input terminal, and generating two-dimensional weighting information by giving a weight value to each of the first information and the second information by a two-dimensional weight value vector;
A neuron that synthesizes the two-dimensional weighting information and other two-dimensional weighting information, and generates two-dimensional composite information composed of composite first information and composite second information;
An neuron element comprising: an output terminal that outputs an output pulse corresponding to the two-dimensional synthesis information.   2. The neuron element according to claim 1, wherein both the first information and the second information are analog information.   6. The neuron element according to claim 5, wherein the first information is a pulse width of the input pulse, and the second information is a generation delay time of the input pulse.   5. The neuron element according to claim 4, wherein the synapse gives a weight value to each of the first information and the second information by a weighting circuit.   5. The neuron element according to claim 4, wherein the two-dimensional synthesis information is a synthesis pulse width and a synthesis generation delay time.   9. The neuron element according to claim 8, wherein the output pulse has a pulse width and a generation time obtained by assigning weight values to the composite pulse width and a composite generation delay time, respectively. An information processing method using a neuron element having an input terminal, a synapse, a neuron, and an output terminal,
Inputting one input pulse having first information and second information to the input terminal;
Performing a first weighting process and a second weighting process to give weight values based on a two-dimensional weight value vector to the first information and the second information by the synapse, respectively, and generating two-dimensional weighting information; ,
Combining the two-dimensional weighting information and other two-dimensional weighting information by the neuron to generate two-dimensional composite information composed of composite first information and composite second information;
Outputting an output pulse corresponding to the two-dimensional synthesis information from the output terminal, and an information processing method using a neuron element.   The information processing method using a neuron element according to claim 10, wherein the first information is a pulse width of the input pulse, and the second information is a generation delay time of the input pulse.   The information processing method using neuron elements according to claim 10, wherein a third weighting process and a fourth weighting process for giving weight values to the two-dimensional composite information are performed, and output pulses are output.

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