JP5085667B2 - MPCP processor for PON system - Google Patents

Description

  The present invention relates to an optical line terminal (OLT) installed in a station and a plurality of ONUs (optical network units) installed in each user's house in a PON (Passive Optical Network) system. The present invention relates to an MPCP processing device for processing an MPCP (Multi-point Control Protocol) interrupt signal for performing access control between a plurality of ONUs with a subscriber line network device).

FIG. 1 shows a configuration example of a PON system (Non-Patent Document 1).
In FIG. 1, the PON system includes an OLT 11 installed in a station, a plurality of m ONUs 12 installed in each user's home, an optical fiber 13 and an optical fiber that connect the OLT 11 and the plurality of m ONUs 12 at 1: m. And a splitter 14.

  In the downlink communication from the OLT to the ONU, a downlink frame to which an LLID (Logical Link IDentifier) assigned to each ONU is time-division multiplexed is transmitted, and the downlink frame is branched by an optical splitter. Forwarded to all ONUs. Each ONU extracts and receives only the downlink frame addressed to itself by the LLID of the downlink frame.

  In upstream communication from the ONU to the OLT, each ONU transmits an upstream frame with the LLID assigned from the OLT in the bandwidth (transmission start time and transmission duration) assigned from the OLT, and the upstream from each ONU. The frames are joined by an optical splitter and transferred to the OLT. The OLT discriminates and receives from which ONU the uplink frame is transmitted based on the LLID of the uplink frame.

  The MPCP of OLT is a multipoint MAC control sublayer obtained by extending the MAC control layer of Ethernet (registered trademark), and performs discovery and uplink signal control for access control between a plurality of ONUs. In the discovery, the OLT automatically detects an ONU connected to the PON system, and performs control to automatically establish a communication link by assigning an LLID to the ONU. In the uplink signal control, band allocation is performed to notify each ONU of the transmission start time and the transmission duration (transmission amount) so that the upstream frames from each ONU do not collide after joining at the optical splitter. Each ONU transmits an uplink frame in each band allocation period.

  The MPCP processing apparatus executes state transition of communication link establishment / disconnection operations triggered by events such as MPCP frame reception from each ONU, completion of MPCP frame transmission to each ONU, and expiration of a plurality of types of timers. This frame transmission / reception, timer count, and the like are executed by hardware because real-time performance is required. On the other hand, the state transition of link establishment / disconnection is executed by software because the procedure is changed or there is a part that is not specified in the standard and is not suitable for hardware. A configuration example of a conventional MPCP processing apparatus that performs such MPCP processing is shown in FIG.

  2, the MPCP processing apparatus includes a plurality of MAC control units 21 corresponding to each ONU, and various functions for establishing and maintaining a communication link are installed in each MAC control unit 21 (Non-patent Document 1). . Note that interrupt events include frame reception, frame transmission completion, and multiple types of timer expiration. Here, since there are a large number of ONUs and the occurrence frequency of events is low, the MPCP processing device notifies the CPU (central processing unit) 22 of various event occurrences generated by hardware by means of interrupt signals, and software. The method of processing is taken.

  However, a plurality of interrupt signals may be generated in each ONU at the minimum reception interval of the MPCP frame, and a plurality of interrupt signals may be generated between the ONUs. Therefore, the MAC control unit corresponding to each ONU An interrupt display register (including information necessary for interrupt processing) 23 is prepared for each interrupt signal. Further, since there is no guarantee that the CPU 22 immediately executes interrupt processing, a means for determining the order in which a plurality of displayed interrupts are processed is required. For example, the interrupt generation order is stored in the interrupt display register 23 corresponding to each ONU, and the interrupt display register 23 is scanned from the CPU 22 that processes the interrupt to determine the processing order.

IEEE802.3ah

  In the conventional MPCP processor, in order to cope with the occurrence of multiple types of interrupts in bursts in each ONU, an interrupt display register for storing the interrupt signal for each interrupt factor (event) is prepared, and the time of occurrence is recorded. Means for processing in the order of occurrence are required. Therefore, the hardware scale is increased, and the CPU that performs interrupt processing is inefficient because it scans the interrupt display register to determine the processing order.

  It is an object of the present invention to provide an MPCP processing device for a PON system that can reduce the amount of buffer required for storing interrupt signals and can process interrupt signals corresponding to each ONU in a predetermined order with a simple configuration. And

The present invention provides an MPCP processing apparatus that outputs an MPCP interrupt signal for controlling access between a plurality of ONUs connected to an OLT in a one-to-many manner to a CPU. Interrupt signals of the same interrupt factor of a plurality of ONUs generated in the order according to the priority order of interrupt factors for a plurality of interrupt signals of one ONU generated at the minimum reception interval of the MPCP frame Output in the order corresponding to the priority order of the ONUs, the arbitration circuit that performs output arbitration of each interrupt signal, and the interrupt signal that is output in order by the output arbitration of the arbitration circuit are stored, and the interrupt signal is stored. And an interrupt display register for outputting to the CPU in the order of storage.

  The arbitration circuit has a function of storing a plurality of interrupt signals of one ONU generated at the minimum reception interval of the MPCP frame in the interrupt display register at the minimum reception interval.

  Further, the arbitration circuit is configured to set the priority order of ONUs in the order of younger identification numbers assigned in the MPCP processing apparatus when a communication link is established.

  The MPCP processor of the present invention arbitrates a plurality of interrupt signals corresponding to one ONU, further arbitrates interrupt signals generated from a plurality of ONUs, stores them in an interrupt display register, and outputs the interrupt signals to the CPU in the order of storage. By performing interrupt processing in this manner, processing for determining the processing order of interrupt signals in the CPU becomes unnecessary, and processing efficiency can be improved. Further, since the occurrence frequency of the event that is the source of the interrupt signal is low, a statistical multiplexing effect can be expected, and it can be handled with one interrupt display register and can be handled with a small memory capacity.

It is a figure which shows the structural example of a PON system. It is a figure which shows the structural example of the conventional MPCP processing apparatus. It is a figure which shows the Example structure of the MPCP processing apparatus of this invention. It is a time chart which shows the transmission / reception space | interval of a MPCP frame.

FIG. 3 shows an embodiment of the MPCP processing apparatus according to the present invention.
In FIG. 3, the MPCP processing apparatus inputs interrupt signals corresponding to ONU1, ONU2,..., For a plurality of interrupt signals of different interrupt factors 1 to n in one ONU, and the same in a plurality of ONUs 1 to m. An arbitration circuit 31 that performs output arbitration for a plurality of interrupt signals that cause an interrupt, and an interrupt display register (FIFO: First In) that makes an interrupt processing request to the CPU while sequentially storing each interrupt signal output from the arbitration circuit 31 First Out) 32. As such an arbitration circuit 31, for example, interrupt signals corresponding to each ONU are aggregated for each interrupt factor, and each interrupt signal is output in the order corresponding to the priority order of the ONU with respect to the same interrupt factor of a plurality of ONUs. The interrupt signal aggregating unit 33 and the interrupt signal output control unit 34 that outputs the interrupt signal output from each interrupt signal aggregating unit 33 in the order corresponding to the priority order of the interrupt factors can be configured.

  Here, as shown in FIG. 4, MPCP frames transmitted by each ONU operating in accordance with MPCP are received in order at the minimum reception interval of the frame length order, but the interval (minimum) at which each ONU transmits the MPCP frame. The transmission interval is set to a time sufficiently longer than the minimum reception interval (32 to 280 times the minimum reception interval). In such an MPCP frame transmission / reception interval, an interrupt signal corresponding to each ONU includes an MPCP frame reception notification generated when receiving an MPCP frame transmitted by each ONU, a timeout notification of an MPCP frame reception interval monitoring timer, etc. There may be several (4 to 5) interrupt signals generated at the minimum reception interval of the MPCP frame. There is also a possibility that an interrupt signal having the same interrupt factor may be generated from a plurality of ONUs at the minimum MPCP frame reception interval. Therefore, the arbitration circuit 31 has a function of storing several interrupt signals in the interrupt display register 32 at the MPCP frame minimum reception interval.

  An operation example of the arbitration circuit 31 is shown. (1) The interrupt signal corresponding to each ONU is collected in the interrupt signal aggregating unit 33 corresponding to each interrupt factor. (2) The interrupt signal aggregation unit 33 outputs one interrupt signal to the interrupt signal output control unit 34. Here, if there are a plurality of interrupt signals corresponding to different ONUs in one interrupt signal aggregating unit 33, for example, according to the priority order of the identification numbers assigned in the MPCP processing apparatus when the communication link is established, An interrupt signal corresponding to the priority ONU is output. (3) The interrupt signal output control unit 34 outputs an interrupt signal of a high priority interrupt factor among the interrupt signals input from the interrupt signal aggregating unit 33 corresponding to each interrupt factor to the interrupt display register 32, and The interrupt signal aggregation unit 33 is instructed to clear the interrupt, and the interrupt signal is cleared. (4) The above processing is repeated between the interrupt signal aggregation unit 33 and the interrupt signal output control unit 34.

  As a result, even if a plurality of interrupt signals are generated in one ONU at the minimum reception interval of the MPCP frame, and the interrupt signal of the same interrupt factor is generated from the plurality of ONUs, the arbitration circuit 31 determines the priority of the interrupt factor and the ONU. Can be output to the interrupt display register 32 in order according to the priority order. Note that all interrupt signals of each ONU that are generated at the minimum MPCP frame reception interval are output from the arbitration circuit 31 to the interrupt display register 32 at the minimum MPCP frame reception interval, so that the order in which the interrupt signals are generated is slightly changed. Will happen, but no major replacement will occur. Further, before an interrupt signal of the same interrupt factor is generated again in the same ONU, all the generated interrupt signals can be stored in the interrupt display register 32 without being missed. The CPU only needs to process the interrupt signals output from the interrupt display register 32 in order, and the processing for determining the processing order of the plurality of interrupt signals corresponding to the plurality of ONUs becomes unnecessary, thereby improving the processing efficiency.

  In addition, since the occurrence frequency of the event that is the source of the interrupt signal is low, a statistical multiplexing effect can be expected, so that it can be handled by one interrupt display register 32 and can be handled with a small memory capacity.

11 OLT (Optical Subscriber Line Termination Equipment)
12 ONU (Optical subscriber line network equipment)
13 Optical Fiber 14 Optical Splitter 21 MAC Control Unit 22 CPU (Central Processing Unit)
23 Interrupt Display Register 31 Arbitration Circuit 32 Interrupt Display Register 33 Interrupt Signal Aggregation Unit 34 Interrupt Signal Output Control Unit

Claims (3)

In an MPCP processing device that outputs an interrupt signal of MPCP (Multi-point Control Protocol) that performs access control between a plurality of ONUs connected in one-to-many with an OLT to a CPU,
Interrupt signals corresponding to the plurality of ONUs are input, and in accordance with the priority order of the interrupt factors for the plurality of interrupt signals of one ONU generated at the minimum reception interval of the MPCP frame, and the minimum of the MPCP frame by outputting in the order corresponding to the priority of the ONU to the interrupt signal of the same interrupt source of the plurality of ONU that occur in the reception interval, the arbitration circuit for outputting the arbitration of the interrupt signal,
An MPCP processing apparatus comprising: an interrupt display register that stores interrupt signals that are sequentially output by output arbitration of the arbitration circuit and outputs the interrupt signals to the CPU in the order of storage. The MPCP processing apparatus according to claim 1,
The arbitration circuit has a function of storing a plurality of interrupt signals of one ONU generated at a minimum reception interval of MPCP frames in the interrupt display register at the minimum reception interval. . The MPCP processing apparatus according to claim 1,
The MPCP processing apparatus, wherein the arbitration circuit is configured to set the priority order of the ONUs in the order of younger identification numbers assigned in the MPCP processing apparatus when a communication link is established.

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