JP5023415B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device composed of a DRAM (Dynamic Random Access Memory) and a manufacturing method thereof, and a semiconductor device in which a DRAM and a logic element are mixedly mounted and a manufacturing method thereof.
[0002]
[Prior art]
Due to the miniaturization competition accelerated year by year, a composite device in which a large-capacity DRAM and a high-speed logic element are mounted on one chip is being developed. As an example of the configuration, memory cell gates of DRAMs are stacked on a substrate, and so-called self-aligned contacts are used to take out diffusion layers of memory cell transistors, while logic elements are formed without using self-aligned contacts. That is the structure.
[0003]
[Problems to be solved by the invention]
However, various problems have also become apparent in stacked DRAMs.
[0004]
In order to maintain the transistor performance, the substrate concentration is increasing with the reduction of DRAM memory cells, and the junction leakage in the DRAM region is approaching a severe state. For this reason, it has become difficult to suppress junction leakage in a megabit class DRAM. That is, it has become difficult to maintain the data retention characteristics of a DRAM that could be controlled with a margin. If this is the case, the only effective means is to increase the capacitor capacity for each generation.
[0005]
In addition, with the reduction in the size of DRAM cells, the contact area between the diffusion layer and the extraction electrode is reduced, and the contact resistance is increased at twice the rate of generation. In the generation after 0.1 μm, this contact resistance is expected to be several kΩ, and is expected to be comparable to the on-resistance of the word transistor of the memory cell. Therefore, not only the cell transistor but also the variation in contact resistance severely affects the DRAM operation, and higher precision is required in manufacturing.
[0006]
Further, with the reduction in the size of DRAM cells, the interlayer insulation distance between the word line and the extraction contact of the diffusion layer formed on the side of the word line is getting closer to each generation. It is said that the limit distance is 20 nm to 30 nm in order to secure this withstand voltage when manufacturing a megabit class DRAM. For this reason, in the generation of DRAMs of 0.1 μm or later, it is necessary to form the extraction contact of the diffusion layer at a distance equal to or smaller than the withstand voltage limit distance.
[0007]
Conventionally, tungsten silicide (WSi)₂) / The word line of DRAM that has suppressed the delay by adopting the polycide structure of doped polysilicon has become stricter in aspect ratio with the recent miniaturization, and has a sufficiently low resistance to suppress the delay of the word line. It has become difficult to obtain. In particular, in stacked DRAMs that require high-speed operation, this word line delay becomes a serious problem that affects the access time of the DRAM. As a technique for reducing the resistance of the gate, reducing the resistance of the wiring by salicide has been put into practical use. However, in order to apply to the gate of a DRAM memory cell, no salicide is formed in the diffusion layer of the DRAM in order to prevent the reduction of the DRAM memory cell due to the inability to use the offset silicon oxide film and maintain the data retention characteristics. It is usually not possible due to difficulties such as requiring a process.
[0008]
In addition, the memory node contact of DRAM must have an opening with no margin due to its cell size, and like the diffusion layer contact, an opening at the withstand voltage limit is necessary, and the technology that efficiently suppresses the resistance increase with the narrow contact diameter. Is needed.
[0009]
On the other hand, the transistor performance of the logic part has also improved remarkably.⁺A gate electrode has become commonly used. However, this p⁺In the gate, impurity boron is diffused to the substrate side by heat treatment. It includes a so-called “penetration” problem and is known to cause serious problems such as variations in characteristics of p-channel transistors and depletion of gate electrodes. Widely used for DRAM diffusion layer contacts. Doped polysilicon is an indispensable material for activation by heat treatment, and attention must be paid to consistency when mixed.
[0010]
In this way, even if the technology is acceptable in the current 0.18 μm generation, some countermeasures will be required in the future 0.1 μm generation and beyond, and in order to maintain the chip performance trend, it is accumulated. A drastic improvement in the type DRAM structure is expected.
[0011]
[Means for Solving the Problems]
The present invention is a semiconductor device and a method for manufacturing the same, which have been made to solve the above problems.
[0012]
A first semiconductor device of the present invention includes an element isolation region formed in a semiconductor substrate, a well diffusion layer formed in the semiconductor substrate isolated by the element isolation region, the semiconductor substrate, and the element isolation region And a channel formed in the semiconductor substrate between the bottom of the groove and the well diffusion layer. The groove is formed in a state where a part of the semiconductor substrate is left on the well diffusion layer. A diffusion layer; a word line embedded in the trench through a gate insulating film; a diffusion layer formed on the semiconductor substrate surface side of the trench sidewall; a silicide layer formed on the word line upper layer; A take-out electrode connected to the diffusion layer in a state of being overlapped with the word line via an insulating film on the word line.
[0013]
In the first semiconductor device, since the channel diffusion layer is formed in the semiconductor substrate between the lower portion of the groove where the channel is formed and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer Becomes higher than the impurity concentration of the semiconductor substrate around the trench. In addition, since the concentration of the semiconductor substrate under the diffusion layer that becomes the source / drain is extremely low, the electric field at the junction of the diffusion layer that becomes the source / drain is weakened, so it is possible to suppress junction leakage in the ppm order. Thereby, the data retention characteristic is extremely improved.
[0014]
Since the silicide layer is formed above the word line, the resistance of the word line is reduced, the delay problem is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line is reduced.
[0015]
In addition, since the diffusion layer is formed on the surface of the semiconductor substrate, and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film, the channel is formed at the bottom of the groove where the word line is formed. It is formed so as to go around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0016]
Further, since the impurity concentration of the diffusion layer decreases in the depth direction, the semiconductor substrate concentration below the diffusion layer in the memory element region does not have to be so high as required for the cell transistor. The electric field is relaxed, and the performance of the data retention characteristic that becomes severe as the cell size of the memory element is reduced is maintained.
[0017]
In addition, it is connected to a diffusion layer formed on the surface of the semiconductor substrate on the word line buried in the groove formed in the semiconductor substrate via the gate insulating film, and overlapping with the word line via the insulating film. Therefore, a sufficient film thickness of 20 nm to 30 nm or more can be secured for the insulating film on the word line. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0018]
According to a first method of manufacturing a semiconductor device of the present invention, a step of forming an isolation region on a semiconductor substrate and then forming a buffer layer on the semiconductor substrate, and a well in the semiconductor substrate separated by the isolation region A step of forming a diffusion layer, and a step of forming a groove at a position where word lines of the buffer layer, the semiconductor substrate, and the element isolation region are formed in a state where a part of the semiconductor substrate is left on the well diffusion layer. Forming a channel diffusion layer in the semiconductor substrate between the bottom of the trench and the well diffusion layer, forming a gate insulating film in the trench and on the semiconductor substrate, and on the semiconductor substrate Forming a conductive layer filling the groove, and removing the conductive layer on the semiconductor substrate on the semiconductor substrate while leaving the conductive layer inside the groove. Forming a word line with the conductive layer left in the trench; forming a diffusion layer on the semiconductor substrate above the trench sidewall; and forming a sidewall insulating film on the trench sidewall on the word line. A step of forming a layer, a step of forming an insulating film on the semiconductor substrate so as to fill an upper portion of the groove, and a state of overlapping the word line on the word line via the insulating film. A step of forming a connection hole reaching the diffusion layer formed in the memory element region; and a step of forming an extraction electrode in the connection hole.
[0019]
In the first method for manufacturing a semiconductor device, since the buffer layer is formed, the buffer layer is used as a mask when the impurity for forming the channel diffusion layer is introduced into the semiconductor substrate at the bottom of the trench. Then, impurities are selectively introduced into the semiconductor substrate at the bottom of the trench to form a channel diffusion layer.
[0020]
As described above, since the channel diffusion layer is formed in the semiconductor substrate between the groove lower portion and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer is higher than the impurity concentration of the semiconductor substrate around the groove. Get higher. Further, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened. For this reason, it becomes possible to suppress junction leakage on the order of ppm, thereby forming a semiconductor device with extremely good data retention characteristics.
[0021]
In addition, it is connected to a diffusion layer formed on the surface of the semiconductor substrate on the word line buried in the groove formed in the semiconductor substrate via the gate insulating film, and overlapping with the word line via the insulating film. Therefore, it is possible to secure a sufficient film thickness of 20 nm to 30 nm or more for the insulating film on the word line. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0022]
Further, since the silicide layer is formed on the upper layer of the word line, the resistance of the word line is reduced and the delay problem is avoided. At the same time, the contact resistance to the word line is reduced.
[0023]
In addition, since the diffusion layer is formed on the semiconductor substrate surface side and the word line is embedded in the groove formed in the semiconductor substrate via the gate insulating film, the channel is the bottom of the groove where the word line is formed. It is formed so as to go around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0024]
Further, since the diffusion layer in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate below the diffusion layer in the memory element region is not so high as required for the cell transistor. Therefore, the electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the cell size of the memory element is reduced is maintained.
[0025]
  A second semiconductor device of the present invention is a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate. That is, the transistor of the memory element includes an element isolation region formed in a semiconductor substrate, a well diffusion layer formed in the semiconductor substrate separated by the element isolation region, and the semiconductor substrate and the element isolation region. A groove formed in a state where a part of the semiconductor substrate is left on the well diffusion layer, and a channel diffusion formed in the semiconductor substrate between the bottom of the groove and the well diffusion layer. A layer, a word line embedded in the trench through a gate insulating film, a diffusion layer formed on the trench sidewall on the semiconductor substrate surface side, a silicide layer formed on the word line upper layer, And a take-out electrode connected to the diffusion layer in a state of overlapping the word line via an insulating film on the word line. The transistor of the logic element is formed on the semiconductor substrate, and is formed on a surface of the semiconductor substrate on both sides of the gate electrode and a gate electrode having a polymetal structure in which a polysilicon electrode and a metal-based electrode are stacked. And a silicide layer formed on the diffusion layer.The gate electrode of the logic element is formed by sequentially forming a polysilicon layer and a dummy layer made of a material having etching selectivity with the polysilicon layer on the semiconductor substrate, and then the polysilicon layer and the dummy layer. And forming a dummy gate with the polysilicon layer and the dummy layer on the semiconductor substrate in the logic element region via the gate insulating film, and then forming a logic element on the surface of the semiconductor substrate on both sides of the dummy gate. Forming a low-concentration diffusion layer, and then forming a sidewall insulating film on the side wall of the dummy gate, and then forming the diffusion layer on the semiconductor gate on both sides of the dummy gate via the low-concentration diffusion layer on the dummy gate side. After that, an insulating film is formed so as to fill the upper portion of the groove and cover the dummy gate, and then the surface of the insulating film is formed The upper portion of the dummy gate is exposed, and the dummy layer is removed to expose the polysilicon layer to form a gate groove, and then the dummy gate polysilicon layer is doped with impurities, and then A heat treatment for activating the extraction electrode and the polysilicon layer is performed, and then the gate groove is replaced with a metal electrode.
[0026]
In the second semiconductor device, since the channel diffusion layer is formed in the semiconductor substrate between the lower part of the groove where the channel is formed and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer Becomes higher than the impurity concentration of the semiconductor substrate around the trench. In addition, since the concentration of the semiconductor substrate under the diffusion layer that becomes the source / drain is extremely low, the electric field at the junction of the diffusion layer that becomes the source / drain is weakened, so it is possible to suppress junction leakage in the ppm order. Thereby, the data retention characteristic is extremely improved.
[0027]
Since the silicide layer is formed above the word line, the resistance of the word line is reduced, the delay problem is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line is reduced. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer is reduced.
[0028]
In addition, since the diffusion layer is formed on the surface of the semiconductor substrate, and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film, the channel is formed at the bottom of the groove where the word line is formed. It is formed so as to go around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0029]
Further, since the impurity concentration of the diffusion layer decreases in the depth direction, the semiconductor substrate concentration below the diffusion layer in the memory element region does not have to be so high as required for the cell transistor. The electric field is relaxed, and the performance of the data retention characteristic that becomes severe as the cell size of the memory element is reduced is maintained.
[0030]
In addition, it is connected to a diffusion layer formed on the surface of the semiconductor substrate on the word line buried in the groove formed in the semiconductor substrate via the gate insulating film, and overlapping with the word line via the insulating film. Therefore, a sufficient film thickness of 20 nm to 30 nm or more can be secured for the insulating film on the word line. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0031]
  According to a second method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, an element isolation region is formed on the semiconductor substrate and then the semiconductor substrate is formed on the semiconductor substrate. A step of forming a buffer layer; a step of forming a well diffusion layer in the semiconductor substrate in the memory element region isolated by the element isolation region; and a state in which a part of the semiconductor substrate is left on the well diffusion layer Forming a groove at a position where the word line of the buffer layer and the semiconductor substrate and the element isolation region is formed, and forming a channel diffusion layer in the semiconductor substrate between the bottom of the groove and the well diffusion layer. A step of forming a gate insulating film in the groove and on the semiconductor substrate; and a conductive layer filling the groove on the semiconductor substrate in the memory element region. A step of forming, forming a well diffusion layer on the semiconductor substrate in the logic device region isolated by the element isolation region, wherein the semiconductor substrateToA step of forming a dummy layer made of a material having etching selectivity between the silicon layer and the polysilicon layer in order, and processing the polysilicon layer and the dummy layer to form the gate insulation on the semiconductor substrate in the logic element region Forming a dummy gate with the polysilicon layer and the dummy layer through a film, and removing the conductive layer on the semiconductor substrate on the semiconductor substrate while leaving the conductive layer inside the groove Forming a word line with the conductive layer left in the trench, forming a diffusion layer on the semiconductor substrate above the trench sidewall, and logic elements on the semiconductor substrate surfaces on both sides of the dummy gate. Forming a low-concentration diffusion layer, forming a sidewall insulating film on a side wall of the dummy gate, and forming a semiconductor substrate on both sides of the dummy gate on the semiconductor substrate. Forming a diffusion layer on the gate side via the low-concentration diffusion layer, forming a sidewall insulating film on the side wall of the groove on the word line, and forming the word line upper layer and the logic element diffusion layer upper layer. A step of forming a silicide layer, a step of forming an insulating film so as to fill the upper portion of the groove and covering the dummy gate, and a memory in a state of overlapping the word line via the insulating film on the word line Forming a connection hole reaching the diffusion layer formed in the element region; forming a take-out electrode in the connection hole; planarizing the insulating film surface and exposing an upper portion of the dummy gate; Removing the dummy layer to expose the polysilicon layer to form a gate groove; and impurity in the polysilicon layer of the dummy gate A step of doping, and performing heat treatment for activating the extraction electrode and the polysilicon layer, a method of manufacturing a semiconductor device including the step of forming a metallic electrode on the gate groove.
[0032]
In the second method for manufacturing a semiconductor device, since the buffer layer is formed, the buffer layer is used as a mask when impurities for forming the channel diffusion layer are introduced into the semiconductor substrate at the bottom of the trench. Then, impurities are selectively introduced into the semiconductor substrate at the bottom of the trench to form a channel diffusion layer.
[0033]
As described above, since the channel diffusion layer is formed in the semiconductor substrate between the groove lower portion and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer is higher than the impurity concentration of the semiconductor substrate around the groove. Get higher. Further, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened. For this reason, it becomes possible to suppress junction leakage on the order of ppm, thereby forming a semiconductor device with extremely good data retention characteristics.
[0034]
In addition, it is connected to a diffusion layer formed on the surface of the semiconductor substrate on the word line buried in the groove formed in the semiconductor substrate via the gate insulating film, and overlapping with the word line via the insulating film. Therefore, it is possible to secure a sufficient film thickness of 20 nm to 30 nm or more for the insulating film on the word line. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0035]
Further, since the silicide layer is formed on the upper layer of the word line, the resistance of the word line is reduced and the delay problem is avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer is reduced.
[0036]
In addition, since the diffusion layer is formed on the semiconductor substrate surface side and the word line is embedded in the groove formed in the semiconductor substrate via the gate insulating film, the channel is the bottom of the groove where the word line is formed. It is formed so as to go around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0037]
Further, since the diffusion layer in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate below the diffusion layer in the memory element region is not so high as required for the cell transistor. Therefore, the electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the cell size of the memory element is reduced is maintained.
[0038]
Further, by using a laminated structure of a polysilicon layer and a dummy layer for the dummy gate formed in the logic element region, the dummy layer is removed after forming the extraction electrode of the diffusion layer in the memory element region, and the dummy gate polysilicon It becomes possible to dope impurities into the layer. Thereafter, heat treatment is performed to form the metal gate electrode, so that the problem of boron penetration in the p-channel gate electrode due to the heat treatment is minimized.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.
[0040]
As shown in FIG. 1, the semiconductor substrate 11 is, for example, 1 × 10.¹⁷/ Cm^ThreeIt is composed of a silicon substrate having a p-type impurity concentration of about. The semiconductor substrate 11 is formed with an element isolation region 12 for isolating a memory element region (hereinafter referred to as a DRAM and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like. The element isolation region 12 is formed to a depth of, for example, about 0.1 μm to 0.2 μm, for example, by STI (Shallow Trench Isolation) technology. Further, a buffer layer 71 covering the element isolation region 12 is provided on the semiconductor substrate 11.
For example, a silicon oxide film is formed to a thickness of 20 nm to 40 nm, for example.
[0041]
The buffer layer 71 is necessary for manufacturing. That is, the buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. The buffer layer 71 is connected to the DRAM junction during ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be described later. In addition, when the silicide layer 27 is formed on the surface of the word line 18 embedded in the groove 14, the silicide layer 27 is formed on the diffusion layer 19 in the DRAM region. It has a function of preventing formation.
[0042]
In the semiconductor substrate 11 in the memory element region, the well diffusion layer 13 has, for example, an upper surface deeper than 150 nm to 200 nm, a lower surface slightly deeper than the depth of the element isolation region 12, and a depth direction. For example, the thickness is about 0.8 μm. The well diffusion layer 13 is P-type, for example, formed by introducing boron. For example, when formed by ion implantation, boron is used as the ion species, and the dose amount is, for example, 5 × 10.¹²/ Cm²~ 7 × 10¹²/ Cm²To the extent.
[0043]
Furthermore, an element isolation diffusion layer (not shown) may be formed in the semiconductor substrate 11 below the element isolation region 12 as necessary.
[0044]
Further, a trench 14 is formed in the element isolation region 12 and the semiconductor substrate 11 so as to penetrate the buffer layer 71 and form a word line (including a gate electrode) in the DRAM region. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and is formed so that the semiconductor substrate 11 remains between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0045]
Further, the edge portion of the bottom of the groove 14 is preferably formed in a so-called round shape in order to avoid the electric field concentration of the cell transistor, and the width of the groove 14 becomes the channel length of the access transistor of the memory element. Therefore, it is desirable that the side wall of the groove 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible.
[0046]
Further, a channel diffusion layer 15 is formed in the semiconductor substrate 11 between the bottom of the groove 14 and the well diffusion layer 13. The channel diffusion layer 15 of the word transistor in the DRAM region has a high concentration (for example, 1.0 × 10¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^Three) Must be a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall and the upper portion of the groove 14 may have a very low concentration. Therefore, the semiconductor substrate 11 portion below the diffusion layer 19 described later has an extremely low concentration (for example, 1.0 × 10 10).¹⁷/ Cm^Three~ 1.0 × 10¹⁸/ Cm^Three).
[0047]
A gate insulating film 16 is formed on the inner surface of the groove 14 and the semiconductor substrate 11. The gate insulating film 15 has a slightly thicker film thickness than a state-of-the-art logic transistor and has a slightly longer gate length. Therefore, even in this generation, application of a silicon oxide film by thermal oxidation is possible. Is possible. Therefore, the gate insulating film 15 in the DRAM region is formed of a silicon oxide film having a thickness of about 1.5 nm to 5 nm, for example.
[0048]
Further, a word line (including a gate electrode) 18 made of, for example, a phosphorus-doped polysilicon film is formed through the gate insulating film 16 so as to fill each groove 14. The word line 18 has a lower layer formed of a polysilicon layer and an upper layer formed of a silicide (for example, salicide) layer 21. A sidewall insulating film 20 is formed of, for example, a silicon nitride film on the side wall of the groove 14 on the polysilicon layer of the word line 18. The word line 18 is preferably 50 nm so that the surface of the word line 18 is at least about 30 nm to 100 nm lower than the surface of the semiconductor substrate 11 above the groove 14 as a distance at which a breakdown voltage is secured with at least a later-described extraction electrode 24. It is formed so as to be lowered by about 90 nm. In this embodiment, for example, it is formed in a state of being lowered by about 50 nm. For this reason, a withstand voltage distance from a take-out electrode 24 of a diffusion layer described later is secured.
[0049]
Further, the silicide layer 21 is made of, for example, cobalt silicide (CoSi).₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. are used. The sidewall insulating film 20 has a function of ensuring a breakdown voltage between the silicide layer 21 and the diffusion layer 19. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0050]
Further, a diffusion layer 19 serving as a source / drain is formed in the semiconductor substrate 11 in the DRAM region. This diffusion layer 19 uses phosphorus as an N-type impurity and has a concentration of 1 × 10 5.¹⁷/ Cm^Three~ 1x10¹⁸/ Cm^ThreeIt has become. Therefore, the semiconductor substrate 11 in this region is 1 × 10¹⁶/ Cm^Three~ × 10¹⁷/ Cm^ThreeIt is set to a very thin concentration.
[0051]
Therefore, this NP junction is a super-graded junction (a junction with a very gentle concentration gradient). The junction in such a state relaxes the electric field at the time of reverse bias, and dramatically contributes to suppression of junction leakage current that is worse by about two orders of magnitude than usual, which occurs in a defective bit of only ppm order in a megabit class DRAM. The data retention characteristics of the defective bits dominate the DRAM chip performance, and it is an important technique for maintaining the data retention characteristics in future DRAMs.
[0052]
For example, the substrate concentration is 5 × 10¹⁶/ Cm^ThreeIf this is the case, a data retention characteristic of 500 ms or more can be obtained at 85 ° C., which is expected to exhibit performance comparable to the data retention characteristic of the previous 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed by rounding the semiconductor substrate 11, the effective channel length can be ensured to be long, and the short channel effect can be used by applying a back bias. Therefore, it is possible to stabilize the transistor characteristics of the DRAM cell which is severe.
[0053]
A first insulating film (insulating film) 22 is formed on the entire surface of the semiconductor substrate 11. The surface of the first insulating film 22 is flattened. Further, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective in suppressing junction leakage in the salicide forming portion, but it is not necessary to form the cap insulating film 80 if unnecessary.
[0054]
Further, a first insulating film (insulating film) 22 is formed on the entire surface. In the first insulating film 22, a connection hole 23 that penetrates the cap insulating film 80, the buffer layer 71 and the like and reaches the diffusion layer 19 in the DRAM region is formed. The connection hole 23 is desirably formed as large as possible in the opening diameter of the connection hole 23 so that the extraction electrode can be brought into contact with the entire surface of the diffusion layer 19. Thereby, the contact resistance is reduced.
[0055]
In the drawing, a state where a slight misalignment is intentionally described is described. However, if excessive over-etching is not performed when the connection hole is opened, the physical distance of the extraction electrode 24 of the word line formed in the connection hole 23 is shown. Can be secured. In the projection design seen from above, the connection hole 23 completely overlaps the word line (gate electrode) 18. In the connection hole 23, an extraction electrode 24 made of, for example, phosphorus-doped polysilicon is formed.
[0056]
The surface of the second insulating film 22 is flattened so that the upper surface of the extraction electrode 24 is flush with the surface of the second insulating film 22. Further, an etching stop layer 25 that covers the extraction electrode 24 is formed on the second insulating film 22.
[0057]
A connection hole 26 reaching the silicide layer 21 on the word line 18 in the DRAM region is formed in the etching stop layer 25, the first insulating film 22, and the cap insulating film 80. An extraction electrode 27 is formed in the connection hole 26. The extraction electrode 27 is made of a tungsten film 86 formed so as to be embedded in the connection hole 26 through an adhesion layer 85 made of a titanium nitride film.
[0058]
A second insulating film 31 covering the extraction electrode 27 is formed on the etching stop layer 25. The second insulating film 31 is formed, for example, by depositing a silicon oxide film to a thickness of 50 nm to 150 nm.
[0059]
A bit contact hole 32 connected to the extraction electrode 24 is formed in the second insulating film 31 and the etching stop layer 25. A bit line 34 is formed on the second insulating film 31, and a part of the bit line 34 is connected to the extraction electrode 24 through the bit contact hole 32. A local wiring 35 is formed on the second insulating film 31. The bit line 34 and the local wiring 35 are formed of, for example, a tungsten film 37, an adhesion layer 36 is formed in the lower part thereof, and a cap layer 38 is formed in the upper part thereof.
[0060]
On the second insulating film 22, an etching stopper layer 41 and a third insulating film 42 that cover the bit line 34 and the local wiring 35 are formed. The etching stopper layer 41 is an ALD silicon nitride film and is formed to a thickness of, for example, 30 nm to 50 nm.
[0061]
A connection hole 43 is formed from the third insulating film 42 to the etching stopper layer 25 to form a storage node contact reaching the extraction electrodes 24 and 24 of the storage node contact. In the connection hole 43, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a film thickness that can ensure the breakdown voltage between the bit line and the storage node contact. Further, a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is made of a material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or ruthenium oxide. The surface of the third insulating film 42 is flattened together with the upper surface of the storage node contact 44, for example.
[0062]
A fourth insulating film 45 is formed on the third insulating film 42. In the fourth insulating film 45, a recess 46 in which a capacitor is formed is formed so that the upper surface of the storage node contact 44 is exposed at the bottom. A capacitor 91 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed in the recess 46. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the electrodes 92 and 94 are made of a ruthenium (Ru) or ruthenium oxide (RuO) material, and the electrodes 92 and 94 are used. The dielectric film 93 formed therebetween has BST (BaTiO_ThreeAnd SrTiO_ThreeA mixed crystal) film is used.
[0063]
A fifth insulating film 47 is formed on the fourth insulating film 45 to cover the MIM structure capacitor 91. The surface of the fifth insulating film 47 is flattened. In the fifth insulating film 47 to the first insulating film 22, connection holes 111, 112, 113 and the like for forming a capacitor extraction electrode, a word line extraction electrode, a local wiring extraction electrode, and the like are formed.
[0064]
In each of the connection holes 111, 112, 113, etc., a capacitor extraction electrode 121, a word line extraction electrode 122, a local wiring extraction electrode 123, and the like are formed.
[0065]
Further, a sixth insulating film 48 is formed on the fifth insulating film 47. In the sixth insulating film 48, wiring grooves 131, 132, 133 reaching the respective electrodes 121, 122, 123 are formed, and first wirings 141-143 are formed in the respective wiring grooves 131-133. . The first wirings 141 to 143 are made of copper wiring, for example. Although not shown, upper layer wiring is further formed as necessary. The electrodes 121 to 123 and the wires 141 to 143 are each formed with a generally known adhesion layer and barrier layer depending on the materials of the electrodes, wires, and insulating films.
[0066]
In the first semiconductor device, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the groove 14 where the channel is formed and the well diffusion layer 13, the groove 14 and the well diffusion layer 13 The impurity concentration in the intermediate region is higher than the impurity concentration of the semiconductor substrate 11 around the trench 14. In addition, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain is extremely low, the junction electric field of the diffusion layer 19 is weakened, so that junction leakage can be suppressed in the ppm order. Thereby, the data retention characteristic is extremely improved.
[0067]
Since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line 18 is reduced.
[0068]
In addition, since the diffusion layer is formed on the surface side of the semiconductor substrate 11 and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film, the channel is a groove in which the word line is formed. It is formed so as to go around the semiconductor substrate on the bottom side. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0069]
Further, since the impurity concentration of the diffusion layer 19 is reduced in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region does not have to be as high as required for the cell transistor. The electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the memory cell shrinks is maintained.
[0070]
In addition, the semiconductor device overlaps the word line 18 via the first insulating film 22 on the word line 18 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode 24 connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the first insulating film 22 on the word line 18 can have a sufficient film thickness of 20 nm to 30 nm or more. It becomes possible. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0071]
An example of an embodiment according to a first method for manufacturing a semiconductor device of the present invention will be described with reference to schematic configuration sectional views of FIGS. 2 to 19 show a manufacturing method for forming a memory element and a logic element on the same semiconductor substrate, and the same components as those described with reference to FIG. 1 are given the same reference numerals.
[0072]
As shown in (1) of FIG. 2, as the semiconductor substrate 11, for example, 1 × 10¹⁷/ Cm^ThreeA silicon substrate having an approximately p-type impurity concentration is prepared. For example, by STI (Shallow Trench Isolation) technology, an element isolation region for isolating a memory element region (hereinafter referred to as a DRAM and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like on the semiconductor substrate 11. 12 is formed. The element isolation region 12 is formed to a depth of about 0.1 μm to 0.2 μm, for example. Next, a buffer layer 71 made of, for example, a silicon oxide film is formed on the semiconductor substrate 11 so as to cover the element isolation region 12 by chemical vapor deposition (hereinafter referred to as CVD, where CVD is an abbreviation for Chemical Vapor Deposition), for example, 20 nm to 40 nm. The thickness is formed.
[0073]
Further, after a resist film 201 is formed on the semiconductor substrate 11, an opening 202 is formed on the memory cell formation region in the DRAM region using a lithography technique.
[0074]
Next, for example, boron is introduced into the semiconductor substrate 11 in the memory element region by ion implantation using the resist film 201 as a mask to form the well diffusion layer 13. As the ion implantation conditions, boron is used as the ion species, and the dose amount is 5 × 10 5, for example.¹²/ Cm²~ 7 × 10¹²/ Cm²For example, it is deeper than 150 nm to 200 nm and slightly deeper than the element isolation region 12 so as to be deeper than the depth of a groove to be formed later. The well diffusion layer 13 has a thickness in the depth direction of, for example, about 0.8 μm.
[0075]
Furthermore, an element isolation diffusion layer (not shown) may be formed in the semiconductor substrate 11 below the element isolation region 12 as necessary.
[0076]
The buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. Further, it functions as a stopper for ion implantation for a region that becomes a junction of the DRAM at the time of ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be performed later. In addition, when salicide is formed on the surface of the word line buried in the trench, the salicide is prevented from being formed in the diffusion layer of the DRAM region. Thereafter, the resist film 201 is removed.
[0077]
Next, as shown in FIG. 3B, after a resist film 203 is formed on the semiconductor substrate 11, an opening 204 is formed in the resist film 203 on a region to be a word line (gate electrode) in the DRAM region by lithography. Form.
[0078]
Next, as shown in FIG. 4C, using the resist film 203 as an etching mask, the buffer layer 71, the element isolation region 12, and the semiconductor substrate 11 are etched (for example, continuously etched) to form an element isolation region. 12 (field) and the semiconductor substrate 11 are formed with a trench 14 in which a word line (including a gate electrode) in the DRAM region is formed. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is left between the well diffusion layer 13 formed earlier and the bottom of the groove 14. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0079]
Further, since the groove 14 is formed only in the DRAM region, it is desirable that the edge portion at the bottom of the groove 14 be formed in a so-called round shape in order to avoid electric field concentration of the cell transistor. Is the channel length of the access transistor of the memory element, it is desirable that the side wall of the trench 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible. Note that the buffer layer 71 formed in the DRAM region is simultaneously etched when the element isolation region 12 is etched. Thereafter, the resist film 203 is removed by a normal removal technique.
[0080]
As for voltages assumed in this generation, the standard logic region is 0.5 V to 1.2 V, the high voltage logic region is 1.5 V to 2.5 V, and the DRAM cell word line boost is 1.5 V to 2 V. .5V.
[0081]
Next, as shown in FIG. 5D, a sacrificial oxide film (not shown) is formed to a thickness of, for example, 10 nm to 20 nm on the entire exposed surface of the semiconductor substrate 11 by, for example, thermal oxidation.
[0082]
Next, channel doping of the access transistor in the DRAM region is performed to form a channel diffusion layer 15 between the bottom of the trench 14 and the well diffusion layer 13.
[0083]
The channel diffusion layer 15 of the word transistor in the DRAM region has a high concentration (for example, 1.0 × 10¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^Three) Must be a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall or upper portion of the groove 14 needs to be almost ion-implanted as a substrate concentration. There is no. In the above ion implantation, the buffer layer 71 provided first is used as a mask for ion implantation on the surface of the semiconductor substrate 11 and the logic element region. Therefore, the channel diffusion layer is formed only at the bottom of the groove 14 without using a new mask. 15 can be formed. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 (see FIG. 30) described later has an extremely low concentration (for example, 1.0 × 10 10¹⁷/ Cm^Three~ 1.0 × 10¹⁸/ Cm^Three) Can be formed.
[0084]
Thereafter, the sacrificial oxide film (not shown) is removed by wet etching, for example. Thereafter, a gate insulating film 16 is formed on the inner surface of the groove 14 in the DRAM region, the semiconductor substrate 11 and the like by an ordinary gate oxide film forming method.
[0085]
As shown in FIG. 6 (5), a gate forming film 72 is formed of a phosphorus-doped polysilicon film on the gate insulating film 16 so as to fill each groove 14 in the DRAM region. Since this gate formation film 72 is used only for word lines in the DRAM region, N⁺Phosphorous doped polysilicon, which is a gate material, can be used. The gate formation film 72 is formed to a thickness of 50 nm to 150 nm, and the film thickness is set to a thickness optimized only for forming a groove-like word line.
[0086]
As shown in FIG. 7 (6), the gate formation film 72 is etched back so that the gate formation film 72 remains inside the trench 14. As a result, a word line (partly functioning as a gate electrode) 18 made of the gate formation film 72 is formed in the trench 14. At this time, the gate forming film 72 is etched back so that the surface of the word line 18 is about 30 nm to 100 nm lower than the surface of the semiconductor substrate 11, thereby ensuring a withstand voltage distance from the extraction electrode of the diffusion layer to be formed later. The In this etch back, the gate insulating film 16 functions as an etching stop layer.
[0087]
Further, ion implantation for forming source / drain is performed on the semiconductor substrate 11 in the DRAM region, thereby forming a diffusion layer 19. As an example of the ion implantation conditions, phosphorus is used as an impurity for ion implantation, and the concentration is 1 × 10.¹⁷/ Cm^Three~ 1x10¹⁸/ Cm^ThreeThe dose amount and the implantation energy are set so that Since the implantation energy penetrating the buffer layer 71 is sufficient, the implantation energy is set to, for example, 20 keV to 50 keV, and the dose amount is set to 1 × 10.¹⁸/ Cm²~ 3x10¹⁸/ Cm²Set to. If ion implantation is performed under these conditions, almost no ions are implanted into the semiconductor substrate 11 below the diffusion layer 19 in the DRAM region. Therefore, the semiconductor substrate 11 in this region is 1 × 10¹⁶/ Cm^Three~ × 10¹⁷/ Cm^ThreeIt becomes possible to set the density to a very low level.
[0088]
Therefore, this NP junction is a super-graded junction (a junction with a very gentle concentration gradient). The junction in such a state relaxes the electric field at the time of reverse bias, and dramatically contributes to suppression of junction leakage current that is worse by about two orders of magnitude than usual, which occurs in a defective bit of only ppm order in a megabit class DRAM. The data retention characteristics of the defective bits dominate the DRAM chip performance, and it is an important technique for maintaining the data retention characteristics in future DRAMs.
[0089]
For example, the substrate concentration is 5 × 10¹⁶/ Cm^ThreeIf this is the case, a data retention characteristic of 500 ms or more can be obtained at 85 ° C., which is expected to exhibit performance comparable to the data retention characteristic of the previous 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed by rounding the semiconductor substrate 11, the effective channel length can be ensured to be long, and the short channel effect can be used by applying a back bias. Therefore, it is possible to stabilize the transistor characteristics of the DRAM cell which is severe.
[0090]
In the above ion implantation, ion implantation is performed slightly shallowly in consideration of diffusion due to heat treatment related to the gate formation of the DRAM region later. However, since the DRAM gate is a substrate buried type, the channel of the DRAM region has a buried gate. Since it is formed at the bottom of the groove 14 to be formed, there is no problem. Further, since it is activated by a subsequent heat treatment, it is not necessary to perform the heat treatment at this stage.
[0091]
Next, as shown in FIG. 8 (7), a protective film 78 that protects the gate of the DRAM region is formed of, for example, a thin silicon nitride film (eg, a thickness of 10 nm to 50 nm). This protective film 78 is later formed in a sidewall shape on the side wall on the word line 18 in the DRAM region, and contributes to securing the breakdown voltage on the side wall of the word line 18 when the salicide is formed.
[0092]
Next, as shown in FIG. 9 (8), the DRAM region protective film 78 is etched by, for example, reactive ion etching (RIE) to expose the word line 18 in the DRAM region. As a result. A side wall 20 made of a protective film 78 is formed on the side wall of the groove 14 on the word line 18. This sidewall 20 has a function of protecting the sidewall. In the reactive ion etching, it is important to prevent the diffusion layer 19 in the DRAM region from being exposed, that is, to leave the buffer layer 71 on the diffusion layer 19.
[0093]
Further, as shown in FIG. 10 (9), a silicide layer 21 is selectively formed on the word line 18 in the DRAM region using a normal silicidation technique. In this manner, the silicide layer 21 is selectively formed on the word line 18 in the DRAM region where low resistance needs to be realized. As this silicide layer, for example, cobalt silicide (CoSi)₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. can be used.
[0094]
Thereafter, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective in suppressing junction leakage in the salicide forming portion, but it is not necessary to form the cap insulating film 80 if unnecessary. Note that as described above, a silicide layer may be formed also on the gate electrode of the transistor in the peripheral circuit portion to form a salicide structure, so that the resistance of the gate electrode can be reduced.
[0095]
Next, as shown in FIG. 11 (10), after a first insulating film (insulating film) 22 is formed on the entire surface, the surface of the first insulating film 22 is planarized by CMP. The method for planarizing the surface of the first insulating film 22 is not limited to CMP as long as the planarization can be realized, and for example, an etch back method or the like can be used. Thereafter, a resist film 215 is formed on the first insulating film 22, and then a connection hole pattern 216 for a diffusion layer extraction contact in the DRAM region is formed in the resist film 215 by a lithography technique.
[0096]
Next, etching is performed using the resist film 215 as an etching mask to form connection holes 23 that penetrate the first insulating film 22 and reach the diffusion layer 19 in the DRAM region, as shown in FIG. To do. At this time, since the word line (gate electrode) 18 in the DRAM region is disposed below the surface of the semiconductor substrate 11 rather than the diffusion layer 19 to be contacted, it is not necessary to use a special technique such as self-alignment contact. Further, it is desirable to make the opening diameter of the connection hole 23 as large as possible so that the entire surface of the diffusion layer 19 of the DRAM can contact the extraction electrode. Thereby, the contact resistance is reduced.
[0097]
In the drawing, the state in which the alignment is slightly shifted is intentionally described. However, if excessive over-etching is not performed when the connection hole is opened, the physical structure of the word line extraction electrode formed in the connection hole 23 in a later step is described. It is possible to ensure a sufficient distance. In the projection design seen from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.
[0098]
Next, an extraction electrode forming film 81 is formed on the first insulating film 22 so as to fill the connection hole 23. This extraction electrode forming film 81 is formed of, for example, phosphorus-doped polysilicon. As the extraction electrode forming film 81 for extracting the diffusion layer, phosphorus-doped polysilicon is preferably selected in the DRAM region in consideration of reduction of junction leakage as in the conventional case. Note that heat treatment for activation is not necessary at this stage.
[0099]
Thereafter, as shown in FIG. 13 (12), the excessive extraction electrode formation film 81 (phosphorus doped polysilicon) on the first insulating film 22 is removed by, for example, CMP, and the diffusion layer is formed in the connection hole 23. The extraction electrode 24 composed of the extraction electrode forming film 81 connected to the N-type electrode 19 is formed, and the first insulating film 22 is polished to flatten the surface.
[0100]
Thereafter, heat treatment is performed. By this heat treatment, the extraction electrode 24 made of polysilicon in the DRAM region is activated. In this heat treatment, RTA (Rapid Thermal Annealing) at 900 ° C. for about 10 seconds is sufficient. However, thermal annealing using a normal furnace can be performed. In the subsequent steps, since a high-temperature thermal process is not performed, for example, when a logic element is formed simultaneously with a DRAM, so-called “penetration” in which boron diffuses from the gate electrode of the logic element is minimized. Can be suppressed.
[0101]
Next, as shown in FIG. 14 (13), an etching stop layer 25 covering the extraction electrode 24 in the DRAM region is formed on the entire surface of the first insulating film 22 with, for example, a silicon oxide film.
[0102]
Thereafter, as shown in (14) of FIG. 15, after a resist film (not shown) is formed on the etching stop layer 25, a connection hole for a word line extraction contact in the DRAM region is formed in the resist film by lithography. A pattern (not shown) is formed. Subsequently, using the resist film as an etching mask, the connection hole reaching the silicide layer 21 on the word line 18 in the DRAM region through the etching stop layer 25, the first insulating film 22 and the cap insulating film 80. 26 is formed.
[0103]
Thereafter, the resist film is removed. Next, an adhesion layer 85 made of a titanium nitride film is formed on the inner surface of the connection hole 26 by an ordinary tungsten plug formation technique, and then a tungsten film 86 is formed so as to fill the connection hole 26. Thereafter, excess portions of the tungsten film 86 and the adhesion layer 85 on the etching stop layer 25 are removed by CMP, and an extraction electrode 27 is formed in the connection hole 26.
[0104]
Next, a second insulating film 31 is formed, for example, by depositing a silicon oxide film with a thickness of 50 nm to 150 nm on the entire surface of the etching stop layer 25 so as to cover the extraction electrode 27.
[0105]
Then, after forming a resist film (not shown) on the second insulating film 31, an opening (not shown) is formed at a position where a bit contact is formed in the resist film by lithography. By using the resist film as a mask, a bit contact hole 32 reaching the predetermined extraction electrode 24 is formed in the etching stopper layer 25 and the second insulating film 31 as shown in FIG.
[0106]
Next, a wiring metal layer for forming the bit line 34 and the local wiring 35 is formed. For the wiring metal layer, first, an adhesion layer 36 formed by laminating, for example, a titanium film and a titanium nitride film is formed on the inner surface of the bit contact hole 32 and the second insulating film 31. Further, a tungsten film 37 as a main material of the metal wiring is formed on the adhesion layer 36 so as to fill the bit contact hole 32. Further, a cap layer 38 is formed on the tungsten film 37 by, for example, a silicon nitride film.
[0107]
Thereafter, the cap layer 38, the tungsten film 37, and the adhesion layer 36 are patterned by a normal lithography technique and an etching technique to form a bit line 34 connected to the bit contact extraction electrode 24 through the bit contact hole 32. The local wiring 35 is formed. Therefore, the cap layer 38 is formed on the bit line 34 and the local wiring 35.
[0108]
Thereafter, an etching stopper layer 41 covering the bit line 34 is formed on the second insulating film 31 with an ALD silicon nitride film to a thickness of, for example, 30 nm to 50 nm.
[0109]
Next, as shown in FIG. 17 (16), a third insulating film 42 is formed on the etching stopper layer 41. Then, the surface of the third insulating film 42 is planarized using, for example, CMP. Next, after forming a resist film 219 on the third insulating film 42, an opening pattern 220 for opening a storage node contact is formed by lithography. The opening pattern 220 can be formed larger than the diameter of the connection hole in which the actual storage node contact is formed.
[0110]
Next, using the resist film 219 as an etching mask, etching is performed from the third insulating film 42 to the etching stop layer 25 as shown in FIG. A connection hole 43 for forming a storage node contact reaching 24 is formed. In this etching, in addition to the resist film 219 (see (16) in FIG. 17), the cap layer 38 and the etching stopper layer 41 serve as an etching mask. The etching stopper layer 41 is partially etched, but remains on the side wall of the bit line 34 as a side wall having a film thickness that can ensure the breakdown voltage between the bit line and the storage node contact. Thereafter, the resist film 219 (see (16) in FIG. 17) is removed.
[0111]
Next, as shown in FIG. 19 (18), a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is formed, for example, by depositing tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide or the like on the third insulating film 42 so as to fill the connection hole 43 and forming a material layer. The excess material layer on the third insulating film 42 is formed by the material layer left in the connection hole 43 by removing the material layer by CMP, for example.
[0112]
Next, a fourth insulating film 45 covering the storage node contact 44 and the like is formed on the third insulating film 42. Next, a recess 46 in which a capacitor is formed in the fourth insulating film 45 is formed so that the upper surface of the storage node contact 44 is exposed at the bottom.
[0113]
Thereafter, a capacitor 91 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed in the recess 46. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the electrodes 92 and 94 are made of a ruthenium (Ru) or ruthenium oxide (RuO) material, The film 93 has BST (BaTiO_ThreeAnd SrTiO_ThreeA mixed crystal) film is used.
[0114]
Next, a fifth insulating film 47 that covers the MIM structure capacitor 91 is formed on the fourth insulating film 45. Thereafter, the surface of the fifth insulating film 47 is planarized by CMP. Next, connection holes 111, 112, 113, and the like for forming capacitor extraction electrodes, word line extraction electrodes, and the like are formed in the fifth insulating film 47 to the second insulating film 31.
[0115]
Further, the capacitor extraction electrode 121, the word line extraction electrode 122, the local wiring extraction electrode 123, and the like are formed in the connection holes 111, 112, 113, and the like. Further, a sixth insulating film 48 is formed on the fifth insulating film 47. Next, wiring grooves 131, 132, 133 reaching the electrodes 121, 122, 123, etc. are formed in the sixth insulating film 48, and wirings 141, 142, 143 are formed in the wiring grooves 131, 132, 133. The wirings 141, 142, and 143 are made of copper wiring, for example. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121, 122, 123 and the wirings 141, 142, 143 are formed with commonly known adhesion layers and barrier layers depending on the materials of the electrodes, wirings, and insulating films.
[0116]
In the first method for manufacturing a semiconductor device, since the buffer layer 71 is formed, the buffer layer 71 is subsequently introduced when an impurity for forming the channel diffusion layer 15 is introduced into the semiconductor substrate 11 at the bottom of the trench 14. As a mask, impurities are selectively introduced into the semiconductor substrate 11 at the bottom of the trench 14 to form a channel diffusion layer 15.
[0117]
As described above, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the trench 14 and the well diffusion layer 13, the impurity concentration in the region between the trench 14 and the well diffusion layer 13 is around the trench 14. It becomes higher than the impurity concentration of the semiconductor substrate 11. Further, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer 19 is weakened. For this reason, it becomes possible to suppress junction leakage on the order of ppm, thereby forming a semiconductor device with extremely good data retention characteristics.
[0118]
In addition, the semiconductor device overlaps the word line 18 via the second insulating film 22 on the word line 18 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode 24 connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the second insulating film 22 on the word line 18 can have a sufficient film thickness of 20 nm to 30 nm or more. Become. Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0119]
Further, since the silicide layer 21 is formed on the upper layer of the word line 18, the resistance of the word line 18 is reduced and the problem of delay is avoided. At the same time, the contact resistance to the word line 18 is reduced.
[0120]
Further, since the diffusion layer 19 is formed on the surface side of the semiconductor substrate 11 and the word line 18 is embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16, the channel is the word line 18. It is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0121]
Further, since the diffusion layer 19 in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region is so high that the cell transistor is required. Since it is not necessary to increase the density, the electric field at the junction is relaxed, and the performance of data retention characteristics that become severe as the memory cell size is reduced is maintained.
[0122]
An embodiment according to a second semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.
[0123]
As shown in FIG. 20, the semiconductor substrate 11 is, for example, 1 × 10.¹⁷/ Cm^ThreeIt is composed of a silicon substrate having a p-type impurity concentration of about. The semiconductor substrate 11 is formed with an element isolation region 12 for isolating a memory element region (hereinafter referred to as a DRAM and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like. The element isolation region 12 is formed to a depth of, for example, about 0.1 μm to 0.2 μm, for example, by STI (Shallow Trench Isolation) technology. Further, a buffer layer 71 covering the element isolation region 12 is formed on the semiconductor substrate 11 with a thickness of, for example, 20 nm to 40 nm using, for example, a silicon oxide film.
[0124]
The buffer layer 71 is necessary for manufacturing. That is, the buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. The buffer layer 71 is connected to the DRAM junction during ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be described later. In addition, when the silicide layer 27 is formed on the surface of the word line 18 embedded in the groove 14, the silicide layer 27 is formed on the diffusion layer 19 in the DRAM region. It has a function of preventing formation.
[0125]
In the semiconductor substrate 11 in the memory element region, the well diffusion layer 13 has, for example, an upper surface deeper than 150 nm to 200 nm, a lower surface slightly deeper than the depth of the element isolation region 12, and a depth direction. For example, the thickness is about 0.8 μm. The well diffusion layer 13 is P-type, for example, formed by introducing boron. For example, when formed by ion implantation, boron is used as the ion species, and the dose amount is, for example, 5 × 10.¹²/ Cm²~ 7 × 10¹²/ Cm²To the extent.
[0126]
Furthermore, an element isolation diffusion layer (not shown) may be formed in the semiconductor substrate 11 below the element isolation region 12 as necessary.
[0127]
Further, a trench 14 is formed in the element isolation region 12 and the semiconductor substrate 11 so as to penetrate the buffer layer 71 and form a word line (including a gate electrode) in the DRAM region. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and is formed so that the semiconductor substrate 11 remains between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0128]
Further, the edge portion of the bottom of the groove 14 is preferably formed in a so-called round shape in order to avoid the electric field concentration of the cell transistor, and the width of the groove 14 becomes the channel length of the access transistor of the memory element. Therefore, it is desirable that the side wall of the groove 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible.
[0129]
Further, a channel diffusion layer 15 is formed in the semiconductor substrate 11 between the bottom of the groove 14 and the well diffusion layer 13. The channel diffusion layer 15 of the word transistor in the DRAM region has a high concentration (for example, 1.0 × 10¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^Three) Must be a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall and the upper portion of the groove 14 may have a very low concentration. Therefore, the semiconductor substrate 11 portion below the diffusion layer 19 described later has an extremely low concentration (for example, 1.0 × 10 10).¹⁷/ Cm^Three~ 1.0 × 10¹⁸/ Cm^Three).
[0130]
A gate insulating film 16 is formed on the inner surface of the groove 14 and the semiconductor substrate 11. The gate insulating film 15 has a slightly thicker film thickness than a state-of-the-art logic transistor and has a slightly longer gate length. Therefore, even in this generation, application of a silicon oxide film by thermal oxidation is possible. Is possible. Therefore, the gate insulating film 15 in the DRAM region is formed of a silicon oxide film having a thickness of about 1.5 nm to 5 nm, for example.
[0131]
Further, a word line (including a gate electrode) 18 made of, for example, a phosphorus-doped polysilicon film is formed through the gate insulating film 16 so as to fill each groove 14. The word line 18 has a lower layer formed of a polysilicon layer and an upper layer formed of a silicide (for example, salicide) layer 21. A sidewall insulating film 20 is formed of, for example, a silicon nitride film on the side wall of the groove 14 on the polysilicon layer of the word line 18. The word line 18 is preferably 50 nm so that the surface of the word line 18 is at least about 50 nm to 100 nm lower than the surface of the semiconductor substrate 11 above the groove 14 as a distance at which a breakdown voltage is secured with at least a later-described extraction electrode 24. It is formed so as to be lowered by about 90 nm. In this embodiment, for example, it is formed in a state of being lowered by about 50 nm. For this reason, a withstand voltage distance from a take-out electrode 24 of a diffusion layer described later is secured.
[0132]
Further, the silicide layer 21 is made of, for example, cobalt silicide (CoSi).₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. are used. The sidewall insulating film 20 has a function of ensuring a breakdown voltage between the silicide layer 21 and the diffusion layer 19. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0133]
Further, a diffusion layer 19 serving as a source / drain is formed in the semiconductor substrate 11 in the DRAM region. This diffusion layer 19 uses phosphorus as an N-type impurity and has a concentration of 1 × 10 5.¹⁷/ Cm^Three~ 1x10¹⁸/ Cm^ThreeIt has become. Therefore, the semiconductor substrate 11 in this region is 1 × 10¹⁶/ Cm^Three~ × 10¹⁷/ Cm^ThreeIt is set to a very thin concentration.
[0134]
Therefore, this NP junction is a super-graded junction (a junction with a very gentle concentration gradient). The junction in such a state relaxes the electric field at the time of reverse bias, and dramatically contributes to suppression of junction leakage current that is worse by about two orders of magnitude than usual, which occurs in a defective bit of only ppm order in a megabit class DRAM. The data retention characteristics of the defective bits dominate the DRAM chip performance, and it is an important technique for maintaining the data retention characteristics in future DRAMs.
[0135]
For example, the substrate concentration is 5 × 10¹⁶/ Cm^ThreeIf this is the case, a data retention characteristic of 500 ms or more can be obtained at 85 ° C., which is expected to exhibit performance comparable to the data retention characteristic of the previous 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed by rounding the semiconductor substrate 11, the effective channel length can be ensured to be long, and the short channel effect can be used by applying a back bias. Therefore, it is possible to stabilize the transistor characteristics of the DRAM cell which is severe.
[0136]
On the other hand, a P-well diffusion layer 51 of an N-channel transistor and an N-well diffusion layer (not shown) of the P-channel transistor are formed on the semiconductor substrate 11 in the standard voltage logic region. Also, a P-well diffusion layer (not shown) of an N-channel transistor and an N-well diffusion layer 61 of a P-channel transistor are formed on the semiconductor substrate 11 in the high voltage logic region. Note that channel doping is performed as necessary.
[0137]
Further, low-concentration diffusion layers 52 and 52 of N-channel transistors are formed in the semiconductor substrate 11 (P-well diffusion layer 51) in the N-channel transistor formation region of the standard voltage logic region. Further, a low-concentration diffusion layer (not shown) of the P-channel transistor is formed on the semiconductor substrate 11 in the p-channel transistor formation region of the standard voltage logic region.
[0138]
Further, low-concentration diffusion layers 62 and 62 of P-channel transistors are formed in the semiconductor substrate 11 (N-well diffusion layer 61) in the formation region of the P-channel transistor in the high voltage logic region. A low concentration diffusion layer (not shown) of the N channel transistor is formed on the semiconductor substrate 11 in the N channel transistor formation region of the high voltage logic region.
[0139]
On the logic element semiconductor substrate 11 (including the element isolation region 12), a logic element gate insulating film 17 is formed. In this generation, the gate insulating film is generally made according to the film thickness, and is made separately using a resist process. As the gate insulating film, silicon oxide or silicon nitride is used when heat resistance is required. In order to prevent boron (B) from penetrating from the P channel gate, for example, a silicon oxynitride film is used for the P channel gate.
[0140]
On the other hand, a gate electrode 51 is formed on the semiconductor substrate 11 in the standard voltage logic region via a gate insulating film 17. The gate electrode 51 is formed of a polysilicon gate layer made of phosphorus-doped polysilicon, and the upper layer is made of a metal gate electrode made of a laminated film of an adhesion layer formed by replacing a dummy layer and a metal layer. For example, a titanium nitride layer is used as the adhesion layer, and a tungsten layer is used as the metal layer. Further, a side wall 54 is formed on the side wall of the gate electrode 51 via the gate insulating film 17. The low concentration diffusion layers 52 and 52 are formed in the semiconductor substrate 11 below the sidewall 54, and the diffusion layers 55 and 55 are formed on the semiconductor substrate 11 on both sides of the gate electrode 51 through the low concentration diffusion layers 52 and 52. Is formed. A silicide layer 58 is formed on the diffusion layer 55. As the silicide layer 58, for example, cobalt silicide (CoSi)₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. can be used.
[0141]
A gate electrode 61 is formed on the semiconductor substrate 11 in the high voltage logic region with a gate insulating film 17 interposed therebetween. The gate electrode 61 is formed of a polysilicon gate layer formed of a boron-doped polysilicon layer, and an upper layer of a metal-based gate electrode formed of a laminated film of an adhesion layer formed by replacing a dummy layer and a metal layer, For example, a titanium nitride layer is used as the adhesion layer, and a tungsten layer is used as the metal layer. Further, a sidewall 64 is formed on the side wall of the gate electrode 61 via the gate insulating film 17. The low concentration diffusion layers 62 and 62 are formed in the semiconductor substrate 11 below the sidewall 64, and the diffusion layers 65 and 65 are formed on the semiconductor substrate 11 on both sides of the gate electrode 61 through the low concentration diffusion layers 62 and 62. Is formed. A silicide layer 68 is formed on the diffusion layer 65. As the silicide layer 58, for example, cobalt silicide (CoSi)₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. can be used.
[0142]
The sidewalls 54 and 64 are preferably formed of silicon oxide having a lower stress than silicon nitride and good releasability by wet treatment. Alternatively, a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film can be used.
[0143]
A gate electrode (gate wiring) 51 having the same structure as the gate electrode 51 is formed on the element isolation region 12 in the logic region.
[0144]
A first insulating film (insulating film) 19 is formed on the entire surface of the semiconductor substrate 11. The surface of the first insulating film 19 is flattened, and the surfaces of the gate electrodes 51 and 61 in the logic region are on the same plane.
[0145]
Further, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective in suppressing junction leakage in the salicide forming portion, but it is not necessary to form the cap insulating film 80 if unnecessary.
[0146]
Further, a first insulating film (insulating film) 22 is formed on the entire surface. In the first insulating film 22, a connection hole 23 that penetrates the cap insulating film 80, the buffer layer 71 and the like and reaches the diffusion layer 19 in the DRAM region is formed. The connection hole 23 is desirably formed as large as possible in the opening diameter of the connection hole 23 so that the extraction electrode can be brought into contact with the entire surface of the diffusion layer 19. Thereby, the contact resistance is reduced.
[0147]
In the drawing, a state where a slight misalignment is intentionally described is described. However, if excessive over-etching is not performed when the connection hole is opened, the physical distance of the extraction electrode 24 of the word line formed in the connection hole 23 is shown. Can be secured. In the projection design seen from above, the connection hole 23 completely overlaps the word line (gate electrode) 18. In the connection hole 23, an extraction electrode 24 made of, for example, phosphorus-doped polysilicon is formed.
[0148]
The surface of the second insulating film 22 is flattened so that the upper surface of the extraction electrode 24 and the upper surfaces of the gate electrodes 51 and 61 are flush with the surface of the second insulating film 22. Further, an etching stop layer 25 that covers the extraction electrode 24 and the gate electrodes 51 and 61 is formed on the second insulating film 22.
[0149]
In the etching stop layer 25, the first insulating film 22 and the cap insulating film 80, connection holes 26 and 58 reaching the silicide layer 21 on the word line 18 in the DRAM region and the silicide layers 57 and 67 of the transistor in the logic region. , 68 are formed. Extraction electrodes 27, 59, and 69 are formed in the connection holes 26, 58, and 68. The extraction electrodes 27, 59, and 69 are made of a tungsten film formed so as to fill the connection holes 26, 58, and 68 through an adhesion layer made of a titanium nitride film.
[0150]
A second insulating film 31 is formed on the etching stop layer 25 to cover the extraction electrodes 27, 59, and 69. The second insulating film 31 is formed, for example, by depositing a silicon oxide film to a thickness of 50 nm to 150 nm.
[0151]
A bit contact hole 32 connected to the extraction electrode 24 and a local hatching contact hole 33 connected to the extraction electrode 59 are formed in the second insulating film 31 and the etching stop layer 25. A bit line 34 is formed on the second insulating film 31, and a part of the bit line 34 is connected to the extraction electrode 24 through the bit contact hole 32. A local wiring 35 is formed on the second insulating film 31, and a part of the local wiring 35 is connected to the extraction electrode 59 through the local wiring contact hole 33. The bit line 34 and the local wiring 35 are formed of, for example, a tungsten film 37, an adhesion layer 36 is formed in the lower part thereof, and a cap layer 38 is formed in the upper part thereof.
[0152]
On the second insulating film 22, an etching stopper layer 41 and a third insulating film 42 that cover the bit line 34 and the local wiring 35 are formed. The etching stopper layer 41 is an ALD silicon nitride film and is formed to a thickness of, for example, 30 nm to 50 nm.
[0153]
A connection hole 43 is formed from the third insulating film 42 to the etching stopper layer 25 to form a storage node contact reaching the extraction electrodes 24 and 24 of the storage node contact. In the connection hole 43, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a film thickness that can ensure the breakdown voltage between the bit line and the storage node contact. Further, a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is made of a material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or ruthenium oxide. The surface of the third insulating film 42 is flattened together with the upper surface of the storage node contact 44, for example.
[0154]
A fourth insulating film 45 is formed on the third insulating film 42. In the fourth insulating film 45, a recess 46 in which a capacitor is formed is formed so that the upper surface of the storage node contact 44 is exposed at the bottom. A capacitor 91 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed in the recess 46. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the electrodes 92 and 94 are made of a ruthenium (Ru) or ruthenium oxide (RuO) material, and the electrodes 92 and 94 are used. The dielectric film 93 formed therebetween has BST (BaTiO_ThreeAnd SrTiO_ThreeA mixed crystal) film is used.
[0155]
A fifth insulating film 47 is formed on the fourth insulating film 45 to cover the MIM structure capacitor 91. The surface of the fifth insulating film 47 is flattened. In the fifth insulating film 47 to the first insulating film 22, a capacitor take-out electrode, a word line take-out electrode, a local wire take-out electrode, a diffusion layer take-out electrode in the logic region, a gate take-out electrode in the logic region, and the like are formed. The connection holes 111, 112, 113, 114 to 116, 117 are formed.
[0156]
In each of the connection holes 111, 112, 113, 114 to 116, 117, etc., there are a capacitor extraction electrode 121, a word line extraction electrode 122, a local wiring extraction electrode 123, a diffusion layer extraction electrode 124 of a standard voltage logic region, and a high voltage logic region. Diffusion layer extraction electrodes 125 and 126, a gate extraction electrode 127 in the logic region, and the like are formed.
[0157]
Further, a sixth insulating film 48 is formed on the fifth insulating film 47. In the sixth insulating film 48, wiring grooves 131, 132, 133, 134, 135, 136 reaching the respective electrodes 121, 122, 123, 124, 127, 125, 126 are formed, and the respective wiring grooves 131-136 are formed. Are formed with first wirings 141 to 146. The first wirings 141 to 146 are made of, for example, copper wiring. Although not shown, upper layer wiring is further formed as necessary. The electrodes 121 to 127 and the wirings 141 to 146 are formed with a generally known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0158]
In the second semiconductor device, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the groove 14 where the channel is formed and the well diffusion layer 13, the groove 14 and the well diffusion layer 13 The impurity concentration in the intermediate region is higher than the impurity concentration of the semiconductor substrate 11 around the trench 14. Further, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain is extremely low, the electric field at the junction of the diffusion layer 19 serving as the source / drain is weakened. Data retention characteristics are thereby greatly improved.
[0159]
Since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line 18 is reduced. Further, since the silicide layers 57 and 67 are formed on the diffusion layers 55 and 65 of the logic element, the contact resistance to the diffusion layers 55 and 65 is reduced.
[0160]
Moreover, since the diffusion layer 19 is formed on the surface side of the semiconductor substrate 11 and the word line 18 is buried in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16, the channel is connected to the word line 18. It is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0161]
Further, since the impurity concentration of the diffusion layer 19 is reduced in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region does not have to be as high as required for the cell transistor. The electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the memory cell shrinks is maintained.
[0162]
Further, the diffusion formed on the surface of the semiconductor substrate 11 on the word line 18 buried in the trench 14 via the gate insulating film 16 so as to overlap the word line 18 via the first insulating film 22. Since the extraction electrode 24 connected to the layer 19 is formed, it is possible to secure a sufficient film thickness of 20 nm to 30 nm or more for the second insulating film 22 on the word line 18. Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0163]
One example of an embodiment according to a method for manufacturing a semiconductor device of the present invention will be described with reference to schematic configuration sectional views of FIGS. 21 to 46 show a manufacturing method for forming the memory element and the logic element on the same semiconductor substrate, and the same reference numerals are given to the same components as described with reference to FIG.
[0164]
As shown in (1) of FIG. 21, as the semiconductor substrate 11, for example, 1 × 10¹⁷/ Cm^ThreeA silicon substrate having an approximately p-type impurity concentration is prepared. For example, by STI (Shallow Trench Isolation) technology, an element isolation region for isolating a memory element region (hereinafter referred to as a DRAM and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like on the semiconductor substrate 11. 12 is formed. The element isolation region 12 is formed to a depth of about 0.1 μm to 0.2 μm, for example. Next, a buffer layer 71 made of, for example, a silicon oxide film is formed on the semiconductor substrate 11 so as to cover the element isolation region 12 by chemical vapor deposition (hereinafter referred to as CVD, where CVD is an abbreviation for Chemical Vapor Deposition), for example, 20 nm to 40 nm. The thickness is formed.
[0165]
Further, after a resist film 201 is formed on the semiconductor substrate 11, the resist film 201 in a portion that becomes a DRAM region is removed using a lithography technique, and a logic region (hereinafter, a standard voltage logic region and a high voltage logic region are divided into logic regions). The resist film 201 is left on.
[0166]
Next, for example, boron is introduced into the semiconductor substrate 11 in the memory element region by ion implantation using the resist film 201 as a mask to form the well diffusion layer 13. As the ion implantation conditions, boron is used as the ion species, and the dose amount is 5 × 10 5, for example.¹²/ Cm²~ 7 × 10¹²/ Cm²For example, it is deeper than 150 nm to 200 nm and slightly deeper than the element isolation region 12 so as to be deeper than the depth of a groove to be formed later. The well diffusion layer 13 has a thickness in the depth direction of, for example, about 0.8 μm.
[0167]
Furthermore, an element isolation diffusion layer (not shown) may be formed in the semiconductor substrate 11 below the element isolation region 12 as necessary.
[0168]
The buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. Further, it functions as a stopper for ion implantation for a region that becomes a junction of the DRAM at the time of ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be performed later. In addition, when salicide is formed on the surface of the word line buried in the trench, the salicide is prevented from being formed in the diffusion layer of the DRAM region.
[0169]
Further, as shown in FIG. 22B, after a resist film 203 is formed on the semiconductor substrate 11, an opening 204 is formed in the resist film 203 on a region to be a word line (gate electrode) in the DRAM region by lithography. Form.
[0170]
Next, as shown in FIG. 23 (3), using the resist film 203 as an etching mask, the buffer layer 71, the element isolation region 12 and the semiconductor substrate 11 are etched (for example, continuously etched) to form an element isolation region. 12 (field) and the semiconductor substrate 11 are formed with a trench 14 in which a word line (including a gate electrode) in the DRAM region is formed. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is left between the well diffusion layer 13 formed earlier and the bottom of the groove 14. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0171]
Further, since the groove 14 is formed only in the DRAM region, it is desirable that the edge portion at the bottom of the groove 14 be formed in a so-called round shape in order to avoid electric field concentration of the cell transistor. Is the channel length of the access transistor of the memory element, it is desirable that the side wall of the trench 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible. Note that the buffer layer 71 formed in the DRAM region is simultaneously etched when the element isolation region 12 is etched. Thereafter, the resist film 203 is removed by a normal removal technique.
[0172]
As for voltages assumed in this generation, the standard logic region is 0.5 V to 1.2 V, the high voltage logic region is 1.5 V to 2.5 V, and the DRAM cell word line boost is 1.5 V to 2 V. .5V.
[0173]
Next, as shown in FIG. 24 (4), a sacrificial oxide film (not shown) is formed to a thickness of, for example, 10 nm to 20 nm on the entire exposed surface of the semiconductor substrate 11 by, eg, thermal oxidation.
[0174]
Next, channel doping of the access transistor in the DRAM region is performed to form a channel diffusion layer 15 between the bottom of the trench 14 and the well diffusion layer 13.
[0175]
The channel diffusion layer 15 of the word transistor in the DRAM region has a high concentration (for example, 1.0 × 10¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^Three) Must be a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall or upper portion of the groove 14 needs to be almost ion-implanted as a substrate concentration. There is no. In the above ion implantation, the buffer layer 71 provided first is used as a mask for ion implantation on the surface of the semiconductor substrate 11 and the logic element region. Therefore, the channel diffusion layer is formed only at the bottom of the groove 14 without using a new mask. 15 can be formed. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 (see FIG. 30) described later has an extremely low concentration (for example, 1.0 × 10 10¹⁷/ Cm^Three~ 1.0 × 10¹⁸/ Cm^Three) Can be formed.
[0176]
Thereafter, the sacrificial oxide film (not shown) is removed by wet etching, for example. Thereafter, a gate insulating film 16 is formed on the inner surface of the groove 14 in the DRAM region, the semiconductor substrate 11 and the like by an ordinary gate oxide film forming method.
[0177]
As shown in (5) of FIG. 25, a gate formation film 72 is formed of a phosphorus-doped polysilicon film on the gate insulating film 16 so as to fill each groove 14 in the DRAM region. This gate formation film 72 is used only for the word line in the DRAM region and not for the P-channel transistor.⁺Phosphorous doped polysilicon, which is a gate material, can be used. The gate formation film 72 is formed to a thickness of 50 nm to 150 nm, and the film thickness is set to a thickness optimized only for forming a groove-like word line. Further, after a resist film 205 is formed on the gate formation film 72, the resist film 205 on the logic area is removed by using a lithography technique while leaving the resist film 205 on the DRAM area.
[0178]
Next, as shown in FIG. 26 (6), the gate formation film 72, the gate insulating film 16 and the buffer layer 71 on the logic element region are removed by etching using the resist film 205 as a mask. In this etching, in the etching of the gate formation film 72, the buffer layer 71 serves as an etching stopper, thereby exposing the surface of the semiconductor substrate 11 in the logic element region. Further, in this etching, hydrofluoric acid-based wet etching is desirable for removing the buffer layer 71. Thereafter, the resist film 205 is removed.
[0179]
Thereafter, as shown in (7) of FIG. 27, a sacrificial oxide film (not shown) is formed on the surface of the logic element region. Next, a resist film (not shown) having an opening over the N channel transistor formation region in the standard voltage logic region is formed, and then ion implantation is performed on the semiconductor substrate 11 using the resist film as a mask. P well diffusion layer 51 is formed. At that time, channel doping can be performed as necessary. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the P channel transistor formation region in the standard voltage logic region is formed, and then ion implantation is performed on the semiconductor substrate 11 using the resist film as a mask. An N well diffusion layer 61 of the channel transistor is formed. At that time, channel doping can be performed as necessary. Thereafter, the resist film is removed.
[0180]
Next, the sacrificial oxide film is removed. Then, the gate insulating film 17 of the logic element is formed on the gate forming film 72 left on the DRAM region and on the semiconductor substrate 11 (including the element isolation region 12) in the logic element region. In this generation, the gate insulating film is generally made according to the film thickness, and is made separately using a resist process. For the gate insulating film, silicon oxide or silicon nitride is used when heat resistance is required. In order to prevent boron (B) from penetrating from the P channel gate, for example, a silicon oxynitride film is used for the P channel gate. During these processes, the DRAM region is covered with the gate forming film 72 made of phosphorus-doped polysilicon, so that the surface is oxidized, but the channel region is only subjected to heat treatment and is not affected by oxidation or the like.
[0181]
As shown in FIG. 28 (8), a polysilicon layer 73 is formed of, for example, non-doped polysilicon on the semiconductor substrate 11, the element isolation region 12, and the gate formation film 72 through the gate insulating film 17. Then, phosphorus is ion-implanted into the gate electrode formation layer in the N channel region to form an N-type gate electrode formation layer. Since the polysilicon layer 73 is optimized for the gate electrode of the transistor in the logic region, for example, the film thickness is preferably 70 nm to 200 nm, preferably about 100 nm. The polysilicon layer 73 in the P channel region is not ion-implanted and is left in a non-doped state. This eliminates the penetration of boron (B) during subsequent LDD (Lightly Doped Drain) formation and sidewall formation.
[0182]
Thereafter, a dummy layer 74 is formed on the polysilicon layer 73. For example, the dummy layer 74 is formed by stacking a tungsten nitride film and a tungsten film. The dummy layer 74 is a film type selected for wet etching performed to expose the polysilicon layer 73 in the logic element region later, and the resistance itself is not related. Any material can be used as long as it can wet-etch the silicon oxide film of the insulating film and the polysilicon layer 73 with a high selectivity. Next, the buffer layer 75 is formed of, for example, a silicon oxide film on the dummy layer 74.
[0183]
Next, after a resist film is formed on the entire surface of the buffer layer 75, the resist film is processed by lithography to form a resist pattern 207 for forming a gate electrode in the logic element region.
[0184]
Next, as shown in FIG. 29 (9), the buffer layer 75, the dummy layer 74, and the polysilicon layer 73 are etched using the resist pattern 207 as a mask, and a dummy gate 76 is formed in each logic element region. Form. The buffer layer 75 is deposited to prevent salicide from being formed on tungsten on the metal-based electrode during later salicide formation, but is not particularly necessary when there is no contamination or processing problem. . Further, this is not necessary when a salicide structure is adopted for the peripheral gate electrode. Thereafter, the resist pattern 207 is removed.
[0185]
As shown in FIG. 30 (10), after forming a resist film 209 covering the dummy gate 76 on the semiconductor substrate 11, the resist film 209, which becomes a DRAM region, is removed using a lithography technique, and the logic region The resist film 209 is left on.
[0186]
Thereafter, using the resist film 209 as a mask, the polysilicon layer 73 is etched back so that the polysilicon layer 73 remains in the trench 14. As a result, a word line (partly functioning as a gate electrode) 18 made of the polysilicon layer 73 is formed in the trench 14. At that time, the polysilicon layer 73 is etched back so that the surface of the word line 18 is about 50 nm to 100 nm lower than the surface of the semiconductor substrate 11, thereby ensuring a withstand voltage distance from the extraction electrode of the diffusion layer to be formed later. The In this etch back, the gate insulating film 16 functions as an etching stop layer.
[0187]
Further, by using the resist film 209 as a mask, ion implantation for forming a source / drain is performed on the semiconductor substrate 11 in the DRAM region to form a diffusion layer 19. As an example of the ion implantation conditions, phosphorus is used as an impurity for ion implantation, and the concentration is 1 × 10.¹⁷/ Cm^Three~ 1x10¹⁸/ Cm^ThreeThe dose amount and the implantation energy are set so that Since the implantation energy penetrating the buffer layer 71 is sufficient, the implantation energy is set to, for example, 20 keV to 50 keV, and the dose amount is set to 1 × 10.¹⁸/ Cm²~ 3x10¹⁸/ Cm²Set to. If ion implantation is performed under these conditions, almost no ions are implanted into the semiconductor substrate 11 below the diffusion layer 19 in the DRAM region. Therefore, the semiconductor substrate 11 in this region is 1 × 10¹⁶/ Cm^Three~ × 10¹⁷/ Cm^ThreeIt becomes possible to set the density to a very low level.
[0188]
Therefore, this NP junction is a super-graded junction (a junction with a very gentle concentration gradient). The junction in such a state relaxes the electric field at the time of reverse bias, and dramatically contributes to suppression of junction leakage current that is worse by about two orders of magnitude than usual, which occurs in a defective bit of only ppm order in a megabit class DRAM. The data retention characteristics of the defective bits dominate the DRAM chip performance, and it is an important technique for maintaining the data retention characteristics in future DRAMs.
[0189]
For example, the substrate concentration is 5 × 10¹⁶/ Cm^ThreeIf this is the case, a data retention characteristic of 500 ms or more can be obtained at 85 ° C., which is expected to exhibit performance comparable to the data retention characteristic of the previous 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed by rounding the semiconductor substrate 11, the effective channel length can be ensured to be long, and the short channel effect can be used by applying a back bias. Therefore, it is possible to stabilize the transistor characteristics of the DRAM cell which is severe.
[0190]
Thereafter, the resist film 209 is removed. In the above ion implantation, ion implantation is performed slightly shallowly in consideration of diffusion due to heat treatment related to the gate formation of the DRAM region later. However, since the DRAM gate is a substrate buried type, the channel of the DRAM region has a buried gate. Since it is formed at the bottom of the groove 14 to be formed, there is no problem. Further, since it is activated by a subsequent heat treatment, it is not necessary to perform the heat treatment at this stage.
[0191]
As shown in (11) of FIG. 31, a resist film (not shown) having an opening over the N-channel transistor formation region in the standard voltage logic region is formed, and then the resist film and dummy gate 76 are used as a mask. Then, ion implantation is performed on the semiconductor substrate 11 (P-well diffusion layer 51) to form low-concentration diffusion layers 52 and 52 of N-channel transistors. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the P-channel transistor formation region in the standard voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and dummy gate (not shown) as a mask. 11 is ion-implanted to form a low-concentration diffusion layer (not shown) of the P-channel transistor. Thereafter, the resist film is removed.
[0192]
Further, similarly, a resist film (not shown) opened on the P channel transistor formation region in the high voltage logic region is formed, and then the semiconductor substrate 11 (using the resist film and the dummy gate 76 as a mask) is formed. Ions are implanted into the N well diffusion layer 61) to form lightly doped diffusion layers 62, 62 of the P channel transistor. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the p-channel transistor formation region in the high voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and gate electrode (not shown) as a mask. 11 is ion-implanted to form a low-concentration diffusion layer (not shown) of the N-channel transistor. Thereafter, the resist film is removed.
[0193]
Next, as shown in FIG. 32 (12), a protective film 78 for protecting the gate of the DRAM region is formed of, for example, a thin silicon nitride film (for example, a thickness of 10 nm to 50 nm). This protective film 78 is later formed in a sidewall shape on the side wall on the word line 18 in the DRAM region, and contributes to securing the breakdown voltage on the side wall of the word line 18 when the salicide is formed.
[0194]
Next, a sidewall formation film 79 is formed on the entire surface. The sidewall formation film 79 is preferably formed of silicon oxide having a lower stress than silicon nitride and good releasability by wet treatment. Alternatively, a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film can be used. The protective film 78 serves as an etching stopper when the sidewall forming film 79 of the peripheral circuit transistor is later removed in the DRAM, and is later formed in a sidewall shape on the side wall on the word line 18 in the DRAM region. At the time of formation, it contributes to securing the breakdown voltage of the side wall of the groove 14.
[0195]
Thereafter, as shown in FIG. 33 (13), a resist film 211 is formed on the entire surface, and the resist film 211 in the logic area is removed by, for example, lithography technique, and the DRAM film is left to protect the DRAM area. Keep it. In this state, the sidewall formation film 79 is etched back.
[0196]
As a result, the sidewall 54 is formed on the sidewall of the dummy gate 76 in the standard voltage logic region by the sidewall formation film 79, and the sidewall 64 is formed on the sidewall of the dummy gate 76 in the high voltage logic region by the sidewall formation film 79. The In the etching, the protective film 78 on the dummy gate 76 is removed by etching depending on the film thickness. Thereafter, the resist film 211 is removed.
[0197]
Next, as shown in (14) of FIG. 34, a resist film (not shown) having an opening over the n-channel transistor formation region in the standard voltage logic region is formed, and then the resist film, dummy gate 76, side Ions are implanted into the semiconductor substrate 11 using the wall 54 as a mask, and n-channel transistor diffusion layers 55 and 55 are formed so as to leave the low concentration diffusion layer 52 on the dummy gate 76 side. Thereafter, the resist film is removed. Similarly, a resist film (not shown) having an opening over the p-channel transistor formation region in the standard voltage logic region is formed, followed by the resist film, dummy gate (not shown), and sidewall (not shown). ) As a mask to form a p-channel transistor diffusion layer (not shown) so as to leave a low-concentration diffusion layer (not shown) on the dummy gate side. Thereafter, the resist film is removed.
[0198]
Further, similarly, a resist film (not shown) having an opening over the n-channel transistor formation region in the high voltage logic region is formed, and then the resist film and the dummy gate 76 are used as a mask on the semiconductor substrate 11. Ion implantation is performed to form n-channel transistor diffusion layers 65 and 65 so as to leave the low concentration diffusion layer 62 on the dummy gate 76 side. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the p-channel transistor formation region in the high voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and a dummy gate (not shown) as a mask. 11 is ion-implanted to form a p-channel transistor diffusion layer (not shown) so as to leave a low concentration diffusion layer (not shown) on the dummy gate side (not shown). Thereafter, the resist film is removed.
[0199]
Next, after a resist film 213 is formed on the entire surface, the resist film 213 in the DRAM region is removed by lithography, and patterning is performed so as to cover the logic region with the resist film 213. Next, using the resist film 213 as a mask, the sidewall formation film 79 made of silicon oxide in the DRAM region is etched back, for example, by wet processing. In this etching, the protective film 78 made of silicon nitride formed immediately above the word line 18 of the previously formed DRAM serves as an etching stopper.
[0200]
Further, using the resist film 213 as it is, the protective film 78 in the DRAM region is etched by, for example, reactive ion etching (RIE) to expose the word line 18 in the DRAM region. As a result. A side wall 20 made of a protective film 78 is formed on the side wall of the groove 14 on the word line 18. This sidewall 20 has a function of protecting the sidewall. In the reactive ion etching, it is important to prevent the diffusion layer 19 in the DRAM region from being exposed, that is, to leave the buffer layer 71 on the diffusion layer 19. Thereafter, the resist film 213 is removed.
[0201]
Further, as shown in (15) of FIG. 35, silicide layers 57, 67, 21 are formed on the diffusion layers 55, 65 in the logic region and the word lines 18 in the DRAM region by using a normal silicidation technique. Are selectively formed. At this time, since the buffer layer 75 made of a silicon oxide film is formed on the top of the dummy gate 76, no silicide layer is formed. In this manner, silicide layers 57, 67, and 21 are selectively formed on the diffusion layers 55 and 65 in the logic region where low resistance needs to be realized and on the word line 18 in the DRAM region. As this silicide layer, for example, cobalt silicide (CoSi)₂), Titanium silicide (TiSi)₂Nickel silicide (NiSi)₂) Etc. can be used.
[0202]
Thereafter, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective in suppressing junction leakage in the salicide forming portion, but it is not necessary to form the cap insulating film 80 if unnecessary. Note that as described above, a silicide layer may be formed also on the gate electrode of the transistor in the peripheral circuit portion to form a salicide structure, so that the resistance of the gate electrode can be reduced.
[0203]
Next, as shown in (16) of FIG. 36, after a first insulating film (insulating film) 22 is formed on the entire surface, the surface of the first insulating film 22 is planarized by CMP. The method for planarizing the surface of the first insulating film 22 is not limited to CMP as long as the planarization can be realized, and for example, an etch back method or the like can be used. Thereafter, a resist film 215 is formed on the first insulating film 22, and then a connection hole pattern 216 for a diffusion layer extraction contact in the DRAM region is formed in the resist film 215 by a lithography technique.
[0204]
Next, etching is performed using the resist film 215 as an etching mask, and reaches the diffusion layer 19 in the DRAM region through the first insulating film 22 and the buffer layer 71 as shown in FIG. A connection hole 23 is formed. At this time, since the word line (gate electrode) 18 in the DRAM region is disposed below the surface of the semiconductor substrate 11 rather than the diffusion layer 19 to be contacted, it is not necessary to use a special technique such as self-alignment contact. Further, it is desirable to make the opening diameter of the connection hole 23 as large as possible so that the entire surface of the diffusion layer 19 of the DRAM can contact the extraction electrode. Thereby, the contact resistance is reduced.
[0205]
In the drawing, the state in which the alignment is slightly shifted is intentionally described. However, if excessive over-etching is not performed when the connection hole is opened, the physical structure of the word line extraction electrode formed in the connection hole 23 in a later step is described. It is possible to ensure a sufficient distance. In the projection design seen from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.
[0206]
Next, an extraction electrode forming film 81 is formed on the first insulating film 22 so as to fill the connection hole 23. This extraction electrode forming film 81 is formed of, for example, phosphorus-doped polysilicon. As the extraction electrode forming film 81 for extracting the diffusion layer, phosphorus-doped polysilicon is preferably selected in the DRAM region in consideration of reduction of junction leakage as in the conventional case. Note that heat treatment for activation is not necessary at this stage.
[0207]
Thereafter, as shown in FIG. 38 (18), the excessive extraction electrode formation film 81 (phosphorus-doped polysilicon) on the first insulating film 22 is removed by CMP, for example, and the diffusion layer is formed in the connection hole 23. The extraction electrode 24 composed of the extraction electrode forming film 81 connected to the N-type electrode 19 is formed, and the first insulating film 22 is polished to flatten the surface. At this time, the buffer layer 75 (see (9) of FIG. 29) of the dummy gate 76 in each logic region is removed to expose the upper portion of the dummy layer 74 of the dummy gate 76.
[0208]
Next, the dummy layer 74 (see (18) in FIG. 38) of the dummy gate 76 in the logic region is removed. As a result, a groove 83 is formed on the polysilicon layer 73 of each dummy gate 76 as shown in FIG. This etching is preferably performed, for example, by wet etching using sulfuric acid / hydrogen peroxide or hydrofluoric acid.
[0209]
Next, after forming a resist film 217 on the entire surface on the first insulating film 22 side, an opening 218 is formed on the p-channel transistor formation region in the logic element region by lithography. Subsequently, for example, boron is ion-implanted as a p-type impurity into the polysilicon layer 73 made of non-doped polysilicon using the resist film 217 as a mask.
[0210]
Thereafter, the resist film 217 is removed. Next, heat treatment is performed. By this heat treatment, activation of the extraction electrode 24 made of polysilicon in the DRAM region and the polysilicon layer 73 doped with impurities in the gate electrode in the logic element region is performed. In this heat treatment, RTA (Rapid Thermal Annealing) at 900 ° C. for about 10 seconds is sufficient. However, thermal annealing using a normal furnace can be performed. In the subsequent processes, since a high-temperature heat process is not performed, so-called “penetration” in which boron diffuses from the gate electrode in the logic element region is minimized.
[0211]
Then, as shown in FIG. 40 (20), a metal-based gate electrode formation film 84 is formed so as to fill the trench 83. The metal gate electrode formation film 84 is generally formed of a laminated film of a metal film (for example, tungsten film) 84W / adhesion film (for example, titanium nitride film 84T). Alternatively, an electrode of tungsten / tungsten nitride, copper / titanium nitride, ruthenium, or the like can be formed.
[0212]
The excess metal gate electrode formation film 84 on the first insulating film 22 is removed by CMP again.
[0213]
As a result, as shown in (21) of FIG. 41, a metal gate electrode 84G made of the metal gate electrode formation film 84 left in the trench 83 is formed, and the metal gate electrode 84G and the polysilicon layer 73 are formed. The gate electrodes 51 and 61 are formed, and the surface of the first insulating film 22 is planarized. At this time, the upper portion of the extraction electrode 24 for extracting the diffusion layer in the DRAM region is also polished, but there is no problem.
[0214]
Next, an etching stop layer 25 that covers the extraction electrode 24 in the DRAM region and the gate electrodes 51 and 61 in the logic element region is formed on the entire surface of the first insulating film 22 with, for example, a silicon oxide film.
[0215]
Thereafter, as shown in (22) of FIG. 42, after forming a resist film (not shown) on the etching stop layer 25, the word line contact contact and logic region of the DRAM region is formed on the resist film by lithography. A connection hole pattern (not shown) for the diffusion layer extraction electrode is formed. Subsequently, using the resist film as an etching mask, the silicide layer 21 on the word line 18 in the DRAM region and the logic region are penetrated through the etching stop layer 25, the first insulating film 22 and the cap insulating film 80. Connection holes 26, 58 and 68 reaching the silicide layers 57 and 67 of the transistor are formed.
[0216]
Thereafter, the resist film is removed. Next, an adhesion layer 85 made of a titanium nitride film is formed on the inner surface of the connection holes 26, 58, 68 by a normal tungsten plug forming technique, and then the tungsten film 86 is embedded so as to fill the connection holes 26, 58, 68. Form. Thereafter, excess portions of the tungsten film 86 and the adhesion layer 85 on the etching stop layer 25 are removed by CMP, and take-out electrodes 27, 59, and 69 are formed in the connection holes 26, 58, and 68.
[0217]
Next, a second insulating film 31 is formed by depositing, for example, a silicon oxide film with a thickness of 50 nm to 150 nm on the entire surface of the etching stop layer 25 so as to cover the extraction electrodes 27, 59 and 69.
[0218]
Then, after forming a resist film (not shown) on the second insulating film 31, an opening (not shown) is formed at a position where a bit contact is formed in the resist film by lithography. By using the resist film as a mask, a bit contact hole 32 and a local wiring contact hole 33 are formed in the second insulating film 31 and the etching stopper layer 25 as shown in FIG.
[0219]
Next, a wiring metal layer for forming the bit line 34 and the local wiring 35 is formed. As the wiring metal layer, first, an adhesion layer 36 formed by laminating, for example, a titanium film and a titanium nitride film is formed on the inner surfaces of the bit contact hole 32 and the local wiring contact hole 33 and the second insulating film 31. Further, a tungsten film 37 serving as a main material of the metal wiring is formed on the adhesion layer 36 so as to bury the bit contact hole 32 and the local wiring contact hole 33. Further, a cap layer 38 is formed on the tungsten film 37 by, for example, a silicon nitride film.
[0220]
Thereafter, the cap layer 38, the tungsten film 37, and the adhesion layer 36 are patterned by a normal lithography technique and an etching technique, and the bit line 34 connected to the bit contact extraction electrode 24 through the bit contact hole 32 and the local wiring contact are formed. A local wiring 35 connected to the extraction electrode 59 through the hole 33 is formed. Therefore, the cap layer 38 is formed on the bit line 34 and the local wiring 35.
[0221]
Thereafter, an etching stopper layer 41 covering the bit line 34, the local wiring 35, etc. is formed on the second insulating film 31 with an ALD silicon nitride film to a thickness of, for example, 30 nm to 50 nm.
[0222]
Next, as shown in FIG. 44 (24), a third insulating film 42 is formed on the etching stopper layer 41. Then, the surface of the third insulating film 42 is planarized using, for example, CMP. Next, after forming a resist film 219 on the third insulating film 42, an opening pattern 220 for opening a storage node contact is formed by lithography. The opening pattern 220 can be formed larger than the diameter of the connection hole in which the actual storage node contact is formed.
[0223]
Next, using the resist film 219 as an etching mask, as shown in FIG. 45 (25), the storage node is etched from the third insulating film 42 to the etching stop layer 25, and the contact extraction electrode 24, A connection hole 43 for forming a storage node contact reaching 24 is formed. In this etching, in addition to the resist film 219 (see (24) in FIG. 44), the cap layer 38 and the etching stopper layer 41 serve as an etching mask. The etching stopper layer 41 is partially etched, but remains on the side wall of the bit line 34 as a side wall having a film thickness that can ensure the breakdown voltage between the bit line and the storage node contact. Thereafter, the resist film 219 (see (24) in FIG. 44) is removed.
[0224]
Next, as shown in FIG. 46 (26), the storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is formed, for example, by depositing tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide or the like on the third insulating film 42 so as to fill the connection hole 43 and forming a material layer. The excess material layer on the third insulating film 42 is formed by the material layer left in the connection hole 43 by removing the material layer by CMP, for example.
[0225]
Next, a fourth insulating film 45 covering the storage node contact 44 and the like is formed on the third insulating film 42. Next, a recess 46 in which a capacitor is formed in the fourth insulating film 45 is formed so that the upper surface of the storage node contact 44 is exposed at the bottom.
[0226]
Thereafter, a capacitor 91 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed in the recess 46. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the electrodes 92 and 94 are made of a ruthenium (Ru) or ruthenium oxide (RuO) material, The film 93 has BST (BaTiO_ThreeAnd SrTiO_ThreeA mixed crystal) film is used.
[0227]
Next, a fifth insulating film 47 that covers the MIM structure capacitor 91 is formed on the fourth insulating film 45. Thereafter, the surface of the fifth insulating film 47 is planarized by CMP. Next, in order to form a capacitor extraction electrode, a word line extraction electrode, a local wiring extraction electrode, a diffusion layer extraction electrode in the logic region, a gate extraction electrode in the logic region, etc. on the fifth insulating film 47 or the second insulating film 31. The connection holes 111, 112, 113, 114 to 116, 117, etc. are formed.
[0228]
Further, in the connection holes 111, 112, 113, 114 to 116, 117, etc., the capacitor extraction electrode 121, the word line extraction electrode 122, the local wiring extraction electrode 123, the diffusion layer extraction electrodes 124 to 126 in the logic region, and the gate in the logic region. An extraction electrode 127 is formed. Further, a sixth insulating film 48 is formed on the fifth insulating film 47. Next, wiring grooves 131 to 136 reaching the electrodes 121 to 127 are formed in the sixth insulating film 48, and wirings 141 to 146 are formed in the wiring grooves 131 to 136. The wirings 141 to 146 are made of, for example, copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121 to 127 and the wirings 141 to 146 are formed with a generally known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0229]
In the second method for manufacturing a semiconductor device, since the buffer layer 71 is formed, the buffer layer 71 is subsequently introduced when an impurity for forming the channel diffusion layer 15 is introduced into the semiconductor substrate 11 at the bottom of the groove 14. As a mask, impurities are selectively introduced into the semiconductor substrate 11 at the bottom of the trench 14 to form a channel diffusion layer 15.
[0230]
As described above, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the trench 14 and the well diffusion layer 13, the impurity concentration in the region between the trench 144 and the well diffusion layer 13 is around the trench 14. It becomes higher than the impurity concentration of the semiconductor substrate 11. Further, since the concentration of the semiconductor substrate 11 under the diffusion layer 19 serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer 19 serving as the source / drain is weakened. For this reason, it becomes possible to suppress junction leakage on the order of ppm, thereby forming a semiconductor device with extremely good data retention characteristics.
[0231]
In addition, the semiconductor device overlaps the word line 18 via the first insulating film 22 on the word line 8 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the first insulating film 22 on the word line 18 can have a sufficient film thickness of 20 nm to 30 nm or more. . Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0232]
Further, since the silicide layer 21 is formed on the upper layer of the word line 18, the resistance of the word line 18 is reduced and the problem of delay is avoided. Further, since the silicide layers 57 and 67 are formed on the diffusion layers 55 and 65 of the logic element, the contact resistance to the diffusion layers 55 and 65 is reduced.
[0233]
Further, since the diffusion layer 19 is formed on the surface side of the semiconductor substrate 11 and the word line 18 is embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16, the channel is the word line 18. It is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0234]
Further, since the diffusion layer 19 in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 does not have to be as high as required for the cell transistor. Therefore, the electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the cell size of the memory element is reduced is maintained.
[0235]
Further, by using a laminated structure of the polysilicon layer 73 and the dummy layer 74 for the dummy gate 76 formed in the logic element region, the dummy layer 74 is removed after the extraction electrode of the diffusion layer in the memory element region is formed, and the dummy gate 76 is formed. It becomes possible to dope impurities into the polysilicon layer 73 of the gate 76. Thereafter, heat treatment is performed to form the metal gate electrode 84G with the metal gate electrode formation film 84, so that the problem of boron penetration in the p-channel gate electrode due to the heat treatment can be minimized.
[0236]
The technique used for the DRAM region can also be applied to the manufacture of a general-purpose DRAM memory chip.
[0237]
【The invention's effect】
As described above, according to the first and second semiconductor devices and the method for manufacturing the same of the present invention, the silicide layer is formed on the word line, so that the word line resistance can be reduced and the microfabrication can be achieved. The problem of word line delay can be avoided.
[0238]
In addition, since the diffusion layer is formed on the semiconductor substrate surface side and the word line is embedded in the groove formed in the semiconductor substrate via the gate insulating film, the channel is on the groove bottom side where the word line is formed It is formed so as to go around the semiconductor substrate. Therefore, since the effective channel length of the cell transistor in the memory element region is sufficiently secured, the transistor characteristics of the memory element (for example, DRAM) having a severe short channel effect are stabilized by applying the back bias.
[0239]
A take-out electrode connected to a diffusion layer formed on the surface of the semiconductor substrate is formed on the word line embedded in the groove formed in the semiconductor substrate in a state of overlapping with the word line via a sidewall, an insulating film, etc. Therefore, the withstand voltage between the diffusion layer and the extraction electrode can be ensured by an insulating film or the like on the word line. For this reason, the entire surface of the diffusion layer of the memory element region located higher than the word line can be used for the contact, so that the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design can be realized, and the contact resistance can be reduced.
[0240]
Therefore, in the upper projection design, the extraction electrode of the diffusion layer in the memory element region and the word line (gate electrode) can overlap, and the cell can be miniaturized. That is, there is no need for a distance for securing a withstand voltage between the word line and the extraction electrode in the substrate surface direction. Therefore, since the entire surface of the diffusion layer of the memory element can be used for the contact, the effective area can be used effectively, the lowest resistance value that can be realized by the cell design is realized, and the contact resistance can be reduced.
[0241]
In addition, since the diffusion layer in the memory element region is formed so that its concentration decreases in the depth direction, it is not necessary to make the substrate concentration below this diffusion layer as high as required for the cell transistor. As a result, the electric field at the junction of the diffusion layer can be relaxed, and the performance of data retention characteristics that become increasingly severe due to the cell reduction in the memory element region can be maintained.
[0242]
Further, according to the second semiconductor device and the manufacturing method thereof, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer can be reduced.
[0243]
In addition, a logic transistor having a so-called replacement gate electrode for realizing a high driving force transistor in the logic region and a memory element can be realized in one chip. As a result, the gate in the logic region does not require care for heat treatment, it is possible to use a high dielectric constant material for the gate insulating film, and the gate electrode can be formed with a polymetal structure.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing an example of an embodiment of a semiconductor device according to the present invention.
FIG. 2 is a schematic cross-sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional view (2) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic cross-sectional view (3) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a schematic cross-sectional view (4) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 6 is a schematic cross-sectional view (5) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 7 is a schematic cross-sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 8 is a schematic cross-sectional view (7) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 9 is a schematic cross-sectional view (8) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 10 is a schematic cross-sectional view (9) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 11 is a schematic cross-sectional view (10) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 12 is a schematic cross-sectional view (11) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 13 is a schematic cross-sectional view (12) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 14 is a schematic cross-sectional view (13) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 15 is a schematic cross-sectional view (14) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 16 is a schematic cross-sectional view (15) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 17 is a schematic cross-sectional view (16) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 18 is a schematic cross-sectional view (17) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 19 is a schematic cross-sectional view (18) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 20 is a schematic cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention.
FIG. 21 is a schematic cross-sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
22 is a schematic cross-sectional view (2) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
FIG. 23 is a schematic cross-sectional view (3) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 24 is a schematic cross-sectional view (4) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 25 is a schematic cross-sectional view (5) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 26 is a schematic cross-sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 27 is a schematic cross-sectional view (7) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 28 is a schematic cross-sectional view (8) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 29 is a schematic cross-sectional view (9) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
30 is a schematic cross-sectional view (10) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
FIG. 31 is a schematic cross-sectional view (11) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 32 is a schematic cross-sectional view (12) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 33 is a schematic cross-sectional view (13) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
34 is a schematic cross-sectional view (14) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
FIG. 35 is a schematic cross-sectional view (15) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 36 is a schematic cross-sectional view (16) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 37 is a schematic cross-sectional view (17) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 38 is a schematic cross-sectional view (18) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 39 is a schematic cross-sectional view (19) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
40 is a schematic cross-sectional view (20) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
41 is a schematic cross-sectional view (21) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
42 is a schematic cross-sectional view (22) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
43 is a schematic cross-sectional view (23) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
44 is a schematic cross-sectional view (24) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
45 is a schematic cross-sectional view (25) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
FIG. 46 is a schematic cross-sectional view (26) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Element isolation region, 13 ... Well diffusion layer, 14 ... Groove, 15 ... Channel diffusion layer, 16 ... Gate insulating film, 18 ... Word line, 19 ... Diffusion layer, 21 ... Silicide layer, 22 ... 1st insulating film, 24 ... extraction electrode

Claims (2)

In a method for manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate,
Forming an isolation region on the semiconductor substrate and then forming a buffer layer on the semiconductor substrate;
Forming a well diffusion layer in the semiconductor substrate of the memory element region isolated by the element isolation region;
Forming a groove at a position where word lines of the buffer layer and the semiconductor substrate and the element isolation region are formed in a state where a part of the semiconductor substrate is left on the well diffusion layer;
Forming a channel diffusion layer in the semiconductor substrate between the bottom of the trench and the well diffusion layer;
Forming a gate insulating film in the trench and on the semiconductor substrate;
Forming a conductive layer filling the groove on the semiconductor substrate in the memory element region;
Forming a well diffusion layer in the semiconductor substrate in the logic element region separated by the element isolation region;
Sequentially forming a dummy layer made of a material having etching selectivity between the polysilicon layer and the polysilicon layer on the semiconductor substrate;
Processing the polysilicon layer and the dummy layer to form a dummy gate with the polysilicon layer and the dummy layer on the semiconductor substrate in the logic element region via the gate insulating film;
Forming a word line with the conductive layer left in the trench by removing the conductive layer on the semiconductor substrate and the upper portion of the trench while leaving the conductive layer inside the trench;
Forming a diffusion layer on the semiconductor substrate above the trench sidewall;
Forming a low concentration diffusion layer of a logic element on a semiconductor substrate surface on both sides of the dummy gate;
Forming a sidewall insulating film on the side wall of the dummy gate;
Forming a diffusion layer on the semiconductor gate on both sides of the dummy gate on the dummy gate side through the low-concentration diffusion layer;
Forming a sidewall insulating film on the trench sidewall on the word line;
Forming a silicide layer on the word line upper layer and the logic element diffusion layer;
Forming an insulating film so as to fill the upper portion of the groove and cover the dummy gate;
Forming a connection hole reaching the diffusion layer formed in the memory element region in a state overlapping with the word line via the insulating film on the word line;
Forming an extraction electrode in the connection hole;
Planarizing the insulating film surface and exposing the upper portion of the dummy gate, further removing the dummy layer to expose the polysilicon layer and forming a gate groove;
Doping the polysilicon layer of the dummy gate with impurities;
Performing a heat treatment for activating the extraction electrode and the polysilicon layer;
And a step of forming a metal-based electrode in the gate groove. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion layer is formed so that an impurity concentration is reduced in a depth direction.

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