JP2004095745A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the resistance of a word line(gate electrode), to suppress joint leak, to ensure the breakdown voltage of a gate insulating film, to suppress short channel effects by extending effective channel length, and to stabilize the transistor characteristics. <P>SOLUTION: This semiconductor device is constituted of a semiconductor substrate 11, a groove 14 formed in the semiconductor substrate 11, a channel diffused layer 15 formed in the semiconductor substrate 11 at the bottom of the groove 14, a word line(gate electrode) 18 buried through a gate insulating film 16 in the groove 14, a groove 183 formed at the groove 14 side wall at the upper part of the word line 18, a side wall insulating film 20 formed at the wide wall of the groove 14 on the word line 18 buried in the groove 183, a diffused layer 19 formed at the surface side of the semiconductor substrate 11 at the groove 14 side wall, and a silicide layer 21 formed in the upper layer of the word line 18 positioned higher than the bottom of the side wall insulating film 20. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a dynamic random access memory (DRAM) and a method of manufacturing the same, and a semiconductor device in which a DRAM and a logic element are mounted and a method of manufacturing the same.
[0002]
[Prior art]
Due to the miniaturization competition accelerated year by year, especially, a composite device in which a large capacity DRAM and a high speed logic element are mounted on one chip is being developed. As an example of the configuration, a memory cell gate of a DRAM is stacked on a substrate, and a so-called self-aligned contact is used to take out a diffusion layer of a memory cell transistor, while a logic element is formed without using a self-aligned contact. The configuration is as follows.
[0003]
[Problems to be solved by the invention]
However, various problems have also become apparent in stacked DRAMs.
[0004]
In order to maintain transistor performance, the substrate density has become higher with the shrinking of DRAM memory cells, and accordingly, the junction leak in the DRAM region has become severer. For this reason, it is becoming difficult to suppress the junction leak in a megabit class DRAM. That is, it has become difficult to maintain the data retention characteristics of the DRAM, which was conventionally controllable with a margin.
[0005]
Further, as the size of the DRAM cell is reduced, the contact area between the diffusion layer and the extraction electrode is reduced, and the contact resistance is increased twice as much in each generation. For example, in the generation of 0.1 μm or later, the contact resistance is expected to be several kΩ, which is expected to be comparable to the on-resistance of the word transistor of the memory cell. Therefore, not only the cell transistor but also the variation in the contact resistance severely affects the operation of the DRAM, and more precision is required in manufacturing.
[0006]
Further, with the reduction in size of DRAM cells, the interlayer insulation distance between a word line and a contact for taking out a diffusion layer formed beside the word line is approaching with each generation. In manufacturing a megabit DRAM, the critical distance is said to be 20 nm to 30 nm in order to ensure this withstand voltage. Therefore, in a DRAM of a generation of 0.1 μm or less, it is necessary to form a contact for taking out the diffusion layer at a distance equal to or less than the withstand voltage limit distance.
[0007]
Conventionally, tungsten silicide (WSi ₂ The word line of a DRAM, which has been suppressed in delay by adopting a polycide structure of doped polysilicon, has become difficult to keep the aspect ratio low with the recent miniaturization, and also to suppress the delay of the word line. It has become difficult to obtain a sufficiently low resistance. In particular, in a stacked DRAM or the like that requires a high-speed operation, the word line delay becomes a serious problem affecting the access time of the DRAM. As a technique for lowering the resistance of the gate, reduction in the resistance of the wiring by salicide has been put to practical use. However, in order to apply the method to the gate of the DRAM memory cell, salicide is not formed in the diffusion layer of the DRAM in order to obstruct the reduction of the DRAM memory cell due to the inability to use the offset silicon oxide film and maintain the data retention characteristics. It cannot be usually adopted due to difficulties such as requiring a process.
[0008]
Also, a DRAM storage node contact must have an opening with no margin due to its cell size, and like the diffusion layer contact, an opening at the breakdown voltage limit is required. Is needed.
[0009]
On the other hand, the transistor performance of the logic section has been remarkably improved. ⁺ Gate electrodes are becoming commonly used. However, this p ⁺ In the gate, boron as an impurity is diffused toward the substrate by heat treatment. It includes the problem of so-called "penetration", and is known to cause serious problems such as variation in characteristics of the p-channel transistor and depletion of the gate electrode. Therefore, it is desirable to minimize the heat treatment temperature in the DRAM forming process.
[0010]
As described above, in the future 0.1 μm generation and beyond, some measures are needed to deal with problems such as variations in the characteristics of the p-channel transistor and depletion of the gate electrode. In order to maintain the chip performance trend, a stacked type It is expected that a drastic improvement in the DRAM structure will be required. The present invention is a further improvement of a trench access transistor (TAT) DRAM cell in which a word line of a DRAM part developed as a countermeasure for this is buried in a “groove” formed in a substrate. That is, the physical distance between the silicide formed on the gate electrode and the gate insulating film is ensured, and deterioration of the gate withstand voltage is suppressed.
[0011]
In the above-mentioned TAT / DRAM cell, in order to secure a physical distance between the silicide layer formed on the gate electrode and the gate insulating film, the silicon nitride film formed on the side wall of the groove for forming the gate electrode in the DRAM portion needs to be formed. Therefore, it is necessary to form the sidewall insulating film thickly. However, when the thickness of the sidewall insulating film is increased, the side effect of increasing the wiring resistance of the gate electrode in the DRAM portion occurs. For this reason, there is a demand for a method capable of ensuring a good physical distance between the silicide layer on the gate electrode and the gate insulating film without any adverse effect on device characteristics.
[0012]
[Means for Solving the Problems]
The present invention is directed to a semiconductor device and a method of manufacturing the same that have been made to solve the above problems.
[0013]
A first semiconductor device of the present invention includes a semiconductor substrate, a groove formed in the semiconductor substrate, a channel diffusion layer formed in the semiconductor substrate at a bottom of the groove, and a gate insulating film in the groove. A buried gate electrode; a groove formed on the side of the groove above the gate electrode; a sidewall insulating film buried in the groove and formed on a side wall of the groove on the gate electrode; A diffusion layer formed on the surface of the semiconductor substrate; and a silicide layer formed on the gate electrode at a position higher than a bottom of the sidewall insulating film.
[0014]
The first conductive layer is formed of a conductive film having a higher etching rate than the second conductive layer. In addition, a well diffusion layer is formed in the semiconductor substrate separated by the element isolation region, and the trench is formed in the semiconductor substrate and the element isolation region while leaving a part of the semiconductor substrate on the well diffusion layer. The channel diffusion layer is formed on the semiconductor substrate between the bottom of the groove and the well diffusion layer.
[0015]
In the above-described semiconductor device, since the groove is formed on the groove side wall above the word line, and the sidewall insulating film is formed on the groove side wall on the word line so as to fill the groove, the silicide layer is formed on the word line. However, since the sidewall insulating film between the silicide layer and the gate insulating film is offset and the distance between the silicide layer and the gate insulating film is sufficiently ensured, the deterioration of the gate insulating withstand voltage is suppressed.
[0016]
In the first semiconductor device, in the configuration in which the channel diffusion layer is formed in the semiconductor substrate between the lower portion of the groove where the channel is formed and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer is increased. Becomes higher than the impurity concentration of the semiconductor substrate around the trench. Also, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain is extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened, so that it is possible to suppress the junction leakage on the order of ppm. Therefore, the data retention characteristics are extremely improved.
[0017]
In the first semiconductor device, since the silicide layer is formed on the gate electrode, the resistance of the gate electrode is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to the gate electrode is reduced.
[0018]
In addition, since the diffusion layer is formed on the surface of the semiconductor substrate and the word line is embedded in the groove formed on the semiconductor substrate via the gate insulating film, the channel is formed at the bottom of the groove where the gate electrode is formed. Formed around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0019]
According to a first method of manufacturing a semiconductor device of the present invention, a step of forming a groove at a position where a gate electrode is formed in a semiconductor substrate on which an element isolation region is formed, and a step of forming a groove in the semiconductor substrate at a bottom of the groove Forming a channel diffusion layer; forming a gate insulating film in the trench and on the semiconductor substrate; forming a first conductive layer on the semiconductor substrate including the inner wall of the trench; Forming a second conductive layer filling the groove on the substrate via the first conductive layer; and forming the second conductive layer inside the groove so that the first conductive layer is lower than the second conductive layer. Removing the first conductive layer and the second conductive layer on the upper portion and on the semiconductor substrate to form a gate electrode with the first conductive layer and the second conductive layer remaining inside the trench; Groove side wall and the second Forming a trench between the conductive layer and a conductive layer; forming a diffusion layer in the semiconductor substrate above the trench sidewall; burying the interior of the trench, and forming a sidewall insulating film on the trench sidewall on the gate electrode; And a step of forming a silicide layer on the gate electrode.
[0020]
Further, a conductive film having an etching rate higher than that of the second conductive layer is used for the first conductive layer. A well diffusion layer is formed in the semiconductor substrate separated by the element isolation region, and the trench is formed in the semiconductor substrate and the element isolation region in a state where a part of the semiconductor substrate is left on the well diffusion layer. Forming the channel diffusion layer on the semiconductor substrate between the bottom of the trench and the well diffusion layer.
[0021]
In the first method of manufacturing a semiconductor device, a trench is formed on the trench sidewall on the upper portion of the gate electrode, and a sidewall insulating film is formed on the trench sidewall on the gate electrode so as to fill the trench. Even if a silicide layer is formed, the sidewall insulating film is offset and the distance between the silicide layer and the gate insulating film is sufficiently ensured, so that a semiconductor device in which deterioration of the gate withstand voltage is suppressed can be obtained. In the first method for manufacturing a semiconductor device, the method for forming a channel diffusion layer in a semiconductor substrate between a lower portion of a groove in which a channel is formed and a well diffusion layer may include forming a region between the groove and the well diffusion layer. The impurity concentration becomes higher than the impurity concentration of the semiconductor substrate around the trench. Further, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened. For this reason, it is possible to suppress the junction leak on the order of ppm, thereby forming a semiconductor device having extremely good data retention characteristics.
[0022]
Furthermore, since the silicide layer is formed on the gate electrode, the resistance of the gate electrode is reduced, and the problem of delay is avoided. At the same time, the contact resistance to the gate electrode is reduced.
[0023]
Further, since a diffusion layer is formed on the surface of the semiconductor substrate and the gate electrode is buried through a gate insulating film in the groove formed in the semiconductor substrate, the channel is formed at the bottom of the groove where the gate electrode is formed. Formed around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0024]
According to a second semiconductor device of the present invention, in a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, a transistor of the memory element includes an element isolation region formed on the semiconductor substrate, And a well diffusion layer formed in the semiconductor substrate separated by the above, and formed in the semiconductor substrate and the element isolation region while leaving a part of the semiconductor substrate on the well diffusion layer. A trench, a channel diffusion layer formed in the semiconductor substrate between the bottom of the trench and the well diffusion layer, a word line embedded in the trench via a gate insulating film, and a top of the word line. A groove formed on the side wall of the groove, a sidewall insulating film formed on the side wall of the groove on the word line including the inside of the groove, and a surface of the semiconductor substrate on the side wall of the groove. The formed diffusion layer, the silicide layer formed on the word line upper layer at a position higher than the bottom of the sidewall insulating film, and the silicide layer formed on the word line with an insulating film interposed therebetween. A transistor of the logic element is formed on the semiconductor substrate, and has a polymetal structure gate electrode in which a polysilicon electrode and a metal-based electrode are laminated. And a diffusion layer formed on the surface of the semiconductor substrate on both sides of the gate electrode, and a silicide layer formed on the diffusion layer.
[0025]
In the second semiconductor device, since the groove is formed on the side of the groove above the word line, and the sidewall insulating film is formed on the side wall of the groove on the word line so as to fill the groove, the silicide layer is formed on the word line. Is formed, the sidewall insulating film between the silicide layer and the gate insulating film is offset, and the distance between the silicide layer and the gate insulating film is sufficiently ensured. You.
[0026]
In the second semiconductor device, since the channel diffusion layer is formed in the semiconductor substrate between the lower portion of the groove where the channel is formed and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer is increased. Becomes higher than the impurity concentration of the semiconductor substrate around the trench. Also, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain is extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened, so that it is possible to suppress the junction leakage on the order of ppm. Therefore, the data retention characteristics are extremely improved.
[0027]
Since the silicide layer is formed above the word line, the resistance of the word line is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line is reduced. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to this diffusion layer is reduced.
[0028]
In addition, since the diffusion layer is formed on the surface of the semiconductor substrate and the word line is buried in the groove formed on the semiconductor substrate via the gate insulating film, the channel is formed at the bottom of the groove where the word line is formed. Formed around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0029]
Further, since the impurity concentration of the diffusion layer is reduced in the depth direction, the concentration of the semiconductor substrate under the diffusion layer in the memory element region does not have to be as high as required for the cell transistor. The electric field is alleviated, and the performance of the data retention characteristic, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0030]
In addition, a word line embedded in a groove formed in the semiconductor substrate via a gate insulating film is connected to a diffusion layer formed on the surface of the semiconductor substrate in a state of overlapping with the word line via an insulating film. Since the extraction electrode is formed, the insulating film on the word line can have a sufficient thickness of 20 nm to 30 nm or more. Thereby, the withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface of the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0031]
According to a second method for manufacturing a semiconductor device of the present invention, in the method for manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, after forming an element isolation region on the semiconductor substrate, Forming a buffer layer, forming a well diffusion layer in the semiconductor substrate in the memory element region separated by the element isolation region, and leaving a part of the semiconductor substrate on the well diffusion layer Forming a groove at a position where a word line is formed in the buffer layer, the semiconductor substrate, and the element isolation region; and forming a channel diffusion layer in the semiconductor substrate between the bottom of the groove and the well diffusion layer. Forming a gate insulating film in the trench and on the semiconductor substrate; and forming a first conductive film on the semiconductor substrate including an inner wall of the trench in a memory element region. Forming a layer, forming a second conductive layer filling the trench through the first conductive layer on the semiconductor substrate, forming a second conductive layer on the semiconductor substrate in a logic element region separated by the element isolation region. Forming a well diffusion layer, forming a polysilicon layer for filling the trench on the semiconductor substrate, and forming a dummy layer of a material having an etching selectivity with respect to the polysilicon layer in order; Processing the dummy layer and forming a dummy gate with the polysilicon layer and the dummy layer on the semiconductor substrate in a logic element region via the gate insulating film; and forming the dummy gate in the trench. Removing the first conductive layer and the second conductive layer on the groove and on the semiconductor substrate so that one conductive layer is lower than the second conductive layer; Forming a word line between the first conductive layer and the second conductive layer left inside, and forming a groove between the groove side wall and the second conductive layer; Forming a diffusion layer on a semiconductor substrate, forming a low-concentration diffusion layer of a logic element on the surface of the semiconductor substrate on both sides of the dummy gate, and forming a sidewall insulating film on a side wall of the dummy gate; Forming a diffusion layer on the semiconductor substrate on both sides of the dummy gate on the dummy gate side via the low-concentration diffusion layer; and burying the inside of the groove and forming a sidewall insulating film on the side wall of the groove on the word line. Forming, forming a silicide layer on the word line and a diffusion layer of the logic element, filling the trench and covering the dummy gate. Forming an insulating film as described above; forming a connection hole on the word line to reach the diffusion layer formed in the memory element region in a state of overlapping with the word line via the insulating film; Forming an extraction electrode in the connection hole, flattening the surface of the insulating film, exposing an upper portion of the dummy gate, removing the dummy layer and exposing the polysilicon layer to form a gate groove Performing a step of doping the polysilicon layer of the dummy gate with an impurity, performing a heat treatment for activating the extraction electrode and the polysilicon layer, and forming a metal-based electrode in the gate groove. This is a method for manufacturing a semiconductor device provided with the same.
[0032]
In the second method of manufacturing a semiconductor device, a groove is formed on the side of the groove above the word line, and a sidewall insulating film is formed on the side wall of the word line so as to fill the groove. Even when the layer is formed, the sidewall insulating film is offset and the distance between the silicide layer and the gate insulating film is sufficiently ensured, so that a semiconductor device in which deterioration of the gate withstand voltage is suppressed can be obtained.
[0033]
In the second method for manufacturing a semiconductor device, since the buffer layer is formed, the buffer layer serves as a mask when the impurity for forming the channel diffusion layer is subsequently introduced into the semiconductor substrate at the bottom of the groove. Then, an impurity is selectively introduced into the semiconductor substrate at the bottom of the groove to form a channel diffusion layer.
[0034]
As described above, since the channel diffusion layer is formed in the semiconductor substrate between the groove lower part and the well diffusion layer, the impurity concentration in the region between the groove and the well diffusion layer is higher than the impurity concentration in the semiconductor substrate around the groove. Get higher. Further, since the concentration of the semiconductor substrate below the diffusion layer serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer serving as the source / drain is weakened. For this reason, it is possible to suppress the junction leak on the order of ppm, thereby forming a semiconductor device having extremely good data retention characteristics.
[0035]
In addition, a word line embedded in a groove formed in the semiconductor substrate via a gate insulating film is connected to a diffusion layer formed on the surface of the semiconductor substrate in a state of overlapping with the word line via an insulating film. Since the extraction electrode is formed, the insulating film on the word line can have a sufficient thickness of 20 nm to 30 nm or more. Thereby, the withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, since the entire surface of the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0036]
Furthermore, since the silicide layer is formed on the word line, the resistance of the word line is reduced, and the problem of delay is avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to this diffusion layer is reduced.
[0037]
Further, since a diffusion layer is formed on the surface of the semiconductor substrate and the word line is buried in the groove formed in the semiconductor substrate via a gate insulating film, the channel is formed at the bottom of the groove where the word line is formed. Formed around the semiconductor substrate on the side. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0038]
Further, since the diffusion layer in the memory element region is formed so that the impurity concentration is reduced in the depth direction, the semiconductor substrate concentration under the diffusion layer in the memory element region is not increased as required for the cell transistor. Therefore, the electric field at the junction is alleviated, and the performance of the data retention characteristic, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0039]
Also, by using a laminated structure of a polysilicon layer and a dummy layer for the dummy gate formed in the logic element region, the dummy layer is removed after the extraction electrode of the diffusion layer in the memory element region is formed, and the polysilicon of the dummy gate is removed. The layer can be doped with impurities. Thereafter, heat treatment is performed to form a metal gate electrode, so that the problem of boron penetration in the p-channel gate electrode due to the heat treatment can be minimized.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment according to the semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG. 1 and a partially enlarged view of FIG. FIG. 1 shows an example in which the semiconductor device of the present invention is applied to a DRAM, and FIG. 2 shows an enlarged schematic view of a portion A in FIG.
[0041]
As shown in FIGS. 1 and 2, the semiconductor substrate 11 is, for example, 1 × 10 ¹⁷ / Cm ³ It is composed of a silicon substrate having a p-type impurity concentration of about one level. On the semiconductor substrate 11, an element isolation region 12 for isolating a memory element region (hereinafter, referred to as a DRAM and referred to as a DRAM region in the drawings), a standard voltage logic region, a high voltage logic region, and the like are formed. The element isolation region 12 is formed to a depth of, for example, about 0.1 μm to 0.2 μm by, for example, STI (Shallow Trench Isolation) technology. Further, on the semiconductor substrate 11, a buffer layer 71 covering the element isolation region 12 is formed of, for example, a silicon oxide film to a thickness of, for example, 20 nm to 40 nm.
[0042]
The buffer layer 71 is necessary for manufacturing. That is, the buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed, and is connected to the junction of the DRAM at the time of ion implantation for adjusting the substrate concentration of the transistor (access transistor) of the memory element described later. In addition, when the silicide layer 21 is formed on the surface of the word line 18 buried in the groove 14, the silicide layer 21 is formed in the diffusion layer 19 in the DRAM region. It has a function of preventing formation.
[0043]
In the semiconductor substrate 11 in the memory element region, a well diffusion layer 13 is formed, for example, in a state in which the upper surface is deeper than 150 nm to 200 nm, and the lower surface is slightly deeper than the depth of the element isolation region 12. It is formed so that the thickness is, for example, about 0.8 μm. The well diffusion layer 13 is P-type and is formed by introducing, for example, boron. For example, when the well diffusion layer 13 is formed by ion implantation, boron is used as an ion species and a dose is set to, for example, 5 × 10 4. ¹² / Cm ² ~ 7 × 10 ¹² / Cm ² Degree.
[0044]
Further, if necessary, an element isolation diffusion layer (not shown) may be formed on the semiconductor substrate 11 below the element isolation region 12.
[0045]
Further, a groove 14 is formed in the element isolation region 12 and the semiconductor substrate 11 so as to penetrate the buffer layer 71 and to form a word line (hereinafter, word line also includes a gate electrode) in the DRAM region. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is formed so as to remain between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0046]
Further, it is desirable that the edge portion at the bottom of the groove 14 is formed in a so-called round shape in order to avoid electric field concentration of the cell transistor, and the width of the groove 14 becomes the channel length of the access transistor of the memory element. Therefore, it is desirable that the side wall of the groove 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible.
[0047]
Further, a channel diffusion layer 15 is formed in the semiconductor substrate 11 between the bottom of the groove 14 and the well diffusion layer 13. As the channel diffusion layer 15 of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10 ¹⁸ / Cm ³ ~ 1.0 × 10 ¹⁹ / Cm ³ The region to be formed is the semiconductor substrate 11 (11a) at the bottom of the groove 14 in which the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall and upper portion of the groove 14 may have a very low concentration. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 described later has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / Cm ³ ~ 1.0 × 10 ¹⁸ / Cm ³ ).
[0048]
A gate insulating film 16 is formed on the inner surface of the groove 14, on the semiconductor substrate 11, and the like. Since the gate insulating film 15 has a slightly larger film thickness than a state-of-the-art logic transistor and a slightly longer gate length, even in this generation, a silicon oxide film formed by thermal oxidation can be used. Is possible. Therefore, the gate insulating film 15 in the DRAM region is formed of, for example, a silicon oxide film having a thickness of about 1.5 nm to 5 nm.
[0049]
Further, a word line (including a gate electrode) 18 made of, for example, a phosphorus-doped polysilicon film is formed via the gate insulating film 16 so as to fill each groove 14. The word line 18 is formed of two polysilicon layers, a first conductive layer 181 and a second conductive layer 182. The first conductive layer 181 is formed of, for example, a phosphorus-doped polysilicon film having a thickness of 5 nm to 10 nm, and the second conductive layer 182 is formed of, for example, a non-doped polysilicon film doped with an impurity (for example, phosphorus). A groove 183 is formed on the wall surface of the groove 14 above the word line 18 (on the first conductive layer 181).
[0050]
On the side wall of the trench 14 on the polysilicon layer of the word line 18, a sidewall insulating film 20 for filling the trench 183 is formed of, for example, a silicon nitride film. Further, the word line 18 is formed of a silicide (for example, salicide) layer 21 as an upper layer. Therefore, the silicide layer 21 is formed above the word line 18 with respect to the gate insulating film 16 with the sidewall insulating film 20 interposed therebetween.
[0051]
The silicide layer 21 functioning as the word line 18 has at least a distance of at least about 30 to 100 nm from the surface of the semiconductor substrate 11 above the groove 14 as a distance at which a withstand voltage with respect to an extraction electrode 24 described later is secured. It is formed so as to be lowered, preferably about 50 nm to 90 nm. In this embodiment, for example, it is formed so as to be lowered by about 50 nm. Therefore, a withstand voltage distance between the diffusion layer and the extraction electrode 24 described later is ensured.
[0052]
Further, the silicide layer 21 is made of, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. are used. The sidewall insulating film 20 has a function of ensuring a withstand voltage between the silicide layer 21 and the diffusion layer 19. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0053]
Further, a diffusion layer 19 serving as a source / drain is formed on the semiconductor substrate 11 in the DRAM region. Phosphorus is used for the diffusion layer 19 as an N-type impurity, and the concentration is 1 × 10 ¹⁷ / Cm ³ ~ 1 × 10 ¹⁸ / Cm ³ It has become. Therefore, the semiconductor substrate 11 in this region is 1 × 10 ¹⁶ / Cm ³ ~ × 10 ¹⁷ / Cm ³ It is set to a very light concentration.
[0054]
Therefore, this NP junction becomes a super graded junction (junction having a very gentle concentration gradient). The junction in such a state relieves the electric field at the time of reverse bias, and dramatically contributes to suppressing junction leakage current, which is about two orders of magnitude worse than usual, which occurs in a defective bit of only a ppm level in a megabit DRAM. The data retention characteristic of the defective bit dominate the chip performance of the DRAM, and is an important technique for maintaining the data retention characteristic in the future DRAM.
[0055]
For example, if the substrate concentration is 5 × 10 ¹⁶ / Cm ³ If this is the case, a data holding characteristic of 500 ms or more at 85 ° C. can be obtained, which is expected to exhibit performance comparable to the data holding characteristic of the previous data even for 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed in a so-called round shape in the semiconductor substrate 11, a long effective channel length can be ensured. It is also possible to stabilize the transistor characteristics of a DRAM cell with severe requirements.
[0056]
On the entire surface of the semiconductor substrate 11, a first insulating film (insulating film) 22 is formed. The surface of the first insulating film 22 is flattened. Further, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective for suppressing the junction leak at the salicide formation portion, but need not be formed if unnecessary.
[0057]
Further, a first insulating film (insulating film) 22 is formed on the entire surface. The first insulating film 22 has a connection hole 23 that penetrates through the cap insulating film 80, the buffer layer 71 and the like and reaches the diffusion layer 19 in the DRAM region. The connection hole 23 is desirably formed as large as possible in diameter so that the extraction electrode can be brought into contact with the entire surface of the diffusion layer 19. Thereby, the contact resistance is reduced.
[0058]
Also, in the drawings, a state in which the alignment is slightly misaligned is intentionally described. However, unless excessive over-etching is performed at the time of opening the connection hole, the physical distance of the extraction electrode 24 of the word line formed in the connection hole 23 will be described. Can be secured. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18. In the connection hole 23, an extraction electrode 24 made of, for example, phosphorus-doped polysilicon is formed.
[0059]
The surface of the second insulating film 22 is flattened so that the upper surface of the extraction electrode 24 is flush with the surface of the second insulating film 22. Further, an etching stop layer 25 covering the extraction electrode 24 is formed on the second insulating film 22.
[0060]
In the etching stop layer 25, the first insulating film 22, and the cap insulating film 80, connection holes 26 reaching the silicide layers 21 on the word lines 18 in the DRAM region are formed. An extraction electrode 27 is formed in the connection hole 26. The take-out electrode 27 is made of a tungsten film 86 formed so as to fill the connection hole 26 via an adhesion layer 85 made of a titanium nitride film.
[0061]
On the etching stop layer 25, a second insulating film 31 covering the extraction electrode 27 is formed. The second insulating film 31 is formed by depositing, for example, a silicon oxide film to a thickness of 50 nm to 150 nm.
[0062]
A bit contact hole 32 connected to the extraction electrode 24 is formed in the second insulating film 31 and the etching stop layer 25. A bit line 34 is formed on the second insulating film 31, and a part of the bit line 34 is connected to the extraction electrode 24 through the bit contact hole 32. Further, a local wiring 35 is formed on the second insulating film 31. The bit line 34 and the local wiring 35 are formed of, for example, a tungsten film 37, an adhesive layer 36 is formed below the tungsten film 37, and a cap layer 38 is formed above the adhesive layer 36.
[0063]
On the second insulating film 22, an etching stopper layer 41 and a third insulating film 42 covering the bit line 34 and the local wiring 35 are formed. The etching stopper layer 41 is a silicon nitride film formed by an ALD (Atomic Layer Deposition) method and has a thickness of, for example, 30 nm to 50 nm.
[0064]
From the third insulating film 42 to the etching stopper layer 25, a connection hole 43 for forming a storage node contact reaching the extraction electrodes 24 of the storage node contact is formed. In the connection hole 43, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a thickness that ensures the withstand voltage between the bit line and the storage node contact. Further, in the connection hole 43, a storage node contact 44 connected to the extraction electrode 24 is formed. The storage node contact 44 is formed of a material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide, or the like. The surface of the third insulating film 42 is flattened together with the upper surface of the storage node contact 44, for example.
[0065]
A fourth insulating film 45 is formed on the third insulating film 42. In the fourth insulating film 45, a concave portion 46 in which a capacitor is formed is formed at the bottom so that the upper surface of the storage node contact 44 is exposed. In the concave portion 46, a capacitor 91 having an MIM (Metal / Insulator / Metal) structure that does not require heat treatment is formed. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or less. At present, for example, ruthenium (Ru) and ruthenium oxide (RuO) -based materials are used for the electrodes 92 and 94, and the electrodes 92 and 94 are used. BST (BaTiO 3) is formed on the dielectric film 93 formed therebetween. ₃ And SrTiO ₃ (Mixed crystal with).
[0066]
On the fourth insulating film 45, a fifth insulating film 47 that covers the capacitor 91 having the MIM structure is formed. The surface of the fifth insulating film 47 is flattened. In the fifth insulating film 47 to the first insulating film 22, connection holes 111, 112, 113, etc. for forming a capacitor lead electrode, a word line lead electrode, a local wiring lead electrode and the like are formed.
[0067]
In each of the connection holes 111, 112, 113, etc., a capacitor lead electrode 121, a word line lead electrode 122, a local wiring lead electrode 123, etc. are formed.
[0068]
Further, a sixth insulating film 48 is formed on the fifth insulating film 47. In the sixth insulating film 48, wiring grooves 131, 132, 133 reaching the electrodes 121, 122, 123 are formed, and in the wiring grooves 131-133, first wirings 141-143 are formed. . The first wirings 141 to 143 are made of, for example, copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121 to 123 and the wirings 141 to 143 are formed with a well-known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0069]
In the first semiconductor device, the groove 183 is formed on the side of the groove 14 above the word line 18 formed in the groove 14, and the word line (including the gate electrode) 18 is formed so as to fill the groove 183. Since the sidewall insulating film 20 is formed on the side wall of the groove 14, the physical distance between the silicide layer 21 on the upper surface of the word line 18 and the gate insulating film 16 depends on the portion formed in the groove 183 of the sidewall insulating film 20. Is sufficiently secured. Therefore, deterioration of the breakdown voltage of the gate insulating film 16 can be prevented.
[0070]
Since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the groove 14 where the channel is formed and the well diffusion layer 13, the impurity concentration in the region between the groove 14 and the well diffusion layer 13 is 14 becomes higher than the impurity concentration of the semiconductor substrate 11 around. In addition, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as a source / drain is extremely low, the electric field at the junction of the diffusion layer 19 is weakened, so that it is possible to suppress the junction leakage on the order of ppm. Thereby, the data retention characteristics are extremely improved.
[0071]
Since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to word line 18 is reduced.
[0072]
In addition, since the diffusion layer is formed on the surface side of the semiconductor substrate 11 and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film, the channel is formed in the groove in which the word line is formed. It is formed so as to go around the semiconductor substrate on the bottom side. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0073]
Further, since the impurity concentration of the diffusion layer 19 is reduced in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region does not have to be as high as required for the cell transistor. In addition, the electric field at the junction is alleviated, and the performance of data retention characteristics, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0074]
Further, the semiconductor device is overlapped with the word line 18 via the first insulating film 22 on the word line 18 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode 24 connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the first insulating film 22 on the word line 18 can have a sufficient thickness of 20 nm to 30 nm or more. Will be possible. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0075]
An example of an embodiment according to a first method of manufacturing a semiconductor device of the present invention will be described with reference to schematic cross-sectional views and partial enlarged schematic views of FIGS. 3 to 23 show a manufacturing method for forming a memory element and a logic element on the same semiconductor substrate, and the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.
[0076]
As shown in FIG. 3A, for example, 1 × 10 ¹⁷ / Cm ³ A silicon substrate having a p-type impurity concentration of the order is prepared. For example, the STI (Shallow Trench Isolation) technology allows the semiconductor substrate 11 to have an element isolation area for isolating a memory element area (hereinafter, referred to as a DRAM and referred to as a DRAM area), a standard voltage logic area, a high voltage logic area, and the like. 12 is formed. This element isolation region 12 is formed at a depth of, for example, about 0.1 μm to 0.2 μm. Next, a buffer layer 71 made of, for example, a silicon oxide film is formed on the semiconductor substrate 11 by, for example, 20 nm to 40 nm so as to cover the element isolation region 12 by chemical vapor deposition (hereinafter, referred to as CVD; CVD is an abbreviation of Chemical Vapor Deposition). Formed to a thickness of
[0077]
Further, after forming a resist film 201 on the semiconductor substrate 11, an opening 202 is formed on a memory cell formation region in a DRAM region by using lithography technology.
[0078]
Next, for example, boron is introduced into the semiconductor substrate 11 in the memory element region by ion implantation using the resist film 201 as a mask to form the well diffusion layer 13. As the ion implantation conditions, boron is used as an ion species, and the dose amount is, for example, 5 × 10 ¹² / Cm ² ~ 7 × 10 ¹² / Cm ² It is formed to a depth of, for example, more than 150 nm to 200 nm and a little deeper than the depth of the element isolation region 12 so as to be deeper than the depth of a groove to be formed later. The thickness of the well diffusion layer 13 in the depth direction is, for example, about 0.8 μm.
[0079]
Further, if necessary, an element isolation diffusion layer (not shown) may be formed on the semiconductor substrate 11 below the element isolation region 12.
[0080]
The buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. In addition, at the time of ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be performed later, it functions as a stopper for ion implantation in a region to be a junction of a DRAM. Further, when a salicide is formed on the surface of the word line buried in the groove, it has a function of preventing salicide from being formed in the diffusion layer in the DRAM region. After that, the resist film 201 is removed.
[0081]
Next, as shown in FIG. 4 (2), after a resist film 203 is formed on the semiconductor substrate 11, an opening 204 is formed in the resist film 203 on a region to be a word line (gate electrode) in a DRAM region by a lithography technique. To form
[0082]
Next, as shown in FIG. 5C, the buffer layer 71, the device isolation region 12, and the semiconductor substrate 11 are etched (for example, continuously etched) using the resist film 203 as an etching mask. A groove 14 for forming a word line (including a gate electrode) in a DRAM region is formed in 12 (field) and the semiconductor substrate 11. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is left between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0083]
Since the groove 14 is formed only in the DRAM region, it is desirable that the edge portion at the bottom of the groove 14 be formed in a so-called round shape in order to avoid electric field concentration of the cell transistor. Becomes the channel length of the access transistor of the memory element, so that the side wall of the groove 14 is desirably formed as perpendicular to the surface of the semiconductor substrate 11 as possible. Note that the buffer layer 71 formed in the DRAM region is simultaneously etched when the element isolation region 12 is etched. Thereafter, the resist film 203 is removed by a normal removal technique.
[0084]
The voltage assumed in this generation is 0.5 V to 1.2 V for the standard logic area, 1.5 V to 2.5 V for the high voltage logic area, and 1.5 V to 2 V for the DRAM cell word line boost. 0.5V.
[0085]
Next, as shown in FIG. 6D, a sacrificial oxide film (not shown) is formed to a thickness of, for example, 10 nm to 20 nm on the entire exposed surface of the semiconductor substrate 11 by, for example, a thermal oxidation method.
[0086]
Next, channel doping of the access transistor in the DRAM region is performed to form a channel diffusion layer 15 between the bottom of the groove 14 and the well diffusion layer 13.
[0087]
As the channel diffusion layer 15 of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10 ¹⁸ / Cm ³ ~ 1.0 × 10 ¹⁹ / Cm ³ The region which must be formed is a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down. There is no. In the above-described ion implantation, the buffer layer 71 provided first serves as a mask for ion implantation on the surface of the semiconductor substrate 11 and the logic element region. Therefore, the channel diffusion layer is formed only at the bottom of the groove 14 without using a new mask. 15 can be formed. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 (see FIG. 35) described later has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / Cm ³ ~ 1.0 × 10 ¹⁸ / Cm ³ ) Can be formed.
[0088]
Thereafter, the sacrificial oxide film (not shown) is removed by, for example, wet etching. Thereafter, a gate insulating film 16 is formed on the inner surface of the groove 14 in the DRAM region, on the semiconductor substrate 11, and the like by an ordinary method for forming a gate oxide film.
[0089]
As shown in FIGS. 7 (5) and 8, the first conductive layer 181 is phosphorus-doped to a thickness of, for example, 5 nm to 10 nm on the surface of the gate insulating film 16 so as to cover the inner wall of each groove 14 in the DRAM region. It is formed by depositing polysilicon. Next, a second conductive layer 182 is formed by depositing non-doped polysilicon to a thickness of 50 nm to 150 nm on the surface of the first conductive layer 181 so as to fill each groove 14 in the DRAM region. This film thickness may be sufficient to fill the groove 14, and the film thickness is set to a film thickness optimized especially for forming a groove-shaped word line.
[0090]
As shown in FIGS. 9 (6) and 10, the first conductive layer 181 and the second conductive layer 182 are etched back so that the first conductive layer 181 and the second conductive layer 182 remain inside the groove 14. In this etching, an etching condition in which the etching rate of the first conductive layer 181 is higher than that of the second conductive layer 182 is used. In other words, the first conductive layer 181 is formed using a conductive film whose etching rate is higher than that of the second conductive layer 182. As a result, the first conductive layer 181 having a higher etching rate is etched more, and a groove 183 is formed between the second conductive layer 182 on the first conductive layer 181 and the side wall of the close contact 4. At the same time, a word line (partly functioning as a gate electrode) 18 including the first conductive layer 181 and the second conductive layer 182 is formed inside the groove 14. At this time, the first conductive layer 181 and the second conductive layer 182 are etched back so that the surface of the word line 18 is lower than the surface of the semiconductor substrate 11 by about 30 nm to 100 nm, so that an electrode for extracting a diffusion layer formed later is formed. Withstand pressure distance is secured. In this etch back, the gate insulating film 16 functions as an etching stop layer.
[0091]
Further, ion implantation for forming a source / drain is performed on the semiconductor substrate 11 in the DRAM region to form a diffusion layer 19. As an example of the ion implantation conditions, phosphorus is used as an impurity to be ion-implanted, and the concentration is 1 × 10 4. ¹⁷ / Cm ³ ~ 1 × 10 ¹⁸ / Cm ³ The dose and the implantation energy are set so that Since the implantation energy penetrating the buffer layer 71 is sufficient, the implantation energy is set to, for example, 20 keV to 50 keV, and the dose is set to 1 × 10 ¹⁸ / Cm ² ~ 3 × 10 ¹⁸ / Cm ² Set to. If ions are implanted under these conditions, almost no ions are implanted into the semiconductor substrate 11 below the diffusion layer 19 in the DRAM region. Therefore, the semiconductor substrate 11 in this region is 1 × 10 ¹⁶ / Cm ³ ~ × 10 ¹⁷ / Cm ³ It is possible to set a very low density. The second conductive layer 182 is also doped with phosphorus by the above-described phosphorus ion implantation, and the first conductive layer 181 and the second conductive layer 182 have the same impurity concentration by the subsequent heat treatment. The first conductive layer 181 and the second conductive layer 182 are used only for word lines in the DRAM region and are not used for P-channel transistors. ⁺ A gate material (eg, phosphorus) can be used as a doping material.
[0092]
Therefore, this NP junction becomes a super graded junction (junction having a very gentle concentration gradient). The junction in such a state relieves the electric field at the time of reverse bias, and dramatically contributes to suppressing junction leakage current, which is about two orders of magnitude worse than usual, which occurs in a defective bit of only a ppm level in a megabit DRAM. The data retention characteristic of the defective bit dominate the chip performance of the DRAM, and is an important technique for maintaining the data retention characteristic in the future DRAM.
[0093]
For example, if the substrate concentration is 5 × 10 ¹⁶ / Cm ³ If this is the case, a data holding characteristic of 500 ms or more at 85 ° C. can be obtained, which is expected to exhibit performance comparable to the data holding characteristic of the previous data even for 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed in a so-called round shape in the semiconductor substrate 11, a long effective channel length can be ensured. It is also possible to stabilize the transistor characteristics of a DRAM cell with severe requirements.
[0094]
In the above-described ion implantation, ion implantation is performed slightly shallower in consideration of diffusion due to heat treatment for forming a gate in a DRAM region later. Since it is formed at the bottom of the groove 14 to be formed, there is no problem at all. In addition, since activation is performed by a subsequent heat treatment, there is no need to perform a heat treatment at this stage.
[0095]
Next, as shown in FIG. 11 (7), a protective film 78 for protecting the gate in the DRAM region is formed of, for example, a thin silicon nitride film (for example, having a thickness of 10 nm to 50 nm). The protective film 78 is formed so as to fill the trench 183, and is formed in a sidewall shape on the side wall on the word line 18 in the DRAM region later, and contributes to securing the withstand voltage of the side wall of the word line 18 during salicide formation.
[0096]
Next, as shown in FIG. 12 (8) and FIG. 13, the protective film 78 in the DRAM region is etched by, for example, reactive ion etching (RIE) to expose the word line 18 in the DRAM region. As a result, the sidewall insulating film 20 made of the protective film 78 is formed on the side wall of the groove 14 on the word line 18 so as to fill the groove 183. This sidewall insulating film 20 has a function of protecting the side wall. In the reactive ion etching, it is important that the diffusion layer 19 in the DRAM region is not exposed, that is, the buffer layer 71 is left on the diffusion layer 19.
[0097]
Further, as shown in FIG. 14 (9), a silicide layer 21 is selectively formed on the word line 18 in the DRAM region by using a normal silicidation technique. In this manner, the silicide layer 21 is selectively formed on the word line 18 in the DRAM region where low resistance needs to be realized. As this silicide layer, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. can be used.
[0098]
Thereafter, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective for suppressing the junction leak at the salicide formation portion, but need not be formed if unnecessary. Note that, as described above, a silicide layer may be formed also on the gate electrode of the transistor in the peripheral circuit portion to form a salicide structure to reduce the resistance of the gate electrode.
[0099]
Next, as shown in FIG. 15 (10), after forming a first insulating film (insulating film) 22 on the entire surface, the surface of the first insulating film 22 is flattened by CMP. The method of planarizing the surface of the first insulating film 22 is not limited to CMP as long as planarization can be realized, and for example, an etch-back method may be used. Then, after forming a resist film 215 on the first insulating film 22, a connection hole pattern 216 for contacting a diffusion layer in the DRAM region is formed in the resist film 215 by lithography.
[0100]
Next, etching is performed using the resist film 215 as an etching mask to form a connection hole 23 that penetrates through the first insulating film 22 and reaches the diffusion layer 19 in the DRAM region, as shown in FIG. I do. At this time, since the word line (gate electrode) 18 in the DRAM region is disposed below the surface of the semiconductor substrate 11 with respect to the diffusion layer 19 to be contacted, there is no need to use a special technique such as a self-aligned contact. Further, it is desirable to form the connection hole 23 as large as possible so that the entire surface of the diffusion layer 19 of the DRAM can contact the extraction electrode. Thereby, the contact resistance is reduced.
[0101]
In the drawings, a state in which the alignment is slightly misaligned is intentionally described. However, unless excessive over-etching is performed at the time of opening the connection hole, the physical characteristics of the word line extraction electrode formed in the connection hole 23 in a later step will be described. It is possible to secure a long distance. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.
[0102]
Next, an extraction electrode forming film 81 is formed on the first insulating film 22 so as to fill the connection holes 23. The extraction electrode forming film 81 is formed of, for example, phosphorus-doped polysilicon. For the extraction electrode forming film 81 for extracting the diffusion layer, it is desirable that phosphorus-doped polysilicon be selected in consideration of the reduction of junction leakage in the DRAM region as in the related art. At this stage, heat treatment for activation is unnecessary.
[0103]
Thereafter, as shown in (12) of FIG. 17, an excessive extraction electrode forming film 81 (phosphorus-doped polysilicon) on the first insulating film 22 is removed by, for example, CMP, and a diffusion layer is formed in the connection hole 23. The extraction electrode 24 made of the extraction electrode forming film 81 connected to the substrate 19 is formed, and the first insulating film 22 is polished to flatten its surface.
[0104]
After that, heat treatment is performed. By this heat treatment, the extraction electrode 24 made of polysilicon in the DRAM region is activated. In this heat treatment, RTA (Rapid Thermal Annealing) at 900 ° C. for about 10 seconds is sufficient, but thermal annealing using an ordinary furnace may be performed. In the subsequent steps, a high-temperature heat step is not performed. For example, when a logic element is formed simultaneously with a DRAM, so-called “penetration” in which boron diffuses from the gate electrode of the logic element is minimized. Can be suppressed.
[0105]
Next, as shown in FIG. 18 (13), an etching stop layer 25 covering the extraction electrode 24 in the DRAM region is formed on the entire surface of the first insulating film 22 with, for example, a silicon oxide film.
[0106]
Thereafter, as shown in (14) of FIG. 19, after forming a resist film (not shown) on the etching stop layer 25, a connection hole for a word line take-out contact in the DRAM region is formed in the resist film by a lithography technique. A pattern (not shown) is formed. Subsequently, using the resist film as an etching mask, a connection hole penetrating through the etching stop layer 25, the first insulating film 22, and the cap insulating film 80 and reaching the silicide layer 21 on the word line 18 in the DRAM region. 26 is formed.
[0107]
After that, the resist film is removed. Next, an adhesion layer 85 made of a titanium nitride film is formed on the inner surface of the connection hole 26 by a normal tungsten plug formation technique, and then a tungsten film 86 is formed so as to fill the connection hole 26. After that, excess portions of the tungsten film 86 and the adhesion layer 85 on the etching stop layer 25 are removed by CMP, and an extraction electrode 27 is formed inside the connection hole 26.
[0108]
Next, a second insulating film 31 is formed on the entire surface of the etching stop layer 25 by, for example, depositing a silicon oxide film to a thickness of 50 nm to 150 nm so as to cover the extraction electrode 27.
[0109]
Then, after forming a resist film (not shown) on the second insulating film 31, an opening (not shown) is formed at a position where a bit contact is to be formed in the resist film by lithography. By etching using the resist film as a mask, a bit contact hole 32 reaching the predetermined extraction electrode 24 is formed in the etching stopper layer 25 and the second insulating film 31 as shown in FIG.
[0110]
Next, a wiring metal layer for forming the bit line 34 and the local wiring 35 is formed. In this wiring metal layer, first, an adhesion layer 36 formed by stacking a titanium film and a titanium nitride film is formed on the inner surface of the bit contact hole 32 and on the second insulating film 31. Further, a tungsten film 37 serving as a main material of the metal wiring is formed on the adhesion layer 36 so as to fill the bit contact holes 32. Further, a cap layer 38 is formed on the tungsten film 37 by, for example, a silicon nitride film.
[0111]
Thereafter, the cap layer 38, the tungsten film 37, and the adhesion layer 36 are patterned by the usual lithography and etching techniques to form the bit lines 34 connected to the bit contact take-out electrodes 24 through the bit contact holes 32. , Local wiring 35 is formed. Therefore, the cap layer 38 is formed on the bit line 34 and the local wiring 35.
[0112]
Thereafter, an etching stopper layer 41 covering the bit line 34 is formed on the second insulating film 31 with an ALD silicon nitride film to a thickness of, for example, 30 nm to 50 nm.
[0113]
Next, as shown in (16) of FIG. 21, a third insulating film 42 is formed on the etching stopper layer 41. Then, the surface of the third insulating film 42 is flattened using, for example, CMP. Next, after a resist film 219 is formed on the third insulating film 42, an opening pattern 220 for opening a storage node contact is formed by lithography. This opening pattern 220 can be formed larger than the diameter of the connection hole where the actual storage node contact is formed.
[0114]
Then, using the resist film 219 as an etching mask, as shown in (17) of FIG. 22, the region from the third insulating film 42 to the etching stop layer 25 is etched to form the extraction electrode 24 of the storage node contact, A connection hole 43 for forming a storage node contact reaching 24 is formed. In this etching, the cap layer 38 and the etching stopper layer 41 serve as an etching mask in addition to the resist film 219 (see (16) in FIG. 21). Although part of the etching stopper layer 41 is etched, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a thickness enough to ensure the withstand voltage between the bit line and the storage node contact. Thereafter, the resist film 219 (see (16) in FIG. 21) is removed.
[0115]
Next, as shown in (18) of FIG. 23, a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is formed, for example, by forming a material layer by depositing tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide, or the like on the third insulating film 42 so as to fill the connection hole 43. The surplus material layer on the third insulating film 42 is formed by the material layer left in the connection hole 43 by removing the material layer by, for example, CMP.
[0116]
Next, a fourth insulating film 45 covering the storage node contact 44 and the like is formed on the third insulating film 42. Next, a concave portion 46 in which a capacitor is formed is formed in the fourth insulating film 45 so that the upper surface of the storage node contact 44 is exposed at the bottom.
[0117]
Thereafter, a capacitor 91 having an MIM (Metal / Insulator / Metal) structure that does not require heat treatment is formed in the concave portion 46. The MIM-structured capacitor 91 is expected to be indispensable in a DRAM of 0.1 μm or less. At present, as an example, the electrodes 92 and 94 are made of ruthenium (Ru) or ruthenium oxide (RuO) -based material, and The film 93 has BST (BaTiO ₃ And SrTiO ₃ And a mixed crystal) film.
[0118]
Next, a fifth insulating film 47 is formed on the fourth insulating film 45 so as to cover the capacitor 91 having the MIM structure. Thereafter, the surface of the fifth insulating film 47 is flattened by CMP. Next, in the fifth insulating film 47 or the second insulating film 31, connection holes 111, 112, 113 and the like for forming a capacitor lead electrode, a word line lead electrode and the like are formed.
[0119]
Further, a capacitor lead electrode 121, a word line lead electrode 122, a local wiring lead electrode 123, and the like are formed in the connection holes 111, 112, 113, and the like. Further, a sixth insulating film 48 is formed on the fifth insulating film 47. Next, wiring grooves 131, 132, 133 reaching the electrodes 121, 122, 123 and the like are formed in the sixth insulating film 48, and wirings 141, 142, 143 are formed in the wiring grooves 131, 132, 133. The wirings 141, 142, 143 are made of, for example, copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121, 122, and 123 and the wirings 141, 142, and 143 are formed with a well-known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0120]
In the first method of manufacturing a semiconductor device, the groove 183 is formed on the side of the groove 14 above the word line (gate electrode) 18, and the groove 14 is formed on the word line (gate electrode) 18 so as to fill the groove 183. Since the sidewall insulating film 20 is formed on the substrate, the silicide layer 21 may be formed on the word line (gate electrode) 18. Since the distance between the silicide layer 21 and the gate insulating film 16 is sufficiently ensured by the portion formed in the groove 183 of the sidewall insulating film 20, a semiconductor device in which the deterioration of the gate withstand voltage is suppressed is obtained.
[0121]
In the first method of manufacturing a semiconductor device, since the buffer layer 71 is formed, when the impurity for forming the channel diffusion layer 15 is introduced into the semiconductor substrate 11 at the bottom of the groove 14, the buffer layer 71 is formed. Is used as a mask, an impurity is selectively introduced into the semiconductor substrate 11 at the bottom of the groove 14, and the channel diffusion layer 15 is formed.
[0122]
As described above, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the groove 14 and the well diffusion layer 13, the impurity concentration in the region between the groove 14 and the well diffusion layer 13 is reduced. It becomes higher than the impurity concentration of the semiconductor substrate 11. Further, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as a source / drain can be kept extremely low, the electric field at the junction of the diffusion layer 19 is weakened. For this reason, it is possible to suppress the junction leak on the order of ppm, thereby forming a semiconductor device having extremely good data retention characteristics.
[0123]
In addition, the semiconductor is overlapped with the word line 18 via the second insulating film 22 on the word line 18 buried in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode 24 connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the second insulating film 22 on the word line 18 can have a sufficient thickness of 20 nm to 30 nm or more. Become. Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0124]
Further, since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, and the problem of delay is avoided. At the same time, the contact resistance to word line 18 is reduced.
[0125]
Further, since a diffusion layer 19 is formed on the front surface side of the semiconductor substrate 11 and a word line 18 is buried in a groove 14 formed in the semiconductor substrate 11 via a gate insulating film 16, a channel is formed. Are formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0126]
Further, since the diffusion layer 19 in the memory element region is formed so that the impurity concentration becomes low in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region is reduced to a level required for the cell transistor. Since it is not necessary to increase the density, the electric field at the junction is alleviated, and the performance of the data retention characteristic, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0127]
An embodiment according to the second semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG. 24 and an enlarged view of a portion E in FIG.
[0128]
As shown in FIGS. 24 and 25, the semiconductor substrate 11 is, for example, 1 × 10 ¹⁷ / Cm ³ It is composed of a silicon substrate having a p-type impurity concentration of about one level. On the semiconductor substrate 11, an element isolation region 12 for isolating a memory element region (hereinafter, referred to as a DRAM and referred to as a DRAM region in the drawings), a standard voltage logic region, a high voltage logic region, and the like are formed. The element isolation region 12 is formed to a depth of, for example, about 0.1 μm to 0.2 μm by, for example, STI (Shallow Trench Isolation) technology. Further, on the semiconductor substrate 11, a buffer layer 71 covering the element isolation region 12 is formed of, for example, a silicon oxide film to a thickness of, for example, 20 nm to 40 nm.
[0129]
The buffer layer 71 is necessary for manufacturing. That is, the buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed, and is connected to the junction of the DRAM at the time of ion implantation for adjusting the substrate concentration of the transistor (access transistor) of the memory element described later. In addition, when the silicide layer 27 is formed on the surface of the word line 18 buried in the groove 14, the silicide layer 27 is formed in the diffusion layer 19 in the DRAM region. It has a function of preventing formation.
[0130]
In the semiconductor substrate 11 in the memory element region, a well diffusion layer 13 is formed, for example, in a state in which the upper surface is deeper than 150 nm to 200 nm, and the lower surface is slightly deeper than the depth of the element isolation region 12. It is formed so that the thickness is, for example, about 0.8 μm. The well diffusion layer 13 is P-type and is formed by introducing, for example, boron. For example, when the well diffusion layer 13 is formed by ion implantation, boron is used as an ion species and a dose is set to, for example, 5 × 10 4. ¹² / Cm ² ~ 7 × 10 ¹² / Cm ² Degree.
[0131]
Further, if necessary, an element isolation diffusion layer (not shown) may be formed on the semiconductor substrate 11 below the element isolation region 12.
[0132]
Further, a groove 14 is formed in the element isolation region 12 and the semiconductor substrate 11 so as to penetrate the buffer layer 71 and to form a word line (including a gate electrode) in the DRAM region. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is formed so as to remain between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0133]
Further, it is desirable that the edge portion at the bottom of the groove 14 is formed in a so-called round shape in order to avoid electric field concentration of the cell transistor, and the width of the groove 14 becomes the channel length of the access transistor of the memory element. Therefore, it is desirable that the side wall of the groove 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible.
[0134]
Further, a channel diffusion layer 15 is formed in the semiconductor substrate 11 between the bottom of the groove 14 and the well diffusion layer 13. As the channel diffusion layer 15 of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10 ¹⁸ / Cm ³ ~ 1.0 × 10 ¹⁹ / Cm ³ The region to be formed is the semiconductor substrate 11 (11a) at the bottom of the groove 14 in which the semiconductor substrate 11 is dug down, and the semiconductor substrate 11 on the side wall and upper portion of the groove 14 may have a very low concentration. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 described later has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / Cm ³ ~ 1.0 × 10 ¹⁸ / Cm ³ ).
[0135]
A gate insulating film 16 is formed on the inner surface of the groove 14, on the semiconductor substrate 11, and the like. Since the gate insulating film 15 has a slightly larger film thickness than a state-of-the-art logic transistor and a slightly longer gate length, even in this generation, a silicon oxide film formed by thermal oxidation can be used. Is possible. Therefore, the gate insulating film 15 in the DRAM region is formed of, for example, a silicon oxide film having a thickness of about 1.5 nm to 5 nm.
[0136]
Further, a word line (including a gate electrode) 18 made of, for example, a phosphorus-doped polysilicon film is formed via the gate insulating film 16 so as to fill each groove 14. The word line 18 is formed of two polysilicon layers, a first conductive layer 181 and a second conductive layer 182. The first conductive layer 181 is formed of, for example, a phosphorus-doped polysilicon film having a thickness of 5 nm to 10 nm, and the second conductive layer 182 is formed of, for example, a non-doped polysilicon film doped with an impurity (for example, phosphorus). A groove 183 is formed on the wall surface of the groove 14 above the word line 18 (on the first conductive layer 181).
[0137]
On the side wall of the trench 14 on the polysilicon layer of the word line 18, a sidewall insulating film 20 for filling the trench 183 is formed of, for example, a silicon nitride film. Further, the word line 18 is formed of a silicide (for example, salicide) layer 21 as an upper layer. Therefore, the silicide layer 21 is formed above the word line 18 with respect to the gate insulating film 16 with the sidewall insulating film 20 interposed therebetween.
[0138]
The silicide layer 21 functioning as the word line 18 has at least a distance of at least about 30 to 100 nm from the surface of the semiconductor substrate 11 above the groove 14 as a distance at which a withstand voltage with respect to an extraction electrode 24 described later is secured. It is formed so as to be lowered, preferably about 50 nm to 90 nm. In this embodiment, for example, it is formed so as to be lowered by about 50 nm. Therefore, a withstand voltage distance between the diffusion layer and the extraction electrode 24 described later is ensured.
[0139]
Further, the silicide layer 21 is made of, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. are used. The sidewall insulating film 20 has a function of ensuring a withstand voltage between the silicide layer 21 and the diffusion layer 19. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0140]
Further, a diffusion layer 19 serving as a source / drain is formed on the semiconductor substrate 11 in the DRAM region. Phosphorus is used for the diffusion layer 19 as an N-type impurity, and the concentration is 1 × 10 ¹⁷ / Cm ³ ~ 1 × 10 ¹⁸ / Cm ³ It has become. Therefore, the semiconductor substrate 11 in this region is 1 × 10 ¹⁶ / Cm ³ ~ × 10 ¹⁷ / Cm ³ It is set to a very light concentration.
[0141]
Therefore, this NP junction becomes a super graded junction (junction having a very gentle concentration gradient). The junction in such a state relieves the electric field at the time of reverse bias, and dramatically contributes to suppressing junction leakage current, which is about two orders of magnitude worse than usual, which occurs in a defective bit of only a ppm level in a megabit DRAM. The data retention characteristic of the defective bit dominate the chip performance of the DRAM, and is an important technique for maintaining the data retention characteristic in the future DRAM.
[0142]
For example, if the substrate concentration is 5 × 10 ¹⁶ / Cm ³ If this is the case, a data holding characteristic of 500 ms or more at 85 ° C. can be obtained, which is expected to exhibit performance comparable to the data holding characteristic of the previous data even for 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed in a so-called round shape in the semiconductor substrate 11, a long effective channel length can be ensured. It is also possible to stabilize the transistor characteristics of a DRAM cell with severe requirements.
[0143]
On the other hand, a P-well diffusion layer 51 of an N-channel transistor and an N-well diffusion layer (not shown) of a P-channel transistor are formed on the semiconductor substrate 11 in the standard voltage logic region. On the semiconductor substrate 11 in the high-voltage logic region, a P-well diffusion layer (not shown) of an N-channel transistor and an N-well diffusion layer 61 of a P-channel transistor are formed. Note that channel doping is performed as necessary.
[0144]
Further, low-concentration diffusion layers 52 of the N-channel transistor are formed in the semiconductor substrate 11 (P-well diffusion layer 51) in the N-channel transistor formation region of the standard voltage logic region. A low-concentration diffusion layer (not shown) of a P-channel transistor is formed on the semiconductor substrate 11 in the p-channel transistor formation region of the standard voltage logic region.
[0145]
Further, low-concentration diffusion layers 62 of a P-channel transistor are formed in the semiconductor substrate 11 (N-well diffusion layer 61) in the P-channel transistor formation region of the high-voltage logic region. A low-concentration diffusion layer (not shown) of the N-channel transistor is formed on the semiconductor substrate 11 in the formation region of the N-channel transistor in the high-voltage logic region.
[0146]
On the semiconductor substrate 11 (including the element isolation region 12) in the logic element region, a gate insulating film 17 of the logic element is formed. In this generation, the gate insulating film is generally formed separately according to the film thickness, and the gate insulating film is formed separately using a resist process. The gate insulating film is made of silicon oxide or silicon nitride when heat resistance is required. Further, in order to prevent penetration of boron (B) from the P-channel gate, for example, a silicon oxynitride film is used for the P-channel gate.
[0147]
On the other hand, on the semiconductor substrate 11 in the standard voltage logic region, a gate electrode 51 is formed via a gate insulating film 17. The gate electrode 51 has a lower layer formed of a polysilicon layer made of phosphorus-doped polysilicon, and an upper layer formed of a metal gate electrode formed of a laminated film of an adhesion layer and a metal layer formed by replacing a dummy layer. For example, a titanium nitride layer is used for the adhesion layer, and a tungsten layer is used for the metal layer. Further, a side wall 54 is formed on the side wall of the gate electrode 51 with the gate insulating film 17 interposed therebetween. The low-concentration diffusion layers 52, 52 are formed on the semiconductor substrate 11 below the sidewalls 54. The diffusion layers 55, 55 are formed on the semiconductor substrate 11 on both sides of the gate electrode 51 via the low-concentration diffusion layers 52, 52. Is formed. A silicide layer 58 is formed on the diffusion layer 55. As the silicide layer 58, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. can be used.
[0148]
Further, a gate electrode 61 is formed on the semiconductor substrate 11 in the high-voltage logic region via a gate insulating film 17. The gate electrode 61 has a lower layer formed of a polysilicon layer formed of boron-doped polysilicon, and an upper layer formed of a metal gate electrode formed of a laminated film of an adhesion layer formed by replacing a dummy layer and a metal layer, For example, a titanium nitride layer is used for the adhesion layer, and a tungsten layer is used for the metal layer. Further, a side wall 64 is formed on the side wall of the gate electrode 61 via the gate insulating film 17. The low-concentration diffusion layers 62, 62 are formed on the semiconductor substrate 11 below the sidewalls 64, and the diffusion layers 65, 65 are formed on the semiconductor substrate 11 on both sides of the gate electrode 61 via the low-concentration diffusion layers 62, 62. Is formed. A silicide layer 68 is formed above the diffusion layer 65. As the silicide layer 58, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. can be used.
[0149]
The sidewalls 54 and 64 are preferably formed of silicon oxide having a lower stress than silicon nitride and having good removability by wet processing. Alternatively, it can be formed using a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film.
[0150]
Further, a gate electrode (gate wiring) 51 having the same structure as the gate electrode 51 is formed on the element isolation region 12 in the logic region.
[0151]
On the entire surface of the semiconductor substrate 11, a first insulating film (insulating film) 19 is formed. The surface of the first insulating film 19 is flattened, and the surfaces of the gate electrodes 51 and 61 in the logic region are on the same plane.
[0152]
Further, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective for suppressing the junction leak at the salicide formation portion, but need not be formed if unnecessary.
[0153]
Further, a first insulating film (insulating film) 22 is formed on the entire surface. The first insulating film 22 has a connection hole 23 that penetrates through the cap insulating film 80, the buffer layer 71 and the like and reaches the diffusion layer 19 in the DRAM region. The connection hole 23 is desirably formed as large as possible in diameter so that the extraction electrode can be brought into contact with the entire surface of the diffusion layer 19. Thereby, the contact resistance is reduced.
[0154]
Also, in the drawings, a state in which the alignment is slightly misaligned is intentionally described. However, unless excessive over-etching is performed at the time of opening the connection hole, the physical distance of the extraction electrode 24 of the word line formed in the connection hole 23 will be described. Can be secured. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18. In the connection hole 23, an extraction electrode 24 made of, for example, phosphorus-doped polysilicon is formed.
[0155]
The surface of the second insulating film 22 is flattened so that the upper surface of the extraction electrode 24 and the upper surfaces of the gate electrodes 51 and 61 are flush with the surface of the second insulating film 22. Further, on the second insulating film 22, an etching stop layer 25 covering the extraction electrode 24 and the gate electrodes 51 and 61 is formed.
[0156]
In the etching stop layer 25, the first insulating film 22, and the cap insulating film 80, the connection holes 26, 58 reaching the silicide layers 21 on the word lines 18 in the DRAM region and the silicide layers 57, 67 of the transistors in the logic region. , 68 are formed. Extraction electrodes 27, 59, and 69 are formed in the connection holes 26, 58, and 68, respectively. The extraction electrodes 27, 59, and 69 are made of a tungsten film formed so as to fill the connection holes 26, 58, and 68 via an adhesion layer made of a titanium nitride film.
[0157]
On the etching stop layer 25, a second insulating film 31 covering the extraction electrodes 27, 59, 69 is formed. The second insulating film 31 is formed by depositing, for example, a silicon oxide film to a thickness of 50 nm to 150 nm.
[0158]
A bit contact hole 32 connected to the extraction electrode 24 and a local hatching contact hole 33 connected to the extraction electrode 59 are formed in the second insulating film 31 and the etching stop layer 25. A bit line 34 is formed on the second insulating film 31, and a part of the bit line 34 is connected to the extraction electrode 24 through the bit contact hole 32. Further, a local wiring 35 is formed on the second insulating film 31, and a part thereof is connected to the extraction electrode 59 through the local wiring contact hole 33. The bit line 34 and the local wiring 35 are formed of, for example, a tungsten film 37, an adhesive layer 36 is formed below the tungsten film 37, and a cap layer 38 is formed above the adhesive layer 36.
[0159]
On the second insulating film 22, an etching stopper layer 41 and a third insulating film 42 covering the bit line 34 and the local wiring 35 are formed. The etching stopper layer 41 is an ALD silicon nitride film and has a thickness of, for example, 30 nm to 50 nm.
[0160]
From the third insulating film 42 to the etching stopper layer 25, a connection hole 43 for forming a storage node contact reaching the extraction electrodes 24 of the storage node contact is formed. In the connection hole 43, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a thickness that ensures the withstand voltage between the bit line and the storage node contact. Further, in the connection hole 43, a storage node contact 44 connected to the extraction electrode 24 is formed. The storage node contact 44 is formed of a material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide, or the like. The surface of the third insulating film 42 is flattened together with the upper surface of the storage node contact 44, for example.
[0161]
A fourth insulating film 45 is formed on the third insulating film 42. In the fourth insulating film 45, a concave portion 46 in which a capacitor is formed is formed at the bottom so that the upper surface of the storage node contact 44 is exposed. In the concave portion 46, a capacitor 91 having an MIM (Metal / Insulator / Metal) structure that does not require heat treatment is formed. The capacitor 91 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or less. At present, for example, ruthenium (Ru) and ruthenium oxide (RuO) -based materials are used for the electrodes 92 and 94, and the electrodes 92 and 94 are used. BST (BaTiO 3) is formed on the dielectric film 93 formed therebetween. ₃ And SrTiO ₃ (Mixed crystal with).
[0162]
On the fourth insulating film 45, a fifth insulating film 47 that covers the capacitor 91 having the MIM structure is formed. The surface of the fifth insulating film 47 is flattened. The fifth insulating film 47 to the first insulating film 22 are used to form a capacitor lead electrode, a word line lead electrode, a local wiring lead electrode, a diffusion layer lead electrode in a logic region, a gate lead electrode in a logic region, and the like. Connection holes 111, 112, 113, 114 to 116, 117 and the like.
[0163]
In each of the connection holes 111, 112, 113, 114 to 116, 117, etc., a capacitor extraction electrode 121, a word line extraction electrode 122, a local wiring extraction electrode 123, a diffusion layer extraction electrode 124 of a standard voltage logic region, a high voltage logic region Of the diffusion layer, a gate extraction electrode 127 of the logic region, and the like.
[0164]
Further, a sixth insulating film 48 is formed on the fifth insulating film 47. Wiring grooves 131, 132, 133, 134, 135, and 136 reaching the electrodes 121, 122, 123, 124, 127, 125, and 126 are formed in the sixth insulating film 48, and the wiring grooves 131 to 136 are formed. Are formed with first wirings 141 to 146. The first wirings 141 to 146 are made of, for example, copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121 to 127 and the wirings 141 to 146 are provided with a well-known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0165]
In the second semiconductor device, a groove 183 is formed on the side of the groove 14 above the word line 18 formed in the groove 14, and the word line (including the gate electrode) 18 is formed so as to fill the groove 183. Since the sidewall insulating film 20 is formed on the side wall of the groove 14, the physical distance between the silicide layer 21 on the upper surface of the word line 18 and the gate insulating film 16 depends on the portion formed in the groove 183 of the sidewall insulating film 20. Is sufficiently secured. Therefore, deterioration of the breakdown voltage of the gate insulating film 16 can be prevented.
[0166]
In the second semiconductor device, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower portion of the groove 14 where the channel is formed and the well diffusion layer 13, the formation of the channel 14 and the well diffusion layer 13 The impurity concentration in the region between them becomes higher than the impurity concentration of the semiconductor substrate 11 around the trench 14. Further, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain is extremely low, the electric field at the junction of the diffusion layer 19 serving as the source / drain is weakened. , Thereby greatly improving data retention characteristics.
[0167]
Since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, the problem of delay is avoided, and the operation speed is improved. At the same time, the contact resistance to word line 18 is reduced. Further, since the silicide layers 57 and 67 are formed on the diffusion layers 55 and 65 of the logic element, the contact resistance to the diffusion layers 55 and 65 is reduced.
[0168]
Moreover, since the diffusion layer 19 is formed on the surface side of the semiconductor substrate 11 and the word line 18 is buried in the groove 14 formed on the semiconductor substrate 11 via the gate insulating film 16, the channel is formed by the word line 18. Are formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0169]
Further, since the impurity concentration of the diffusion layer 19 is reduced in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region does not have to be as high as required for the cell transistor. In addition, the electric field at the junction is alleviated, and the performance of data retention characteristics, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0170]
Further, a diffusion layer formed on the surface of the semiconductor substrate 11 on the word line 18 buried in the trench 14 via the gate insulating film 16 in a state of overlapping with the word line 18 via the first insulating film 22. Since the extraction electrode 24 connected to the layer 19 is formed, the second insulating film 22 on the word line 18 can have a sufficient thickness of 20 nm to 30 nm or more. Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0171]
An example of an embodiment according to a method for manufacturing a semiconductor device of the present invention will be described with reference to schematic sectional views and partial enlarged views of FIGS. 26 to 52 show a manufacturing method for forming a memory element and a logic element on the same semiconductor substrate, and the same components as those described with reference to FIG. 25 are denoted by the same reference numerals.
[0172]
As shown in FIG. 26A, as the semiconductor substrate 11, for example, 1 × 10 ¹⁷ / Cm ³ A silicon substrate having a p-type impurity concentration of the order is prepared. For example, the STI (Shallow Trench Isolation) technology allows the semiconductor substrate 11 to have an element isolation area for isolating a memory element area (hereinafter, referred to as a DRAM and referred to as a DRAM area), a standard voltage logic area, a high voltage logic area, and the like. 12 is formed. This element isolation region 12 is formed at a depth of, for example, about 0.1 μm to 0.2 μm. Next, a buffer layer 71 made of, for example, a silicon oxide film is formed on the semiconductor substrate 11 by, for example, 20 nm to 40 nm so as to cover the element isolation region 12 by chemical vapor deposition (hereinafter, referred to as CVD; CVD is an abbreviation of Chemical Vapor Deposition). Formed to a thickness of
[0173]
Further, after a resist film 201 is formed on the semiconductor substrate 11, the resist film 201 in a portion to be a DRAM region is removed by using lithography technology, and a logic region (hereinafter, a standard voltage logic region and a high voltage logic region are defined as a logic region). Is left on the resist film 201).
[0174]
Next, for example, boron is introduced into the semiconductor substrate 11 in the memory element region by ion implantation using the resist film 201 as a mask to form the well diffusion layer 13. As the ion implantation conditions, boron is used as an ion species, and the dose amount is, for example, 5 × 10 ¹² / Cm ² ~ 7 × 10 ¹² / Cm ² It is formed to a depth of, for example, more than 150 nm to 200 nm and a little deeper than the depth of the element isolation region 12 so as to be deeper than the depth of a groove to be formed later. The thickness of the well diffusion layer 13 in the depth direction is, for example, about 0.8 μm.
[0175]
Further, if necessary, an element isolation diffusion layer (not shown) may be formed on the semiconductor substrate 11 below the element isolation region 12.
[0176]
The buffer layer 71 has a function of a buffer film when the well diffusion layer 13 is formed. In addition, at the time of ion implantation for adjusting the substrate concentration of a transistor (access transistor) of a memory element to be performed later, it functions as a stopper for ion implantation in a region to be a junction of a DRAM. Further, when a salicide is formed on the surface of the word line buried in the groove, it has a function of preventing salicide from being formed in the diffusion layer in the DRAM region.
[0177]
Further, as shown in FIG. 27 (2), after forming a resist film 203 on the semiconductor substrate 11, an opening 204 is formed in the resist film 203 on a region to be a word line (gate electrode) in the DRAM region by lithography technology. To form
[0178]
Next, as shown in (3) of FIG. 28, the buffer layer 71, the element isolation region 12, and the semiconductor substrate 11 are etched (for example, continuously etched) using the resist film 203 as an etching mask, and the element isolation region is etched. A groove 14 for forming a word line (including a gate electrode) in a DRAM region is formed in 12 (field) and the semiconductor substrate 11. The depth of the groove 14 is, for example, about 100 nm to 150 nm, and the semiconductor substrate 11 is left between the well diffusion layer 13 formed previously and the bottom of the groove 14. Note that a slight difference may occur between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0179]
Since the groove 14 is formed only in the DRAM region, it is desirable that the edge portion at the bottom of the groove 14 be formed in a so-called round shape in order to avoid electric field concentration of the cell transistor. Becomes the channel length of the access transistor of the memory element, so that the side wall of the groove 14 is desirably formed as perpendicular to the surface of the semiconductor substrate 11 as possible. Note that the buffer layer 71 formed in the DRAM region is simultaneously etched when the element isolation region 12 is etched. Thereafter, the resist film 203 is removed by a normal removal technique.
[0180]
The voltage assumed in this generation is 0.5 V to 1.2 V for the standard logic area, 1.5 V to 2.5 V for the high voltage logic area, and 1.5 V to 2 V for the DRAM cell word line boost. 0.5V.
[0181]
Next, as shown in FIG. 29D, a sacrificial oxide film (not shown) is formed to a thickness of, for example, 10 nm to 20 nm on the entire exposed surface of the semiconductor substrate 11 by, for example, a thermal oxidation method.
[0182]
Next, channel doping of the access transistor in the DRAM region is performed to form a channel diffusion layer 15 between the bottom of the groove 14 and the well diffusion layer 13.
[0183]
As the channel diffusion layer 15 of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10 ¹⁸ / Cm ³ ~ 1.0 × 10 ¹⁹ / Cm ³ The region which must be formed is a portion of the semiconductor substrate 11 (11a) at the bottom of the groove 14 where the semiconductor substrate 11 is dug down. There is no. In the above-described ion implantation, the buffer layer 71 provided first serves as a mask for ion implantation on the surface of the semiconductor substrate 11 and the logic element region. Therefore, the channel diffusion layer is formed only at the bottom of the groove 14 without using a new mask. 15 can be formed. Therefore, the portion of the semiconductor substrate 11 below the diffusion layer 19 (see FIG. 30) described later has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / Cm ³ ~ 1.0 × 10 ¹⁸ / Cm ³ ) Can be formed.
[0184]
Thereafter, the sacrificial oxide film (not shown) is removed by, for example, wet etching. Thereafter, a gate insulating film 16 is formed on the inner surface of the groove 14 in the DRAM region, on the semiconductor substrate 11, and the like by an ordinary method for forming a gate oxide film.
[0185]
As shown in FIG. 30 (5), a first conductive layer 181 is coated on the surface of the gate insulating film 16 to a thickness of, for example, 5 nm to 10 nm with phosphorus-doped polysilicon so as to cover the inner wall of each groove 14 in the DRAM region. Deposit and form. Next, a second conductive layer 182 is formed by depositing non-doped polysilicon to a thickness of 50 nm to 150 nm on the surface of the first conductive layer 181 so as to fill each groove 14 in the DRAM region. This film thickness may be sufficient to fill the groove 14, and the film thickness is set to a film thickness optimized especially for forming a groove-shaped word line. Further, after forming a resist film 205 on the second conductive layer 182, the resist film 205 on the logic region is removed by a lithography technique while leaving the resist film 205 on the DRAM region.
[0186]
Then, as shown in FIG. 31 (6), the second conductive layer 182, the first conductive layer 181, the gate insulating film 16 and the buffer layer 71 on the logic element region are removed by etching using the resist film 205 as a mask. I do. In this etching, in the etching of the second conductive layer 182 and the first conductive layer 181, the buffer layer 71 serves as an etching stopper, thereby exposing the surface of the semiconductor substrate 11 in the logic element region. Further, in this etching, the etching for removing the buffer layer 71 is preferably a hydrofluoric acid-based wet etching. After that, the resist film 205 is removed.
[0187]
Thereafter, as shown in FIG. 32 (7), a sacrificial oxide film (not shown) is formed on the surface of the logic element region. Next, a resist film (not shown) having an opening on the N-channel transistor formation region in the standard voltage logic region is formed, and then ion implantation is performed on the semiconductor substrate 11 using the resist film as a mask. Is formed. At that time, channel doping can be performed as necessary. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the P-channel transistor formation region in the standard voltage logic region is formed, and then the resist film is used as a mask to ion-implant the semiconductor substrate 11. An N-well diffusion layer 61 of a channel transistor is formed. At that time, channel doping can be performed as necessary. After that, the resist film is removed.
[0188]
Next, the sacrificial oxide film is removed. Then, the gate insulating film 17 of the logic element is formed on the gate forming film 72 left on the DRAM area and on the semiconductor substrate 11 (including the element isolation area 12) in the logic element area. In this generation, the gate insulating film is generally formed separately according to the film thickness, and is separately formed using a resist process. Silicon oxide or silicon nitride is used when heat resistance is required for the gate insulating film. Further, in order to prevent penetration of boron (B) from the P-channel gate, for example, a silicon oxynitride film is used for the P-channel gate. During these processes, since the DRAM region is covered with the gate forming film 72 made of phosphorus-doped polysilicon, its surface is oxidized, but the channel region is only subjected to heat treatment and is not affected by oxidation or the like.
[0189]
As shown in FIG. 33 (8), a polysilicon layer 73 is formed of, for example, non-doped polysilicon on the semiconductor substrate 11, the element isolation region 12, and the second conductive layer 182 via the gate insulating film 17. Then, phosphorus is ion-implanted into the gate electrode formation layer in the N-channel region to form an N-type gate electrode formation layer. Since the polysilicon layer 73 is optimized for the gate electrode of the transistor in the logic region, it is preferable to form the polysilicon layer 73 to have a thickness of, for example, 70 nm to 200 nm, and preferably about 100 nm. Note that the polysilicon layer 73 in the P-channel region is not ion-implanted and is kept in a non-doped state. This eliminates the penetration of boron (B) during subsequent LDD (Lightly Doped Drain) formation and sidewall formation.
[0190]
After that, a dummy layer 74 is formed on the polysilicon layer 73. The dummy layer 74 is formed by stacking, for example, a tungsten nitride film and a tungsten film. The dummy layer 74 is a film type selected for wet etching performed to expose the polysilicon layer 73 in the logic element region later, and has no relation to the resistance itself. Any material can be used as long as it can wet-etch the silicon oxide film of the insulating film and the polysilicon layer 73 with a high selectivity. Next, a buffer layer 75 is formed on the dummy layer 74 by, for example, a silicon oxide film.
[0191]
Next, after forming a resist film on the entire surface of the buffer layer 75, the resist film is processed by lithography technology to form a resist pattern 207 for forming a gate electrode in a logic element region.
[0192]
Next, as shown in FIG. 34 (9), the buffer layer 75, the dummy layer 74, and the polysilicon layer 73 are etched using the resist pattern 207 as a mask, and a dummy gate 76 is formed in each logic element region. To form The buffer layer 75 is deposited to prevent salicide from being formed on tungsten on the metal-based electrode at the time of forming salicide later, but is not particularly necessary when there is no contamination or processing problem. . This is not necessary when a salicide structure is used for the peripheral gate electrode. After that, the resist pattern 207 is removed.
[0193]
As shown in FIG. 35 (10), after forming a resist film 209 covering the dummy gate 76 on the semiconductor substrate 11, the resist film 209 in a portion to be a DRAM region is removed by using a lithography technique, and a The resist film 209 is left.
[0194]
Thereafter, using the resist film 209 as a mask, the first conductive layer 181 and the second conductive layer 182 are etched back so that the first conductive layer 181 and the second conductive layer 182 remain inside the groove 14. In this etching, an etching condition in which the etching rate of the first conductive layer 181 is higher than that of the second conductive layer 182 is used. In other words, the first conductive layer 181 is formed using a conductive film whose etching rate is higher than that of the second conductive layer 182. As a result, the first conductive layer 181 having a higher etching rate is etched more, and a groove 183 is formed between the second conductive layer 182 on the first conductive layer 181 and the side wall of the groove 14. At the same time, a word line (partly functioning as a gate electrode) 18 including the first conductive layer 181 and the second conductive layer 182 is formed inside the groove 14. At this time, the first conductive layer 181 and the second conductive layer 182 are etched back so that the surface of the word line 18 is lower than the surface of the semiconductor substrate 11 by about 50 nm to 100 nm, so that an extraction electrode of a diffusion layer formed later is formed. Withstand pressure distance is secured. In this etch back, the gate insulating film 16 functions as an etching stop layer.
[0195]
Further, using the resist film 209 as a mask, ion implantation for forming a source / drain is performed on the semiconductor substrate 11 in the DRAM region to form a diffusion layer 19. As an example of the ion implantation conditions, phosphorus is used as an impurity to be ion-implanted, and the concentration is 1 × 10 4. ¹⁷ / Cm ³ ~ 1 × 10 ¹⁸ / Cm ³ The dose and the implantation energy are set so that Since the implantation energy penetrating the buffer layer 71 is sufficient, the implantation energy is set to, for example, 20 keV to 50 keV, and the dose is set to 1 × 10 ¹⁸ / Cm ² ~ 3 × 10 ¹⁸ / Cm ² Set to. If ions are implanted under these conditions, almost no ions are implanted into the semiconductor substrate 11 below the diffusion layer 19 in the DRAM region. Therefore, the semiconductor substrate 11 in this region is 1 × 10 ¹⁶ / Cm ³ ~ × 10 ¹⁷ / Cm ³ It is possible to set a very low density. The second conductive layer 182 is also doped with phosphorus by the above-described phosphorus ion implantation, and the first conductive layer 181 and the second conductive layer 182 have the same impurity concentration by the subsequent heat treatment. The first conductive layer 181 and the second conductive layer 182 are used only for word lines in the DRAM region and are not used for P-channel transistors. ⁺ A gate material (eg, phosphorus) can be used as a doping material.
[0196]
Therefore, this NP junction becomes a super graded junction (junction having a very gentle concentration gradient). The junction in such a state relieves the electric field at the time of reverse bias, and dramatically contributes to suppressing junction leakage current, which is about two orders of magnitude worse than usual, which occurs in a defective bit of only a ppm level in a megabit DRAM. The data retention characteristic of the defective bit dominate the chip performance of the DRAM, and is an important technique for maintaining the data retention characteristic in the future DRAM.
[0197]
For example, if the substrate concentration is 5 × 10 ¹⁶ / Cm ³ If this is the case, a data holding characteristic of 500 ms or more at 85 ° C. can be obtained, which is expected to exhibit performance comparable to the data holding characteristic of the previous data even for 4 to 5 generations. In addition, since the access transistor in the DRAM region has a channel formed in a so-called round shape in the semiconductor substrate 11, a long effective channel length can be ensured. It is also possible to stabilize the transistor characteristics of a DRAM cell with severe requirements.
[0198]
After that, the resist film 209 is removed. In the above-described ion implantation, ion implantation is performed slightly shallower in consideration of diffusion due to heat treatment for forming a gate in a DRAM region later. Since it is formed at the bottom of the groove 14 to be formed, there is no problem at all. In addition, since activation is performed by a subsequent heat treatment, there is no need to perform a heat treatment at this stage.
[0199]
As shown in FIG. 37 (11), a resist film (not shown) having an opening on the N-channel transistor formation region in the standard voltage logic region is formed, and then the resist film and the dummy gate 76 are used as a mask. Then, ions are implanted into the semiconductor substrate 11 (P-well diffusion layer 51) to form low-concentration diffusion layers 52, 52 of the N-channel transistor. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the formation region of the P-channel transistor in the standard voltage logic region is formed, and then the resist film and the dummy gate (not shown) are used as a mask to form a semiconductor substrate. Ion implantation is carried out on 11 to form a low concentration diffusion layer (not shown) of the P-channel transistor. After that, the resist film is removed.
[0200]
Further, in the same manner, a resist film (not shown) having an opening on the formation region of the P-channel transistor in the high-voltage logic region is formed, and subsequently, using the resist film and the dummy gate 76 as a mask, the semiconductor substrate 11 ( Ion implantation is performed on the N-well diffusion layer 61) to form low-concentration diffusion layers 62, 62 of the P-channel transistor. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the high-voltage logic region is formed, and then the resist film and the gate electrode (not shown) are used as a mask to form a semiconductor substrate. Ion implantation is carried out on 11 to form a low concentration diffusion layer (not shown) of the N-channel transistor. After that, the resist film is removed.
[0201]
Next, as shown in FIG. 38 (12), a protective film 78 for protecting the gate in the DRAM region is formed of, for example, a thin silicon nitride film (for example, having a thickness of 10 nm to 50 nm). The protective film 78 is formed so as to fill the trench 183, and is formed in a sidewall shape on the side wall on the word line 18 in the DRAM region later, and contributes to securing the withstand voltage of the side wall of the word line 18 during salicide formation.
[0202]
Next, a sidewall forming film 79 is formed on the entire surface. This sidewall forming film 79 is preferably formed of silicon oxide having a lower stress than silicon nitride and having good removability by wet processing. Alternatively, it can be formed using a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film. The protective film 78 serves as an etching stopper when the sidewall forming film 79 of the transistor for a peripheral circuit is later removed in the DRAM, and is formed in a sidewall shape on the sidewall on the word line 18 in the DRAM region later. During formation, it contributes to ensuring the withstand voltage of the side wall of the groove 14.
[0203]
Thereafter, as shown in (13) of FIG. 39, a resist film 211 is formed on the entire surface, the resist film 211 in the logic region is removed by, for example, lithography technology, and the resist film 211 in the DRAM region is left to protect the DRAM region. Keep it. In this state, the sidewall forming film 79 is etched back.
[0204]
As a result, the sidewall 54 is formed on the side wall of the dummy gate 76 in the standard voltage logic region with the sidewall forming film 79, and the side wall 64 is formed on the side wall of the dummy gate 76 in the high voltage logic region. You. In the above etching, the protective film 78 on the dummy gate 76 is removed by etching depending on its thickness. After that, the resist film 211 is removed.
[0205]
Next, as shown in (14) of FIG. 40, a resist film (not shown) having an opening on the n-channel transistor formation region in the standard voltage logic region is formed. Ion implantation is performed on the semiconductor substrate 11 using the wall 54 as a mask, and diffusion layers 55 and 55 of the n-channel transistor are formed so as to leave the low concentration diffusion layer 52 on the dummy gate 76 side. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the standard voltage logic region is formed, and then the resist film, a dummy gate (not shown), and a sidewall (not shown) are formed. Using a mask as a mask, ions are implanted into the semiconductor substrate 11 to form a diffusion layer (not shown) of the p-channel transistor so as to leave a low-concentration diffusion layer (not shown) on the dummy gate side. After that, the resist film is removed.
[0206]
Further, in the same manner, a resist film (not shown) having an opening on the n-channel transistor formation region in the high-voltage logic region is formed, and subsequently, the resist film and the dummy gate 76 are used as a mask to form a semiconductor substrate 11 on the semiconductor substrate 11. By performing ion implantation, diffusion layers 65 and 65 of the n-channel transistor are formed such that the low concentration diffusion layer 62 is left on the dummy gate 76 side. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the high-voltage logic region is formed, and then the resist film and the dummy gate (not shown) are used as a mask to form a semiconductor substrate. Ion implantation is performed to form a diffusion layer (not shown) of a p-channel transistor while leaving a low concentration diffusion layer (not shown) on the dummy gate side (not shown). After that, the resist film is removed.
[0207]
Next, after forming a resist film 213 on the entire surface, the resist film 213 in the DRAM region is removed by lithography technology, and patterning is performed so that the resist film 213 covers the logic region. Next, using the resist film 213 as a mask, the sidewall formation film 79 made of silicon oxide in the DRAM region is etched back by, for example, a wet process. In this etching, the protection film 78 made of silicon nitride formed immediately above the word line 18 of the DRAM formed earlier serves as an etching stopper.
[0208]
Further, using the resist film 213 as it is, the protective film 78 in the DRAM region is etched by, for example, reactive ion etching (RIE) to expose the word line 18 in the DRAM region. As a result. A sidewall insulating film 20 made of a protective film 78 is formed on the side wall of the groove 14 on the word line 18. This sidewall insulating film 20 has a function of protecting the side wall. In the reactive ion etching, it is important that the diffusion layer 19 in the DRAM region is not exposed, that is, the buffer layer 71 is left on the diffusion layer 19. After that, the resist film 213 is removed.
[0209]
Further, as shown in FIG. 41 (15), silicide layers 57, 67, 21 are formed on the respective diffusion layers 55, 65 in the logic region and the word lines 18 in the DRAM region by using a normal silicidation technique. Are selectively formed. At this time, since the buffer layer 75 made of a silicon oxide film is formed on the top of the dummy gate 76, no silicide layer is formed. In this way, the silicide layers 57, 67, 21 are selectively formed on the respective diffusion layers 55, 65 in the logic area where low resistance needs to be realized, and on the word lines 18 in the DRAM area. As this silicide layer, for example, cobalt silicide (CoSi ₂ ), Titanium silicide (TiSi ₂ ) Nickel silicide (NiSi ₂ ) Etc. can be used.
[0210]
Thereafter, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 80 is effective for suppressing the junction leak at the salicide formation portion, but need not be formed if unnecessary. Note that, as described above, a silicide layer may be formed also on the gate electrode of the transistor in the peripheral circuit portion to form a salicide structure to reduce the resistance of the gate electrode.
[0211]
Next, as shown in (16) of FIG. 42, after forming a first insulating film (insulating film) 22 on the entire surface, the surface of the first insulating film 22 is flattened by CMP. The method of planarizing the surface of the first insulating film 22 is not limited to CMP as long as planarization can be realized, and for example, an etch-back method may be used. Then, after forming a resist film 215 on the first insulating film 22, a connection hole pattern 216 for contacting a diffusion layer in the DRAM region is formed in the resist film 215 by lithography.
[0212]
Next, etching is performed using the resist film 215 as an etching mask, and as shown in (17) of FIG. 43, penetrates through the first insulating film 22, the buffer layer 71, etc., and reaches the diffusion layer 19 in the DRAM region. The connection hole 23 is formed. At this time, since the word line (gate electrode) 18 in the DRAM region is disposed below the surface of the semiconductor substrate 11 with respect to the diffusion layer 19 to be contacted, there is no need to use a special technique such as a self-aligned contact. Further, it is desirable to form the connection hole 23 as large as possible so that the entire surface of the diffusion layer 19 of the DRAM can contact the extraction electrode. Thereby, the contact resistance is reduced.
[0213]
In the drawings, a state in which the alignment is slightly misaligned is intentionally described. However, unless excessive over-etching is performed at the time of opening the connection hole, the physical characteristics of the word line extraction electrode formed in the connection hole 23 in a later step will be described. It is possible to secure a long distance. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.
[0214]
Next, an extraction electrode forming film 81 is formed on the first insulating film 22 so as to fill the connection holes 23. The extraction electrode forming film 81 is formed of, for example, phosphorus-doped polysilicon. For the extraction electrode forming film 81 for extracting the diffusion layer, it is desirable that phosphorus-doped polysilicon be selected in consideration of the reduction of junction leakage in the DRAM region as in the related art. At this stage, heat treatment for activation is unnecessary.
[0215]
Thereafter, as shown in (18) of FIG. 44, the excessive extraction electrode forming film 81 (phosphorus-doped polysilicon) on the first insulating film 22 is removed by, for example, CMP, and the diffusion layer is formed in the connection hole 23. The extraction electrode 24 made of the extraction electrode forming film 81 connected to the substrate 19 is formed, and the first insulating film 22 is polished to flatten its surface. At this time, the buffer layer 75 (see (9) in FIG. 34) of the dummy gate 76 in each logic region is removed to expose the upper portion of the dummy layer 74 of the dummy gate 76.
[0216]
Next, the dummy layer 74 (see (18) in FIG. 44) of the dummy gate 76 in the logic region is removed. As a result, a groove 83 is formed on the polysilicon layer 73 of each of the dummy gates 76, as shown in FIG. This etching is preferably performed by, for example, wet etching with sulfuric acid / hydrogen peroxide or hydrofluoric / nitric acid.
[0217]
Next, after forming a resist film 217 on the entire surface on the first insulating film 22 side, an opening 218 is formed by lithography on the formation region of the p-channel transistor in the logic element region. Subsequently, using the resist film 217 as a mask, for example, boron is ion-implanted as a p-type impurity into the polysilicon layer 73 made of non-doped polysilicon.
[0218]
After that, the resist film 217 is removed. Next, heat treatment is performed. By this heat treatment, the extraction electrode 24 made of polysilicon in the DRAM region and the polysilicon layer 73 doped with impurities of the gate electrode in the logic element region are activated. In this heat treatment, RTA (Rapid Thermal Annealing) at 900 ° C. for about 10 seconds is sufficient, but thermal annealing using an ordinary furnace may be performed. In the subsequent steps, a high-temperature heat step is not performed, so that the so-called “penetration” in which boron diffuses from the gate electrode in the logic element region is minimized.
[0219]
Then, as shown in (20) of FIG. 46, a metal-based gate electrode formation film 84 is formed so as to fill the inside of the groove 83. The metal-based gate electrode forming film 84 is generally formed as a laminated film of a metal film (for example, a tungsten film) 84W / an adhesion film (for example, a titanium nitride film 84T). Alternatively, an electrode of tungsten / tungsten nitride, copper / titanium nitride, ruthenium, or the like can be formed.
[0220]
The surplus metal-based gate electrode forming film 84 on the first insulating film 22 is removed again by CMP.
[0221]
As a result, as shown in (21) of FIG. 47, a metal gate electrode 84G made of the metal gate electrode forming film 84 left in the groove 83 is formed, and the metal gate electrode 84G and the polysilicon layer 73 are formed. The gate electrodes 51 and 61 are formed, and the surface of the first insulating film 22 is planarized. At this time, the upper portion of the extraction electrode 24 for extracting the diffusion layer in the DRAM region is also polished, but there is no problem.
[0222]
Next, an etching stop layer 25 covering the extraction electrode 24 in the DRAM region and the gate electrodes 51 and 61 in the logic element region is formed on the entire surface of the first insulating film 22 with, for example, a silicon oxide film.
[0223]
Thereafter, as shown in (22) of FIG. 48, after forming a resist film (not shown) on the etching stop layer 25, the resist film is formed on the resist film by a lithography technique. A connection hole pattern (not shown) for a diffusion layer extraction electrode is formed. Subsequently, by using the resist film as an etching mask, the silicide layer 21 on the word line 18 in the DRAM region penetrating through the etching stop layer 25, the first insulating film 22 and the cap insulating film 80, and the The connection holes 26, 58, 68 reaching the silicide layers 57, 67 of the transistor are formed.
[0224]
After that, the resist film is removed. Next, an adhesion layer 85 made of a titanium nitride film is formed on the inner surface of each of the connection holes 26, 58, and 68 by a normal tungsten plug forming technique, and then a tungsten film 86 is formed so as to fill the connection holes 26, 58, and 68. To form After that, excess portions of the tungsten film 86 and the adhesion layer 85 on the etching stop layer 25 are removed by CMP, and extraction electrodes 27, 59, and 69 are formed inside the connection holes 26, 58, and 68.
[0225]
Next, a second insulating film 31 is formed, for example, by depositing a silicon oxide film to a thickness of 50 to 150 nm on the entire surface of the etching stop layer 25 so as to cover the extraction electrodes 27, 59, and 69.
[0226]
Then, after forming a resist film (not shown) on the second insulating film 31, an opening (not shown) is formed at a position where a bit contact is to be formed in the resist film by lithography. By etching using the resist film as a mask, a bit contact hole 32 and a local wiring contact hole 33 are formed in the second insulating film 31 and the etching stopper layer 25 as shown in FIG.
[0227]
Next, a wiring metal layer for forming the bit line 34 and the local wiring 35 is formed. In this wiring metal layer, first, an adhesion layer 36 formed by stacking a titanium film and a titanium nitride film is formed on the inner surfaces of the bit contact holes 32 and the local wiring contact holes 33 and on the second insulating film 31. Further, a tungsten film 37 serving as a main material of the metal wiring is formed on the adhesion layer 36 so as to fill the bit contact hole 32 and the local wiring contact hole 33. Further, a cap layer 38 is formed on the tungsten film 37 by, for example, a silicon nitride film.
[0228]
Thereafter, the cap layer 38, the tungsten film 37, and the adhesion layer 36 are patterned by the usual lithography and etching techniques to form a bit line 34 connected to the bit contact take-out electrode 24 through the bit contact hole 32, and a local wiring contact. The local wiring 35 connected to the extraction electrode 59 through the hole 33 is formed. Therefore, the cap layer 38 is formed on the bit line 34 and the local wiring 35.
[0229]
Thereafter, an etching stopper layer 41 covering the bit line 34, the local wiring 35, and the like is formed on the second insulating film 31 with an ALD silicon nitride film to a thickness of, for example, 30 nm to 50 nm.
[0230]
Next, as shown in (24) of FIG. 50, a third insulating film 42 is formed on the etching stopper layer 41. Then, the surface of the third insulating film 42 is flattened using, for example, CMP. Next, after a resist film 219 is formed on the third insulating film 42, an opening pattern 220 for opening a storage node contact is formed by lithography. This opening pattern 220 can be formed larger than the diameter of the connection hole where the actual storage node contact is formed.
[0231]
Then, using the resist film 219 as an etching mask, as shown in (25) of FIG. 51, the storage node from the third insulating film 42 to the etching stop layer 25 is etched to form the contact extraction electrode 24, A connection hole 43 for forming a storage node contact reaching 24 is formed. In this etching, in addition to the resist film 219 (see (24) in FIG. 50), the cap layer 38 and the etching stopper layer 41 serve as an etching mask. Although part of the etching stopper layer 41 is etched, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a thickness enough to ensure the withstand voltage between the bit line and the storage node contact. Thereafter, the resist film 219 (see (24) in FIG. 50) is removed.
[0232]
Next, as shown in (26) of FIG. 52, a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is formed, for example, by forming a material layer by depositing tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium oxide, or the like on the third insulating film 42 so as to fill the connection hole 43. The surplus material layer on the third insulating film 42 is formed by the material layer left in the connection hole 43 by removing the material layer by, for example, CMP.
[0233]
Next, a fourth insulating film 45 covering the storage node contact 44 and the like is formed on the third insulating film 42. Next, a concave portion 46 in which a capacitor is formed is formed in the fourth insulating film 45 so that the upper surface of the storage node contact 44 is exposed at the bottom.
[0234]
Thereafter, a capacitor 91 having an MIM (Metal / Insulator / Metal) structure that does not require heat treatment is formed in the concave portion 46. The MIM-structured capacitor 91 is expected to be indispensable in a DRAM of 0.1 μm or less. At present, as an example, the electrodes 92 and 94 are made of ruthenium (Ru) or ruthenium oxide (RuO) -based material, and The film 93 has BST (BaTiO ₃ And SrTiO ₃ And a mixed crystal) film.
[0235]
Next, a fifth insulating film 47 is formed on the fourth insulating film 45 so as to cover the capacitor 91 having the MIM structure. Thereafter, the surface of the fifth insulating film 47 is flattened by CMP. Next, on the fifth insulating film 47 or the second insulating film 31, a capacitor lead electrode, a word line lead electrode, a local wiring lead electrode, a diffusion layer lead electrode in a logic region, a gate lead electrode in a logic region, and the like are formed. Connection holes 111, 112, 113, 114 to 116, 117, etc. are formed.
[0236]
Further, the capacitor extraction electrode 121, the word line extraction electrode 122, the local wiring extraction electrode 123, the diffusion layer extraction electrodes 124 to 126 of the logic area, and the gate of the logic area are formed in the connection holes 111, 112, 113, 114 to 116, 117 and the like. An extraction electrode 127 is formed. Further, a sixth insulating film 48 is formed on the fifth insulating film 47. Next, wiring grooves 131 to 136 reaching the electrodes 121 to 127 and the like are formed in the sixth insulating film 48, and wirings 141 to 146 are formed in the wiring grooves 131 to 136. The wirings 141 to 146 are made of, for example, copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 121 to 127 and the wirings 141 to 146 are formed with a well-known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.
[0237]
In the second method of manufacturing a semiconductor device, the groove 183 is formed on the side of the groove 14 above the word line (gate electrode) 18, and the side wall of the groove 14 on the word line (gate electrode) 18 is filled so as to fill the groove 183. Since the sidewall insulating film 20 is formed on the substrate, the silicide layer 21 may be formed on the word line (gate electrode) 18. Since the distance between the silicide layer 21 and the gate insulating film 16 is sufficiently ensured by the portion formed in the groove 183 of the sidewall insulating film 20, a semiconductor device in which the deterioration of the gate withstand voltage is suppressed is obtained.
[0238]
In the second method for manufacturing a semiconductor device, since the buffer layer 71 is formed, when the impurity for forming the channel diffusion layer 15 is introduced into the semiconductor substrate 11 at the bottom of the groove 14, the buffer layer 71 is formed. Is used as a mask, an impurity is selectively introduced into the semiconductor substrate 11 at the bottom of the groove 14, and the channel diffusion layer 15 is formed.
[0239]
As described above, since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the lower part of the groove 14 and the well diffusion layer 13, the impurity concentration in the region between the groove 144 and the well diffusion layer 13 is reduced. It becomes higher than the impurity concentration of the semiconductor substrate 11. Further, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer 19 serving as the source / drain is weakened. For this reason, it is possible to suppress the junction leak on the order of ppm, thereby forming a semiconductor device having extremely good data retention characteristics.
[0240]
In addition, the semiconductor is overlapped with the word line 18 via the first insulating film 22 on the word line 8 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16. Since the extraction electrode connected to the diffusion layer 19 formed on the surface of the substrate 11 is formed, the first insulating film 22 on the word line 18 can have a sufficient thickness of 20 nm to 30 nm or more. . Thereby, a withstand voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is ensured. Therefore, since the entire surface of the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.
[0241]
Further, since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, and the problem of delay is avoided. Further, since the silicide layers 57 and 67 are formed on the diffusion layers 55 and 65 of the logic element, the contact resistance to the diffusion layers 55 and 65 is reduced.
[0242]
Further, since a diffusion layer 19 is formed on the front surface side of the semiconductor substrate 11 and a word line 18 is buried in a groove 14 formed in the semiconductor substrate 11 via a gate insulating film 16, a channel is formed. Are formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which is formed. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect are stabilized by applying a back bias.
[0243]
Further, since the diffusion layer 19 in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate 11 under the diffusion layer 19 does not have to be so high as required for the cell transistor. As a result, the electric field at the junction is alleviated, and the performance of the data retention characteristic, which becomes more severe as the cell size of the memory element is reduced, is maintained.
[0244]
Further, by using a laminated structure of the polysilicon layer 73 and the dummy layer 74 for the dummy gate 76 formed in the logic element region, the dummy layer 74 is removed after forming the extraction electrode of the diffusion layer in the memory element region, and the dummy layer 74 is removed. It becomes possible to dope the polysilicon layer 73 of the gate 76 with an impurity. Thereafter, a heat treatment is performed to form the metal gate electrode 84G with the metal gate electrode forming film 84, so that the problem of boron penetration in the p-channel gate electrode due to the heat treatment can be minimized.
[0245]
The technology used for the DRAM area can be applied to the manufacture of memory chips for general-purpose DRAMs.
[0246]
【The invention's effect】
As described above, according to the first and second semiconductor devices and the method of manufacturing the same of the present invention, the groove is formed on the side wall of the groove above the word line formed in the groove formed in the semiconductor substrate. Since the sidewall insulating film is formed on the side wall of the trench on the word line (including the gate electrode) so as to fill the trench, the silicide layer on the upper surface of the word line is formed by the portion formed in the trench of the sidewall insulating film. The physical distance between the gate insulating film and the gate insulating film is sufficiently ensured. For this reason, it is possible to prevent the withstand voltage of the gate insulating film from deteriorating without giving a side effect to the device characteristics. Since the silicide layer is formed on the word line, the resistance of the word line can be reduced, and the problem of the word line delay, which is a problem in miniaturization, can be avoided.
[0247]
Further, a diffusion layer is formed on the surface of the semiconductor substrate, and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film. Formed around the semiconductor substrate. Therefore, since the effective channel length of the cell transistor in the memory element region is sufficiently ensured, the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect by applying a back bias are stabilized.
[0248]
On a word line embedded in a groove formed in a semiconductor substrate, an extraction electrode connected to a diffusion layer formed on the surface of the semiconductor substrate is formed in a state overlapping with the word line via a sidewall, an insulating film, and the like. Therefore, withstand voltage between the diffusion layer and the extraction electrode can be ensured by the insulating film or the like on the word line. Therefore, the entire surface of the diffusion layer in the memory element region at a position higher than the word line can be used for the contact, and the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design can be realized, and the contact resistance can be reduced.
[0249]
Therefore, in the upper projection design, the extraction electrode of the diffusion layer in the memory element region and the word line (gate electrode) can overlap, and the cell can be miniaturized. In other words, there is no need for a distance between the word line and the extraction electrode in the direction of the substrate surface for ensuring the withstand voltage. Therefore, since the entire surface of the diffusion layer of the memory element can be used for the contact, the effective area can be used effectively, the lowest resistance value achievable in the cell design can be realized, and the contact resistance can be reduced.
[0250]
In addition, since the diffusion layer in the memory element region is formed so that its concentration decreases in the depth direction, it is not necessary to increase the substrate concentration below the diffusion layer as required for the cell transistor. For this reason, the electric field at the junction of the diffusion layer can be reduced, and the performance of data retention characteristics, which becomes more and more severe due to the reduction in the cell size of the memory element region, can be maintained.
[0251]
Further, according to the second semiconductor device and the method for manufacturing the same, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer can be reduced.
[0252]
Further, a logic transistor having a so-called replacement gate electrode for realizing a high driving force transistor in a logic region and a memory element can be realized as one chip. As a result, the gate of the logic region does not need to be treated for heat treatment, a high dielectric constant material can be used for the gate insulating film, and the gate electrode can be formed with a polymetal structure.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing an example of an embodiment of a semiconductor device of the present invention.
FIG. 2 is an enlarged schematic view of a portion A in FIG.
FIG. 3 is a schematic cross-sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic sectional view (2) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a schematic sectional view (3) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a schematic sectional view (4) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 7 is a schematic sectional view (5) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
8 is an enlarged schematic view of a portion B in FIG. 7;
FIG. 9 is a schematic sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 10 is an enlarged schematic view of a portion C in FIG. 9;
FIG. 11 is a schematic sectional view (7) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 12 is a schematic cross-sectional view (8) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 13 is an enlarged schematic view of a portion D in FIG.
FIG. 14 is a schematic cross-sectional view (9) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 15 is a schematic sectional view (10) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 16 is a schematic sectional view (11) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 17 is a schematic sectional view (12) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 18 is a schematic sectional view (13) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 19 is a schematic sectional view (14) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 20 is a schematic sectional view (15) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 21 is a schematic sectional view (16) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 22 is a schematic sectional view (17) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 23 is a schematic sectional view (18) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 24 is a schematic sectional view showing an example of an embodiment of a semiconductor device of the present invention.
25 is an enlarged schematic view of a portion E in FIG. 24.
FIG. 26 is a schematic cross-sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 27 is a schematic sectional view (2) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 28 is a schematic sectional view (3) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 29 is a schematic cross-sectional view (4) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 30 is a schematic sectional view (5) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 31 is a schematic sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 32 is a schematic sectional view (7) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 33 is a schematic cross-sectional view (8) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 34 is a schematic cross-sectional view (9) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 35 is a schematic sectional view (10) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 36 is an enlarged schematic view of a portion F in FIG. 35;
FIG. 37 is a schematic sectional view (11) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 38 is a schematic sectional view (12) showing an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention;
FIG. 39 is a schematic sectional view (13) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 40 is a schematic cross-sectional view (14) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 41 is a schematic structural sectional view (15) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
FIG. 42 is a schematic sectional view (16) showing an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention;
FIG. 43 is a schematic sectional view (17) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
FIG. 44 is a schematic sectional view (18) showing an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention;
FIG. 45 is a schematic sectional view (19) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 46 is a schematic sectional view (20) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 47 is a schematic sectional view (21) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 48 is a schematic sectional view (22) showing an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention;
FIG. 49 is a schematic sectional view (23) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
FIG. 50 is a schematic sectional view (24) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
FIG. 51 is a schematic sectional view (25) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
FIG. 52 is a schematic sectional view (26) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 14 ... Groove, 15 ... Channel diffusion layer, 16 ... Gate insulating film, 18 ... Word line (including gate electrode), 19 ... Diffusion layer, 20 ... Side wall insulating film, 21 ... Silicide layer,

Claims (8)

A semiconductor substrate;
A groove formed in the semiconductor substrate,
A channel diffusion layer formed on the semiconductor substrate at the bottom of the groove;
A gate electrode embedded in the groove via a gate insulating film;
A groove formed on the side wall of the groove above the gate electrode;
A sidewall insulating film embedded in the trench and formed on a sidewall of the trench on the gate electrode;
A diffusion layer formed on the semiconductor substrate surface side of the groove side wall;
And a silicide layer formed on the gate electrode at a position higher than the bottom of the sidewall insulating film. A well diffusion layer is formed in the semiconductor substrate separated by an element isolation region formed in the semiconductor substrate;
The trench is formed in the semiconductor substrate and the element isolation region while leaving a part of the semiconductor substrate on the well diffusion layer,
2. The semiconductor device according to claim 1, wherein the channel diffusion layer is formed on the semiconductor substrate between a bottom of the groove and the well diffusion layer. Forming a groove at a position where a word line is formed on a semiconductor substrate;
Forming a channel diffusion layer in the semiconductor substrate at the bottom of the groove;
Forming a gate insulating film in the trench and on the semiconductor substrate;
Forming a first conductive layer on the semiconductor substrate including the inner wall of the groove;
Forming a second conductive layer filling the groove on the semiconductor substrate via the first conductive layer;
Removing the first conductive layer and the second conductive layer over the groove and the semiconductor substrate so that the first conductive layer inside the groove is lower than the second conductive layer; Forming a gate electrode between the first conductive layer and the second conductive layer left inside, and forming a groove between the groove side wall and the second conductive layer;
Forming a diffusion layer on the semiconductor substrate above the trench sidewalls;
Forming a sidewall insulating film on the side wall of the groove on the gate electrode while filling the inside of the groove;
Forming a silicide layer on the gate electrode. 4. The method according to claim 3, wherein the first conductive layer is formed of a film having a higher etching rate than the second conductive layer. Forming a well diffusion layer in the semiconductor substrate separated by an element isolation region formed in the semiconductor substrate;
The trench is formed in the semiconductor substrate and the element isolation region while leaving a part of the semiconductor substrate on the well diffusion layer,
4. The method according to claim 3, wherein the channel diffusion layer is formed on the semiconductor substrate between a bottom of the groove and the well diffusion layer. In a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate,
The transistor of the memory element,
An element isolation region formed in the semiconductor substrate,
A well diffusion layer formed in the semiconductor substrate separated by the element isolation region;
A groove formed in the semiconductor substrate and the element isolation region and formed on the well diffusion layer while leaving a part of the semiconductor substrate;
A channel diffusion layer formed in the semiconductor substrate between the bottom of the groove and the well diffusion layer;
A word line embedded in the trench via a gate insulating film;
A groove formed on the side wall of the groove above the word line;
A sidewall insulating film formed on a side wall of the trench on the word line including in the trench,
A diffusion layer formed on the semiconductor substrate surface side of the groove side wall;
A silicide layer formed above the word line at a position higher than the bottom of the sidewall insulating film;
An extraction electrode connected to the diffusion layer in a state of overlapping with the word line via an insulating film on the word line,
The transistor of the logic element,
A gate electrode formed on the semiconductor substrate, having a polymetal structure in which a polysilicon electrode and a metal-based electrode are stacked;
A diffusion layer formed on the semiconductor substrate surface side on both sides of the gate electrode;
And a silicide layer formed on the diffusion layer. In a method of manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate,
Forming a buffer layer on the semiconductor substrate after forming an element isolation region on the semiconductor substrate;
Forming a well diffusion layer in the semiconductor substrate in the memory element region separated by the element isolation region;
Forming a groove at a position where a word line of the buffer layer, the semiconductor substrate, and the element isolation region is formed, with a part of the semiconductor substrate remaining on the well diffusion layer;
Forming a channel diffusion layer in the semiconductor substrate between the bottom of the groove and the well diffusion layer;
Forming a gate insulating film in the trench and on the semiconductor substrate;
Forming a first conductive layer on the semiconductor substrate including an inner wall of the groove in a memory element region;
Forming a second conductive layer filling the groove on the semiconductor substrate via the first conductive layer;
Forming a well diffusion layer on the semiconductor substrate in the logic element region separated by the element isolation region;
Forming a polysilicon layer for filling the trench and a dummy layer made of a material having an etching selectivity for the polysilicon layer on the semiconductor substrate,
Processing the polysilicon layer and the dummy layer, forming a dummy gate with the polysilicon layer and the dummy layer via the gate insulating film on the semiconductor substrate in a logic element region;
Removing the first conductive layer and the second conductive layer above the groove and the semiconductor substrate so that the first conductive layer inside the groove is lower than the second conductive layer; Forming a word line with the first conductive layer and the second conductive layer left inside, and forming a groove between the groove side wall and the second conductive layer;
Forming a diffusion layer on the semiconductor substrate above the trench sidewalls;
Forming a low concentration diffusion layer of a logic element on the surface of the semiconductor substrate on both sides of the dummy gate;
Forming a sidewall insulating film on a side wall of the dummy gate;
Forming a diffusion layer on the dummy gate side on the semiconductor substrate on both sides of the dummy gate via the low concentration diffusion layer;
Forming a sidewall insulating film on the side wall of the groove on the word line while filling the inside of the groove;
Forming a silicide layer on the word line and on the diffusion layer of the logic element;
Forming an insulating film so as to fill the upper portion of the groove and cover the dummy gate;
Forming a connection hole on the word line reaching the diffusion layer formed in the memory element region in a state of overlapping with the word line via the insulating film;
Forming an extraction electrode in the connection hole;
Forming a gate groove by flattening the insulating film surface and exposing the upper part of the dummy gate, further removing the dummy layer to expose the polysilicon layer,
Doping the polysilicon layer of the dummy gate with an impurity,
Performing a heat treatment to activate the extraction electrode and the polysilicon layer;
Forming a metal-based electrode in the gate groove. 8. The method according to claim 7, wherein the first conductive layer is formed of a conductive film having a higher etching rate than the second conductive layer.

Images