JP5014547B2 - Method for forming electrode of electronic switching element or transistor on substrate - Google Patents

Description

[0001]
The present invention relates to solution processed devices and methods of forming such devices.
[0002]
Semiconducting shared polymer thin-film transistors (TFTs) have recently been developed for low-cost, logic (C. Dury, et. Al., APL73, 108 (1998)) and high-resolution active matrix display photoelectric integrated on plastic substrates The application of integrated circuits and pixel transistor switches (H. Sirringhaus, et al., Science 280, 1741 (1998), A. Dodabalapur, et al., Appl. Phys. Lett. 73, 142 (1998)) It came to be held. High performance TFTs have been demonstrated in test devices with polymer semiconductor and inorganic metal electrodes and a gate dielectric layer. The best 0.1cm that can match the performance of amorphous silicon TFT²/ Vs and 10⁶-10⁸The charge carrier mobility of the on-off current ratio was reached (H. Sirringhous, et al., Advance in Solid State Physics 39, 101 (1999)).
[0003]
A thin device characteristic film of a conjugated polymer semiconductor can be formed on a substrate by coating a polymer solution in an organic solvent. Therefore, this technique is ideally suited for solution processing that is inexpensive, has a wide area, and does not cause a chemical reaction to a flexible plastic substrate. In order to take full advantage of the potential costs and ease of processing, it is desirable that all components of the device, including the semiconductive layer, dielectric layer, and conductive electrodes and interconnects, be deposited from solution.
[0004]
In order to produce all-polymer TFT elements and circuits, the following major problems must be solved.
-Consistency of the multilayer structure: during solution application of the next semiconductive layer, insulating layer and / or conductive layer, the underlying layer is dissolved or dissolved by the solvent used for the deposition of the next layer Should not be inflated. If the solvent is incorporated into the underlying layer, expansion will generally occur that will cause degradation of the properties of that layer.
-High resolution patterning of electrodes: The conductor layer needs to be patterned to form TFT channels with well-defined internal connections and channel lengths L ≦ 10 μm.
In order to manufacture a TFT circuit, the vertical internal connection region (via hole) needs to be formed so as to electrically connect a plurality of electrodes in a plurality of layers of different elements.
[0005]
WO 99/10939 A2 demonstrates a method for producing an all-polymer TFT by converting a solution-treated layer into an insoluble state prior to depositing the next layer of the device. This solves the problem of dissolution and expansion of the underlying layer. However, this problem limits the choice of semiconductive materials that can be used to small and in some ways undesirable types of precursor polymers. Further, since the cross-linking of the dielectric gate insulating layer makes it difficult to manufacture a via hole penetrating the dielectric layer, a technique such as mechanical punching is used (WO 99/10939 A1).
[0006]
  According to one aspect of the present invention, a method is provided for forming an electronic device including a conductive material or a semiconductive material in a plurality of regions on a substrate, and the operation of the device is performed from a first region to a second region. And the method forms a mixture by mixing the material with a liquid, the first zone of the first region of the substrate and the second region of the second region of the substrate. Two zones, the first zone being repellent to the mixture which is larger than the second zone.liquidAnd forming a confinement structure on the substrate that includes a first zone and a third zone of the third region of the substrate separated from the second region by the first region, This first zone is repellent to this mixture which is larger than this third zone.liquidAnd depositing the material on the substrate by applying the mixture onto the substrate, whereby the deposited material is the first and second of the device. And the relative repellent properties of this first zone.liquidThis first region of the substrate is separated from the region that is electrically isolated in its plane by gender and resists current across the first zone between the separated regions of the deposited material. The relative repellency of this first zone so that there is noliquidCan be limited by gender.
[0007]
  In accordance with another aspect of the present invention, a method is provided for forming an electronic switching element on a substrate that includes a conductive material or semi-conductive material in a plurality of regions, the method mixing the material and a liquid. A first zone of the first region of the substrate and a second zone of the second region of the substrate, wherein the first zone is more than the second zone Large repellent to this mixtureliquidAnd forming a confinement structure on the substrate that includes a first zone and a third zone of the third region of the substrate separated from the second region by the first region, This first zone is repellent to this mixture which is larger than this third zone.liquidAnd depositing the material on the substrate by applying the mixture onto the substrate, whereby the deposited material is in the first and third zones. Relative repellentliquidIt can be restricted to this second zone by gender.
[0008]
The width of the first region between the second and third regions is suitably less than 20 μm, preferably less than 10 μm. The material formed in the isolated regions moderately forms the source and drain electrodes of the transistor.
[0009]
The method suitably includes depositing other materials in the space between the spaced regions. Other materials deposited in the spaces between the separation regions may form the transistor channel. The first material may be conductive and the other material may be semiconductive. This other material may be a polymer material. Other materials may be deposited from solution, a liquid solution that is not substantially water repellent by the first zone.
[0010]
The width of the second zone is reasonably less than 20 μm. The width of this second zone is reasonably less than 10 μm. The material deposited in the second zone is reasonably conductive. Such materials moderately form internal connections.
[0011]
The width of the overlapping region between the gate electrode of the transistor and each of the source and drain electrodes is preferably less than 20 μm.
[0012]
The width of the overlapping region between the gate electrode of the transistor and each of the source and drain electrodes is preferably smaller than 10 μm.
[0013]
The surface of the substrate may be provided by a self-assembled monolayer and at least one of the first and second zones may be defined by the patterning of the self-assembled monolayer.
[0014]
The step of patterning the self-assembled monolayer may be performed by exposure to light through a shadow mask.
[0015]
The step of patterning the self-assembled monolayer may be performed by contacting the substrate with a soft stamp.
[0016]
The first and second zones may be formed on the exposed surface of a layer deposited on the planar structural member.
[0017]
The contact angle of the mixture in the first region is reasonably greater than the contact angle of the mixture in the second region by 20 °, 40 ° or 80 °.
[0018]
A method according to any of the preceding claims, wherein the surface of the substrate is provided by a self-assembled monolayer and at least one of the first and second zones is defined by patterning of the self-assembled monolayer.
[0019]
The step of patterning the self-assembled monolayer is suitably performed by exposure to light through a shadow mask.
[0020]
The step of patterning the self-assembled monolayer is performed by contacting the substrate with a soft stamp.
[0021]
A method according to any of the preceding claims, wherein the surface of the substrate is provided by a nonpolar material and at least one of the first and second zones is defined by a surface treatment of a nonpolar polymer.
[0022]
This non-polar material may be polyimide.
[0023]
The method may include mechanically rubbing or otherwise surface treating the polyimide to facilitate polyimide molecular alignment.
[0024]
The method may include the step of optically treating the polyimide to promote molecular alignment of the polyimide.
[0025]
The surface treatment may be etching. The surface treatment may be a plasma treatment. This plasma is preferably a carbon tetrafluoride and / or oxygen plasma.
[0026]
This surface treatment may include exposure to ultraviolet light.
[0027]
Preferably one of the zones is a second zone.
[0028]
The first zone may induce or be capable of inducing a semiconductive material or an ordered molecular structure of the conductive material.
[0029]
The first zone most preferably can induce alignment of the polymer chain in the conducting polymer or semiconducting polymer.
[0030]
The first zone can reasonably induce alignment of a chain of polymeric material deposited over the first zone.
[0031]
The alignment is preferably in the direction extending between the second and third zones.
[0032]
Preferably, the chain is a chain of other materials.
[0033]
Preferably, the conductive polymer or semiconductive polymer is deposited by droplet deposition.
[0034]
Preferably, the conductive polymer or semiconductive polymer is deposited by ink jet printing.
[0035]
Preferably, at least one width of the zone is smaller than the droplet diameter formed by the ink jet printing step.
[0036]
Preferably, the boundary between the first and second zones is optically different and the method optically detects the boundary between the first and second zones and ink jet printing in response to this detection Positioning the element relative to the substrate.
[0037]
The first material may be a polymer, preferably a conjugated polymer. The first material may be an inorganic particulate material that can be suspended in a liquid.
[0038]
According to another aspect of the invention, there is provided a logic circuit, display element or memory element formed by the method of any of the preceding claims.
[0039]
According to another aspect of the invention, there is provided a logic circuit, display element or memory element comprising an active matrix array of a plurality of transistors formed by the method of any of the preceding claims.
[0040]
The present invention will now be described by way of example with reference to the accompanying drawings.
[0041]
The preferred fabrication method shown here enables the fabrication of all organic solution treated thin film transistors in which no layer is converted or crosslinked to an insoluble form. Each layer of such an element may remain in a form that can be dissolved by the solvent in the solution from which the layer is deposited. As will be described in detail below, this facilitates the manufacture of via holes that penetrate the dielectric insulating layer by local deposition of solvent.
[0042]
Such an element may comprise, for example, one or more of the following components.
-Patterned conductive source-drain and gate electrodes and interconnects.
-0.01 cm²Semiconductive layer with charge carrier mobility greater than / Vs and 10^FourGreater high on-off current switching ratio.
A thin gate insulating layer.
A diffusion barrier layer that protects the semiconducting and insulating layers from unintentional doping due to impurity and ion diffusion;
-A surface improvement layer that enables high resolution patterning of the gate electrode by printing technology.
A via hole for internal connection through the dielectric layer.
[0043]
However, it will be appreciated that the methods described herein are not limited to the fabrication of devices having all the features described above.
[0044]
The manufacture of the element of the first embodiment will be described with reference to FIG. The device of FIG. 1 is a thin film field effect transistor (TFT) configured to have a top gate structure.
[0045]
On a cleaned 7059 glass substrate 1 by inkjet printing an aqueous solution consisting of the conductive polymer polyethylene dioxythiophene / polystyrosulphonate (PEDOT (0.5 weight percent) / PSS (0.8 weight percent)). The source-drain electrodes 2, 3 and the internal connection lines between the electrodes and the contact pads (not shown) are deposited. Other solvents such as methanol, ethanol, isopropanol, or acetone may be added to affect the surface tension, viscosity, and wettability of the ink. PEDOT / PSS is commercially available from Bayer (available as "Baytron P"). Inkjet (IJP) printers are of the piezoelectric type. This is equipped with a precision two-dimensional conversion stage and a microscope stage, which makes it possible to align a plurality of subsequently printed patterns with each other. Inkjet print (IJP) heads are driven by voltage pulses. Suitable drive conditions for ejecting droplets with a typical solid content of 0.4 ng per drop are achieved with a pulse height of 20V, a rise time of 10 μs, and a fall time of 10 μs. After drying on a glass substrate, the droplets form PEDOT dots with a typical diameter of 50 μm and a typical thickness of 500 mm.
[0046]
Inkjet printing (IJP) of source-drain electrodes is performed in air. The sample is then transported into an inert atmosphere glove box system. The substrate is then spin dried in an organic solvent that is later used to deposit the active semiconductive layer, such as mixed xylene in the case of a polyfluorene polymer. The substrate is then annealed at 200 ° C. for 20 minutes in an inert nitrogen atmosphere to remove residual solvent and other volatile materials in the PEDOT / PSS electrode. Then, a thick film of the active semiconductive polymer 4 having a thickness of 200 to 1000 mm is deposited by spin coating. Various semiconducting polymers such as (regioregular) poly-3-hexylthiophene (P3HT), polyfluorene copolymers such as poly-9,9'-diotyl fluorene-co-dithiophene (F8T2) have been used. F8T2 is a preferred choice because it exhibits good stability during deposition of the gate electrode in air. Spin coat a 5-10 mg / ml solution of F8T2 in anhydrous mixed xylene (purchased from Romil) at 1500-2000 rpm. In the case of P3HT, a 1 weight percent solution in mixed xylene was used. The underlying PEDOT electrode does not dissolve in nonpolar organic solvents such as xylene. The film is then spin dried in a solvent, such as isopropanol or methanol, which is later used to deposit the gate insulating layer 5.
[0047]
A subsequent annealing step can be performed to improve the charge transfer characteristics of the semiconductive polymer. In order to obtain a polymer exhibiting a liquid crystal phase at a high temperature, the polymer chains can be oriented parallel to each other by annealing at a temperature higher than the liquid-crystal transition. In the case of F8T2, inert N at 275-285 ° C. for 5-20 minutes₂Annealing is performed in an atmosphere. The sample is then rapidly quenched to room temperature to freeze the chain orientation and form amorphous glass. When preparing a sample on a flat glass substrate without an alignment layer, the polymer adopts a multi-domain structure in which several liquid-crystalline domains with random orientations are present in the TFT channel. A transistor element in which F8T2 is prepared in a glass state by quenching from a liquid-crystal layer is about 5 · 10.^-3cm²The mobility of / Vs is shown. This value is greater than or equal to the mobility when measured with an element including an F8T2 film in a spinning state. The as-deposited device also has a higher turn-on voltage V₀Indicates. This is because the density of local electron trap states of the glass phase is lower than that of the partially precipitated phase that is crystallized.
[0048]
When the polymer is prepared in a single domain state in which the polymer chains are uniaxially aligned parallel to the transistor channel, typically 3-5 times more improved mobility can be obtained. This can be achieved by coating the glass substrate with a suitable alignment layer, such as a mechanically rubbed polyimide layer (reference numeral 9 in FIG. 1 (b)). In the single domain state, the polymer chains are aligned uniaxially parallel to the rubbing direction of the underlying polyimide layer. This further improves charge carrier mobility in devices where the TFT channel is parallel to the chain alignment direction. Such a process is described in more detail in our pending UK patent application 9914489.1.
[0049]
Gate insulation by depositing a semiconductive layer and then spin-coating a solution of polyhydroxystyrene (also called polyvinylphenol (PVP)) from a polar solvent that does not dissolve the underlying semiconductive polymer Layer 5 is deposited. A preferred choice of solvent is an alcohol such as methanol, 2-propanol or butanol, in which the solubility of a nonpolar polymer such as F8T2 is exceptionally low and does not swell. The thickness of the gate insulating layer is between 300 nm (solution concentration is 30 mg / ml) and 1.3 μm (solution concentration is 100 mg / ml). Other insulating polymers and solvents that meet solubility requirements such as poly-vinyl alcohol (PVA) in water, poly-methyl-methacrylate (PMMA) in butyl acetate, or propylene glycol methyl ether acetate may be used.
[0050]
Next, the gate electrode 6 is deposited on the gate insulating layer. The gate electrode layer may be deposited directly on the gate insulating layer (see FIG. 1 (c)), or for process reasons such as surface modification, diffusion barrier or solvent compatibility, 1 Two or more intermediate layers may be interposed (see FIGS. 1 (a) and (b)).
[0051]
The PEDOT / PSS gate 6 may be printed directly on the PVP insulating layer 5 in order to form a simpler device as shown in FIG. The substrate is transported in air to an inkjet printing (IJP) station, where again a PEDOT / PSS gate electrode pattern is printed from the working solution. The underlying PVP gate insulating layer has low solubility in water so that the dielectric integrity is protected during printing of the PEDOT / PSS gate electrode. PVP has a high density of polar hydroxyl groups, but its solubility in water is low because it has a skeleton similar to ultra-nonpolar polystyrene. Similarly, PMMA does not dissolve in water. FIG. 2 shows the transfer characteristics of an inkjet printed (IJP) TFT comprising an F8T2 semiconductive layer, a PVP gate insulating layer, and inkjet printed (IJP) PEDOT / PSS source-drain and gate electrodes. Element characteristics are measured in a nitrogen atmosphere. Each series of measurements is indicated by a rising (upward triangle) and falling (downward triangle) gate voltage, respectively. The properties relate to devices made from freshly prepared batches of PEDOT / PSS (Baytron P) (a) and one year old batches (b). The transistor activity is clearly visible, but the device has a positive threshold voltage V₀It was found that the comparative device produced with the deposited gold source-drain and gate electrodes showed a normally off behavior while exhibiting a unique normally on behavior with> 10V (V₀<0). In devices made from “old” batches of PEDOT (see FIG. 2 (b)), a large hysteresis effect was observed, due to the high concentration of mobile ionic impurities (see below). ) Large depletion state (V_g= + 40V), when the sweep starts, the transistor^f ₀≒ + 20V (upward triangle) turns on. However, in reverse scan (downward triangle), the transistor is V^r ₀> +35 only off.
[0052]
Normally on behavior and hysteresis effects are likely to occur due to diffusion of ionic material into one of the layers of the device. V₀An unusually large positive value of indicates that the ion is negative. A positive material compensates for some of the mobile charge in the storage layer and V₀Is expected to lead to more negative values. In order to determine the origin of this ionic material, the top-gate inkjet printing (IJP) PEDOT electrode was replaced with a deposited gold electrode, and the other layers and PEDOT source / drain electrodes were fabricated as described above. In this structure, it was found that the device is normally off and exhibits a stable threshold voltage. This means that doping and hysteresis effects in all-polymer devices are mobile and ionic impurities from solution deposition of the conductive polymer top gate electrode and from the device PEDOT solution / film to the underlying layers. Is related to the possible diffusion of.
[0053]
It has been found that by depositing a gate electrode on a heated substrate, the threshold voltage value can be controlled and the amount of hysteresis can be reduced. This shortens the drying time of the droplets on the substrate. FIG. 3B shows the transfer characteristics of the TFT element in which the substrate is heated to 50 ° C. during the deposition of the gate electrode. The hysteresis effect is very small compared to the case of gate deposition at room temperature (FIG. 3b).₀Is a relatively small positive value of 6V. By controlling the deposition temperature, the threshold voltage is set to V₀= 1 to 20V can be adjusted.
[0054]
A device including a gate electrode directly deposited on a PVP layer as shown in FIG. 1C is a depletion type. This normally-on behavior is useful for a depletion type logic circuit such as a simple depletion load logic inverter (FIG. 14A).
[0055]
In order to produce an enhancement-type normally-off TFT, the incorporation of a diffusion barrier layer can prevent doping of the semiconductive material during gate deposition. In the device of FIGS. 1 (a) and (b), a thin layer 7 of nonpolar polymer is deposited on the PVP gate insulating layer before depositing the conductive polymer gate electrode. This layer is believed to act as a diffusion barrier that prevents diffusion of ionic materials through the mesopolar PVP insulator. PVP contains high density polar hydroxyl groups that tend to increase the conductivity and diffusivity of ions through the membrane. Several such as poly-9,9'-dioctylfluorene (F8), polystyrene (PS), poly (9,9'-dioctyl-fluorene-co-N- (4-butylphenyl) diphenylamine) (TBF) or F8T2 A nonpolar polymer was used. Thin films of these polymers of about 50-100 nm can be deposited on the surface of the PVP gate insulation layer from solutions in non-polar organic solvents such as xylene in which PVP does not dissolve.
[0056]
Direct printing of PEDOT / PSS from a polar solution in water onto a nonpolar barrier layer or onto an intermediate polar polymer such as PMMA proved problematic due to insufficient wettability and large contact angle . In order to cope with this, the surface modification layer 8 is deposited on the nonpolar polymer. Since this layer forms a hydrophilic surface rather than a hydrophobic surface, PEDOT / PSS is likely to be formed thereon. Thereby, the gate electrode pattern can be printed with high resolution. To form the surface modified layer, a thin layer of PVP may be deposited from an aqueous isopropanol solution. The underlying diffusion barrier layer does not dissolve in this aqueous solution. The thickness of the PVP layer is preferably 50 nm. PEDOT / PSS can be printed at high resolution on the surface of PVP. Another surface modification layer may be employed. Examples include soap-like surfactants or thin layers of polymers containing hydrophilic and hydrophobic functional groups. These molecules tend to be attracted towards the underlying nonpolar polymer and free surface interface, respectively, to phase separate into hydrophobic and hydrophilic groups. In addition, non-polar diffusion barrier₂It is also possible to make the surface hydrophilic by exposing it to plasma for a short time. Proper plasma processing without compromising TFT device performance is a 13.5 MHz O with 50 W intensity.₂Exposure to plasma for 12 seconds.
[0057]
If the gate electrode is printed from a solvent less polar than water, such as an alcohol-containing formulation (isopropanol, methanol, etc.), a surface modification layer over the nonpolar diffusion barrier is not necessary.
[0058]
The integrity of the layer sequence relies on alternating deposition of polymer material from polar and non-polar solvents. The solubility of the first layer in the solvent used to deposit the second layer is desirably less than 0.1 weight percent per volume, and preferably less than 0.01 weight percent per volume.
[0059]
Solvent compatibility criteria can be quantified using the Hildebrand solubility parameter, which can quantify the degree of polarity (D.W. van Krevelen, Properties of polymers, Elsevier, Amsterdam (1990)). The solubility behavior of each polymer (solvent) is determined by three characteristic parameters δ_d, Δ_p, Δ_hDescribed by. These parameters characterize dispersion interactions, polarity, and hydrogen bonding interactions between liquid polymer (solvent) molecules. The values of these parameters can be calculated if the molecular structure is known by adding contributions from different functional groups of the polymer. These can be tabulated by the most common polymers. Often δ_pAnd δ_dΔy in combination²= Δ_d ²+ Δ_p ²It can be.
[0060]
The free energy of mixing is ΔG_m= ΔH_m-T ・ ΔS_mObtained by. In this equation, ΔS_m> 0 is the entropy of mixing and ΔH_m= V · φp · φs · ((δ_v ^p−δ_v ^s)²+ (Δ_h ^p−δ_h ^s)²(V: volume; φp, φs: volume fraction of polymer (P) / solvent (S) in the mixture). From this equation, the polymer (P) becomes ΔH_mIs smaller, that is, D = ((δ_v ^p−δ_v ^s)²+ (Δ_h ^p−δ_h ^s)²)^1/2It is expected that the smaller the is, the easier it is to dissolve in the solvent (S). As a rough guide, if the interaction parameter D is less than about 5, the polymer dissolves in the solvent. If D is between 5 and 10, swelling is often observed. If D is greater than 10, the polymer does not substantially dissolve in the solvent and does not swell. In order to obtain a sufficiently steep interface in a solution processed TFT element, it is therefore desirable that the solvent value D of each polymer layer and the next layer is greater than about 10. This is particularly important in semiconductive polymers and gate dielectric solvents. In the case of F8T2 and isopropanol (butyl acetate), we estimate D to be about 16 (12).
[0061]
For some device configurations, the overall multilayer structure consists of a polymer that contains mainly polar groups and dissolves in highly polar solvents such as water, and that contains little or no polar groups, such as xylene. It can be constituted by alternately superposing the polymer dissolved in the nonpolar solvent one after another. In this case, δ of the solvent of the polymer layer and the next layer_pAre different, the interaction parameter D becomes large. Examples include PEDOT / PSS high-polarity source-drain electrodes, nonpolar semiconducting layers such as F8T2, high-polarity gate dielectric layers such as polyvinyl alcohol deposited from aqueous solutions, and deposition of a series of layers. Examples include a transistor element including a nonpolar dispersion barrier layer of TFB that also functions as a barrier layer, and a PEDOT / PSS gate electrode.
[0062]
However, it is often convenient to have a nonpolar semiconductive layer and a polar gate electrode layer separated by a single dielectric layer. This series of layers is also possible by using an intermediate polar polymer layer deposited from an intermediate polar solvent sandwiched between highly polar and non-polar polymer layers. An intermediate polar polymer is a polymer that contains both polar and non-polar groups and is substantially insoluble in highly polar solvents. Analogously to this, mesopolar solvents contain both polar and nonpolar groups, but are substantially soluble in nonpolar polymers. From the point of view of solubility parameters, the medium polar solvent has a solubility parameter δ_hCan be defined as significantly different from the value of the underlying polymer. In this case, even if the solvent polar solubility parameter δ_p(Δ_v) Is similar to the value of the underlying polymer layer, swelling can be avoided (large D). A mesopolar polymer may contain certain functional groups, such as hydroxyl groups, which render the mesopolar polymer soluble in solvents containing functional groups that are attracted to the polymer functional groups. Such an attraction action may be a hydrogen bond interaction. Such a function of the polymer can be used to increase its solubility in intermediate polar solvents and lower its solubility in polar solvents. An example of an intermediate polar polymer is a PVP gate dielectric layer sandwiched between a nonpolar semiconductive layer and a PEDOT / PSS gate electrode (FIG. 1c). Examples of intermediate polar solvents include alkyl alcohols such as IPA (δ_h= 8; F8T2: δ_h≒ 0).
[0063]
FIG. 4 shows the output (a) of a fully polymerized F8T2 inkjet printing (IJP) TFT comprising a PVP gate insulating layer, an F8 diffusion barrier layer, and a PVP surface modification layer as shown in FIG. 1 (a). And transmission (b) characteristics are shown (L = 50 μm). Element is V₀A clean and almost ideal normal off-transistor operation with a turn-on of ≦ 0V. The threshold voltage shift between upward (upward triangle) and downward (downward triangle) voltage sweep is ≦ 1V. The device characteristics are very similar to a standard device with gold source-drain and gate electrodes and manufactured under inert atmosphere conditions. Field effect mobility is about 0.005 to 0.01 cm²/ Vs, V_gThe on-off current ratio measured between = 0 and −60V is about 10^Four-10^FiveIt is an order.
[0064]
The device was fabricated with a wide range of non-polar dispersion barrier layers such as F8, TFB (FIG. 5 (a) is transfer characteristic), PS (FIG. 5 (b) is transfer specific), and F8T2. In each case, clean normal off behavior, small hysteresis effects and threshold voltage shifts were observed. These were almost the same as the values of the comparative element provided with the gold source-drain electrodes. This supports the interpretation that insertion of a non-polar polymer under the gate electrode prevents ionic impurities from diffusing during and after solution deposition of the gate insulating layer. With this discovery, we were able to obtain a TFT threshold voltage with good reproducibility and good operational stability.
[0065]
A normally-off device with a diffusion barrier is preferred over the depletion device described above. This is because the former can be expected to have a longer threshold voltage stability and a longer lifetime.
[0066]
For semiconductive layers, 10^-3cm²/ Vs, preferably 10^-2cm²Any solution can be used as long as it can process conjugated polymer or oligomeric materials exhibiting appropriate field effect mobility above / Vs. For suitable materials see, for example, H.E. Katz, J. Mater. Chem. 7, 369 (1997) or Z. Bao, Advanced Materials 12, 227 (2000).
[0067]
One important requirement for producing printed TFTs with good stability and high on-off current ratio is against unintentional doping with oxygen in the air and water during the processing and printing process. Good stability of the semiconductive material is mentioned. Printed TFTs have been manufactured using the full range of semiconductive polymers such as F8T2 (see above) or regioregular P3HT deposited from mixed xylene solutions as the active semiconductive layer. 0.05 to 0.1 cm for P3HT TFTs prepared in a test element structure in an inert atmosphere²The field effect mobility of / Vs is slightly higher than that of F8T2. However, (regioregular) P3HT is unstable to doping with oxygen and / or water, resulting in increased membrane conductivity and poor on-off current ratio during the printing process in air. This means that the ionization potential of P3HT is I_pThis is related to the relatively low value of ≈4.9 eV. > 10 for P3HT⁶In order to achieve this, a reduction de-doping process such as exposure to hydrazine vapor is required to achieve this (H. Sirringhaus, et al., Advances in Solid State Physics). 39, 101 (1999)). However, this post-reduction processing step cannot be performed for the inkjet printing (IJP) TFTs described above, because doing so would also de-doped the PEDOT electrodes, thus significantly reducing their conductivity. . Therefore, in order to achieve a high current switching ratio, it is important to use a polymer semiconductor with good stability against unintentional doping with oxygen or water.
[0068]
A preferred type of material to achieve good environmental stability and high mobility is an AB rigid rod block copolymer containing A and B blocks arranged in a normal sequence. Suitable A blocks are ladders with high band gaps that are well defined structurally. They have an ionization potential greater than 5.5 eV as a homopolymer and good environmental stability. Examples of suitable A blocks include fluorene derivatives (US Pat. No. 5,777,070), indenofluorene derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenylene or ladder type phenylene derivatives (J. Grimme et al ., Adv. Mat. 7, 292 (1995)). Suitable B-locks include hole transports with lower band gaps, containing different atoms such as sulfur or nitrogen, and having an ionization potential of less than 5.5 eV as a homopolymer. Examples of the hole transfer B block include thiophene derivatives or triallylamine derivatives. The effect of the B block is to reduce the ionization potential of the block copolymer. The ionization potential of the block copolymer is preferably 4.9 eV ≦ I_pThe range is 5.5 eV. Examples of such copolymers include F8T2 (ionization potential is 5.5 eV) or TFT (US Pat. No. 5,777,070).
[0069]
Other suitable hole transfer polymers include homopolymers of polythiophene derivatives with an ionization potential greater than 5 eV, such as polythiophenes with alkoxy or fluorinated side chains (R.D. McCullough, Advanced Materials 10, 93 (1998)).
[0070]
Instead of hole transfer semiconductive polymers, soluble electron transfer materials can also be used. These materials require a high electron affinity greater than 3 eV, preferably greater than 3.5 eV, to prevent residual atmospheric impurities such as oxygen from acting as carrier traps. Suitable materials include solution solution processable electron transfer small molecule semiconductors (HE Katz, et al., Nature 404, 478 (200)) and polythiophene derivatives having electron-depleted fluorinated side chains. A structurally well-defined ladder A block with a large high ionization potential greater than 5,5 eV and an electron transfer B block that increases the electron affinity of the copolymer to a value greater than 3 eV, preferably greater than 3.5 eV Also suitable are AB type block copolymers having: Examples of A blocks include fluorene derivatives (US 5,777,070), indenofluorene derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenylene or ladder type phenylene derivatives (J. Grimme et al., Adv. Mat). 7, 292 (1995)). Examples of electron transfer B blocks include benzothiadiazole derivatives (US 5,777,070), phenylene derivatives, naphthalene tetracarboxyldiimide derivatives (HE Kats et al., Nature 404, 478 (2000)), and fluorinated thiophene derivatives. It is done.
[0071]
In order for the logic circuit to operate at high speed, the channel length L of the transistor, the overlap between the source / drain and the gate d should be as small as possible, i.e. typically a few μm. The most important dimension is L. This is because the operating speed of the transistor circuit is L^-2This is because it is almost proportional to. This is particularly important for semiconductive layers with relatively low mobility.
[0072]
Such high resolution patterning cannot be achieved with current inkjet printing technology. The current inkjet printing technology is limited to a characteristic dimension of 10 to 20 μm even with the latest inkjet printing (IJP) technology (FIG. 6). If faster operation and denser feature packing are required, techniques that allow for more precise feature resolution must be employed. The technology described below uses ink surface interaction to confine ink jet droplets on the substrate surface. This technique can be utilized to achieve channel lengths that are much smaller than those achievable with conventional inkjet printing.
[0073]
This confinement technique can be utilized to allow the material deposited on the substrate to be deposited with precise resolution. The surface of the substrate is first treated so that the material deposited in the selected portion is relatively attracted and relatively repelled. For example, a region in which the substrate is pre-patterned may be partially hydrophobic, and the other regions may be partially hydrophilic. Subsequent deposition can be accurately defined by a pre-patterning step performed with high resolution and / or precise alignment.
[0074]
One embodiment of pre-patterning is shown in FIG. FIG. 7 shows the manufacture of the element of the type shown in FIG. 1 (c), but the channel length L is particularly precise. The same components as those in FIG. 1C have the same reference numbers. FIG. 7A shows a method for manufacturing a pre-patterned substrate. FIG. 7 (b) shows printing and ink confinement on a pre-patterned substrate.
[0075]
Before depositing the source-drain electrodes 2, 3, a thin film polyimide layer 10 is formed on the handle sheet 1. This polyimide layer is finally patterned and removed from where the source-drain electrodes are to be formed. This removal step can be performed by a photolithography step to allow precise feature definition and / or precise alignment. As an example of such a process, polyimide is covered with a layer of photoresist 11. By patterning the photoresist by photolithography, the photoresist can be removed from the location where the polyimide is to be removed. Next, the polyimide is removed by a process in which the photoresist is resistant. Then, by accurately removing the photoresist, it is possible to leave a precisely patterned polyimide. The reason for choosing polyimide is that while it is relatively hydrophobic, the glass substrate is relatively hydrophilic. In the next step, a PEDOT material for forming source-drain electrodes is deposited on the hydrophilic substrate region 12 by ink jet printing. When the ink droplet spreads on the glass substrate region and hits the hydrophobic polyimide region 10, the ink is repelled and is prevented from flowing into the hydrophobic surface region.
[0076]
Due to this confinement effect, the ink is deposited only on the hydrophilic surface region, and a high resolution pattern with a small gap and a transistor channel length of less than 10 μm can be defined (FIG. 7B).
[0077]
An example of a process that can remove the polyimide or that can be employed to increase the specific surface effect after removal of the polyimide is shown in FIG. The polyimide layer 10 and the photoresist 11 are exposed to oxygen plasma. Oxygen plasma etches the thin film (500 mm) polyimide layer faster than the thick film (1.5 μm) photoresist layer. The exposed bare glass surface 12 in the source-drain electrode region is exposed to O before removing the photoresist.₂It becomes very hydrophilic when exposed to plasma. It should be noted that during polyimide removal, the polyimide surface is protected by photoresist and remains hydrophobic.
[0078]
If necessary, the surface of the polyimide can be further CF_FourHydrophobicity can be further increased by exposure to plasma. CF_FourThe plasma fluorinates the polyimide surface but does not interact with the hydrophilic positive glass substrate. Such further plasma treatment can be performed before removing the photoresist, in which case only the sidewalls of the polyimide pattern 10 are fluorinated. Alternatively, it can be performed after removing the resist.
[0079]
O₂The contact angle of PEDOT / PSS in water on 7059 glass treated with plasma is the contact angle on the polyimide surface is θ_pt≒ 70-80 ° compared to θ_glass= 20 °. The contact angle of PEDOT / PSS in water on fluorinated polyimide is 120 °.
[0080]
As mentioned above, when PEDOT / PSS is deposited from an aqueous solution onto a pre-patterned polyimide layer, the PEDOT / PSS ink will remain in the source-drain electrode region even if the channel length L is only a few μm. It is confined (FIG. 7 (b)).
[0081]
In order to easily confine the ink droplet, the kinetic energy of the ink droplet is kept as small as possible. The larger the droplet size, the greater the kinetic energy and the greater the likelihood that the expanding droplet will “neglect” the hydrophobic confinement structure and overflow to the adjacent hydrophilic region.
[0082]
Preferably, the ink droplet 13 is deposited on the hydrophilic substrate region 12 at a distance d between the center of the droplet and the polyimide boundary. On the other hand, d is sufficiently small, and the spreading ink must reach the boundary so that the PEDOT film extends over the entire area to the polyimide boundary. On the other hand, d must be large enough so that rapidly spreading ink does not “overflow” into the hydrophobic surface area. This increases the risk of PEDOT being deposited on the polyimide region 10 defining the TFT channel and may cause a short circuit between the source and drain electrodes. PEDOT droplets with a solid content of 0.4 ng₂It has been found that a value of d≈30-40 μm is suitable when depositing on a plasma-treated 7059 glass with a lateral pitch between two successive droplets of 12.5 μm. The minimum value of d depends on the wettability on the surface as well as the deposition pitch, ie the lateral distance between the subsequently deposited droplets, the frequency with which the droplets are deposited, and the drying time of the solution.
[0083]
A hydrophobic confinement layer for defining the transistor channel length may provide a second function. This layer can be used as an alignment template for later deposition of the semiconductive polymer in the channel of the transistor. The polyimide layer 10 can be mechanically rubbed or photo-aligned and then used as an alignment layer to provide a single domain alignment of the liquid-crystalline semiconductive polymer 4 (FIG. 1 (b)).
[0084]
The gate electrode 6 can be similarly defined by a patterning layer 14 formed on the gate insulating layer 5 that provides a surface region that attracts and repels the solution from which the gate electrode is deposited. By aligning the patterned layer 6 with respect to the source-drain pattern, the overlapping region between the source / drain and gate electrodes can be minimized (FIG. 7 (c)).
[0085]
Materials other than polyimide can be used as a pre-patterned layer. Other precision pre-patterning techniques other than photolithography can also be used. FIG. 8 demonstrates the ability of the structure of relatively hydrophobic and hydrophilic layers to limit the liquid “ink” deposited by inkjet printing. FIG. 8 shows an optical micrograph of a substrate containing a polyimide 10 flake, the flake being processed as described above to be relatively hydrophobic, and a large area of the exposed glass substrate 12 being relatively hydrophilic. Is processed as described above. The PEDOT material that becomes the source and drain electrodes is deposited by ink jet printing consisting of a series of droplet running lines 2 and 3 approaching the flake 10. The ink jet material shows a weak contrast, but appears to be an unexpectedly terminated form of the deposited material end faces 2 and 3, and this deposited material is limited by the flakes 10 even when dug down to a flake thickness L = 5 μm.
[0086]
FIG. 9 is a photograph of the inkjet deposition process in the vicinity of the polyimide flakes 10. This video was taken with a strobe camera attached below the transparent substrate. The edges of the polyimide pattern 10 can be seen as white lines. The ink droplet 21 is ejected from the nozzles of the ink jet head 20 and is deposited at its center at a distance d from the polyimide flake 10. Such images can be used for accurate local alignment of ink jet deposition with respect to the flake pattern 10, and are used to automate the local alignment procedure using pattern recognition (see below).
[0087]
FIGS. 10 and 11 show the output and transfer characteristics formed as shown in FIG. 7c and have channel lengths L of 20 μm and 7 μm, respectively, defined by the differential wetting process described above. . In any case, the channel width W is 3 mm. FIG. 10A shows the output characteristics of a 20 μm element. FIG. 10B shows output characteristics of the 7 μm element. FIG. 11A shows the transfer characteristics of a 20 μm element. FIG. 11B shows the transfer characteristics of the 7 μm element. The 7 μm device exhibits characteristic short channel operation with reduced source and drain output and limited output conductance in saturation. The short channel / element mobility and the ON-OFF current ratio are similar to those of the long channel / element described above. That is, μ = 0.005-0.01 cm²/ Vs and I_ON/ I_OFF= 10^Four-10^FiveIt is.
[0088]
Ink limitations are the result of differences in wetting characteristics on hydrophobic and hydrophilic surfaces, and do not require the presence of microstructured features. In the above example, the polyimide film can be made very thin (500 mm), which is much thinner (a few micrometers) than the size of the inkjet droplets in liquid form. Thus, another technique for fabricating a pre-pattern of the substrate can be used to functionalize the surface of the glass substrate with a patterned self-assembled monolayer (SAM). For example, SAM contains a hydrophobic alkyl such as trifluoropropyl-trimethoxylen or a fluoro group or an alkoxy group. SAMs can be exposed to UV light through shadow masks (H. Sugiura et al., Langmuir 2000, 885 (2000)) or microcontact printing (Brittain et al., Physics World May 1998, p. 31). It can be patterned by appropriate techniques.
[0089]
Substrate pre-patterning can be easily shared with the process flow described above, such as pre-patterning performed prior to TFT layer deposition. Accordingly, a wide range of patterning and printing techniques can be used and high resolution pre-patterns can be generated without the risk of degradation of the active polymer layer.
[0090]
Similar techniques can be applied to pre-pattern the surface or surface modification layer of the gate insulating layer prior to deposition of the gate electrode to achieve a small overlap capacitance. As shown in FIG. 7C, the gate electrode 6 is defined by the pattern layer 14. One possible embodiment of this type of pre-patterning method is a self-assembled monolayer (SAM) microcontact printing method or UV photopatterning method containing chlorosilanes or methoxy silanes such as octadecyltrichlorosilane. is there. These molecules are SiO which chemically bond with the hydroxyl groups on the extreme surface and make it surface hydrophobic.₂Alternatively, a stable monomolecular layer is formed on the surface of the glass substrate. The inventors have found that similar monolayers can be formed on the surface of a gate dielectric monomolecule (polymer) such as PVP or PMMA. This appears to be due to the binding of molecules to hydroxyl groups on the PVP surface. A surface free energy pattern consisting of thin hydrophilic lines with a well-defined small overlap by a source-drain electrode surrounded by a SAM coated hydrophobic region is easily defined by a soft lithographic stamp process. This stamping process can be performed under an optical microscope or mask aligner to match the stamp pattern with respect to the underlying source-drain electrodes. When the conductive aqueous polymer ink is deposited on top, the deposition is limited to thin hydrophilic lines defined by the self-assembled monolayer. In this way, a thinner line width can be achieved than can be achieved with a normal line width on the unpatterned gate electrode layer. This reduces the source / drain-to-gate overlap capacitance.
[0091]
With the help of a pre-patterned substrate, high speed logic circuits based on the TFT and the described via hole manufacturing process can be manufactured.
[0092]
One of the decisive conditions for manufacturing transistor circuits over a large area is deposition alignment and alignment with respect to the pattern on the substrate. Achieving proper alignment is particularly difficult for flexible substrates that exhibit distortion over a large area. If the substrate is distorted between successive patterning steps, the next mask level during the photolithography process no longer overlaps with the underlying pattern. The high resolution inkjet printed circuit boards developed here are suitable for achieving precise alignment over a large area even on plastic (plastic) substrates. This is because the position of the inkjet head can be locally adjusted with respect to the pattern on the substrate (FIG. 9). This local alignment process is possible automatically using a pattern recognition technique that uses an image such as the pattern of the technique of FIG. 9 to correct the position of the inkjet head in combination with a feedback mechanism.
[0093]
In order to form a multi-transistor integrated circuit using devices of the type described above, it is desirable to form via holes and be directly interconnected through the thickness of the device. This is because this type of circuit is particularly compact. One method for forming such an internal connection is to use a solvent-formed via hole as described below. This method has the practical advantage that the above-described TFT solvent-treated layer is not converted to an insoluble form at all. This allows the opening of via holes due to local deposition of solvent.
[0094]
In order to form a solvent-formed via hole (FIG. 12 (a)), a certain amount of a suitable solvent 29 is locally deposited on the top of the layer, where a via hole is formed. A solvent that can dissolve the lower layer in which holes are formed is selected. Until the via hole is formed, the solvent penetrates the layer by progressive dissolution. Dissolved material is deposited on the sidewall W of the via hole. The type of solvent and the method for depositing it are selected according to the particular application. However, four preferred aspects are:
1. Solvent and processing conditions are that the solvent is evaporated or otherwise easily removed so that it does not interfere with subsequent processing and does not dissolve the element transiently or incorrectly. ;
2. The solvent is deposited by a selected process such as IJP so that a precisely controlled amount of solvent can be applied exactly where desired on the substrate; and
3. The diameter of the via hole is affected by the surface tension of the solvent droplets and the ability of the solvent to wet the substrate; and
4). The solvent does not dissolve the lower layer where the electrical connection is made.
[0095]
FIG. 12 (a) shows the deposition of a methanol solvent (including 20 ng per droplet) droplet 29 on a partially formed transistor device of the general type shown in FIG. 1 (c). The partial device of FIG. 12A includes a 1.3 μm thick PVP insulating layer 28, F8T2 semiconductive layer 27, PEDOT electrode layer 26 and glass substrate 25. In this example, it is desirable to form a via hole that penetrates the insulating PVP layer. Methanol is selected as a solvent because of its ability to readily dissolve PVP, i.e., it easily evaporates so as not to interfere with subsequent processing steps, and also has satisfactory wetting properties for PVP. In order to form a via hole in this example, an inkjet (IJP) print head is moved to a position on the substrate where the via hole is to be formed. Accordingly, the required number of appropriately sized methanol droplets are dropped from an inkjet (IJP) printhead until the via hole is completed. The period between successive droplets is selected to match the ratio at which methanol dissolves the layers of the device. Each droplet is preferably completely or almost completely evaporated before the next droplet is deposited. Care must be taken that when the via hole reaches the underlying nonpolar semiconductive layer, the etching process is stopped and the underlying layer is not removed. Other solvents such as isopropanol, ethanol, butanol or acton can also be used. In order to achieve high throughput, it is desirable to complete the via hole by deposition of a single solvent droplet. For a 300 nm thick film and a droplet having a volume of 30 pl and a diameter of 50 μm, this requires a solubility of the layer in a solvent higher than 1-2% by weight per volume. A higher boiling point is even more desirable when it is necessary to form via holes with a single droplet. In the case of PVP, 1,2 dimethyl-2-imidazolidione (DMI) having a boiling point of 225 ° C. can be used.
[0096]
FIG. 12 (b) shows the effect of dropping several drops of methanol in sequence at the position of the via hole. The right panel shows a photomicrograph of the device after dropping 1, 3 and 10 droplets. The left panel shows the Dectak surface profile measurement result of the same element across the formed via hole. (The position of the via hole is generally indicated by the position “V” in each panel.) When several drops are dropped continuously at the same position, the crater is opened in the PVP film. The crater depth increased with the action of successive droplets, and after about 6 droplets, the surface of the underlying F8T2 layer was turned. The dissolved PVP material was deposited in the wall W at the side of the via hole. The diameter of the via hole is about 50 μm limited by the size of the droplet. This size is suitable for many applications such as logic circuits and large area displays.
[0097]
The diameter of the via hole is determined by the size of the inkjet solvent droplet. The hole diameter was observed to be directly proportional to the droplet diameter (see FIG. 12c). The outer diameter of the side wall is determined by the size and diffusion of the first droplet and is independent of the thickness of the dissolved polymer layer. For applications where smaller holes are required, such as high resolution displays, even when smaller droplet sizes are used, or even if the substrate surface is pre-patterned by appropriate techniques, Drops can be restricted. Other solvents can also be used.
[0098]
From the surface profile measurement results, it can be seen that the formation of the via hole dissolves the substance and moves it to the edge of the via hole, and the hole remains after the solvent is evaporated (indicated by W in FIG. 12B). It should be noted that the transferred material has a smoother shape than that shown in FIG. 12 (b), and the x- and y-axis of the surface morphology is a different scale plot of FIG. 12 (b). (X is in μm units and y is in Å units).
[0099]
The mechanism of via hole formation, i.e. the movement of the material to the side walls, is thought to be similar to the well-known coffee stain effect that occurs when the contact line of a dry droplet containing solute is pinned. It is done. The pinning action occurs, for example, due to surface roughness or chemical heterogeneity. It should be noted that good solvent deposition always generates surface roughness during dissolution. As the solvent evaporates, it occurs because the capillary flow is replaced by solvent evaporation near the contact line. More solvent evaporates near the contact line due to the larger surface to bulk ratio near the contact line. The capillary flow rate is large compared to the typical diffusion rate, e.g. the solute is transported to the edge of the droplet, and solute deposition occurs only near the rim and not at the center of the dry droplet (RD Deegan et al., Nature 389, 827 (1997)). Solute diffusion tends to result in a preferred uniform reprecipitation of the polymer over the entire area when the solvent dries rather than the formation of sidewalls. Theoretically predictable is the capillary flow velocity V (r) (r: is the distance from the center; R: the radius of the droplet) is (R−r)^-proportional to λ, where λ = (π−2θ_c) / (2π-2θ_c). Therefore, when V increases with increasing λ, the contact angle θ_cBecomes smaller. Therefore, the earlier the amount of precipitation at the edge, the smaller the contact angle.
[0100]
Therefore, for the opening of the via hole, what is important is that (a) the contact line of the initial droplet is pinned and (b) the contact angle of the droplet on the top of the polymer to be dissolved is sufficiently small And (c) solvent evaporation is fast enough that polymer solute diffusion is negligible. In the case of IPA on PVP, the contact angle is on the order of 12 °, and the droplets typically dry within less than 1 s.
[0101]
The smaller the contact angle, the faster the capillary flow velocity inside the droplet. That is, the formation of the side wall becomes more certain. However, on the other hand, the smaller the contact angle, the larger the droplet diameter. Thus, there is an optimum contact angle to achieve a small diameter via hole with well-defined sidewalls. In order to achieve a larger contact angle with a good solvent, the surface of the substrate is treated, for example, with a self-assembled monolayer with a greater repulsion of the solvent. This self-assembled monolayer is patterned to provide, for example, hydrophobic and hydrophilic surface regions, so that solvent precipitation is limited to small areas.
[0102]
The depth of the via hole and the etching rate can be adjusted by a combination of the number of droplets of solvent dropped, the frequency with which the droplets are deposited, and the rate of evaporation of the solvent compared to the rate that is the ability to dissolve the substrate. it can. The environment in which precipitation occurs and the temperature of the substrate affect the evaporation rate. A layer of material that is insoluble or slowly soluble in the solvent can be used to limit the depth of dissolution.
[0103]
Since the TFT layer sequence is composed of alternating polar and nonpolar layers, it is possible to select a solvent and a combination of solvents to stop etching at a definite depth.
[0104]
In order to perform contact through the via hole, a conductive layer is deposited thereon, thereby extending into the via hole and making electrical connection with the material below the via hole. FIG. 13A shows an element of the type shown in FIG. 12A, which includes the step of forming the gold electrode 25 after the formation of the via hole described above.
[0105]
FIG. 13 shows current / voltage characteristics measured between the lower PEDOT electrode 25 and the conductive electrode 29 deposited on the top of the PVP gate insulating layer 28 in a curve 30. The diameter of the via hole was 50 μm. For comparison, curve 31 shows a standard sample in which no via hole is located in the overlap region between the top electrode and the bottom electrode. The characteristic clearly shows that the current passing through the via hole is several times higher than the leakage current passing through the gate insulating portion where no via hole exists. The measurement current passing through the via hole is limited by the conductivity of the PEDOT electrode, and can be known by performing the conductivity measurement of the individual PEDOT electrodes. The resistance value R of the via hole is not limited by the resistance value of the via hole._vA low limit estimate can be obtained from these measurements. That is, R_v<500 kΩ.
[0106]
The method for forming a via hole described above with reference to FIG. 12 is for a depletion layer type device (as shown in FIG. 1C) without a diffusion barrier, and for a device in which a diffusion barrier is deposited after opening a via hole. Directly applicable to FIG. 14A shows an element in which a via hole is formed and the gate electrode is deposited without being interposed in the diffusion barrier layer. FIG. 14B shows a similar element in which the diffusion barrier polymer 7 is formed during the deposition of the gate electrode 6 after the formation of the via hole. In this case, the diffusion barrier layer has a via hole resistance R_vIt is necessary to exhibit excellent charge transfer characteristics in order to minimize. The optimum diffusion barrier is a thin layer of TFB as shown in FIG.
[0107]
If uniform low contact resistance is required, the semiconductive layer is also removed at the via hole site. This is preferably done after the diffusion barrier is formed. The diffusion barrier 7 and the semiconductive polymer 4 are locally dissolved by an excellent ink-jet print (IJP) deposition of the solvent, and in this example is xylene. By mixing an excellent solvent for the semiconductive material and the insulating material, both layers are dissolved simultaneously. An element in which this is performed following the deposition of the gate electrode is shown in FIG.
[0108]
The solvent mixture can be used to reduce the diameter of the via hole by increasing the contact angle of the solvent mixture on the layer to be dissolved.
[0109]
Another way to form via-hole interconnects, and thus deposit and bridge conductive materials, is to deposit materials that can locally modify the underlying layer substrate and make them conductive. It is to make. As an example, local IJP deposition of a solution containing a mobile dopant can be diffused into one layer or several layers. This is shown in FIG. 14 (d), where region 32 contains material that has been rendered conductive by treatment with a dopant. This dopant is a small conjugate such as triallylamine (TPD) such as N, N′-diphenyl-N, N′-bis (3-methyldiphenyl)-(1,1′biphenyl) -4,4′-diamine. Is a molecule. The dopant is preferably added as a solvent case.
[0110]
Via hole formation via a PVP dielectric layer allows the TFT gate electrode to be connected to the source or drain electrode in the underlying layer when needed for a logic inverter device, for example as shown in FIG. Can be used to connect. Similar via-hole connections are required for most logic transistor circuits. FIG. 16 is a plot of the characteristics of the enhancement-load inverter element formed by the two normally-off transistor elements shown in FIG. Shown are two inverters having different ratios of channel length to channel length (W / L) for two transistors (plot 35 is a 3: 1 ratio, plot 36 is 5: 1). When the input voltage changes from logic low to logic high, the output voltage changes from the logic high (−20V) to the logic low (≈0V) state. The inverter gain, i.e. the maximum slope of the characteristic, is greater than 1, which is a requirement to allow the production of more complex circuits such as ring oscillators.
[0111]
Via holes as described above can also be used to provide electrical connections between internal connection lines in different layers. For complex electronic circuits, multi-level interconnects are needed. This can be made by placing a sequence of internal connections 72 and different dielectric layers 70, 71 deposited from a compatible solvent (FIG. 15 (d)). The via hole 73 can then be formed in the manner described above using an internal connection line with automatic etch stop.
[0112]
Examples of suitable dielectric materials are polar polymers (70) such as PVP and nonpolar dielectric polymers (71) such as polystyrene. These can be precipitated in different ways from polar and nonpolar solvents. Via holes can be opened by local deposition of a good solvent for each dielectric layer while the underlying dielectric layer comprises an etch stop layer.
[0113]
In selecting materials and deposition processes for devices of the type described above, significant advantages can be obtained if each layer is deposited from a solvent that does not substantially melt the underlying layer directly. You should keep in mind that it is possible. In this way, successive layers can be made by solvent treatment. One way to simplify the selection of such materials and process steps is to use two or more different methods from polar and non-polar solvents, as exemplified for the layer sequences described above. It is intended to deposit a layer. In this method, a multilayer element containing a soluble layer, a conductive layer, a semiconductive layer, an insulating layer, etc. can be easily formed. This makes it possible to avoid the problem of dissolution and swelling of the underlying layer.
[0114]
The device structures, materials and processes described above are merely exemplary. It is clear that they may be changed.
[0115]
Other device structures different from the top gate structure shown in FIG. 1 may be used. Another structure is the more standard bottom gate structure shown in FIG. 17, which may incorporate a diffusion barrier 7 and a surface modification layer 8 if required. In FIG. 17, the same reference numerals are the same as those in FIG. Other device structures in which different layers have a continuous structure can also be used. Elements other than transistors can be formed in a similar manner.
[0116]
PEDOT / PSS can be replaced by any conductive polymer that can be deposited from the solvent. Examples include polyaniline and polypyrrole. Nonetheless, some attractive features of PEDOT / PSS are: (a) impurities due to polymerization with inherently low diffusivity, (b) good temperature stability and stability in air, and (c) efficiency. The work function of 5.1≈eV is well matched to the ionization potential of a common hole transporting conductive polymer that allows good hole charge carrier injection.
[0117]
Efficient charge carrier injection is particularly important for short channel transistor devices having a channel length L <10 μm. In such an element, the source-drain contact resistance effect may limit the TFT current for a small source-drain voltage (FIG. 10 (b)). In devices with comparable channel lengths, injection from PEDOT source / drain electrodes was found to be more efficient than injection from inorganic gold electrodes. This indicates that a polymerized source / drain electrode having an ionization potential that is well matched to the semiconducting one is preferred over an inorganic electrode material.
[0118]
The conductivity of PEDOT / PSS deposited from an aqueous solution (Baytron P) is approximately 0.1-1 S / cm. High conductivity up to 100 S / cm can be obtained with a composition containing a mixture of solvents (Bayer CPP 105T containing isopropanol and N-methyl-2-pyrrolidone (NMP)). In the latter case, care must be taken that the solvent combination of the composition is compatible with the solubility requirements of the layer sequence. For applications requiring uniformly high conductivity, other conductive polymers such as colloidal suspensions of metal inorganic particles in liquids or conductors suitable for processing in solution can be used. .
[0119]
The processes and devices described herein are not limited to devices made of polymer treated with a solution. Some of the conductive electrodes of the TFT and / or interconnects in a circuit or display element (see below) can be, for example, by printing a colloidal suspension or by electroplating a pre-patterned substrate It can be formed from inorganic conductors that can be deposited. In devices where all layers are not deposited from solution, one or more PEDOT / PSS portions of the device can be replaced with insoluble conductive materials such as vacuum deposited conductors.
[0120]
The semiconductive layer can be further replaced with a semiconductive material suitable for processing with another solution. Possible small conjugated molecules with solubilizing side chains (JG Laquindanum, et al., J. Am. Chem. Soc. 120, 664 (1998)), semiconductive organic-inorganic hybrids self-assembled from solution Examples include materials (CR Kagan, et al., Sciencs 286, 946 (1999)) or inorganic semiconductors (BA Ridley, et al., Science 286, 746 (1999)) deposited in solutions such as CdSe nanoparticles. Can be mentioned.
[0121]
The electrodes can be patterned by other techniques different from inkjet printing. Appropriate techniques include soft lithographic printing (JA Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (WO 99 / 10939) or plating, or simple dip coating of a patterned substrate having a hydrophobic surface area and a hydrophilic surface area. Ink jet printing is considered to be particularly suitable for large areas where patterns are formed with good resistance, especially for flexible plastic substrates.
[0122]
Instead of a glass sheet, one or more elements could be deposited on another substrate material such as Perspex or on a flexible plastic substrate such as polyethersulfone. Such materials are preferably sheet-shaped, preferably polymeric materials, and should be transparent and / or flexible.
[0123]
All layers and components of the element and circuit are preferably deposited and patterned by solution processing and printing techniques, while one or more components such as semiconductive layers are further deposited by vacuum deposition techniques. And / or may be patterned by a photolithographic process.
[0124]
An element such as a TFT made as described above is a more complex circuit or part of an element in which one or more such elements can be integrated with each other and / or other elements. . Examples of applications include logic circuits and active matrix circuit configurations for displays or memory elements, or user-defined gate array circuits.
[0125]
The basic component of the logic circuit is an inverter shown in FIG. If all the transistors on the substrate are either depletion type or accumulation type, three possible structures are possible. The depletion load inverter (FIG. 15 (a)) is usually suitable for devices that are (FIG. 1 (c) and FIG. 3), and the enhancement-load structure (FIG. 15 (b)) is usually an off-transistor (FIG. 15). 1 (a / b) and FIG. 4). The two structures each require a via hole between the load transistor and its source gate and drain electrodes. Another structure is a resistive load inverter (FIG. 15C). Resistive load inverter elements can be made by printing thin, narrow PEDOT lines of appropriate length and conductivity, such as load resistors. By reducing the conductivity of the PEDOT, for example, by increasing the ratio of PSS to PEDOT, the length of the resistor line can be minimized. The conductivity of Baytron P PEDOT / PSS having a PEDOT / (PEDOT + PSS) weight ratio of 0.4 was measured to be approximately 0.2 S / cm in the deposited film. N₂By annealing at 280 ° C. for 20 minutes under atmosphere, the conductivity increased to 2 S / cm. By diluting the solution with / PSS, the conductivity could be reduced by magnitude. For a PEDOT / (PEDOT + / PSS) weight ratio of 0.04, 10^-3The S / cm conductivity was measured after annealing at 280 ° C. A resistor with a resistance of 50 MΩ was made by inkjet printing a line of PEDOT having a width of approximately 60 μm and a length of 500 μm.
[0126]
Different inkjet printing components developed, i.e. transistors, via-hole interconnects, resistors, capacitors, multi-layer interconnects, etc. are integrated to create an integrated electronic circuit by a combination of direct printing and solution processing. Is possible. Inkjet printing can be used for all processing steps where lateral patterning is required. The simple inverter circuit described above is the basic unit for more complex logic circuits.
[0127]
Solution-treated TFTs as described above can be used in a liquid crystal (LCD) display with the appropriate circuit shown in FIG. 18 (a), or electrophoresis with the appropriate circuit shown in FIG. 18 (b). Active matrix displays such as displays (B. Comiskry et al., Nature 394, 253 (1998)); and as pixel switching transistors in light-emitting diode displays (H. Sirringhaus, et al., Science 280, 1741 (1998)) Or it can be used as an active matrix addressing element of a memory element such as a random access memory (RAM). In FIGS. 18 (a) and (b), the transistors T1 and / or T2 can be formed from transistors as described above. The functional unit 40 represents a display or memory element having current and voltage supply pads.
[0128]
  Examples of possible device structures for controlling the voltage of the electrodes of an LCD or electrophoretic display are:Including a gate insulating layer,The gate insulating layer includes a multi-layer structure containing a diffusion barrier and / or a surface modifying layer, as in FIG.
[0129]
Referring to FIG. 18, the TFT source and gate electrodes 2, 3 are connected to active matrix data lines 44 and addressing lines 43, which are different to achieve proper conductivity over the entire length. Made of conductive material. The drain electrode 3 of the TFT may further be a pixel electrode 41. The pixel electrodes can be formed from different conductive materials as in FIG. In elements that rely on the application of electric fields rather than charge carrier injection, it is not necessary for this electrode 41 to be in a direct contact display element 40 such as liquid crystal ink or electrophoretic ink. In this structure, the total pixel area occupied by the TFT and interconnect lines achieves an appropriate aperture ratio and reduces potential crosstalk between the display element 40 and the data and addressing lines 43, 44 signals. Therefore, it needs to be kept small.
[0130]
  ThanMore complexIn the structureAll or most of the pixel area can be used for TFT and interconnect lines, and the display elements are shielded from the data line 44 and addressing line 43 signals by the pixel electrode 41. thislikeThe creation of the structure involves adding an additional dielectric to connect the pixel electrode 41 to the TFT drain electrode 3.Layer andConductive materialQualityRequires via holes to be filled. Via holes can be created by the procedure described above.
[0131]
  Note that in this structure, the aperture ratio can be maximized and approached 100%. This structure can also be used for display applications with backlights such as LCD displays that can communicate because all polymer TFTs as made here are highly transparent in the visible spectral range.For example,F8T2 polymer TFAt TThe polymer chain is uniaxially aligned with a liquid crystalline semiconductive polymer rubbed to a polyimide alignment layer that also acts as a pre-patterned layer for high resolution printingBut itIs highly transparent in the majority of the visible spectral range due to the relatively high bandgap of F8T2.TheEven better transparency can be achieved when semiconductive layers such as F8, TFB, polyfluorene derivatives (US Pat. No. 5,777,070) with high band gap are used. The alignment of the polymer chains gives rise to optical anisotropy, so that light polarized parallel to the alignment direction (plot labeled with “||”) is labeled with the alignment direction (“⊥”). Are absorbed more strongly than light polarized perpendicular to the plot. Optical anisotropy is further applied to LCD displays to increase the optical transparency of the TFT by directing the alignment direction of the polymer chain perpendicular to the polarizer between the glass back and the backlight. Can be used. Under polarized light, the transistor element is almost colorless in visible light when the F8T2 layer thickness is 500 mm or less. All other layers of TFTs including PEDOT have low optical absorption in the visible spectral range.
[0132]
Another advantage of the optically low absorption of the semiconductive layer is the reduced TFT characteristic photoelectric sensitivity to visible light. In the case of amorphous silicon TFTs, the black matrix needs to be used to prevent large off-currents under optical illumination. In the case of polymer TFTs with wide band gap semiconductors, it is not necessary to prevent the TFTs from ambient light and from the backlight of the display.
[0133]
  Includes additional dielectric layers and via holes as described aboveThe structure further provides for the drive transistor T1 of the LED display by creating an interdigitated array of source and drain electrodes having a large channel width W where the TFT drive current uses a sufficient area directly below the pixel electrode 41 (FIG. 18 (b)).
[0134]
  Alternatively, the bottom gate TFT structure of FIG. 17 can also be used for all of the above applications.The
[0135]
One important technological issue for the creation of active matrix circuits is the contact between the PEDOT / PSS TFT and pixel electrodes 2, 3, 6 and the metal interconnect lines 43, 44, 41. Due to its strong acidic nature, PEDOT / PSS is not compatible with many common inorganic metals such as aluminum. Aluminum is easily oxidized in contact with PEDOT / PSS. One possible solution is to connect the interconnect lines and pixel electrodes 43, 44, 41 to indium tin oxide (ITO), or tantalum, tungsten, and other refractory metals, or to this environment or appropriate barrier layer. Made from other materials that have even greater stability in use.
[0136]
  For display applications, as further described above, ThingsIt is desirable to make a TFT with a narrow channel length by printing on a pre-patterned substrate.
[0137]
A similar device structure for an active matrix transistor switch is used when the pixel element to be controlled is not a display element but a memory element such as a capacitor or a diode, as in, for example, a dynamic random access memory. It is also possible.
[0138]
  In addition to the conductive electrode, some other layers of TFTs can be further patterned by direct printing methods such as screen printing or inkjet printing (IJP).For exampleThe active layer of the semiconductive layer 4 and the gate insulating layer 5 can be directly printed. In this case, via holes are not required, but the connection can be made by direct printing of a suitable gate electrode pattern 6. In areas where addressing lines 43 or internal connection lines 44 overlap, dielectric polymerーThin islands can be printed to provide electrical insulationThe
[0139]
A plurality of elements formed as described above can be formed on one substrate and interconnected by a conductive layer. The device can be formed at a single level or at more than one level, with some devices formed on top of the other. In particular, a compact circuit arrangement is formed using interconnect strips and via holes as described above.
[0140]
The technology developed here for the creation of inkjet printed transistors, via holes and interconnect lines can be used to create integrated electronic circuits by inkjet printing. A fabricated substrate containing an array of hydrophilic and hydrophobic surface regions can be used to define the channel length of the transistor and / or the width of the interconnect lines. The substrate can further contain an array of highly conductive metallic interconnect lines. Using a combination of inkjet printing and continuous layer deposition from solution, the array of transistor elements is defined with custom channel widths at custom locations. An integrated circuit is then created by making electrical connections between multiple pairs of transistors and appropriate internal connections using via holes and conductive line inkjet printing.
[0141]
It is also possible that the assembled substrate can already contain one or more components of the transistor element. The substrate can contain, for example, a completed array of inorganic transistor elements, each having at least one exposed electrode. In this case, the integrated circuit inkjet creation is the electrical connection between multiple pairs of transistors and single-level or multi-level interconnect deposition using inkjet printed via holes, interconnect lines and isolation pads. A connection is formed (see FIG. 15D).
[0142]
In addition to the transistor element, the electronic circuit can further comprise another active circuit element such as a display, a memory element, a capacitive element, a resistive element, and a passive circuit element.
[0143]
  Using the techniques described above, a unit having a plurality of transistors can be formed and then configured for a particular subsequent use by solution-based processing. For example, in the shape of a gate array, a plurality of transistors of the type shown in FIGS. 1A, 1B, or 1C are used.TThe substrate having, for example, can be formed on a plastic sheetTheAnother element, such as a diode or a capacitor, can further be formed on the sheet. Next, the sheetLeA printing head for a suitable solvent (eg, methanol) to form, and a conductive trap.TheForm and place in an inkjet printer with a suitable material (eg, PEDOT) to fill the via hole. Inkjet printers can operate under the control of a suitably programmed computer that recognizes the location and structure of the transistors on the sheet. Next, by combining the via hole composition and the internal connection step, the ink jet printer can configure a circuit that performs a desired electronic function or logic function by internally connecting transistors in a desired manner. This technology, as a result, makes it possible to compose a logic circuit on a substrate using small, inexpensive elements.
[0144]
  An example of the application of such a circuit is for the printing of active electronic tickets, travel goods and identification tags. A ticket or tag printing element can be mounted with a number of unconfigured units, each with a base that maintains a plurality of transistors. The ticket printing element includes a computer capable of controlling the ink jet printer as described above and capable of determining an electronic circuit that displays the validity function of the ticket. When a ticket needs to be printed, the printing element configures the substrate for the appropriate electronic circuit by printing via holes and / or conductive materials, so that the transistors on the substrate are properly configured Is done. The substrate can then be encapsulated, for example by sealing with an adhesive plastic sheet, and the electrical connection terminator.LeExpose. Tickets are then distributed. When a ticket is confirmed, the input is applied to one or more input terminals, and the output of the circuit of the one or more output terminals is monitored to verify its functionality. The ticket is preferably printed on a flexible plastic substrate for convenient use as a ticket.
[0145]
Other user-defined circuits for pricing or for tagging can be made in a similar manner. The verification and reading of the circuit can also be performed, for example, by remote probing using radio frequency radiation (Physics World March 1999, page 31).
[0146]
The end user's possibility to define the circuit by simple inkjet printing with the appropriate connection to the standard array is to provide significantly increased flexibility compared to the factory designed circuit.
[0147]
The present invention is not limited to the above-described examples. Aspects of the invention include all novel and / or inventive aspects of the concepts described herein, or inventive combinations of the features described herein.
[0148]
This invention includes all features or combinations of features disclosed herein, either implicitly, clearly, or in their entirety, without being limited to the scope of any of the definitions set forth above. Applicants are drawing attention to the fact that they can. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
[Brief description of the drawings]
FIG. 1 shows different device configurations of solution-treated all-polymer TFTs.
FIG. 2 shows the transfer characteristics of the polymer TFT according to FIG. 1c with F8T2 active layer, PVP gate insulating layer, and PEDOT / PSS gate electrode.
FIG. 3 shows the transfer characteristics of the polymer TFT according to FIG. 1c with F8T2 active layer, PVP gate insulating layer, and PEDOT / PSS gate electrode deposited at room temperature (a) and approximately 50 ° C.
FIG. 4 shows the output (a) and transfer characteristics (b) of an F8T2 all-polymer TFT including an F8 diffusion barrier and a PVP surface modification layer as in FIG. 1 (a).
FIG. 5 shows the transfer characteristics of an F8T2 all-polymer TFT as in FIG. 1 (a) with TFB (a) and polystyrene (b) diffusion barriers and PVP surface modification layers.
FIG. 6 shows an optical micrograph of an all-polymer TFT according to FIG. 1 (a) with F8T2 active layer and source-drain electrodes printed directly on an exposed glass substrate.
FIG. 7 shows the fabrication of a TFT with small channel length and small overlapping capacitance by patterning the substrate surface into hydrophobic and hydrophilic regions.
FIG. 8 shows an optical micrograph of the channel region of a transistor with L = 20 μm (a) and L = 5 μm (b) after IJP deposition of a PEDOT / PSS source / drain electrode near a hydrophobic polyimide bank.
FIG. 9 shows an optical micrograph taken during the deposition of ink droplets near a polyimide bank.
FIG. 10 shows the output and transfer characteristics of a transistor formed as in FIG. 7C and having L = 20 μm and 7 μm, respectively.
FIG. 11 shows the output and transfer characteristics of a transistor formed as in FIG. 7C and having L = 20 μm and 7 μm, respectively.
FIGS. 12A and 12B are schematic diagrams of (a) Dektak profile measurement and (b) optical micrographs of a process of forming a via hole by continuous adhesion of the outer diameter and inner diameter of the via hole determined by the diameter of the ink droplet.
FIG. 12-2 is a diagram showing the relationship between the outer diameter and inner diameter of a via hole, the diameter of an inkjet droplet, and the thickness of a PVP layer.
FIG. 13 shows current-voltage characteristics through a via hole having a bottom PEDOT electrode and a top electrode.
FIG. 14 shows different processes for manufacturing via holes.
FIG. 15 illustrates the application of via holes such as logic inverters (depletion load (a), enhancement load (b) and resistance load (c) and multi-level interconnect (d).
FIG. 16 shows the characteristics of an enhancement load inverter as in FIG. 1 (a) manufactured with printed all-polymer TFTs with two transistor different size W / L ratios.
FIG. 17 illustrates another bottom gate device configuration.
FIG. 18 shows a schematic diagram of an active matrix pixel in which the display or memory element is controlled by voltage (a) or current (b).
FIG. 19 illustrates a possible configuration of active matrix pixels.
FIG. 20 shows the polarized optical absorption of aligned F8T2 TFTs.
FIG. 21 (a) Overlapping regions between polymer TFTs with patterned active layer islands produced by printing semi-conductive layers and insulating layers and conductive interconnects separated by printed insulating islands. Indicates.
FIG. 22 shows a matrix of transistor elements connected by a network of IJP internal connections to produce a user defined electronic circuit.

Claims (47)

A source electrode and a drain electrode of the transistor to a method of forming on a substrate, before SL method,
Forming a mixture by mixing the electrode material with the liquid;
A first zone of the first region of the substrate, and a second zone of the second region of the substrate having a liquid repellency to the previous SL first zone is less than said mixture, by the first region and said third region of said substrate spaced apart from the second region, the third child of forming a containment structure comprising a zone on the substrate having a first liquid repellent on the zone is less than said mixture And
The mixture is confined in the second region and the third region by the relative liquid repellency of the first zone, and on the substrate such that it is not in the first region of the substrate. mixture how you characterized in that droplets adhere.   The method of claim 1, wherein a width of the first region between the second region and the third region is less than 20 μm.   The method of claim 1, wherein a width of the first region between the second region and the third region is less than 10 μm. The method according to claim 1, comprising the step of adhering other materials to the first region. 5. The method of claim 4 , wherein other material deposited on the first region forms a channel of the transistor. The method of claim 5, wherein the pre-SL other materials is semiconductive. The method according to any one of claims 4 to 6, wherein the other material is a polymeric material. 8. A method according to any one of claims 4 to 7 , wherein the other material is deposited from a solution. 9. The method of claim 8 , wherein the other material is deposited from a liquid solution that is not substantially water repellent by the first zone. A method of forming an electronic switching element including a conductive material or a semiconductive material in a plurality of regions on a substrate,
Forming a mixture by mixing the material and liquid;
A first zone of the first region of the substrate, and a second zone of the second region of the substrate having a liquid repellency to the previous SL Small said mixture Ri by the first zone, the second Forming a confinement structure on the substrate comprising a third zone of the substrate separated from the first region by a region and a third zone having a liquid repellency to the mixture that is greater than the second zone ; and the child,
The mixture is how you characterized by droplets adhering said mixture onto said substrate so as to be confined in the second zone by the relative liquid repellency of the first and third zones . The method of claim 1 0, wherein the width of said second zone being less than 20 [mu] m. The method of claim 1 0, wherein the width of said second zone being less than 10 [mu] m. The method according to any one of claims 1 0 to 1 2, wherein said material is electrically conductive. The electronic switching element is a transistor including a gate electrode and a source electrode and a drain electrode, according to claim 1 3 method, wherein said material forming said gate electrode of said transistor. The claims 1 to 4, the method according to the width of the overlap region between each gate electrode and the source electrode and the drain electrode is equal to or less than 20μm of the transistor. The claims 1 to 4, the method according to the width of the overlap region between each gate electrode and the source electrode and the drain electrode is equal to or less than 10μm of the transistor. The surface of the substrate is given by the self-assembled monolayer, and claim 1 0 to 1 the first and second zones of at least one, characterized in that defined by the patterning of self-assembled monolayer 6 The method in any one of. The method of claim 17 , wherein the step of patterning the self-assembled monolayer is performed by exposure to light through a shadow mask. The method of claim 18 , wherein patterning a self-assembled monolayer is performed by contacting the substrate with a soft stamp. Wherein the substrate comprises a planar structural members, said first and second zones, any one of claims 1 to 19, characterized in that it is formed on the exposed surface of the layer is deposited on said planar structural members The method described in 1. 21. A method according to any preceding claim , wherein the contact angle of the mixture in the first region is 20 degrees greater than the contact angle of the mixture in the second region. 21. A method according to any preceding claim , wherein the contact angle of the mixture in the first region is 40 degrees greater than the contact angle of the mixture in the second region. 21. A method as claimed in any preceding claim , wherein the contact angle of the mixture in the first region is 80 degrees greater than the contact angle of the mixture in the second region. 21. Any of the preceding claims , wherein the surface of the substrate is provided by a self-assembled monolayer and at least one of the first and second zones is defined by patterning of the self-assembled monolayer. The method of crab. Self-assembly step of patterning the monolayer, claims 2 to 4 The method according to, characterized in that it is performed by exposure to light through a shadow mask. The step of patterning the self-assembled monolayer, claims 2 to 4 The method according to, characterized in that it is carried out by contacting the substrate with the soft stamp. The surface of the substrate is given by a non-polar material, and any one of claims 1 to 26 wherein the first and second zones of at least one, characterized in that it is defined by the surface treatment of the non-polar polymer The method described in 1. 28. The method of claim 27 , wherein the nonpolar material is polyimide. 29. The method of claim 28 , comprising mechanically rubbing the polyimide to facilitate molecular alignment of the polyimide. 29. The method of claim 28 , comprising optically treating the polyimide to facilitate molecular alignment of the polyimide. 28. The method of claim 27 , wherein the surface treatment is etching. 28. The method of claim 27, wherein the surface treatment is a plasma treatment. 3. A method according to, characterized in that said plasma is a carbon tetrafluoride and / or oxygen plasma. 28. The method of claim 27 , wherein the surface treatment includes exposure to ultraviolet light. The method according to any one of claims 27 to 3 4, characterized in that said second zone is defined by the surface treatment of the non-polar polymer. 10. A method according to any one of claims 4 to 9 , wherein the first zone induces an aligned molecular structure of the other material. 10. A method according to any of claims 4 to 9 , wherein the first zone is capable of inducing polymer chain alignment in the other material . The method of claim 1, wherein the first zone, characterized in that it induces the alignment of the chain of the deposited polymeric material over said first zone. 38. The method of claim 37 , wherein the alignment is in a direction extending between the second and third zones. 40. A method according to any preceding claim, wherein the droplets of the mixture are deposited by ink jet printing. 46. A method according to claim 44 or 45 , wherein the droplets are deposited such that the mixture widens the boundary between the first zone and the second zone . The boundary between the first and second zones is optically different, and the method detects a boundary between the first and second zones, and in response to this detection, the ink jet printing element is the method of claim 4 0, characterized in that it comprises a step of positioning the substrate. 43. A method according to any preceding claim, wherein the material of the mixture is a polymer. The method according to any one of claims 1 to 39, wherein the material of said mixture is conjugated polymer. The method according to any one of claims 1 to 4 3 material of said mixture, characterized in that an inorganic fine particle that can be suspended in the liquid. 46. A method according to any preceding claim, wherein the transistor element or electronic element is part of a logic circuit, display element or memory element. 46. A method according to any preceding claim, wherein the transistor element or electronic element forms part of an active matrix array of transistors for a logic circuit, display element or memory element .

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