JP4979893B2 - Physical quantity distribution detection device, physical information acquisition method, and physical information acquisition device - Google Patents

Description

  The present invention relates to a physical quantity distribution detection device, a physical information acquisition method, and a physical information acquisition device. More specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged, and the physical quantity distribution converted into an electric signal by the unit components is converted into an electric signal. For example, the present invention relates to a technique for acquiring information for a predetermined purpose, which is suitable when using a physical quantity distribution detection device (physical quantity distribution detection device) such as a solid-state imaging device. In particular, the present invention relates to an exposure control (electronic shutter in a broad sense) function with a small accumulation period difference between pixels or lines.

  For example, physical quantities formed by arranging multiple unit components (for example, pixels) that are sensitive to changes in physical quantities, such as electromagnetic waves input from outside such as light and radiation, or pressure (contact etc.) Distribution detection semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell or an in-pixel amplifier). For example, many CMOS solid-state imaging devices have such a configuration (see, for example, Non-Patent Document 1).

Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publisher, August 10, 2003, First Edition: Chapters 6 and 7

  In such an amplification type solid-state imaging device, in order to read out a pixel signal to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are assigned to a predetermined address. The data is read out in order or arbitrarily. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  In the address-type solid-state imaging device, for example, a MOS transistor is used as a switching element for selecting a pixel or a switching element for reading a signal charge. Further, MOS transistors are used in the horizontal scanning circuit and the vertical scanning circuit, and there is an advantage that the switching element and the pixel portion can be manufactured with a series of configurations.

  For example, in a MOS type solid-state imaging device, each unit pixel has a MOS transistor, and the signal charge accumulated in the pixel by photoelectric conversion is read to the pixel signal generation unit, and the signal charge is read as a current signal or voltage signal. It is the structure which converts to and outputs.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons and holes) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element of the pixel signal generation unit and read out as image information.

  As a result, an output signal substantially linear with respect to the amount of charge accumulated in the unit pixel by photoelectric conversion is obtained from the pixel signal generation unit, and the dynamic range of the image sensor is determined by the amount of charge that can be accumulated in the unit pixel. The dynamic range of the image sensor is determined by the saturation signal amount and noise level of the pixel.

  By the way, in this type of XY address type solid-state imaging device, for example, a pixel unit is configured by arranging a large number of pixel transistors in a two-dimensional matrix, and a signal corresponding to incident light for each pixel or line (row). Accumulation of electric charge is started, and an electronic exposure time is controlled by reading out a current or voltage signal based on the accumulated signal charge from the imaging unit in order from each pixel by addressing. This is called an electronic shutter function in a broad sense. Here, in the MOS (including CMOS) type, as an example of address control, a method of simultaneously accessing one row and reading a pixel signal from a pixel unit in a row unit (hereinafter also referred to as a row unit readout method or a column readout method). ) Is often used.

  Even in an XY address type imaging apparatus, for example, signal charges are not read out in order to realize a narrowly-defined electronic shutter function that electronically sets the exposure time to a time different from the normal exposure time. In some cases, unnecessary signal charges are reset (discharged) from the pixels for one row to the signal lines in the horizontal blanking period.

  Here, in the XY address type imaging apparatus, the exposure time corresponding to the shutter speed of the electronic shutter, that is, the time corresponding to the pixel accumulation time is determined from the discharge time of the signal charge to the read time of the signal charge, Since the pixel signal is read for each exposure time (accumulation frame time) of each surface element, an accumulation sequential readout method is adopted. For this reason, a time difference occurs in the exposure of the pixels arranged in the plane. In the case of such a reading format, if the subject moves, the time for capturing light for each pixel is shifted, and “motion distortion” occurs in one screen. This is because a charge-coupled image sensor holds signals and reads them with delayed transfer, so that it becomes a storage-synchronized readout method that can synchronize the exposure of all pixels, and no “motion distortion” occurs in one screen. And very different.

  For example, in the row-by-row readout method, the accumulation period is shifted by the scanning time for each horizontal scanning line, so that there is a problem in that the accumulation time differs depending on the row (horizontal scanning line) on the right and left in the horizontal direction. This causes a problem of temporal shading distortion in which a fast moving subject is distorted and imaged.

<Conventional exposure time control function>
FIGS. 11 to 13 are diagrams for explaining a conventional exposure control (electronic shutter) function in an XY address type imaging apparatus. As shown in FIG. 11, the vertical address setting unit 414x of the vertical scanning unit 414 has a function of designating a normal readout target row address φTG, in addition to a row address of a shutter target unit pixel 403 (shutter pixel), that is, a shutter. It also has a function of generating address information (specifically, transfer gate pulses TGs as drive pulses) that specify pixel positions.

  From the shutter timing control functional element of the vertical address setting unit 414x, a wiring configuration is adopted in which the drive pulse φTGs for designating the row address to be shuttered is supplied to all the unit pixels 403 in the same row. Thereby, the unit pixel 403 in the row designated by the drive pulse φTGs is designated as the shutter pixel.

  When the CMOS image sensor 12 is used as a solid-state image sensor, generally, from the basic operation method, a pixel that outputs a signal starts accumulation of signal charges obtained by photoelectric conversion again from that point. For this reason, the accumulation period is shifted in accordance with the scanning timing of the imaging surface, that is, the accumulation period is shifted by the scanning time for each scanning line, which is so-called line exposure. Unlike CCD (Charge Coupled) type, global exposure that accumulates the light incident on the photoelectric conversion element during the same period as signal charge and reads it from all pixels to the vertical CCD at the same time to satisfy the simultaneous accumulation (Global Exposure) It is not.

  Here, for example, as shown in FIG. 11, a case is considered in which the readout row n and the shutter row ns are separated by Δs rows in the imaging region. Since the accumulation of signal charges starts again after the pixel in the target column of row ns that has received the instruction of the electronic shutter is reset, for example, when the scanning direction of the imaging surface is from top to bottom, row n and row n + Δs The time difference has a predetermined relationship between the frame rate and the number of scanning lines, and by adjusting the interval between the readout row n and the shutter row ns, the accumulation time of the signal read from the CMOS image sensor is set to the line period (1 The horizontal scanning period) can be changed as an adjustment unit.

  Here, in the conventional CMOS sensor, at the time of imaging one screen, the electronic shutter control is performed in units of rows by setting one readout row n and one shutter row ns. With respect to the readout row n at a certain point set by the vertical address setting unit 414x, the readout row for the pixels in all columns (H1, H2,..., Hh) by the shutter timing control functional element of the vertical address setting unit 414x. The pixel is reset by setting the shutter row ns at any row position except n, that is, at a position (time point) separated by Δs rows. This reset operation can be realized by sweeping away the charge accumulated in the photoelectric conversion element before the shutter timing. In the case of a CMOS image sensor, for example, it can be realized by turning on the transfer gate.

  The time until the pixels in the shutter row ns are set to the next readout row n by the vertical address setting unit 414x is the accumulation time, that is, the time interval between the readout row n and the shutter row ns is the accumulation time. As a result, the accumulation time can be controlled in units of rows. When setting the normal exposure time, the shutter row ns is not accessed, and charges are accumulated for the time corresponding to the frame rate.

  In this way, by utilizing the characteristic of line exposure of the CMOS image sensor, the driving pulse φTGs for electronic shutter is supplied to each unit pixel 403 in the row in units of rows, thereby reading row n and shutter row n + Δs. Can be set in each unit pixel 403 in units of rows, and the accumulation time can be easily controlled for each row.

  However, as described above, the XY address type image pickup apparatus employs an accumulation sequential readout method in which each surface element is read out every accumulation frame time. In this case, the drive pulse φTGs is supplied in units of rows, so the accumulation simultaneous readout is performed. This method is greatly different from the CCD type, which is a global exposure (see FIG. 12D), and becomes line exposure (also referred to as rolling shutter or focal plane accumulation) (see the lower part of FIG. 12A). ).

  When the shutter speed is slow and the pixel accumulation time is set sufficiently long, the shift in the accumulation period can be ignored, but if the shutter speed is set so fast that it does not differ from the horizontal scanning period, the horizontal direction of the object Due to the difference between the movement and the scanning time point (accumulation period) (see FIG. 12B), as shown in FIG. 12C, the difference in the accumulation period is the time in the line direction (row direction; horizontal scanning direction). Shading distortion (also referred to as focal poon phenomenon) appears as a motion distortion in the image and becomes a problem.

  In order to solve this problem, a function called a global shutter is realized in which a mechanical shutter is used in combination or the exposure accumulation period of each pixel is constant (exposure at the same time) when an electronic shutter operation is performed. A configuration is proposed. For example, for each pixel, a charge storage unit is provided between the charge generation unit and the pixel signal generation unit, and after exposing all pixels simultaneously, the signal charge generated by the charge generation unit is transferred to the charge storage unit at the same time. A structure has been proposed (see, for example, Patent Document 1).

US Pat. No. 5,986,297

  In the mechanism of the global shutter function described in Patent Document 1, signal charges generated by the incidence of light on the photoelectric conversion elements of the charge generation unit are transferred to and accumulated in the charge storage unit at the same time for all pixels. The pixel signals are sequentially converted at the read timing. In this method, light is incident on the photoelectric conversion element after the transfer, so that the charge accumulated in the charge generation unit is discharged prior to the next exposure accumulation.

  As a result, a pixel signal corresponding to the amount of signal charge accumulated in the charge accumulation unit can be obtained, and the exposure time without causing a difference in exposure accumulation period by adjusting the transfer timing to the charge accumulation unit after exposure. A control function can be realized.

  However, in the mechanism described in Patent Document 1, in order to realize a global shutter function that is an exposure time control function that does not cause a difference in accumulation period, the light is incident on the photoelectric conversion element of the charge generation unit. It is necessary to once transfer the signal charges to all the pixels simultaneously to the global shutter charge storage unit.

  For this reason, as shown in FIG. 13, for each unit pixel 403, a charge accumulation unit (floating diffusion 438 in the figure) is provided between the readout selection transistor 434 of the charge generation unit 432 and the pixel signal generation unit 432, and all pixels And a transfer gate unit 446 that exposes the charge generation unit (photodiode PD) 432 and transfers signal charges generated by the charge generation unit 432 to the charge storage unit (floating diffusion 438) at the same time. There is a need to.

  In this case, a transfer electrode (gate electrode) formed of a single layer or a two-layer structure of polysilicon, for example, is disposed on the substrate surface side of the transfer gate portion 446 and the charge storage portion (storage gate portion) 444. A frame shift pulse is input to the gate electrode of the transfer gate portion 446 (particularly referred to as the frame shift gate FSG), and a storage pulse is input to the gate electrode of the charge storage portion 444 (particularly referred to as the storage gate STG). As a result, the drive timing control becomes complicated.

  In addition, since the charge accumulation unit 444 is a part that accumulates charges for a period of 1H (H: horizontal scanning period) or more, the problem of dark current noise becomes larger than in the case of conventional line exposure.

  The present invention has been made in view of the above circumstances, and suppresses / eliminates the problem of dark current noise and accumulation period differences with a simple structure and control method even when signals are read out in units of rows. It is an object of the present invention to provide a mechanism with an approach (technical idea) different from the global shutter function described in Patent Document 1 that realizes an exposure time control function that can be performed.

According to the present invention, a plurality of light receiving elements as detection units that output a signal corresponding to the amount of incident light, and a plurality of unit pixels formed in a two-dimensional shape are divided into a plurality of vertical signal lines and a plurality of vertical control lines . An imaging unit configured to be connected , wherein the plurality of unit pixels formed in a two-dimensional shape are connected to the plurality of vertical signal lines so that unit pixel signals can be simultaneously read from a plurality of regions in units of rows. And
A vertical address setting unit and vertical drive unit for driving on the basis of the plurality of vertical control lines to the vertical address, the vertical address setting unit in cooperation with the selected shutter pixels in performing exposure time control operation, the respective regions A plurality of vertical control lines connected to each unit pixel, and a shutter timing control unit that performs an electronic shutter for controlling an exposure time or a charge accumulation time in a row unit for each region of the plurality of unit pixels. And
The detection signal of the detection unit of the unit pixel read to the plurality of vertical signal lines in accordance with the scanning of the vertical scanning unit is input, and the input detection signal is selected according to the scanning signal of the horizontal scanning unit A horizontal selection switch that outputs to the horizontal signal line;
Have
The shutter timing control unit selects a shutter row and sets a shutter pixel in order to perform the exposure time control operation when driving for the electronic shutter, and between the readout row selected by the vertical address setting unit By adjusting the time interval of the shutter pixels in the above, the exposure time to the unit pixel of the imaging unit is adjusted for each readout region,
A solid-state imaging device is provided.

Preferably, the shutter timing control unit, a control line which is divided into front Symbol plurality of regions, in the same vertical direction, sequentially drive control from one to the other.
Preferably, the shutter timing control unit, a control line which is divided into a front Symbol plurality of regions, a control line of the adjacent divided area, sequentially drives and controls the vertical direction of the mutually different orientations.
Preferably, the shutter timing control unit, a control line which is divided into a front Symbol plurality of regions, a control line sequentially toward both ends from the center of the divided areas, and drives the control.

Preferably, a frame memory is connected to the horizontal signal line, and detection signals of a plurality of unit pixels output from the horizontal signal line and read out by drive control of the control lines divided into the plurality of regions are output. Is stored in the frame memory in accordance with the position of the control line.

Preferably, when the number of the divided regions is three or more, the solid-state imaging device is configured as a back-illuminated solid-state imaging device.

According to the present invention, a plurality of light-receiving elements serving as detection units that output signals according to the amount of incident light, and a plurality of unit pixels arranged in a two-dimensional manner include a plurality of vertical signal lines and a plurality of control lines . performed against the imaging section, which is constituted by connection, a vertical address setting unit and vertical drive unit for driving on the basis of a plurality of control lines to the vertical address, an exposure time control operation in cooperation with the vertical driving unit A vertical scanning unit having a shutter timing control unit that selects a shutter pixel and performs an electronic shutter that controls an exposure time or a charge accumulation time for each region obtained by dividing the plurality of control lines into a plurality of regions. the inputs detection signals of the detecting portion of the unit pixel read out before Symbol plurality of vertical signal lines have accompanied with scanning of the vertical scanning unit, which is the input in accordance with the scanning signal of the horizontal scanning unit detects Select the signal And outputs to the horizontal signal line, a drive control method in the solid-state imaging device having a horizontal selection switch section,
The shutter timing control unit selects a shutter row and sets a shutter pixel in the same manner as during normal operation in the vertical address setting unit when driving for an electronic shutter, and reads out a row selected by the vertical address setting unit. Adjusting the exposure time to the detection unit of the imaging unit for each region by adjusting the time interval of the shutter pixels between
A drive control method in a solid-state imaging device is provided.

  For example, when dividing the detection area into a plurality of parts, it is preferable to divide the detection area equally.

  When the number of divisions is 3 or more, it is preferable that the physical quantity distribution detection device is a backside illumination type. Here, the back-illuminated type in the present invention is a wiring layer that forms a signal line for reading a unit signal from the unit signal generator from the detection region on one side of the element layer on which the detector is formed. Means that the physical quantity is configured to be incident on the detection unit from the other surface side of the element layer.

  Note that it is not essential that all the wirings for the unit signal generator are provided in the wiring layer on the other surface side, and at least the other region signal lines for reading out the unit signal from the detection region are the other side. The wiring layer may be provided on the wiring layer opposite to the surface side.

  According to the present invention, the detection area is divided into a plurality of areas, the same detection condition is set for each of the divided areas, and the unit signal is read from the unit component of each area.

  By dividing the detection area into a plurality of systems and simultaneously performing signal detection for each area and reading unit signals independent for each area, the accumulation time error within one frame is reduced, thereby reducing the image Motion distortion can be reduced. Although the exposure time control is performed for each area, the basic exposure control is the same as that of the conventional line exposure, so the control structure is simple and the dark current noise generated by the global shutter function described in Patent Document 1 is reduced. There is no problem.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example.

  However, this is merely an example, and the target device is not limited to a MOS imaging device. A semiconductor device for detecting a physical quantity distribution in which a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, are arranged in a line shape or a matrix shape, particularly for one row. Embodiments to be described later can be similarly applied to a row unit readout method in which all unit component elements are simultaneously accessed and unit signals are read out in row units.

<Configuration Example of CMOS Image Sensor; First Embodiment>
FIG. 1 is a schematic configuration diagram of a first embodiment of a CMOS image sensor which is an example of a solid-state imaging device. This CMOS image sensor is applied as an electronic still camera or FA (Factory Automation) camera capable of capturing a color image, for example.

  In the CMOS image sensor 12 of the first embodiment, unit pixels including a light receiving element (photoelectric conversion element such as a photodiode) as a detection unit (not shown) that outputs a signal corresponding to the amount of incident light are arranged in a square lattice of rows and columns. It has an arrayed (that is, a two-dimensional matrix) imaging unit, the signal output from each unit pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit and other functional units Is a column type provided for each vertical column.

  That is, as shown in FIG. 1, the CMOS image sensor 12 includes an imaging unit (pixel unit) 410 in which a plurality of unit pixels 403 (an example of unit components) are arranged in rows and columns (in a two-dimensional matrix). (Corresponding to the imaging unit 12a in FIG. 1), a so-called area sensor, a drive control unit 407 (corresponding to the drive control unit 12c in FIG. 1) provided outside the imaging unit 410, and columns arranged in each vertical column A column processing unit 420 (corresponding to the analog front end unit 12b in FIG. 1) having a signal processing unit (denoted as a column circuit in the figure) 422, a read current source unit 427, a horizontal selection switch unit 460, an output unit 488, It has.

  The read current source unit 427 is provided on a signal path (vertical signal line 418) between the imaging unit 410 and the column processing unit 420, and a drain terminal is connected to each vertical signal line 418 (not shown). A load transistor section including a load MOS transistor is arranged, and a load control section (load MOS controller) for driving and controlling each load MOS transistor is provided (see FIG. 2 described later).

  As the drive control unit 407, for example, a horizontal scanning unit 412 and a vertical scanning unit 414 are provided. Further, as another component of the drive control unit 407, operation of a drive signal for supplying a control pulse at a predetermined timing to each functional unit of the CMOS image sensor 12 such as the horizontal scanning unit 412, the vertical scanning unit 414, or the column processing unit 420. 416 (an example of a read address controller) is provided.

  Each element of the drive control unit 407 is integrally formed in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique together with the imaging unit 410, and is an example of a semiconductor system. It is configured as an element (imaging device).

  In FIG. 1, some of the rows and columns are omitted for simplicity, but in reality, tens to thousands of unit pixels 403 are arranged in each row and each column of the imaging unit 410. . Although illustration is omitted, the image pickup unit 410 is formed with a color separation filter having a predetermined color coding for each pixel. Although not shown, each pixel of the imaging unit 410 includes a photoelectric conversion element such as a photodiode and a transistor circuit (see FIG. 2 described later).

  The unit pixel 403 is output from the unit pixel 403 after being amplified by a vertical scanning unit 414 via a vertical control line 415 for selecting a vertical column and a unit signal generation unit having amplifying elements detected by a plurality of detection units. Are connected to the column processing unit 420 via vertical signal lines 418 as transmission lines for transmitting the pixel signals S0 (_1 to h; pixel numbers in one row).

  The horizontal scanning unit 412 and the vertical scanning unit 414 start a reading position selection operation (typically a shift operation) in response to a driving pulse given from the driving signal operation unit 416. The vertical control line 415 includes various pulse signals for driving the unit pixel 403.

  The horizontal scanning unit 412 defines a horizontal readout column (horizontal address) (selects each column signal processing unit 422 in the column processing unit 420), and a horizontal address setting unit 412x. And a horizontal driving unit 412y that guides each signal of the column processing unit 420 to the horizontal signal line 486 in accordance with the read address defined in FIG.

  Although not shown in the figure, the horizontal address setting unit 412x includes a shift register or a decoder, selects pixel information from the column signal processing unit 422 in a predetermined order, and selects the selected pixel information as a horizontal signal. It functions as a selection means for outputting to the line 486.

  The vertical scanning unit 414 defines a vertical readout row (vertical address) and a horizontal readout column (horizontal address) (selects a row of the imaging unit 410), and a vertical address setting unit 414x. A vertical drive unit 414y that drives by supplying a pulse to the control line for the unit pixel 403 on the readout address (in the horizontal direction) defined by the address setting unit 414x.

  In general, the vertical address setting unit 414x can be configured to perform electronic shutter control in units of rows in addition to the row from which a signal is read, but the electronic shutter control in the present embodiment is Unlike a normal CMOS sensor, the imaging unit 410 is divided into regions, and the shutter time (exposure time, charge accumulation time) is controlled in units of rows for each region.

  For this reason, in the present embodiment, the vertical scanning unit 414 includes a dedicated shutter timing control unit 414z separately from the vertical address setting unit 414x in order to perform electronic shutter control for each region. The shutter timing control unit 414z and the vertical drive unit 414y constitute a shutter control unit that supplies a drive pulse for realizing an exposure time control function (electronic shutter function) to the unit pixel 403 for each pixel.

  The shutter timing control unit 414z is for selecting a shutter pixel in performing the exposure time control operation, and constitutes an electronic shutter pixel selection unit together with the vertical drive unit 414y. The shutter timing control unit 414z sets the shutter pixel position by selecting the shutter row in the same manner as the normal operation in the vertical address setting unit 414x when driving for the electronic shutter, and the vertical address setting unit 414x performs the normal operation. By adjusting the time interval of the shutter pixels with respect to the selected readout row, the exposure time (accumulation time) for the photoelectric conversion element (detection unit) of the imaging unit 410 is adjusted for each region (details will be described later). ).

  Although not shown, the drive signal operation unit 416 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock necessary for the operation of each unit and a pulse signal at a predetermined timing, and an input clock via a terminal 401a. A communication interface functional block that receives data instructing CLK0, an operation mode, and the like, and outputs data DATA including information of the CMOS image sensor 12 via a terminal 401b. Further, the horizontal address signal is output to the horizontal address setting unit 412x and the vertical address signal is output to the vertical address setting unit 414x, and the address setting units 412x and 414x select the corresponding row or column in response thereto.

  The drive signal operation unit 416 may be provided as another semiconductor integrated circuit independently of other functional elements such as the imaging unit 410 and the horizontal scanning unit 412. In this case, an imaging device which is an example of a semiconductor system is constructed by the imaging device including the imaging unit 410 and the horizontal scanning unit 412 and the drive signal operation unit 416. This imaging device may be provided as an imaging module in which peripheral signal processing circuits, power supply circuits, and the like are also incorporated.

  The column processing unit 420 is configured to include a column signal processing unit 422 for each vertical column (column), and each column signal processing unit 422 receives a pixel signal for one row, and each column signal processing unit 422 receives a pixel signal of a corresponding column. S0 (_1 to h; pixel number in one row) is processed to output a processed pixel signal S1 (_1 to h; pixel number in one row).

  For example, although not shown, the column signal processing unit 422 includes a storage unit having a storage capacity, and is based on a pixel signal (unit signal) S0 read from the unit pixel 403 via the vertical signal line 418. A signal holding function of a line memory structure for storing a potential signal Vm representing physical information for a predetermined purpose can be provided. Similarly, it may have a storage capacity and be provided with a function of a noise removing means using a CDS (Correlated Double Sampling) process.

  When performing the CDS process, pixel information is obtained for pixel information in the voltage mode input via the vertical signal line 418 based on two sample pulses such as the sample pulse SHP and the sample pulse SHD given from the drive signal operation unit 416. By taking the difference between the signal level immediately after reset (noise level: 0 level) and the true signal level, fixed pattern noise (FPN) due to fixed variation for each pixel and noise called reset noise Remove signal components.

  Note that the column signal processing unit 422 may be provided with an AGC (Auto Gain Control) circuit having a signal amplification function or other processing function circuit, if necessary, at a subsequent stage such as a CDS processing function unit.

  At the subsequent stage of the column processing unit 420, a horizontal selection switch unit 460 having a horizontal reading switch (selection switch) (not shown) is provided. The output end of the column signal processing unit 422 in each vertical column is connected to the input end i of the selection switch of the horizontal selection switch unit 460 corresponding to each vertical column for sequentially reading the pixel signal S2 from the column signal processing unit 422. ing.

  The control gate terminal c of each vertical column of the horizontal selection switch unit 460 is connected to the horizontal driving unit 412y of the horizontal scanning unit 412 that controls and drives the readout address in the horizontal direction. On the other hand, a horizontal signal line 486 that sequentially transfers and outputs pixel signals in the row direction is commonly connected to the output terminals o of the selection switches in the vertical columns of the horizontal selection switch unit 460. An output unit 488 is provided at the rear end of the horizontal signal line 486.

  The horizontal signal line 486 transmits individual pixel signals S0 (specifically, pixel signals S2 based thereon) transmitted from the unit pixels 403 via the vertical signal lines 418 in the horizontal direction, which is the arrangement direction of the vertical signal lines 418. It functions as a readout line for outputting in a predetermined order, and a signal selected by a selection switch (not shown) existing for each vertical column is taken out from the column signal processing unit 422 and passed to the output unit 488.

  That is, the voltage signal of each vertical column corresponding to the signal charge representing the pixel information processed by the column signal processing unit 422 is generated by horizontal read pulses φg1 to φgh corresponding to the horizontal selection signals φH1 to φHh from the horizontal scanning unit 412. A selection switch provided for each vertical column to be driven is selected at a predetermined timing and read out to the horizontal signal line 486. Then, the signal is input to an output unit 488 provided at the rear end of the horizontal signal line 486.

  The output unit 488 amplifies the pixel signals S2_1 to h (h = n) of each unit pixel 403 output from the imaging unit 410 through the horizontal signal line 486 with an appropriate gain, and then outputs the signal as an imaging signal S3 to an external circuit (not shown). It is supplied via an output terminal 488. For example, the output unit 488 may perform only buffering, or may perform black level adjustment, column variation correction, color-related processing, or the like before that.

  That is, in the column type CMOS image sensor 12 of the present embodiment, the output signal (voltage signal) from the unit pixel 403 is the vertical signal line 418 → column processing unit 420 (column signal processing unit 422) → horizontal signal line 486. → Transmitted in the order of output unit 488. The drive is such that the pixel output signals for one row are sent in parallel to the column processing unit 420 via the vertical signal line 418, and the processed signals are serially output via the horizontal signal line 486. The transfer operation of the pixel signal to the column processing unit 420 is simultaneously performed on the unit pixels 403 for one row.

  As long as driving for each vertical column or horizontal column is possible, each pulse signal is supplied to the unit pixel 403 from either the horizontal direction or the vertical column direction, that is, driving for applying a pulse signal. The physical wiring method of the clock line is free.

  In the CMOS image sensor 12 having such a configuration, the horizontal scanning unit 412 and the vertical scanning unit 414 and the drive signal operation unit 416 for controlling them are used to sequentially select each pixel of the imaging unit 410 in the horizontal unit. A CMOS image sensor of a type that simultaneously reads out information of one horizontal parallel pixel is configured.

  An external circuit (not shown) provided at the subsequent stage of the output unit 488 is a substrate (printed substrate or semiconductor substrate) different from the solid-state imaging device in which the imaging unit 410 and the drive control unit 407 are integrally formed in the same semiconductor region. The circuit configuration corresponding to each photographing mode is adopted.

  A solid-state imaging device (an example of a semiconductor device or a physical information acquisition device according to the present invention) including an imaging unit 410, a drive control unit 407, and the like and an external circuit constitute a CMOS imaging device 12 as a solid-state imaging device. The drive control unit 407 is separated from the imaging unit 410 and the column processing unit 420, and the imaging unit 410 and the column processing unit 420 constitute a solid-state imaging device (an example of a semiconductor device). You may comprise with the control part 407 as an imaging device (an example of the physical information acquisition apparatus which concerns on this invention).

  Although an example in which the external circuit in charge of signal processing in the subsequent stage of the solid-state image sensor is performed outside the solid-state image sensor (imaging chip) is shown here, all or a part of the external circuit (for example, an A / D converter or digital) The functional element of the amplifier unit or the like may be built in the chip of the solid-state imaging device. That is, the imaging unit 410, the drive control unit 407, and the like constitute an external circuit on the same semiconductor substrate as the solid-state imaging element integrally formed in the same semiconductor region, and are substantially similar to the solid-state imaging device and physical information. You may comprise as an acquisition apparatus and the same thing.

  In the figure, the horizontal selection switch unit 460 and the drive control unit 407 are provided together with the imaging unit 410 to constitute the CMOS imaging element 12 as a solid-state imaging device, and the solid-state imaging device substantially functions as a physical information acquisition device. However, the physical information acquisition device is not necessarily limited to such a configuration. It is not a requirement that the entire horizontal selection switch unit 460 and the drive control unit 407 or one functional part be integrally formed in the same semiconductor region as the imaging unit 410. The horizontal selection switch unit 460 and the drive control unit 407 are formed on a circuit board different from the imaging unit 410 (which means not only another semiconductor substrate but also a general circuit board), for example, a circuit board on which an external circuit is provided. May be.

  Here, in the CMOS image sensor 12 of the present embodiment, a functional unit that reads and processes pixel signals generated by the imaging unit 410 in which a plurality of unit pixels 403 are arranged while dividing the imaging unit 410 into a plurality of regions. The first feature is that a plurality of systems (particularly the column processing unit 420) are provided. In addition, the second feature is that the processing units of the plurality of systems are divided and arranged at positions opposite to the two-dimensional region of the imaging unit 410.

  In particular, in the CMOS image sensor 12 of the first embodiment, the imaging unit 410 is divided equally so that the pixel lines in the two regions are the same, corresponding to the first feature point, and the second feature. Corresponding to the points, the functional units (column processing unit 420, horizontal scanning unit 412, horizontal selection switch unit 460, output unit 488) for reading out and processing the pixel signals are divided into two systems (N = 2), respectively. It is characterized in that it is arranged with the imaging unit 410 interposed therebetween.

  Specifically, as shown in FIG. 1, the vertical signal line 418 is equally divided into two areas in the upper and lower directions (respectively, reference elements u and d are attached), and the upper area 410 u and the lower area of the imaging unit 410 are divided. 410d is configured to read out pixel signals in independent row units while simultaneously accumulating charges in row units, that is, setting an exposure time by an electronic shutter. For this purpose, it is necessary to provide the column processing unit 420 independently at a minimum.

  For example, the column processing unit 420, the read current source unit 427, the horizontal scanning unit 412, the horizontal selection switch unit 460, the horizontal signal line 486, and the output unit 488 are paired (represented with reference elements a and b, respectively). Thus, each pair is arranged separately in two vertical directions of the vertical signal line 418. In the figure, a and b are arranged, the a system for one vertical signal line 418a is arranged on the lower side in the figure, and the b system for the other vertical signal line 418b is arranged on the upper side in the figure. Yes.

  In this case, the potential signals Vma and Vmb held in the storage unit (not shown) provided in the two systems of column signal processing units 422a and 422b are independently (in terms of time may be processed simultaneously). The signals are read out to the horizontal signal lines 486a and 486b and transferred to the output units 488a and 488b, and a synthesis process for generating one screen is performed using the output signals S3a and S3b at the subsequent stage of the output units 488a and 488b.

<Relationship between unit pixel circuit configuration example and drive circuit>
FIG. 2 shows a configuration example of a unit pixel (pixel cell) 403 used in the CMOS image sensor 12 shown in FIG. 1 and a driving circuit related to an exposure time control (electronic shutter) function for driving the unit pixel 403 (FIG. 2). 2 is a diagram for explaining a relationship with one vertical scanning unit 414, particularly a shutter timing control unit 414z).

  The configuration of the unit pixel 403 in the imaging unit 410 is the same as that of a normal CMOS image sensor. In this embodiment, a general-purpose 4TR configuration can be used as the CMOS sensor, and the 4TR configuration can be used. For example, as described in Japanese Patent No. 2708455, a 3TR configuration having three transistors can be used. Of course, these pixel configurations are merely examples, and any CMOS image sensor array configuration can be used.

  As the intra-pixel amplifier, for example, a floating diffusion amplifier configuration using a floating diffusion (FDA) having a diffusion layer having a parasitic capacitance as a main part as a charge storage part is used. As an example, with respect to the charge generation unit, a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, and a vertical selection for setting a row address A configuration having a transistor and an amplifying transistor having a source follower configuration, which is an example of a detection element that detects a change in potential of the floating diffusion, can be used.

  For example, the unit pixel 403 shown in FIG. 2 has a four-transistor pixel configuration (4TR configuration) in which four transistors (TRansistors) are included in the unit pixel. Specifically, the unit pixel 403 has a photoelectric conversion function for receiving light and converting it into a charge, and a charge generation composed of a photodiode, a photogate, and the like having both functions of a charge storage function for storing the charge. Compared to the unit 432 and the charge generation unit 432, a read selection transistor (transfer transistor) 434 which is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor 436 which is an example of a reset gate unit, and a vertical selection And an amplifying transistor 442 having a source follower configuration which is an example of a detection element that detects a change in potential of the floating diffusion 438.

  The horizontal wiring is common to the pixels in the same row, and during normal driving without electronic shutter control, all unit pixels 403 in the same row are simultaneously driven and controlled by the vertical driving unit 414y of the vertical scanning unit 414. For example, a transfer drive buffer 452, a reset drive buffer 454, and a selection drive buffer 456 are accommodated in the vertical drive unit 414y.

  The unit pixel 403 includes a pixel signal generation unit 405 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 438 that is an example of a charge injection unit having a function of a charge storage unit. The pixel signal generation unit 405 is an example of a unit signal generation unit that generates a pixel signal as a unit signal. The pixel signal generation unit 405 generates a potential corresponding to the amount of charge transferred from the charge generation unit 432 to the floating diffusion 438 to generate a vertical signal. It functions as a means for transmitting to the line 418. The floating diffusion 438 has a diffusion layer having parasitic capacitance in the main part.

  In the reset transistor 436 in the pixel signal generation unit 405, the source is connected to the floating diffusion 438, the drain is connected to the power supply VDD, and the reset pulse RST is input from the reset drive buffer 454 to the gate (reset gate RG). The reset transistor 436 has a function of resetting the potential of the floating diffusion 438.

  Here, the unit pixel 403 is a pixel having a 4TR configuration including a vertical selection transistor 440 inserted in series with the amplification transistor 442, and the unit pixel 403 includes the amplification transistor 442 and the vertical selection transistor 440. Of these, the amplification transistor 442 is of a type on the vertical signal line 418 side.

  That is, the vertical selection transistor 440 has a drain connected to the power supply VDD, a source connected to the drain of the amplification transistor 442, and further connected to the vertical signal line 418 (418), and a gate (in particular, a vertical selection gate SELV) is vertical. A selection line 457 is connected. A vertical selection signal SEL is applied to the vertical selection line 457.

  As an example, the amplifying transistor 442 has a gate connected to the floating diffusion 438 on the output side of the read selection transistor 434, a drain connected to the source of the vertical selection transistor 440, and a source connected to the pixel line 451. It is connected to the signal line 418 (418).

  The amplifying transistor 442 is connected to the vertical signal line 418 via the pixel line 451, and the vertical signal line 418 is a load MOS transistor 427z that forms part of the constant current source In of the read current source unit 427 for each vertical column. A load control signal SFLACT from a load control unit (not shown) is commonly input to the gate terminals of the load MOS transistors 427z.

  The amplifying transistor 442 continues to flow a predetermined constant current by a load MOS transistor 427z connected to each amplifying transistor 442 at the time of signal reading. In other words, the load MOS transistor 427z makes a signal output to the vertical signal line 418 by assembling a source follower with the amplification transistor 442 in the selected row.

  Although not limited to such a connection configuration, illustration of the vertical selection transistor 440 and the amplification transistor 442 is reversed, and the drain of the vertical selection transistor 440 is connected to the source of the amplification transistor 442. May be connected to the vertical signal line 418 (418) via the pixel line 451, and the gate may be connected to the vertical selection line 457.

  In the 4TR configuration as shown in FIG. 2, since the floating diffusion 438 is connected to the gate of the amplifying transistor 442, the amplifying transistor 442 outputs a signal corresponding to the potential of the floating diffusion 438 (hereinafter referred to as FD potential) in the voltage mode. Thus, the signal is output to the vertical signal line 418 (418) via the pixel line 451.

  The reset transistor 436 resets the floating diffusion 438. The read selection transistor (transfer transistor) 434 transfers the signal charge generated by the charge generation unit 432 to the floating diffusion 438. A large number of pixels are connected to the vertical signal line 418. To select a pixel, the vertical selection transistor 440 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 418, and the signal of the selected pixel is output to the vertical signal line 418.

  Here, as the wiring for the unit pixel 403, three of a transfer gate wiring (read selection line TRG) 453, a reset wiring (RST) 455, and a vertical selection line (SEL) 457 for row address selection are arranged in the horizontal direction. The vertical signal line 418 and the drain line (Vdd supply wiring) are laid in the vertical direction, and internal wiring (wiring in the pixel) such as connecting the floating diffusion 438 and the gate of the amplifying transistor 442 is laid. Further, although not shown here, there are two-dimensional wirings used for the light shielding film for the pixel boundary portion and the black level detection pixel.

  Further, as a component unique to the present embodiment, the unit pixel 403 is configured such that at least a transfer gate pulse for adjusting the exposure time is supplied from the vertical scanning unit 414 to the transfer drive buffer 452 for each row. . If necessary, the reset gate pulse RST for adjusting the exposure time may be supplied to the reset transistor 436 for each row.

  For example, the vertical scanning unit 414 has a vertical address setting unit 414x as a dedicated functional unit for controlling the accumulation time (exposure time) in addition to the vertical address setting unit (normal scanning) 414x for setting a readout row related to normal scanning. As in the normal operation, the vertical shutter timing control unit 414z that outputs a transfer gate pulse TGs for selecting a row of a unit pixel (shutter pixel) to be shuttered is provided, and a normal readout row and a row of shutter pixels The interval (that is, the row position of the shutter pixel) can be specified.

  Further, according to the configuration of the shutter timing control unit 414z, the vertical drive unit 414y drives the read selection transistor 434 with respect to the normal read row and the selected row of the shutter pixels at least with respect to the transfer drive buffer 452.

  The transfer drive buffer 452 applies a read pulse (transfer gate pulse) TG designating a normal read row from the vertical address setting unit 414x and a transfer gate pulse TGs designating a shutter pixel row from the vertical shutter timing control unit 414z. On the other hand, a logical sum circuit is configured to operate.

  The read selection transistor 434 is driven by a transfer signal TRG from the transfer drive buffer 452 via a transfer gate line (read selection line TRG) 453. The reset transistor 436 is driven by a reset signal φRST from the reset drive buffer 454 via a reset wiring (RST) 455. The vertical selection transistor 440 is driven by a vertical selection signal φSEL from the selection drive buffer 456 via a vertical selection line (SELV) 457. Each drive buffer can be controlled by a vertical address setting unit 414x or a shutter timing control unit 414z.

  Here, in the present embodiment, the shutter timing control unit 414z that controls the charge accumulation time for each row has a predetermined column position on a predetermined row via the transfer drive buffer 452 and the transfer gate wiring (read selection line) 455. The readout selection transistor 434 of the unit pixel 403 is controlled. The readout row control by the vertical address setting unit 414x is control in units of rows, and the shutter timing control unit 414z controls the shutter row position accordingly.

  The storage timing is controlled by dividing the assigned rows by the shutter timing control unit 414z for controlling the accumulation time and the vertical address setting unit 414x for controlling the address position (row) for normal reading. In other words, by using the time difference between the row addresses in the vertical column direction for setting the exposure time, an exposure time control function with the line period as one adjustment unit is realized.

  Further, as will be described in detail later, as a feature point of the exposure time control function of the present embodiment, the imaging unit 410 is divided into a plurality of regions, and a readout row and a shutter row are similarly set for each region. The transfer operation of the pixel signals to the column processing unit 420 is simultaneously performed for all the unit pixels 403 for one row.

  In addition, such accumulation time setting is not performed only by the vertical address setting unit 414x, but a shutter timing control unit 414z dedicated to the electronic shutter is provided to control the accumulation time, so that the control is easy. Become.

  In addition, instead of performing exposure time control in units of rows, for example, after reading out the pixel signal on the long-time accumulation side within the same horizontal period, the short-time accumulation is performed, and the pixel on the short-time accumulation side is immediately It is also possible to read out the signal. However, in this case, since the short-time accumulation side has an accumulation time of one horizontal period (for example, 64 microseconds) or less, there is no flexibility in setting the accumulation time on the short-time side.

<Exposure Time Control Function; First Embodiment>
3 and 4 are diagrams for explaining the exposure time control function when the CMOS image sensor 12 of the first embodiment is used.

  As shown in FIG. 3, the vertical scanning unit 414 has a normal read target row address φTG as a functional element that generates address information (specifically, transfer gate pulses TGs as drive pulses) for designating shutter pixel positions. In addition to the vertical address setting unit 414x for designating, a shutter timing control unit 414z for designating the row address φTGs of the unit pixel 403 (shutter pixel) to be shuttered is provided.

  Here, the vertical address setting unit 414x and the shutter timing control unit 414z of the first embodiment simultaneously output the row addresses φTG and φTGs one row at a time in each of the upper region 410u and the lower region 410d. The same exposure condition as the same detection condition, that is, the shutter speed is set for each region.

  For this reason, the vertical address setting unit 414x supplies the drive pulses φTGu and φTGd for designating the normal readout row for each region to all the unit pixels 403 in the same row in each of the upper region 410u and the lower region 410d. Adopt a simple wiring configuration. As a result, the unit pixel 403 of each readout row nu, nd of the upper region 410u and the lower region 410d designated by the drive pulses φTGu, φTGu is designated as a readout pixel.

  The shutter timing control unit 414z supplies the drive pulses φTGsu and φTGsd for each region designating the row address to be shuttered to all unit pixels 403 in the same row in each of the upper region 410u and the lower region 410d. Adopt a simple wiring configuration. As a result, the unit pixel 403 of each shutter row nsu, nsd in the upper region 410u and lower region 410d designated by the drive pulses φTGsu, φTGsu is designated as the shutter pixel.

  Here, in the upper region 410u and the lower region 410d, the readout row nu and the shutter row nsu are separated by Δsu rows, and the readout row nd and the shutter row nsd are separated by Δsd rows, and Δsu = Δsd. By adjusting the interval Δsu between the readout row nu and the shutter row nsu while maintaining the same interval Δsd between the readout row nd and the shutter row nsd, the upper region 410u with the line period (one horizontal scanning period) as an adjustment unit. In each of the lower region 410d and the lower region 410d, the accumulation time of signals read from the CMOS image sensor (that is, the exposure time by the electronic shutter) can be controlled to be the same.

  When the lower region 410d and the upper region 410u of the imaging unit 410 are arranged in two vertical signal lines 418a and 418b in pairs, the signal processing units divided into two systems are arranged at the same time. When reading out independent pixel signals while performing charge accumulation in units (exposure time setting by an electronic shutter), there is a degree of freedom as to where the vertical scanning start points STd and STu are located. As an example, as shown in FIG. 4B, it may be set at the boundary between the lower region a and the upper region b.

  Like the configuration of the CMOS image sensor 12 of the first embodiment, the image pickup unit 410 is divided into two systems (N = 2) such as a lower region 410d and an upper region 410u, and pixel signals are received from the image pickup unit 410. Even when the functional units (column processing unit 420, horizontal scanning unit 412, horizontal selection switch unit 460, and output unit 488) to be read and processed are divided into two systems (N = 2), the shutter speed is equal to the horizontal scanning period. When the speed is set so fast that it does not change, due to the difference between the horizontal movement of the object and the scanning time point (see FIG. 4B), as shown in FIG. Time shading distortion in the line direction (row direction; horizontal scanning direction) appears in the image.

  However, by dividing the region into two systems (N = 2) and simultaneously storing charges in units of rows, and reading out independent pixel signals, the amount of temporal shading distortion, that is, within one frame (Frame), can be obtained. The motion distortion of the image can be reduced by reducing the storage time error of the image, specifically by reducing the error to ½ compared to the conventional case. As an additional effect, reading of unit signals independent for each region is performed simultaneously, that is, in parallel, while simultaneously performing signal detection for each divided region, so that the reading time in the vertical direction can be shortened.

  Although exposure time control is performed for each area, the basic exposure control is the same as that of the conventional line exposure, and dark current noise caused by accumulating charges for a period of 1 H or more in the global shutter function described in Patent Document 1. No problem arises. Basic exposure control is the same as conventional line exposure, and it is only necessary to perform address control in the same manner for each area to be divided. Since this control only sets a plurality of address positions, the control structure is simple. It is.

  Further, as in the first embodiment, if each pair of signal processing units divided into two systems is arranged in two vertical directions of the vertical signal line 418, pixels generated by the unit pixel 403 are generated. One vertical signal line 418a and 418b for extracting a signal may be provided in each of the lower region 410d and the upper region 410u of the imaging unit 410 (N / 2 = 2/2 = 1). Since the wiring state of the signal lines 418a and 418b can be regarded as substantially one as in the conventional configuration, unlike the second embodiment described later, the vertical signal lines 418a and 418b may block light. Absent.

<Variation 1 of the first embodiment>
FIG. 5 is a diagram for explaining a first modification of the exposure time control function when the CMOS image sensor 12 of the first embodiment is used.

  In the exposure time control operation of the first embodiment, the vertical scanning of the divided lower region 410d and upper region 410u is set at the boundary between the lower region a and the upper region b. However, other settings can be made.

  For example, as shown in FIG. 5A, the scanning start point STu of the upper area 410u is set to the boundary of the lower area a and the upper area b while the scanning start point STd of the lower area 410d is set to the boundary of the imaging unit 410. It can also be set at the top. In this case, the scanning end point ENu of the upper region 410u is the boundary between the lower region a and the upper region b, similarly to the scanning start point STd of the lower region 410d.

  In contrast to the case shown in FIG. 5A, as shown in FIG. 5B, the scanning start point STu of the upper region 410u is set at the boundary between the lower region a and the upper region b. The scanning start point STd of the lower area 410d can also be set at the bottom of the imaging unit 410. In this case, the scanning end point ENd of the lower region 410d is the boundary between the lower region a and the upper region b, similarly to the scanning start point STu of the upper region 410u.

  As described above, even when the starting point of the vertical scanning is set at various positions, it is divided into two systems (N = 2), and independent pixel signals can be read out while simultaneously storing charges in units of rows. Since this can be done, the time shading distortion can be reduced to ½ compared to the conventional case. Since the wiring state of the vertical signal lines 418a and 418b in the entire image pickup unit 410 can be regarded as substantially one as in the conventional configuration, there is no possibility that the vertical signal lines 418a and 418b block light.

  In addition, the purpose of the first feature point in the first embodiment is to divide the imaging unit 410 that is a detection region into a plurality of systems and perform signal detection under the same detection condition for each region at the same time. This is to reduce the amount of temporal shading distortion compared to the conventional one by reading out unit signals independently for each region. As long as this is the case, the region is divided evenly so that the pixel lines in the two regions are the same. It is not essential to do. For example, as shown in FIG. 5C, even if the area is divided so that the number of lines belonging to the upper area 410u is smaller than the number of lines belonging to the lower area 410d, temporal shading distortion is reduced as compared with the conventional case. can do.

<Modification 2 of the first embodiment>
FIG. 6 is a diagram for explaining a second modification of the exposure time control function when the CMOS image sensor 12 of the first embodiment is used.

  The greatest point in the first embodiment is that a functional unit (particularly a column) that reads and processes pixel signals generated by the imaging unit 410 in which a plurality of unit pixels 403 are arranged while dividing the imaging unit 410 into a plurality of regions. This is a first feature point in which a plurality of processing units 420) are provided, and a second feature point is provided in which the processing units of the plurality of systems are arranged at positions opposite to the two-dimensional region of the imaging unit 410. That is not essential.

  For example, as shown in FIG. 6, a column processing unit 420, a horizontal scanning unit 412, a horizontal selection switch unit 460, a horizontal signal line 486, and an output unit 488 are paired (represented with reference elements a and b, respectively). Thus, each pair can be arranged in one of the two vertical directions of the vertical signal line 418. In the figure, a / b is used, and both the a system for one vertical signal line 418a and the b system for the other vertical signal line 418b are arranged on the lower side in the figure.

  As described above, the scanning start points STd and STu for vertical scanning of the divided lower region 410d and upper region 410u can be set at various positions as described above.

  Also in the embodiment shown in FIG. 6, the potential signals Vma and Vmb held in the storage unit (not shown) provided in the two systems of column signal processing units 422a and 422b are processed independently (in parallel with time, May be read out to the horizontal signal lines 486a and 486b and passed to the output units 488a and 488b, and a composition for generating one screen using the output signals S3a and S3b at the subsequent stage of the output units 488a and 488b. Perform processing.

  In such an embodiment shown in FIG. 6 as well, it is possible to read out independent pixel signals while dividing the region into two systems (N = 2) and simultaneously storing charges in units of rows, respectively. The shading distortion can be reduced to ½ compared to the conventional case.

  However, as can be seen from FIG. 6, the wiring state of the vertical signal lines 418a and 418b of the entire imaging unit 410 is per pixel column in either the lower region 410d or the upper region 410u (lower region 410d in the figure). N (two in this example) need to be arranged in parallel. That is, not only the vertical signal line 418 for the area to which the pixel belongs but also the vertical signal lines 418 for other areas need to be drawn out to the imaging unit 410 in the same direction position.

  When forming a wiring layer that forms a wiring with respect to the active element of the imaging unit 410, a surface sensor having a normal surface-receiving pixel structure that takes incident light into the photoelectric conversion element from the same surface side as the wiring layer is used in addition to this. The vertical signal line 418 for the above region becomes a factor that blocks light.

  In order to solve this problem, a back-illuminated sensor structure may be used as in the second embodiment described later. In the back-illuminated type, a wiring layer that forms a wiring with respect to the active element is formed on one surface side of the element layer on which the photoelectric conversion element is formed, and incident light is transmitted to the other surface side of the element layer, that is, A back-side light-receiving pixel structure that takes in the photoelectric conversion element from the side opposite to the wiring layer is employed. By adopting such a back-surface light receiving type pixel structure, the need for wiring considering the light receiving surface is eliminated. That is, wiring can be performed on the photoelectric conversion element region without worrying about the problem of light shielding by wiring, and the degree of freedom of wiring is increased.

  Therefore, when the pixel signals for the lower region 410d and the upper region 410u divided into regions are read in the vertical direction, a plurality of vertical signal lines (such as the vertical signal lines 418a and 418b) can be used without worrying about light blocking factors. 2 in this example) can be arranged in parallel.

<Configuration Example of CMOS Image Sensor; Second Embodiment>
FIG. 7 is a schematic configuration diagram of a second embodiment of a CMOS image sensor 12 which is an example of a solid-state image sensor. The CMOS image sensor 12 of the second embodiment divides a functional unit (particularly the column processing unit 420) that reads and processes a pixel signal generated by the imaging unit 410 while dividing the imaging unit 410 into three or more regions. It has the 1st characteristic in the point provided only. In addition, the second feature is that the processing units for the region divisions are arranged in a plurality of positions with respect to the two-dimensional region of the imaging unit 410.

  In particular, in the CMOS image sensor 12 of the second embodiment, the imaging unit 410 is equally divided into four regions so that the pixel lines in the two regions are the same, corresponding to the first feature point, It is characterized in that four column processing units 420 for reading and processing pixel signals are provided. Corresponding to the second feature point, the horizontal scanning unit 412, the horizontal selection switch unit 460, the horizontal signal line 486, and the output unit 488 are divided into two systems (N = 2), respectively, and these are sandwiched by the imaging unit 410. It is characterized in that it is arranged on both sides.

  Specifically, as shown in FIG. 7A, column processing units 420a and 420b corresponding to the lower region 410a in charge of the vertical signal line 418a and the lower region 410b in charge of the vertical signal line 418b are provided. The column processing units 420c and 420d corresponding to the upper region 410c in charge of the vertical signal line 418c and the upper region 410d in charge of the vertical signal line 418d are arranged on the upper side in the drawing.

  In addition, a horizontal scanning unit 412d, a horizontal selection switch unit 460d, a horizontal signal line 486d, and an output unit 488d are respectively shown in the drawing as functional units that read signals from the column processing units 420a and 420b arranged on the lower side in the horizontal direction. A horizontal scanning unit 412u, a horizontal selection switch unit 460u, a horizontal signal line 486u, and an output unit 488u are provided as functional units that are arranged on the lower side and read out signals from the column processing units 420c and 420d arranged on the upper side in the horizontal direction. Arranged on the upper side in the figure.

  In this case, potential signals Vma and Vmb held in a storage unit (not shown) provided in the lower two column signal processing units 422a and 422b are converted into horizontal signals in a predetermined order (for example, from left to right in the figure). Read to line 486d and pass to output 488d. Further, the potential signals Vmc and Vmd held in the storage unit (not shown) provided in the upper two column signal processing units 422c and 422d are applied in the predetermined order (for example, from the left to the right in the figure) with the horizontal signal line 486u. To the output unit 488u. This horizontal reading is performed independently in the upper and lower directions (same time parallel processing may be used). Then, after the output units 488d and 488u, a synthesis process for generating one screen is performed using the output signals S3d and S3u.

  The horizontal selection switch unit 460, the output unit 488, the horizontal scanning unit 412, and the output unit 488 are also divided into four systems corresponding to the four divisions (a, b, c, d) of the column processing unit 420, respectively. May be.

  The method of setting the readout row and the shutter row in each of the lower region 410a, 410b and the upper region 410c, 410d is omitted from the description with reference to the drawing. However, if it is performed according to the two-divided case shown in FIG. Good.

  In addition, for the lower regions 410a and 410b and the upper regions 410c and 410d of the image pickup unit 410, charge accumulation is performed in units of rows (exposure time setting by an electronic shutter), and independent pixel signals are read out. The vertical scanning start points STda, STdb, STuc, and STud are flexible. As an example, as shown in FIG. 7B, the scanning starting points STda and STuc are preferably set at the upper and lower edges, and the scanning starting points STdb and STud are set at the boundary between the lower region b and the upper region d. .

  As in the configuration of the CMOS image sensor 12 of the second embodiment, the image pickup unit 410 is divided into three systems (N = 3) or more (four systems in this example), and pixel signals are read from the image pickup unit 410 and processed. Even when the function units (the column processing unit 420, the horizontal scanning unit 412, the horizontal selection switch unit 460, and the output unit 488) are appropriately divided according to the area division, the shutter speed is not much different from the horizontal scanning period. When the setting is fast, due to the difference between the horizontal movement of the object and the scanning time point (see FIG. 7B), as shown in FIG. Time shading distortion in the row direction (horizontal scanning direction) appears in the image.

  However, by dividing the area into three or more systems (N = 3) and simultaneously accumulating charges in units of rows and reading independent pixel signals, the amount of distortion is 1 / 3 or less (in this example, 1/4). In other words, the time shading distortion can be reduced to 1 / N when equal division is performed by increasing the number N of divisions of the regions.

  Although illustration is omitted, it is not essential to divide the area equally so that the pixel lines in the N areas are the same as in the modification of the first embodiment shown in FIG. Even with non-uniform region division, temporal shading distortion can be reduced as compared to the conventional case.

  However, the wiring state of the vertical signal lines 418a, 418b, 418c, and 418d of the entire imaging unit 410 is plural per pixel column (this example) in the lower region 410a and the upper region 410c, as can be seen from FIG. Then, it is necessary to arrange N / 2 = 2) in parallel. That is, when the number N of area divisions is 3 or more, not only the vertical signal line 418 for the area to which the own pixel belongs but also the vertical signal line 418 for other areas in the same direction position with respect to the imaging unit 410. Need to be pulled out.

  Therefore, as in the second modification of the first embodiment shown in FIG. 6, when forming a wiring layer that forms a wiring with respect to the active element of the imaging unit 410, incident light is transmitted from the same surface side as the wiring layer. In a surface sensor having a normal surface-receiving type pixel structure to be taken into a photoelectric conversion element, this wiring blocks light. In order to solve this problem, a back-illuminated sensor structure in which incident light is taken into the photoelectric conversion element from the surface opposite to the wiring layer may be used. Hereinafter, the backside illumination type sensor structure will be described.

<Back-illuminated sensor structure; sectional view>
FIG. 8 is a cross-sectional view showing an example of the structure of the back-illuminated imaging unit 410 and the peripheral circuit unit. In FIG. 8A, the wafer is polished by CMP (Chemical Mechanical Polishing) to form a semiconductor element layer 631 made of silicon (Si) having a thickness of about 10 to 20 μm. Desirable ranges of the thickness are 5 to 15 μm for visible light, 15 to 50 μm for infrared light, and 3 to 7 μm for ultraviolet region. A light shielding film 633 is formed on one surface side of the semiconductor element layer 631 with the SiO 2 film 632 interposed therebetween.

  Unlike the wiring, the light shielding film 633 is laid out in consideration of only optical elements. An opening 633 A is formed in the light shielding film 633. A silicon nitride film (SiN) 634 is formed on the light shielding film 633 as a passivation film, and a color filter 635 and a micro lens 636 are formed above the opening 633A. In other words, light entering from one surface side of the semiconductor element layer 631 has a pixel structure that is guided to the light receiving surface of the photodiode 433 formed in the semiconductor element layer 631 through the microlens 636 and the color filter 635. ing. A wiring layer 638 on which transistors and metal wirings are formed is provided on the other surface side of the semiconductor element layer 631, and a substrate support material 639 having a thickness of several hundred μm is further attached below the wiring layer 638.

  Here, the first layer in the wiring layer 638 is a wiring in a pixel, the second layer is a vertical wiring for a vertical signal line 418, a drain line, and the like, and the third layer is a transfer gate wiring ( Readout selection line TRG) 453, reset wiring (RST) 455, and vertical selection line (SEL) 457 for setting a row address are used as horizontal wirings.

  In the present embodiment, the vertical wiring for the vertical signal line 418 is not limited to the area to which the own pixel belongs, but the area division, the readout line and the shutter line for each area, which are characteristic features of the present invention. For this control, as described above, when the number N of area divisions is at least 3 or more, those for other areas are always arranged.

  In this case, when the number N of area divisions is relatively small, a plurality of vertical signal lines 418 can be sufficiently provided only by the second layer. However, when the number N of area divisions increases, vertical signals for other areas are used. As the number of lines 418 increases, it may happen that the second layer alone is not sufficient. In such a case, it may be dealt with by increasing the fourth and subsequent layers. Increasing the number of layers in the wiring layer 638 does not affect the optical design on the light receiving surface side. This point is significantly different from the surface light receiving type which increases the number of layers and affects the optical design on the light receiving surface side.

  Of course, regardless of the area division number N, the vertical signal line 418 for the area to which the pixel belongs is arranged in the second layer, and the vertical signal line 418 for other areas is arranged in the fourth and subsequent layers. It may be. Further, the vertical signal line 418 for the region to which the own pixel belongs may be arranged in the fourth and subsequent layers. In this case, the number of wirings in the second layer can be reduced, and the pixel can be miniaturized.

  Here, in the conventional CMOS image sensor, the wiring layer side is the front surface side, and the surface light receiving type pixel structure that takes in incident light from the wiring layer side is adopted, whereas the CMOS image sensor of the second embodiment In FIG. 12, since incident light is taken in from the surface (back surface) opposite to the wiring layer 638, it has a back surface light receiving type pixel structure.

  As is apparent from the backside light-receiving pixel structure, the light shielding film 633 only exists as a metal layer between the microlens 636 and the photodiode 433, and the light shielding film 633 has a high height from the photodiode 433. Is as low as the thickness of the SiO 2 film 632 (for example, about 0.5 μm), it is possible to eliminate the limitation of light collection due to kicking in the metal layer.

<Back-illuminated sensor structure; pixel layout example>
9 and 10 are diagrams for explaining a layout example of a back-illuminated pixel. Here, FIG. 9 is a plan pattern diagram showing an active region (a region of a gate oxide film), a gate (polysilicon) electrode, and a contact portion between them. As can be seen from FIG. 9, one photodiode (PD) 433 (corresponding to the charge generation unit 432 in FIG. 2) and four transistors 434, 436, 440, 442 exist per unit pixel 403.

  FIG. 10 is a plan pattern diagram showing the metal wiring above the gate electrode and the contact portion between them together with the active region. Here, the metal wiring (for example, aluminum wiring) has a three-layer structure. The first layer is a wiring in a pixel, the second layer is a vertical wiring, that is, a vertical signal line 418 or a drain line. The third layer is used as a horizontal wiring, that is, a transfer gate wiring (read selection line TRG) 453, a reset wiring (RST) 455, and a vertical selection line (SEL) 457 for setting a row address.

  Here, regardless of the area division number N, the vertical signal line 418 for the area to which its own pixel belongs is arranged in the second layer, and the vertical signal lines 418 for other areas are arranged in the fourth and subsequent layers. The plurality of vertical signal lines 418 are overlapped (stacked).

  Although illustration is omitted, when the vertical signal lines 418 for other regions are also arranged in the second layer, a plurality of vertical signal lines 418 are arranged in parallel in the second layer.

  As can be seen from the wiring patterns in FIGS. 8A and 10, the vertical signal line 418, the transfer gate wiring 453, the reset wiring (RST) 455, and the vertical selection line (SEL) 457 overlap with the photodiode region. Wired. These wirings are arranged avoiding the photodiode region because the conventional pixel structure adopts a surface light-receiving pixel structure that takes in light from the wiring layer side.

  On the other hand, as can be seen from FIG. 8A, the pixel structure of the second embodiment employs a back-surface light receiving pixel structure that takes in light from the surface opposite to the wiring layer (back surface side). The wiring can be routed on the photoelectric conversion element region such as a photodiode without worrying about the problem of light shielding by the wiring.

  Further, as can be seen from FIG. 8A, since the wiring layer 638 does not exist on the light receiving surface side, the light shielding film 633, the color filter 635, and the micro lens 636 can be formed at a low position with respect to the light receiving surface. Therefore, it is advantageous in terms of color mixing and peripheral light reduction under sensitivity.

  In the back-illuminated sensor structure shown in this example, not only the vertical signal line 418 but also other wirings (wiring in the pixel, vertical wiring excluding the vertical signal line 418, horizontal wiring) The incident light is arranged on the surface opposite to the side that takes in the photoelectric conversion element, but this is not essential. In other words, at least for each divided region, one pixel column is required for reading out pixel signals in independent row units while simultaneously performing charge accumulation in row units, that is, setting an exposure time by an electronic shutter. However, it is only necessary to apply to a plurality of vertical signal lines 418. In this case, for example, when the surface irradiation type sensor structure is modified, the layer structure as shown in FIG. 8B is obtained.

  For example, when diverting a sensor that has already been optically designed as a surface type, and making it a global shooter (high speed) with compatibility of characteristics (Compatibility), it is necessary to use a digital control line and an analog system. A certain vertical signal line can be used for isolation between the front surface and the back surface.

  However, as a practical problem, a wiring layer 642 for the vertical signal line 18 is arranged on the side opposite to the light receiving surface with the semiconductor element layer 631 on which the photodiode 433 and the like are formed interposed therebetween, and other wirings are provided on the light receiving surface side. Although it is not impossible to arrange the wiring layer 638 for (intra-pixel wiring, vertical wiring, horizontal wiring), the number of processes increases.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, accumulation of signal charges corresponding to incident light is started for each line (row), and a current or voltage signal based on the accumulated signal charges is sequentially picked up from each pixel by addressing. The example of application to an apparatus of a row-by-row readout system (column readout system that controls electronic exposure time to be read from) has been described, but accumulation of signal charges corresponding to incident light is started for each pixel, and the accumulated The present invention can be similarly applied to a method of reading a current or voltage signal based on a signal charge.

  In the above embodiment, a CMOS type solid-state imaging device that is sensitive to electromagnetic waves input from the outside such as light and radiation is exemplified. However, the pixel accumulation time and readout time are determined by address setting. The mechanism described in the above embodiment can be applied to any physical quantity distribution detection device that detects a change in a physical quantity of a certain type.

  For example, a fingerprint authentication device that detects a fingerprint image based on a change in electrical characteristics or a change in optical characteristics based on pressure is used for information related to fingerprints. In the mechanism for detecting other physical changes, such as Japanese Patent Laid-Open No. 2001-125734, the above embodiment can be applied to suppress / eliminate problems of dark current noise and accumulation period differences.

It is a schematic block diagram of 1st Embodiment of a CMOS image sensor. It is a figure explaining the relationship between one structural example of a unit pixel, and the drive circuit in connection with an exposure time control function. It is FIG. (1) explaining the exposure time control function at the time of using the CMOS image sensor of 1st Embodiment. It is FIG. (2) explaining the exposure time control function at the time of using the CMOS image sensor of 1st Embodiment. It is a figure explaining the 1st modification of the exposure time control function at the time of using the CMOS image sensor of 1st Embodiment. It is a figure explaining the 2nd modification of the exposure time control function at the time of using the CMOS image sensor of 1st Embodiment. It is a schematic block diagram of 2nd Embodiment of a CMOS image sensor. It is sectional drawing which shows an example of the structure of a back irradiation type imaging part and a peripheral circuit part. It is FIG. (1) explaining the example of a layout of a back irradiation type pixel. It is FIG. (2) explaining the example of a layout of a back irradiation type pixel. It is FIG. (1) explaining the exposure time control function in the conventional XY address type imaging device. It is FIG. (2) explaining the exposure time control function in the conventional XY address type imaging device. It is FIG. (3) explaining the exposure time control function in the conventional XY address type imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 12 ... CMOS image sensor, 403 ... Unit pixel, 405 ... Pixel signal generation part, 407 ... Drive control part, 410 ... Imaging part, 412 ... Horizontal scanning part, 412x ... Horizontal address setting part, 412y ... Horizontal drive part, 414 ... Vertical scanning unit, 414x ... vertical address setting unit, 414y ... vertical drive unit, 414z ... shutter timing control unit, 415 ... vertical control line, 416 ... drive signal operation unit, 418 ... vertical signal line, 420 ... column processing unit, 422 ... column signal processing unit (column circuit), 427 ... read current source unit, 432 ... charge generation unit, 434 ... read selection transistor, 436 ... reset transistor, 438 ... floating diffusion, 440 ... vertical selection transistor, 442 ... amplification Transistor 451... Pixel line 452 transfer transfer buffer 454. Gate drive buffer, 456 ... selection driving buffer 460 ... horizontal selection switch section, 486 ... horizontal signal line, 488 ... output unit, 631 ... semiconductor element layer, 638 ... wiring layer, 639 ... substrate support member

Claims (7)

A plurality of light receiving elements as detection units that output signals according to the amount of incident light, and a plurality of unit pixels formed in a two-dimensional shape are connected to a plurality of vertical signal lines and a plurality of vertical control lines . In the imaging unit , the plurality of unit pixels formed in a two-dimensional shape are connected to the plurality of vertical signal lines so that unit pixel signals can be simultaneously read from a plurality of regions in units of rows,
A vertical address setting unit and vertical drive unit for driving on the basis of the plurality of vertical control lines to the vertical address, the vertical address setting unit in cooperation with the selected shutter pixels in performing exposure time control operation, the respective regions A plurality of vertical control lines connected to each unit pixel, and a shutter timing control unit that performs an electronic shutter for controlling an exposure time or a charge accumulation time in a row unit for each region of the plurality of unit pixels. And
The detection signal of the detection unit of the unit pixel read to the plurality of vertical signal lines in accordance with the scanning of the vertical scanning unit is input, and the input detection signal is selected according to the scanning signal of the horizontal scanning unit A horizontal selection switch that outputs to the horizontal signal line;
Have
The shutter timing control unit selects a shutter row and sets a shutter pixel in order to perform the exposure time control operation when driving for the electronic shutter, and between the readout row selected by the vertical address setting unit By adjusting the time interval of the shutter pixels in the above, the exposure time to the unit pixel of the imaging unit is adjusted for each readout region,
Solid-state imaging device. The shutter timing control unit sequentially drives and controls a control line for reading from the plurality of readout regions from one to the other in the same vertical direction;
The solid-state imaging device according to claim 1. The shutter timing control unit sequentially drives and controls the control lines for reading from the plurality of readout areas, and the control lines of adjacent divided areas in different vertical directions;
The solid-state imaging device according to claim 1. The shutter timing control unit sequentially drives and controls the control lines for reading from the plurality of readout areas from the center of the divided areas toward both ends;
The solid-state imaging device according to claim 1. A frame memory is connected to the horizontal signal line;
Detection signals of a plurality of unit pixels read out from the horizontal signal lines and read out from the control lines for reading out from the plurality of readout areas are sent to the frame memory in accordance with the positions of the control lines. Remembered,
The solid-state imaging device according to claim 1. When the plurality of readout areas are 3 or more, the solid-state imaging device is configured as a back-illuminated solid-state imaging device.
The solid-state imaging device according to claim 1. A plurality of light receiving elements as detection units that output signals according to the amount of incident light, and a plurality of unit pixels formed in a two-dimensional shape are connected to a plurality of vertical signal lines and a plurality of vertical control lines . The plurality of unit pixels formed in the two-dimensional shape are connected to the plurality of vertical signal lines so that unit pixel signals can be simultaneously read out from a plurality of regions in units of rows , A vertical address setting unit and a vertical driving unit that drive a vertical control line based on a vertical address, and a shutter pixel is selected in performing an exposure time control operation in cooperation with the vertical address setting unit, and unit pixels in each region a connected plurality of vertical control lines in units of rows for each of the areas of the plurality of unit pixels, having a shutter timing control unit for performing an electronic shutter for controlling the exposure time or the charge accumulation time The detection signal of the detection unit of the unit pixel read out to the vertical scanning unit and the plurality of vertical signal lines in accordance with the scanning of the vertical scanning unit is input, and is input according to the scanning signal of the horizontal scanning unit And a horizontal selection switch unit that selects the detected signal and outputs it to a horizontal signal line, and a drive control method in a solid-state imaging device,
The shutter timing control unit at the time of driving the electronic shutter, by selecting the sheet Yatta line for performing the exposure time control operation to set the shutter pixels, between the read rows selected by the vertical address setting unit By adjusting the time interval of the shutter pixels in the above, the exposure time to the unit pixel of the imaging unit is adjusted for each readout region,
A drive control method in a solid-state imaging device.

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