JP6863355B2 - Image sensor and image sensor - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

The following Patent Document 1 describes a plurality of pixels including a plurality of pixels, each of which includes (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier. And a solid-state imaging device including a connection switch that selectively connects the charge-voltage conversion regions to each other are disclosed.

Japanese Patent Application Laid-Open No. 2008-546313

In the conventional solid-state image sensor, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion regions is expanded, so that the dynamic range can be increased. It can be expanded.

Further, in the conventional solid-state imaging device, by turning off the connection switch and separating the charge-voltage conversion region from the other charge-voltage conversion region, the charge-voltage conversion capacity becomes smaller and the charge-voltage conversion coefficient becomes larger. Therefore, the SN ratio at the time of high-sensitivity reading becomes high.

However, in the conventional solid-state image sensor, even if the connection switch is turned off, the SN ratio at the time of high-sensitivity readout cannot be increased so much.

The present invention has been made in view of such circumstances, and is a solid-state image sensor capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the solid-state image sensor. The purpose is to provide the device.

The imaging device according to the first aspect of the present invention has a first pixel block having a first node to which the photoelectrically converted charge is transferred, a reset unit for resetting the potential of the first node, and photoelectric. For a second pixel block having a second node to which the converted charge is transferred, a connection portion having a plurality of switches for connecting the first node and the second node, and the first node. A control line which is arranged in parallel and outputs a control signal for controlling the reset unit is provided , and the connection unit includes a first switch, a second switch, the first switch, and the second switch. The first switch has at least a wiring connected to and is connected between the first node and the wiring when the potential of the first node is reset by the reset unit. Is controlled by .
The imaging device according to the second aspect of the present invention has a first pixel block having a first node to which the photoelectrically converted charge is transferred, and a reset unit for resetting the potential of the first node, and photoelectric. To control a second pixel block having a second node to which the converted charge is transferred, a connection unit having a plurality of switches for connecting the first node and the second node, and the reset unit. The connection unit includes at least a first switch, a second switch, and wiring connected to the first switch and the second switch. , The control line is arranged parallel to the wiring.
The image pickup device according to the third aspect of the present invention includes an image pickup device according to the first or second aspect.

According to the present invention, it is possible to provide a solid-state image pickup device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity readout, and an image pickup device using the solid-state image pickup device.

It is a schematic block diagram which shows typically the electronic camera by 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the solid-state image sensor in FIG. It is a circuit diagram which enlarges and shows the vicinity of three pixel blocks in FIG. It is a schematic plan view which shows typically the vicinity of the three pixel blocks shown in FIG. It is a schematic plan view which shows the vicinity of one pixel block in FIG. 4 enlarged. It is a timing chart which shows the predetermined operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows other operation modes of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a circuit diagram which shows the vicinity of three pixel blocks of a solid-state image sensor by a comparative example. 9 is a schematic plan view schematically showing the vicinity of the three pixel blocks shown in FIG. 9. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention. FIG. 5 is a schematic plan view schematically showing the vicinity of the three pixel blocks shown in FIG. It is a circuit diagram which shows the schematic structure of the solid-state image sensor of the electronic camera by the 3rd Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the solid-state image sensor of the electronic camera according to the 4th Embodiment of this invention. It is a circuit diagram which enlarges and shows the vicinity of four pixel blocks in FIG. It is a timing chart which shows the predetermined operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows other operation modes of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a circuit diagram which shows the schematic structure of the solid-state image sensor of the electronic camera according to the 5th Embodiment of this invention. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera according to the 6th Embodiment of this invention. It is a circuit diagram which enlarges and shows the vicinity of four pixel blocks in FIG. 22. It is a timing chart which illustrates the state of resetting the potential of the node P (n). It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera by 7th Embodiment of this invention. FIG. 5 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 25. It is a timing chart which shows the 1st operation mode of the solid-state image sensor of the electronic camera by 7th Embodiment of this invention. It is a timing chart which shows the operation mode of the 2nd A of the solid-state image sensor of the electronic camera by 7th Embodiment of this invention. It is a timing chart which shows the operation mode of the 2nd B of the solid-state image sensor of the electronic camera by 7th Embodiment of this invention. It is a timing chart which illustrates the state of resetting the potential of the node P (n).

Hereinafter, the solid-state image pickup device and the image pickup apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to the first embodiment of the present invention.

The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this, and is mounted on other electronic cameras such as compact cameras and mobile phones. It can be applied to various imaging devices such as electronic cameras and electronic cameras such as video cameras that capture moving images.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of the photographing lens 2 are driven by the lens control unit 3. The image pickup surface of the solid-state image pickup device 4 is arranged in the image space of the photographing lens 2.

The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. During normal main shooting (still image shooting), for example, the image sensor 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time. The solid-state image sensor 4 is controlled. Further, in the electronic viewfinder mode, when shooting a moving image, or the like, the image pickup control unit 5 controls the solid-state image sensor 4 so as to perform a predetermined readout operation while performing, for example, a so-called rolling electronic shutter. At these times, the image pickup control unit 5 controls the solid-state image pickup device 4 so as to perform the read operation of each operation mode described later according to the setting value of the ISO sensitivity, as will be described later. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state image sensor 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. A lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like are also connected to the bus 8. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

The CPU 9 in the electronic camera 1 drives the image pickup control unit 5 in accordance with the instructions of the electronic viewfinder mode, moving image shooting, normal main shooting (still image shooting), or the like by the operation of the operation unit 14. At this time, the lens control unit 3 appropriately adjusts the focus and the aperture. The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. The digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 causes the display unit 10 to display the image signal in the electronic viewfinder mode, and records the image signal in the recording medium 11a when shooting a moving image. In the case of normal main shooting (still image shooting) or the like, the CPU 9 performs the operation unit 14 after the digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and stored in the memory 7. Based on the command of the above, the image processing unit 13 and the image compression unit 12 perform desired processing as necessary, and the recording unit 11 outputs the processed signal and records it on the recording medium 11a.

FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state image sensor 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of the three pixel blocks BL sequentially arranged in the column direction in FIG. FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. FIG. 5 is a schematic plan view showing the vicinity of one pixel block BL in FIG. 4 in an enlarged manner. In the present embodiment, the solid-state image sensor 4 is configured as a CMOS-type solid-state image sensor, but is not limited to this, and may be configured as, for example, another XY address-type solid-state image sensor.

As shown in FIGS. 2 to 4, the solid-state image sensor 4 is arranged in a two-dimensional matrix in N rows and M columns, and has a pixel block BL having two pixels PX (PXA, PXB) and one of the pixel blocks BL. Connection transistors SWa and SWb as a plurality of connection switches, a vertical scanning circuit 21, control lines 22 to 27 provided for each row of the pixel block BL, and each column of the pixel PX (column of the pixel block BL). A plurality of (M) vertical signal lines 28 provided (for each) and receiving signals from pixels PX (pixel block BL) in the corresponding rows, a constant current source 29 provided in each vertical signal line 28, and each. It has a column amplifier 30, a CDS circuit (correlation double sampling circuit) 31 and an A / D converter 32 provided corresponding to the vertical signal line 28, and a horizontal readout circuit 33.

As the column amplifier 30, an analog amplifier may be used, or a so-called switched capacitor amplifier may be used. Further, the column amplifier 30 does not necessarily have to be provided.

For convenience of drawing notation, although it is shown as M = 2 in FIG. 2, the number of columns M is actually a larger arbitrary number. Further, the number of lines N is not limited. When the pixel block BL is distinguished for each row, the pixel block BL on the jth row is indicated by the reference numeral BL (j). This point also applies to other elements and control signals described later. 2 and 3 show pixel blocks BL (n-1) to BL (n + 1) in the n-1th to n + 1th rows over three rows.

In the drawings, the reference numerals of the lower pixels in FIGS. 2 and 3 of the pixel block BL are referred to as PXA, and the reference numerals of the upper pixels in FIGS. 2 and 3 are referred to as PXB. When the explanation is made without distinction, both may be described by adding a reference numeral PX. Further, in the drawing, the code of the photodiode of the pixel PXA is PDA, and the code of the photodiode of the pixel PXB is PDB, and the two are distinguished. May be explained. Similarly, the code of the transfer transistor of the pixel PXA is TXA, and the code of the transfer transistor of the pixel PXB is TXB. In some cases. In the present embodiment, the photodiode PDs of the pixels PX are arranged in a 2N row and M column in a two-dimensional matrix.

In the present embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and stores signal charges according to incident light, and a transfer transistor as a transfer switch that transfers charges from the photodiode PD to the node P. Has TX.

In the present embodiment, the plurality of pixels PX form a pixel block BL for each of two pixel PXs (PXA, PXB) in which photodiode PDs are sequentially arranged in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL are a set of nodes P, an amplification transistor AMP, a reset transistor RST, and selection. It shares a transistor SEL. A capacitance (charge-voltage conversion capacitance) is formed in the node P with the reference potential, and the charge transferred to the node P is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the node P. The reset transistor RST constitutes a reset switch that resets the potential of the node P. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). In FIGS. 2 and 3, n indicates a row of pixel block BL. For example, the pixel block BL of the first row is formed by the pixel PX (PXA) of the first row and the pixel PX (PXB) of the second row, and the pixel PX (PXA) of the third row and the pixel PX of the fourth row. (PXB) and the pixel block BL of the second row are configured.

In the present invention, for example, the pixel block BL may be configured for each of three or more pixel PXs in which the photodiode PDs are sequentially arranged in the column direction.

Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light having different color components are arranged in a predetermined color arrangement on the light incident side of the photodiode PD of each pixel PX. (For example, Bayer arrangement). The pixel PX outputs an electric signal corresponding to each color by color separation by a color filter.

An electrical connection path provided between a node P of one pixel block BL and a node P of the other pixel block BL for each of two pixel block BLs adjacent to each other in the column direction of each pixel block BL. Two connection transistors SWa and SWb as two connection switches are provided in series in a connection path (connection portion) which is (connection portion) and is unique between them. As a result, in the present embodiment, the nodes P of the three or more pixel blocks BL are connected in a beaded shape by the plurality of connection paths (connection portions). Of these two connected transistors SWa and SWb, the connected transistor SWa is arranged on the side of the node P of the lower pixel block BL in FIGS. 2 and 3, and the connected transistor SWb is shown in FIG. And the one arranged on the side of the node P of the upper pixel block BL in FIG.

For example, an electrical connection path between the node P (n) of the pixel block BL (n) on the nth row and the node P (n + 1) of the pixel block BL on the n + 1th line, and a unique connection path between them. Two connecting transistors SWa (n) and SWb (n) are provided in series therein. As shown in FIG. 4, the connecting transistor SWa (n) is formed in the region of the pixel block BL (n), while the connecting transistor SWb (n) is formed in the region of the pixel block BL (n + 1). However, the same (n) is added to the end of the reference numerals of these connected transistors SWa (n) and SWb (n) to indicate that they are provided in series in the same unique connection path. .. In the present invention, three or more connecting switches may be provided in series in each of the unique connection paths, but in order to simplify the structure, each of the unique connections is made as in the present embodiment. It is preferable to provide two connecting transistors SWa and SWb in series in the path.

In FIGS. 2 and 3, VDD is the power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWa, and SWb are all nMOS transistors.

The gate of the transfer transistor TXA is commonly connected to the control line 26 line by line, to which the control signal φTXA is supplied from the vertical scanning circuit 21. The gate of the transfer transistor TXB is commonly connected to the control line 25 line by line, to which the control signal φTXB is supplied from the vertical scanning circuit 21. The gate of the reset transistor RST is commonly connected to the control line 24 line by line, to which the control signal φRST is supplied from the vertical scanning circuit 21. The gate of the selection transistor SEL is commonly connected to the control line 23 line by line, and the control signal φSEL is supplied from the vertical scanning circuit 21 to the control line 23. The gate of the connecting transistor SWa is commonly connected to the control line 22 for each row, and the control signal φSWa is supplied to the control line 22 from the vertical scanning circuit 21. The gate of the connecting transistor SWb is commonly connected to the control line 27 for each row, and the control signal φSWb is supplied from the vertical scanning circuit 21 to the control line 27. For example, the control signal φTXA (n) is supplied to the gate of the transfer transistor TXA (n), the control signal φTXB (n) is supplied to the gate of the transfer transistor TXB (n), and the gate of the reset transistor RST (n). The control signal φRST (n) is supplied to the gate, the control signal φSEL (n) is supplied to the gate of the selection transistor SEL (n), and the control signal φSWa (n) is supplied to the gate of the connecting transistor SWa (n). Then, the control signal φSWb (n) is supplied to the gate of the connecting transistor SWb (n).

Each transistor TXA, TXB, RST, SEL, SWa, SWb is turned on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWa, φSWb are high level (H), and when the corresponding control signals are low level (L). Turn off.

Under the control of the image pickup control unit 5 in FIG. 1, the vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb for each row of the pixel block BL, and connects the pixel block BL and the connection. By controlling the transistors SWa and SWb, a still image reading operation, a moving image reading operation, and the like are realized. In this control, for example, a read operation of each operation mode described later is performed according to a set value of ISO sensitivity. By this control, each vertical signal line 28 is supplied with a signal (analog signal) of the pixel PX in the corresponding row.

In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode described later in response to a command (control signal) from the imaging control unit 5 in FIG.

The signal read out on the vertical signal line 28 is amplified by the column amplifier 30 in each column and further amplified by the CDS circuit 31 as an optical signal (a signal including optical information photoelectrically converted by the pixel PX) and a dark signal (light). After processing to obtain the difference from the signal for difference including the noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Will be done. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ) Is output.

The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is at a high level (H), the column amplifier 30 The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is an optical signal. Sample as. Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock or pulse from the timing generation circuit. As the configuration of such a CDS circuit 31, a known configuration can be adopted.

Here, the structure of the pixel block BL will be described with reference to FIGS. 4 and 5. Actually, a color filter, a microlens, etc. are arranged on the upper part of the photodiode PD, but they are omitted in FIGS. 4 and 5. In addition, in FIGS. 4 and 5, the layout of the power supply line, the ground line, the control lines 22 to 27, and the like is omitted.

In the present embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as a photodiode PD is arranged in the P-type well. There is. In FIG. 5, reference numerals 41 to 49 are N-type impurity diffusion regions that are a part of each of the above-mentioned transistors. Reference numerals 61 to 67 are gate electrodes of each transistor made of polysilicon. The diffusion regions 42 and 45 are regions in which the power supply voltage VDD is applied by a power supply line (not shown).

The photodiodes PDA (n) and PDB (n) are an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) arranged on the surface side thereof (FIG.). It is an embedded photodiode consisting of (not shown). The photodiodes PDA (n) and PDB (n) photoelectrically convert incident light and accumulate the generated charge in the charge storage layer.

The transfer transistor TXA (n) is an nMOS transistor having a charge storage layer of a photodiode PDA (n) as a source, a diffusion region 41 as a drain, and a gate electrode 61 as a gate. The transfer transistor TXB (n) is an nMOS transistor having a charge storage layer of a photodiode PDB (n) as a source, a diffusion region 41 as a drain, and a gate electrode 62 as a gate. The diffusion region 41 is provided between the photodiode PDA (n) and the photodiode PDB (n). The diffusion region 41 is also used as a diffusion region that serves as a drain of the transfer transistor TXA (n) and a diffusion region that serves as a drain of the transfer transistor TXB (n). The gate electrode 61 of the transfer transistor TXA (n) is arranged on the photodiode PDA (n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB (n) is arranged on the photodiode PDB (n) side of the diffusion region 41.

The amplification transistor AMP (n) is an nMOS transistor having a diffusion region 42 as a drain, a diffusion region 43 as a source, and a gate electrode 63 as a gate. The selection transistor SEL (n) is an nMOS transistor having a diffusion region 43 as a drain, a diffusion region 44 as a source, and a gate electrode 64 as a gate. The diffusion region 44 is connected to the vertical signal line 28. The reset transistor RST (n) is an nMOS transistor having a diffusion region 45 as a drain, a diffusion region 46 as a source, and a gate electrode 65 as a gate.

The connection transistor SWa (n) is an nMOS transistor having a diffusion region 46 as a source, a diffusion region 47 as a drain, and a gate electrode 66 as a gate. The connection transistor SWb (n-1) is an nMOS transistor having a diffusion region 48 as a drain, a diffusion region 49 as a source, and a gate electrode 67 as a gate.

The gate electrode 63 of the pixel block BL (n), the diffusion regions 41 and 46, and the diffusion region 48 of the connecting transistor SWb (n-1) are electrically connected to each other by the wiring 71 (n) to conduct electricity. In the present embodiment, the node P (n) corresponds to the wiring 71 (n) and the entire portion electrically connected to and conducting the wiring 71 (n).

The structure of the pixel block BL other than the nth row is the same as the structure of the pixel block BL (n) of the nth row described above. The structure of the connected transistor SWa other than the connected transistor SWa (n) is the same as the structure of the connected transistor SWa (n) described above. The structure of the connected transistor SWb other than the connected transistor SWb (n) is the same as the structure of the connected transistor SWb (n) described above.

Then, with respect to the two connecting transistors SWa and SWb provided in series in each of the unique connecting paths, the diffusion region 47 of the connecting transistor SWa and the diffusion region 49 of the connecting transistor SWb are connected by the wiring 72. Has been done. For example, the diffusion region 47 of the connection transistor SWa (n-1) and the diffusion region 49 of the connection transistor SWb (n-1) are electrically connected by the wiring 72 (n-1). The wiring 72 (n-1) connects the connection portions between the connection transistors SWa (n-1) and SWb (n-1) when the connection transistors SWa (n-1) and SWb (n-1) are off. It is configured. The diffusion region 47 of the connection transistor SWa (n) and the diffusion region 49 of the connection transistor SWb (n) are electrically connected by the wiring 72 (n). The wiring 72 (n) constitutes a connection portion between the connecting transistors SWa (n) and SWb (n) when the connecting transistors SWa (n) and SWb (n) are off.

Here, as shown in FIG. 4, the amount of misalignment in the row direction between the two connecting transistors SWa and SWb provided in series in each of the unique connection paths is Ls, and the row direction of the photodiode PD is defined as Ls. Let Pg be the pitch of. In the present invention, the relationship between the pitch Pg and the misalignment Ls is not limited, but in order to reduce the capacitance value Cfd1 of the capacitance CA described later, it is preferable that pg <Ls <2 × Pg. In the present embodiment, for example, the connecting transistor SWb (n-1) is arranged in the vicinity of the connecting transistor SWa (n), and the misalignment amount Ls is set to be slightly less than 2 × Pg, and the wiring 71. The length of (n) is shortened as much as possible, and the capacitance value Cfd1 of the capacitance CA (n) described later is made as small as possible.

In FIGS. 2 to 5, CA (n) is a capacitance between the node P (n) and the reference potential when the connected transistors SWa (n) and SWb (n-1) are off. Let the capacity value of the capacity CA (n) be Cfd1. CB (n) indicates the capacitance between the wiring 72 (n) and the reference potential when the connected transistors SWa (n) and SWb (n) are off. Let the capacitance value of the capacitance CB (n) be Cfd2. These points are the same for the rows of other pixel blocks BL.

The capacitance CA (n) is the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region 46 of the reset transistor RST (n), and the source of the connection transistor SWa (n). It is composed of the capacitance of the diffusion region 46, the capacitance of the drain diffusion region 48 of the connecting transistor SWb (n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71 (n). , The sum of those capacity values is the capacity value Cfd1 of the capacity CA (n). This point is the same for the rows of other pixel blocks BL.

Here, both the value of the channel capacitance when the connected transistor SWa is turned on and the value of the channel capacitance when the connected transistor SWb is turned on are defined as Csw. Usually, the capacitance value Csw is a small value with respect to the capacitance values Cfd1 and Cfd2.

Now, focusing on the pixel block BL (n), both the connected transistors SWa (n) and SWb (n-1) are turned off (that is, the connected transistor in the on state of the connected transistors SWa and SWb is the node. It will not be in a state of being electrically connected to P (n), and the connection path provided with the connecting transistors SWa and SWb will not be in a state of being electrically connected to the node P (n)). The capacitance (charge-voltage conversion capacitance) between the node P (n) and the reference potential is the capacitance CA (n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is Cfd1. This state corresponds to the state of the period T2 in FIG. 6 showing the first operation mode described later.

Further, paying attention to the pixel block BL (n), when the connected transistor SWa (n) is turned on, the connected transistors in the on state other than the connected transistors SWa (n) among the connected transistors SWa and SWb are connected to the node P (n). If the state is not electrically connected to (specifically, if the connected transistors SWb (n-1) and SWb (n) are off), the node P (n) and the reference The capacitance (charge-voltage conversion capacitance) between the potential and the potential is the capacitance CA (n) plus the channel capacitance when the capacitance CB (n) and the connecting transistor SWa (n) are on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2. This state corresponds to the state of the period T2 in FIG. 7, which shows the operation mode of the second A described later.

Further, paying attention to the pixel block BL (n), when both the connected transistors SWa (n) and SWb (n) are turned on, among the connected transistors SWa and SWb, other than the connected transistors SWa (n) and SWb (n). Unless the connected transistor in the ON state is electrically connected to the node P (n) (specifically, the connected transistors SWb (n-1) and SWa (n + 1) are turned off. If), the charge-voltage conversion capacitance of the node P (n) is the channel capacitance when the capacitance CB (n), the connected transistors SWa (n), and SWb (n) are turned on with respect to the capacitance CA (n). The capacity CA (n + 1) is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is 2 × Cfd1 + Cfd2 + 2 × Csw≈2 × Cfd1 + Cfd2. This state corresponds to the state of the period T2 in FIG. 8 showing the operation mode of the second B described later.

As described above, if there is no connected transistor in the on state electrically connected to the node P (n) among the connected transistors SWa and SWb, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is the minimum. Therefore, the charge-voltage conversion coefficient due to the charge-voltage conversion capacity becomes large, so that the reading with the highest SN ratio becomes possible.

On the other hand, if the number of on-state connected transistors electrically connected to the node P (n) among the connected transistors SWa and SWb is increased to one or more desired number, the node P (n) Since the capacitance value of the charge-voltage conversion capacitance can be increased to a desired value and a large amount of signal charge can be handled, the number of saturated electrons can be increased. As a result, the dynamic range can be expanded.

The node P (n) of the pixel block BL (n) has been described above, but the same applies to the node P of the other pixel block BL.

FIG. 6 is a timing chart showing the first operation mode of the solid-state image sensor 4 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and is electrically connected to the node P of the selected pixel block BL among the connected transistors SWa and SWb in the ON state. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on in the state where there is no connecting transistor of (the state where the charge-voltage conversion capacity of the node P is the minimum), and the selected pixel block BL is selected. This is an example of an operation of sequentially reading out the signals of the photodiodes PDA and PDB of the above for each row. In the example shown in FIG. 6, the signals of all pixels PXA and PXB are read, but the present invention is not limited to this, and for example, thinning-out reading may be performed by thinning out the pixel rows. This point is the same for each of the examples shown in FIGS. 7 and 8 described later.

In FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixels in the n + 1th row in the period T3. It shows the situation where the block BL (n + 1) is selected. Since the operation when the pixel block BL of any row is selected is the same, only the operation when the pixel block BL (n) of the nth row is selected will be described here.

Before the start of the period T2, the exposure of the photodiodes PDA (n) and PDB (n) has already been completed in the predetermined exposure period. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and in electronic viewfinder mode or movie shooting. , So-called rolling electronic shutter operation. Immediately before the start of the period T2, all the transistors SEL, RST, TXA, TXB, SWa, and SWb are turned off.

In the period T2, φSEL (n) in the nth row is set to H, the selection transistor SEL (n) in the pixel block BL (n) in the nth row is turned on, and the pixel block BL (n) in the nth row is set to H. Be selected.

Further, in the period T2, φSWa (n) and φSWb (n-1) are set to L, and the connected transistors SWa (n) and SWb (n-1) are turned off. As a result, in the period T2, there is no connected transistor in the on state that is electrically connected to the node P (n) of the selected pixel block BL (n) among the connected transistors SWa and SWb. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is Cfd1, which is the minimum.

For a certain period from the start of the period T2, φRST (n) is set to H, the reset transistor RST (n) on the nth line is temporarily turned on, and the potential of the node P (n) is temporarily reset to the power supply potential VDD. To.

The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t1 in the period T2, and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) on the nth line, and then the selection transistor. The signal further amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

For a certain period from the subsequent time point t2 in the period T2, φTXA (n) is set to H and the transfer transistor TXA (n) on the nth row is turned on. As a result, the signal charge stored in the photodiode PDA (n) of the pixel block BL (n) on the nth row is transferred to the charge-voltage conversion capacitance of the node P (n). The potential of the node P (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of the node P (n), excluding the noise component.

At the subsequent time point t3 during the period T2, the optical signal sampling signal φSIGC is set to H, the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) on the nth line, and then the selection transistor SEL (n). ) And the signal further amplified by the column amplifier 30 via the vertical signal line 28 are sampled by the CDS circuit 31 as an optical signal.

After that, after the time when φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from the time point t1 and the optical signal sampled in a certain time from the time point t3. .. The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

Then, φRST (n) is set to H, the reset transistor RST (n) on the nth row is temporarily turned on for a certain period from the time point t4 in the period T2, and the potential of the node P (n) is temporarily set to the power supply potential VDD. Will be reset to.

The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t5 in the period T2, and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) on the nth line, and then the selection transistor. The signal further amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

For a certain period from the subsequent time point t6 in the period T2, φTXB (n) is set to H and the transfer transistor TXB (n) on the nth row is turned on. As a result, the signal charge stored in the photodiode PDB (n) of the pixel block BL (n) on the nth row is transferred to the charge-voltage conversion capacitance of the node P (n). The potential of the node P (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of the node P (n), excluding the noise component.

At the subsequent time point t7 during the period T2, the optical signal sampling signal φSIGC is set to H, the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) on the nth line, and then the selection transistor SEL (n). ) And the signal further amplified by the column amplifier 30 via the vertical signal line 28 are sampled by the CDS circuit 31 as an optical signal.

After that, after the time when φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from the time point t5 and the optical signal sampled in a certain time from the time point t7. .. The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

As described above, in the first operation mode, there is no connected transistor in the on state that is electrically connected to the node P of the selected pixel block BL among the connected transistors SWa and SWb, so that the selected transistor is selected. Since the capacity value of the charge-voltage conversion capacity of the node P of the pixel block BL is minimized and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity is large, reading at the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 is instructed to perform the first operation mode.

FIG. 7 is a timing chart showing the operation mode of the second A of the solid-state image sensor 4 shown in FIG. The second operation mode is one of the second operation modes. In this second operation mode, each pixel block BL is sequentially selected row by row, and one or more predetermined number of connected transistors in the on state among the connected transistors SWa and SWb are selected pixel blocks. While electrically connected to the node P of the BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on, and the photodiodes PDA and PDB of the selected pixel block BL are sequentially turned on. This is an example of an operation of sequentially reading the signals of. The second operation mode is an example of the operation in which the predetermined number is one in the second operation mode.

In FIG. 7, similarly to FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixel block BL (n) in the nth row is selected in the period T3. Indicates a situation in which the pixel block BL (n + 1) on the n + 1th row is selected. The difference between the operation mode of the second A shown in FIG. 7 and the operation mode of the first operation mode shown in FIG. 6 is described below.

In the operation mode of the second A shown in FIG. 7, φSWa (n) is set to H and φSWb (n-1) is set to L in the period T2 in which the pixel block BL (n) in the nth row is selected. The connection transistor SWa (n) is turned on and the connection transistor SWb (n-1) is turned off. As a result, in the period T2, one of the connected transistors SWa and SWb in the ON state (here, the connected transistor SWa (n)) is the node P (n) of the selected pixel block BL (n). ) Is electrically connected. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is one step larger than that of the first operation mode shown in FIG.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the operation mode of the second A, one of the connected transistors SWa and SWb in the ON state is electrically connected to the node P of the selected pixel block BL. The capacity value of the charge-voltage conversion capacity of the node P of the selected pixel block BL is increased by one step, and the number of saturated electrons in the charge-voltage conversion capacity of the node P can be increased by one step. As a result, the dynamic range can be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 is instructed to perform the operation mode of the second A.

FIG. 8 is a timing chart showing the operation mode of the second B of the solid-state image sensor 4 shown in FIG. The second B operation mode is another operation mode of the second operation mode, and is an operation example in which the predetermined number is two.

In FIG. 8, similarly to FIGS. 6 and 7, the pixel block BL (n-1) in the n-1th row is selected in the period T1, and the pixel block BL (n) in the nth row is selected in the period T2. , The situation where the pixel block BL (n + 1) in the n + 1th row is selected in the period T3 is shown. The difference between the operation mode of the second B shown in FIG. 8 and the operation mode shown in the first operation mode shown in FIG. 6 and the operation mode shown in the second A shown in FIG. 7 is described below.

In the operation mode of the second B shown in FIG. 8, φSWa (n) and φSWb (n) are set to H and φSWb (n-1) is set in the period T2 in which the pixel block BL (n) in the nth row is selected. , ΦSWa (n + 1) is set to L, the connected transistors SWa (n) and SWb (n) are turned on, and the connected transistors SWb (n-1) and SWa (n + 1) are turned off. As a result, in the period T2, two on-state connected transistors (here, the connected transistors SWa (n) and SWb (n)) of the connected transistors SWa and SWb are selected as the pixel block BL (n). It is in a state of being electrically connected to the node P (n) of. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is 2 × Cfd1 + Cfd2 + 2Csw≈2 × Cfd1 + Cfd2, which is two steps larger than the first operation mode shown in FIG.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the operation mode of the second B, the two on-state connecting transistors of the connecting transistors SWa and SWb are electrically connected to the node P of the selected pixel block BL. The capacity value of the charge-voltage conversion capacity of the node P of the selected pixel block BL is increased by two steps, and the number of saturated electrons in the charge-voltage conversion capacity of the node P can be increased by two steps. As a result, the dynamic range can be expanded by two steps. For example, when the ISO sensitivity setting value is two steps smaller than the highest value, the imaging control unit 5 is instructed to perform the operation mode of the second B.

In the second operation mode, the predetermined number may be three or more.

Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 4 in the present embodiment will be described. FIG. 9 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state image sensor according to this comparative example, and corresponds to FIG. FIG. 10 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIGS. 4 and 5. In FIGS. 9 and 10, the same or corresponding elements as those in FIGS. 3, 4 and 5 are designated by the same reference numerals, and duplicate description thereof will be omitted. Although the diffusion region and the gate electrode are not designated in FIG. 10, their codes are the same as those in FIG. 5, so refer to FIG.

The difference between this comparative example and the present embodiment is that each connecting transistor SWb is removed, and the removed connection transistor SWb is short-circuited by the wiring 171 including the wirings 71 and 72. .. For example, in the present embodiment, the connecting transistor SWb (n-1) is removed, and the gate electrode of the pixel block BL (n) is provided by the wiring 171 (n) including the wirings 71 (n) and 72 (n-1). 63, the diffusion regions 41 and 46, and the diffusion region 47 of the connecting transistor SWa (n-1) are electrically connected to each other to conduct conduction.

In FIGS. 9 and 10, CAB (n) is the capacitance between the node P (n) and the reference potential when the connected transistors SWa (n) and SWa (n-1) are off. The capacity value of the capacity CAB (n) is defined as Cfd. These points are the same for the rows of other pixel blocks BL.

The capacitance CAB (n) includes the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the source diffusion region 46 of the reset transistor RST (n), and the source diffusion region of the connection transistor SWa (n). It is composed of 46, the capacitance of the drain diffusion region 47 of the connecting transistor SWa (n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP (n), and the wiring capacitance of the wiring 171 (n). The sum of the values is the capacitance value Cfd of the capacitance CAB (n). This point is the same for the rows of other pixel blocks BL.

The wiring capacitance of the wiring 171 (n) is substantially equal to the sum of the wiring capacitance (floating capacitance) of the wiring 71 (n) and the wiring capacitance of the wiring 171 (n). Therefore, the capacity value Cfd of the capacity CAB (n) is substantially equal to the sum of the capacity value Cfd1 of the capacity CA (n) and the capacity value Cfd2 of the capacity CB (n) described above in the present embodiment, and Cfd≈Cfd1 + Cfd2. It becomes.

In this comparative example, focusing on the pixel block BL (n), when both the connected transistors SWa (n) and SWa (n-1) are turned off, the charge-voltage conversion capacitance of the node P (n) is the capacitance CAB ( n). Therefore, the capacity value of the charge-voltage conversion capacity of the node P (n) becomes Cfd, which is the minimum in the comparative example, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity becomes large. Can be read.

In this comparative example, focusing on the pixel block BL (n), one or more predetermined number of connected transistors in the on state of each connected transistor SWa are electrically connected to the node P (n). In this state, the capacitance value of the charge-voltage conversion capacitance of the node P (n) increases according to the number of connected transistors in the ON state, and the number of saturated electrons can be increased. As a result, the dynamic range can be expanded.

However, in this comparative example, the capacitance value of the charge-voltage conversion capacitance of the node P (n) cannot be made smaller than Cfd≈Cfd1 + Cfd2. Therefore, according to this comparative example, the charge-voltage conversion coefficient cannot be increased so much, and it cannot be read out with a very high SN ratio.

On the other hand, according to the present embodiment, since the connected transistor SWb is added, the minimum capacitance value of the charge-voltage conversion capacitance of the node P (n) is set to Cfd1≈Cfd-Cfd2 as described above. It can be made smaller than the comparative example.

Therefore, according to the present embodiment, the dynamic range can be expanded and the SN ratio at the time of high-sensitivity reading can be improved as compared with the comparative example.

In the present embodiment, the connecting transistors SWa and SWb are provided between all the two nodes P that are sequentially adjacent to each other in the column direction, but the present invention is not necessarily limited to this. For example, no connecting transistors SWa and SWb are provided between the q nodes (q is an integer of 2 or more) arranged in the column direction and the nodes P adjacent to the node P on the lower side in the figure. You may keep the space open at all times. In this case, as the number of q is smaller, the maximum number of the predetermined number in the second operation mode becomes smaller and the degree of expansion of the dynamic range decreases, but the SN at the time of high-sensitivity reading is compared with the comparative example. The ratio can be improved.

Each operation example described with reference to FIGS. 6 to 8 is an example of an operation of reading out the signal charge of the photodiode PD of each pixel PX without mixing it with the signal charge of the photodiode PD of another pixel PX. Met. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, the connected transistors SWa (n-1), SWb (n-1), SWa (n), and SWb (n) are turned on, and the nodes P (n-1), P (n), and P (n + 1) are connected to each other. When TXA (n-1), TXA (n), and TXA (n + 1) are turned on at the same time by connecting them, three pixels of the same color PXA (n-1) and PXA (n) in the case of assuming a Bayer arrangement or the like. , PXA (n-1) photodiodes PDA (n-1), PDA (n), PDA (n-1) nodes P (n-1), P (n), P in which the signal charges are connected to each other. It is averaged by (n + 1), and the function of mixed reading of three pixels of the same color can be realized. At this time, the connection transistors SWb (n-2) and SWa (n + 1) are turned off, and the connection is electrically connected to the nodes P (n-1), P (n), and P (n + 1). By minimizing the number of transistors, the charge-voltage conversion capacitance value at the connected nodes P (n-1), P (n), P (n + 1) is minimized, and the same color 3 pixels are mixed at the highest SN ratio. It can be read. On the other hand, in addition to the connected transistors SWa (n-1), SWb (n-1), SWa (n), and SWb (n), one or more on-state connected transistors are nodes P (n-1), P. If it is electrically connected to (n) and P (n + 1), the charges at the connected nodes P (n-1), P (n) and P (n + 1) are increased according to the number of the connections. The voltage conversion capacitance value becomes large, and the dynamic range of the same color 3-pixel mixed reading can be expanded.

[Second Embodiment]
FIG. 11 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state image sensor of the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIGS. 4 and 5. In FIGS. 11 and 12, the same or corresponding elements as those in FIGS. 3, 4 and 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

The difference between the present embodiment and the first embodiment is that an adjustment capacitance CB'having a capacitance value Cfd3 is added to each wiring 72. Since the capacitance CB (n) is the capacitance between the wiring 72 (n) and the reference potential when the connected transistors SWa (n) and SWb (n) are off, the adjustment capacitance CB'(n) Is also included in the capacity CB (n), but the adjusted capacity CB'adds the capacity value Cfd3 to the configuration forming the capacity value Cfd2 of the capacity CB (n) in the first embodiment. In order to clearly indicate that it is a component, the adjusted capacitance CB'is shown separately from the capacitance CB (n) in FIGS. 11 and 12. In the first embodiment, the capacitance value of the capacitance CB (n) is Cfd2, whereas in the present embodiment, the capacitance value of the capacitance CB (n) is Cfd2 + Cfd3. These points are the same for the other capacitance CB, the wiring 72, and the adjustment capacitance CB'.

According to the present embodiment, the same advantages as those of the first embodiment can be obtained, and the capacity value of the capacity CB can be set to an arbitrary desired capacity value by providing the adjustment capacity CB'. it can.

Specifically, the adjustment capacitance CB'is defined as, for example, (i) the area of the wiring 72 by making at least a part of the wiring width of the wiring 72 wider than the wiring width of other wiring in the pixel block BL. Is wider than the area of the wiring 72 in the first embodiment, (ii) connecting the MOS capacitance to the wiring 72, and (iii) connecting the diffusion capacitance that does not constitute the connecting transistors SWa and SWb. (Iv) Make the area of the drain diffusion region 47 of the connection transistor SWa wider than the area of the drain diffusion region 47 in the first embodiment, and (v) make the area of the source diffusion region 49 of the connection transistor SWb wider than the area of the first embodiment. It can be configured by making one or a combination of two or more of the area larger than the area of the source diffusion region 49 in the embodiment.

Here, an example of setting the capacity value Cfd3 of the adjustment capacity CB'will be described. It is desirable that the capacity value of the charge-voltage conversion capacity of the node P is an integral multiple of the reference capacity value. However, in the structure of the first embodiment described above, when the adjustment capacity CB'is not added, the capacity value Cfd2 of the capacity CB is generally smaller than the capacity value Cfd1 of the capacity CA. Therefore, for example, in order to double the capacitance value of the charge-voltage conversion capacitance of the node P (n) with the reference capacitance value, the connection transistors SWa (n) and SWb (n) are turned on and the node P (n) is turned on. ) Is set to 2 × Cfd1 + Cfd2 + 2 × Csw, and two pixel blocks BL (n) and BL (n + 1) are used.

On the other hand, in the present embodiment, when the adjustment capacitance CB'is formed so that the capacitance value Cfd3 of the adjustment capacitance CB'is Cfd1-Cfd2, the capacitance value of the capacitance CB becomes cfd2 + Cfd3 = Cfd1. Therefore, in order to double the capacity value of the charge-voltage conversion capacity of the node P (n) to the reference capacity value, it is only necessary to turn on the connection transistor SWa (n), and one pixel block BL (n). All you have to do is use. Further, when handling a larger amount of saturated charge, the number of pixel blocks BL to be connected can be significantly reduced.

The setting example of the capacity value Cfd3 of the adjustment capacity CB'is only an example, and is not limited to this.

In order to bring the capacity value of the charge-voltage conversion capacity of the node P close to an integral multiple of the reference dose value, the capacity value of the capacity CB is a value within ± 20% of the capacity value of the capacity CA. It is preferable, and it is more preferable that the value is within the range of ± 10% with respect to the capacity value of the capacity CA.

[Third Embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state image sensor 84 of an electronic camera according to a third embodiment of the present invention, and corresponds to FIG. In FIG. 13, elements that are the same as or correspond to the elements in FIG. 2 are designated by the same reference numerals, and duplicate description thereof will be omitted.

The difference between the present embodiment and the first embodiment is that in the first embodiment, the photodiode PDB and the transfer transistor TXB are removed in each pixel block BL in the first embodiment. The point is that the pixel block BL is a pixel PXA. However, in the present embodiment, the density in the row direction of the photodiode PDA is doubled the density in the row direction of the photodiode PDA in the first embodiment, and the photodiode in the first embodiment is used. It is the same as the density in the column direction of the entire PDA and PDB. In the present embodiment, n indicates the row of the pixel block BL and at the same time indicates the row of the pixel PXA.

In other words, in the first embodiment, each pixel block BL is composed of two pixel PXs (PXA, PXB), whereas in the present embodiment, each pixel block BL is one. It is composed of the pixels PX (PXA) of. Then, in the first embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of nodes P, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in this embodiment, only the PXA) has a set of nodes P, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL.

Basically, the description of the first embodiment fits as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of the present embodiment will be omitted here.

The present embodiment also provides the same advantages as the first embodiment.

In the present invention, the same modification as that obtained by modifying the first embodiment may be applied to the second embodiment.

[Fourth Embodiment]
FIG. 14 is a circuit diagram showing a schematic configuration of a solid-state image sensor 94 of an electronic camera according to a fourth embodiment of the present invention, and corresponds to FIG. FIG. 15 is an enlarged circuit diagram showing the vicinity of the four pixel blocks BL sequentially arranged in the column direction in FIG. 14, and corresponds to FIG. In FIGS. 14 and 15, elements that are the same as or correspond to the elements in FIGS. 2 and 3 are designated by the same reference numerals, and duplicate description thereof will be omitted. The difference between the present embodiment and the first embodiment is described below.

In the present embodiment, in the first embodiment, the first connecting transistor SWa, the second connecting transistor SWb, and the wirings 71 and 72 are removed, and instead, the first node Pa and the corresponding node Pa correspond to the first node Pa. First transistor SWA as a first switch unit that electrically connects and disconnects from the second node Pb, and a second switch that electrically connects and disconnects between the two second nodes Pb. A second transistor SWB as a unit and wirings 97 and 98 are provided.

The first node Pa (n) of the pixel block BL (n) corresponds to the node P (n) in the first embodiment. The transfer transistor TXA (n) transfers an electric charge from the photodiode PDA (n) to the first node Pa (n), and the transfer transistor TXB (n) is transferred from the photodiode PDB (n) to the first node Pa (n). ) To transfer the charge. A capacitance (charge-voltage conversion capacitance) is formed in the first node Pa (n) with the reference potential, and the charge transferred to the first node Pa (n) is converted into a voltage by the capacitance. To. The amplification transistor AMP (n) outputs a signal corresponding to the potential of the first node Pa (n). The reset transistor RST (n) resets the potential of the first node Pa (n). These points are the same for the rows of other pixel blocks BL.

The first transistor SWA (n) constitutes a first switch unit that electrically connects and disconnects between the first node Pa (n) and the corresponding second node Pb (n). ing. Such a first switch unit can be configured by combining switches such as a plurality of transistors, but in order to simplify the structure, a single first transistor SWA as in the present embodiment. It is preferably composed of (n). These points are the same for the other first transistor SWA.

Each second transistor SWB is a second node Pb corresponding to the first node Pa of one pixel block BL and the other for each of two pixel blocks BL adjacent to each other in the column direction of each pixel block BL. A second switch unit is configured so as to electrically connect and disconnect from the second node Pb corresponding to the first node Pa of the pixel block BL of the above. As a result, in the present embodiment, the first node Pa of the three or more pixel blocks BL is connected in a string by the plurality of second switch portions. The second switch unit as described above can be configured by combining switches such as a plurality of transistors, but in order to simplify the structure, a single second transistor as in the present embodiment. It is preferably composed of SWB.

For example, the second transistor SWB (n) is the second node Pb (n) corresponding to the first node Pa (n) of the pixel block BL (n) in the nth row and the pixels in the n-1th row. It is provided so as to electrically connect and disconnect from the second node Pb (n-1) corresponding to the first node Pa (n-1) of the block BL (n-1). This point is the same for the other second transistor SWB.

The gate electrode of the amplification transistor AMP (n) of the pixel block BL (n), the source region of the reset transistor RST (n), the drain diffusion region of the transfer transistors TXA (n) and TXB (n), and the first transistor SWA. The source diffusion regions of (n) are electrically connected to each other by wiring 97 (n) to conduct electricity. The first node Pa (n) corresponds to the wiring 97 (n) and the entire portion electrically connected to the wiring 97 (n) to be electrically connected to the wiring 97 (n). These points are the same for the rows of other pixel blocks BL.

The drain diffusion region of the first transistor SWA (n), the drain diffusion region of the second transistor SWB (n), and the source diffusion region of the second transistor SWB (n + 1) are electrically connected to each other by the wiring 98 (n). It is connected and conducting. The second node Pb (n) corresponds to the wiring 98 (n) and the entire portion electrically connected and conducting with the wiring 98 (n). These points are the same for the other first transistor SWA and the other second transistor SWB.

The gate of the first transistor SWA is commonly connected to the control line 95 for each row, to which the control signal φSWA is supplied from the vertical scanning circuit 21. The gate of the second transistor SWB is commonly connected to the control line 96 line by row, to which the control signal φSWB is supplied from the vertical scanning circuit 21.

In FIGS. 14 and 15, CC (n) is the capacitance between the first node Pa (n) and the reference potential when the first transistor SWA (n) is off. Let the capacitance value of the capacitance CC (n) be Cfd1'. The CD (n) is the capacitance between the wiring 98 (n) and the reference potential when the first transistor SWA (n) and the second transistors SWB (n) and SWB (n + 1) are off. is there. The capacity value of the capacity CD (n) is Cfd2'. These points are the same for the other first transistor SWA and the other second transistor SWB.

The capacitance CC (n) is the capacitance of the drain diffusion region of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the reset transistor RST (n), and the source of the first transistor SWA (n). It is composed of the capacitance of the diffusion region, the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 97 (n), and the total of these capacitance values is the capacitance value Cfd1'of the capacitance CC (n). Become. This point is the same for the rows of other pixel blocks BL.

Since the capacitance of the source diffusion region of the second transistor SWB (n) is not a component of the capacitance CC (n), the capacitance value Cfd1'of the capacitance CC (n) becomes smaller by that amount. In this regard, in the first embodiment, not only the capacitance of the source diffusion region 46 of the connecting transistor SWa (n) but also the capacitance of the drain diffusion region 48 of the connecting transistor SWb (n-1) is a component of the capacitance CB. Therefore, the capacity value Cfd1 of the capacity CB is increased by that amount. That is, the capacitance value Cfd1'in the present embodiment is smaller than the capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance.

Here, the value of the channel capacitance when the first transistor SWA is ON and the value of the channel capacitance when the second transistor SWB is ON are both set to Csw. Usually, the capacitance value Csw is a small value with respect to the capacitance values Cfd1'and Cfd2'.

Now, paying attention to the pixel block BL (n), the first transistor SWA (n) is turned off (that is, the on-state transistor of each of the first transistor SWA and each second transistor SWB is the first. The capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CC (n). It becomes. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1'. This state corresponds to the state of the period T2 in FIG. 16 showing the first operation mode described later.

Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) is turned on, among the first transistor SWA and each second transistor SWB, other than the first transistor SWA (n). Unless the on-state transistor is electrically connected to the first node Pa (n) (specifically, here, the second transistors SWB (n), SWB (n + 1)). (If is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CD (n) and the first transistor with respect to the capacitance CC (n). The channel capacitance when SWA (n) is on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1'+ Cfd2' + Csw≈Cfd1'+ Cfd2'. This state corresponds to the state of the period T2 in FIG. 17, which shows the operation mode of the second A described later.

Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, among the first transistor SWA and each second transistor SWB, Unless the on-state transistors other than the transistors SWA (n) and SWB (n + 1) are electrically connected to the first node Pa (n) (here, specifically, the transistor SWB). (If (n), SWA (n + 1), SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is the capacitance CD (n) with respect to the capacitance CC (n). The channel capacitance at the time of turning on the capacitance CD (n + 1) and the transistors SWA (n) and SWB (n + 1) is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 ′ + 2 × Cfd2 ′ + 2 × Csw≈Cfd1 ′ + 2 × Cfd2 ′. This state corresponds to the state of the period T2 in FIG. 18 showing the operation mode of the second B described later.

Furthermore, focusing on the pixel block BL (n), when the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, each first transistor SWA and each second transistor are turned on. Among the transistors SWB in the above, unless the on-state transistors other than the transistors SWA (n), SWA (n + 1), and SWB (n + 1) are electrically connected to the first node Pa (n). (Specifically, if the transistors SWB (n) and SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is relative to the capacitance CC (n). The channel capacitances of the capacitance CD (n), the capacitance CD (n + 1), the capacitance CC (n + 1), and the transistors SWA (n), SWA (n + 1), and SWB (n + 1) at the time of on are added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 ′ + 2 × Cfd2 ′ + 3 × Csw≈2 × Cfd1 ′ + 2 × Cfd2 ′. This state corresponds to the state of the period T2 in FIG. 19 showing the operation mode of the second C described later.

Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistors SWB (n + 1) and SWB (n + 2) are turned on, each of the first transistor SWA and each second transistor is turned on. Among the transistors SWB, the on-state transistors other than the transistors SWA (n), SWB (n + 1), and SWB (n + 2) must be electrically connected to the first node Pa (n) ( Here, specifically, if the transistors SWA (n + 1), SWA (n + 2), SWB (n), and SWB (n + 3) are off), the charge-voltage conversion capacitance of the first node Pa (n) is To the capacitance CC (n), the channel capacitances of the capacitance CD (n), the capacitance CD (n + 1), the capacitance CD (n + 2), and the transistors SWA (n), SWB (n + 1), and SWB (n + 2) are added. It will be the one that was done. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 ′ + 3 × Cfd2 ′ + 3 × Csw≈Cfd1 ′ + 3 × Cfd2 ′. This state corresponds to the state of the period T2 in FIG. 20, which shows the operation mode of the second C described later.

As described above, if there is no on-state transistor electrically connected to the first node Pa (n) among the first transistor SWA and each second transistor SWB, the first node Pa ( Since the capacity value of the charge-voltage conversion capacity of n) becomes the minimum capacity value Cfd1'and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity becomes large, it is possible to read at the highest SN ratio. Then, as described above, the capacitance value Cfd1'is smaller than the minimum capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance. Therefore, according to the first embodiment, the first embodiment. Compared with the embodiment, the charge-voltage conversion coefficient becomes larger, and reading with a higher SN ratio becomes possible.

On the other hand, among the first transistor SWA and each second transistor SWB, the number of on-state transistors electrically connected to the first node Pa (n) is increased to one or more desired number. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) can be increased to a desired value, and a large signal charge amount can be handled, so that the number of saturated electrons can be increased. it can. As a result, the dynamic range can be expanded.

The first node Pa (n) of the pixel block BL (n) has been described above, but the same applies to the first node Pa (n) of the other pixel block BL.

FIG. 16 is a timing chart showing the first operation mode of the solid-state image sensor 94 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and the first node Pa of the selected pixel block BL among the first transistor SWA and each second transistor SWB is selected. On the other hand, in the state where there is no on-state transistor electrically connected (the state in which the charge-voltage conversion capacity of the first node Pa is the minimum), the transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read out row by row. In the example shown in FIG. 16, the signals of all pixels PXA and PXB are read, but the present invention is not limited to this, and for example, thinning-out reading may be performed by thinning out the pixel rows. This point is the same for each of the examples shown in FIGS. 17 to 20 described later.

Since the operation of the first operation mode shown in FIG. 16 is clear from the above description, the detailed description thereof will be omitted.

FIG. 17 is a timing chart showing the operation mode of the second A of the solid-state image sensor 94 shown in FIG. The second operation mode is one of the second operation modes. In this second operation mode, each pixel block BL is sequentially selected row by row, and one or more predetermined number of on-state transistors of each first transistor SWA and each second transistor SWB are selected. , The transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on in a state of being electrically connected to the first node Pa of the selected pixel block BL, and the selected pixel is selected. This is an example of an operation of sequentially reading out the signals of the photodiodes PDA and PDB of the block BL line by line. The second operation mode is an example of the operation in which the predetermined number is one (one of the first transistor SWA) in the second operation mode.

Since the operation of the operation mode of the second A shown in FIG. 17 is clear from the above description, the detailed description thereof will be omitted.

FIG. 18 is a timing chart showing the operation mode of the second B of the solid-state image sensor 94 shown in FIG. The operation mode of the second B is another operation mode of the second operation mode, and the predetermined number is two (one of the first transistor SWA and one of the second transistor SWB). This is an example of the operation. Since the operation of the operation mode of the second B shown in FIG. 18 is clear from the above description, the detailed description thereof will be omitted.

FIG. 19 is a timing chart showing the operation mode of the second C of the solid-state image sensor 94 shown in FIG. The operation mode of the second C is still one other operation mode of the second operation mode, and the predetermined number is three (two of the first transistor SWA and one of the second transistor SWB). This is an operation example. Since the operation of the operation mode of the second C shown in FIG. 19 is clear from the above description, the detailed description thereof will be omitted.

FIG. 20 is a timing chart showing a second D operation mode of the solid-state image sensor 94 shown in FIG. The second operation mode is still one operation mode of the second operation mode, and the predetermined number is three (one of the first transistor SWA and two of the second transistor SWB). This is an operation example. Since the operation of the second D operation mode shown in FIG. 20 is clear from the above description, the detailed description thereof will be omitted.

According to the present embodiment, the dynamic range can be expanded and the SN ratio at the time of high-sensitivity reading can be improved as compared with the comparative example, as in the first embodiment. Further, according to the present embodiment, the charge-voltage conversion coefficient becomes larger than that of the first embodiment, and high-sensitivity reading with a higher SN ratio becomes possible.

In the present embodiment, the second transistor SWB is provided between all the two second nodes Pb sequentially adjacent to each other in the column direction, but the present invention is not necessarily limited to this. For example, between the second node Pb every r (r is an integer of 2 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb, The second transistor SWB may not be provided and the space between them may be left open at all times. In this case, as the number of r is smaller, the maximum number of the predetermined number in the second operation mode becomes smaller and the degree of expansion of the dynamic range decreases, but the SN at the time of high-sensitivity reading is compared with the comparative example. The ratio can be improved. Further, for example, between the second node Pb every s (s is an integer of 1 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. May not be provided with the second transistor SWB and may be electrically short-circuited between them. Further, for example, between the second node Pb every u (u is an integer of 1 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. While providing only the second transistor SWB, between the second node Pb other than every u node arranged in the column direction and the second node Pb adjacent to the second node Pb on the lower side in the figure. It may be electrically short-circuited.

As in the second embodiment, the wiring 98 may be provided with an adjustment capacity in the present embodiment. Further, also in the present embodiment, the capacity value of the capacity CD may be set to a value within the range of ± 20% with respect to the capacity value of the capacity CC, or ± 10% with respect to the capacity value of the capacity CC. The value may be within the range. These points are the same for the fifth embodiment described later.

Each operation example shown in FIGS. 16 to 20 was an example of an operation of reading out the signal charge of the photodiode PD of each pixel PX without mixing it with the signal charge of the photodiode PD of another pixel PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, the first node Pa (n-1) is turned on by turning on the first transistors SWA (n-1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1). , Pa (n), Pa (n + 1) are connected to each other, and TXA (n-1), TXA (n), TXA (n + 1) are turned on at the same time. A first in which the signal charges of the photodiodes PDA (n-1), PDA (n), and PDA (n-1) of the pixels PXA (n-1), PXA (n), and PXA (n-1) are connected to each other. It is averaged by the nodes Pa (n-1), Pa (n), and Pa (n + 1) of the above, and the function of mixed reading of three pixels of the same color can be realized. At this time, the second transistors SWB (n-2) and SWB (n + 2) are turned off and electrically connected to the first nodes Pa (n-1), Pa (n) and Pa (n + 1). Charge-voltage conversion capacitance values at the connected first nodes Pa (n-1), Pa (n), Pa (n + 1) by minimizing the number of on-state first or second transistors. Is the minimum, and the same color 3-pixel mixed reading can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA (n-1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1), each first transistor SWA and each second transistor If one or more on-state transistors of the transistors SWB of the above are electrically connected to the first node Pa (n-1), Pa (n), Pa (n + 1), the transistor is used. Depending on the number, the charge-voltage conversion capacitance values at the connected first nodes Pa (n-1), Pa (n), and Pa (n + 1) increase, and the dynamic range of the same color 3-pixel mixed readout is expanded. Can be done.

[Fifth Embodiment]
FIG. 21 is a circuit diagram showing a schematic configuration of a solid-state image sensor 104 of an electronic camera according to a fifth embodiment of the present invention, and corresponds to FIG. In FIG. 21, elements that are the same as or correspond to the elements in FIG. 14 are designated by the same reference numerals, and duplicate description thereof will be omitted.

The difference between the present embodiment and the fourth embodiment is that in the fourth embodiment, the photodiode PDB and the transfer transistor TXB are removed in each pixel block BL, and each of them is different from the fourth embodiment. The point is that the pixel block BL is a pixel PXA. However, in the present embodiment, the density in the row direction of the photodiode PDA is doubled the density in the row direction of the photodiode PDA in the fourth embodiment, and the photodiode in the fourth embodiment is used. It is the same as the density in the column direction of the entire PDA and PDB. In the present embodiment, n indicates the row of the pixel block BL and at the same time indicates the row of the pixel PXA.

In other words, in the fourth embodiment, each pixel block BL is composed of two pixel PXs (PXA, PXB), whereas in the present embodiment, each pixel block BL is one. It is composed of the pixels PX (PXA) of. Then, in the fourth embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in the present embodiment, only the PXA) has a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. doing.

Basically, the description of the fourth embodiment fits as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of the present embodiment will be omitted here.

The present embodiment also provides the same advantages as the fourth embodiment.

[Sixth Embodiment]
FIG. 22 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state image sensor of the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 23 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 22, and corresponds to FIGS. 4 and 5. In FIGS. 22 and 23, the same or corresponding elements as the elements in FIGS. 3, 4 and 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

Note that, in FIG. 23, the control line 24 (n), which is not shown in FIGS. 4 and 5, is specified, but the control line 24 (n) is not newly added in the present embodiment. .. That is, although the control line 24 (n) also exists in the other embodiments, the illustration is omitted.

The control line 24 (n) is a control line through which the control signal φRST (n) is transmitted, as described with reference to FIG. 3 in the first embodiment. The gate of the reset transistor RST (n) is commonly connected to the control line 24 (n) line by line, to which the control signal φRST (n) is supplied from the vertical scanning circuit 21. As shown in FIG. 23, the control line 24 (n) is arranged so as to be substantially parallel to the node P (n), and is located between the control line 24 (n) and the node P (n). The binding capacitance CRSTA (n) is formed. In the following description, the capacitance value of the coupling capacitance CRSTA (n) is defined as Cra.

The difference between the present embodiment and the first embodiment is described below. In the present embodiment, in each pixel block BL (n), the dummy wiring DP (n) is arranged substantially in parallel with the wiring 72 (n). The dummy wiring DP (n) is a wiring pattern in which a part of the control line 24 (n) is extended. That is, one end of the dummy wiring DP (n) is connected to the control line 24 (n), but the other end extending between the pixel blocks BL is not connected anywhere, especially for circuit control. It can be said that this is a dummy wiring pattern that has no meaning. By arranging the dummy wiring DP (n) substantially parallel to the wiring 72 (n), the wiring 72 (n) and the dummy wiring DP (n) are coupled as shown in FIGS. 22 and 23. Capacitive CRSTB (n) is formed. In the following description, the capacitance value of the coupling capacitance CRSTB (n) is defined as Crb. In the first embodiment, the control line 24 (n) and the wiring 72 (n) are hardly connected, and the Crb is extremely small. In the present embodiment, since the dummy wiring DP (n) is provided, Crb takes a large value as compared with the first embodiment.

The shape of the dummy wiring DP (n) may be different from that described above. For example, only the portion parallel to the wiring 72 (n) may be used, and the portion extending between the pixel blocks BL may be omitted. Further, in order to increase the coupling capacitance CRSTB (n), it is desirable to make the pattern of the dummy wiring DP (n) as thick as possible. Further, the coupling capacitance between the control line 24 (n) and the wiring 72 (n) may be increased by a method different from that for providing the dummy wiring DP (n).

FIG. 24 is a timing chart illustrating how the potential of the node P (n) is reset. At time t0, the control signal φRST (n) is set to H, the reset transistor RST (n) on the nth line is temporarily turned on, and the potential of the node P (n) is temporarily reset to the power supply potential VDD. After that, when the control signal φRST (n) is set to L, the reset transistor RST (n) is turned off. At this time, the potential of the node P (n) decreases from the power supply potential VDD by the feedthrough amount ΔV, and becomes the potential VDARK.

When the connected transistors SWa (n), SWb (n), and SWb (n-1) are off, the feedthrough amount ΔV is (Cra / Cfd1) × Vrst. Here, Vrst is the amplitude of the control signal φRST (n). As described above, Cfd1 is the capacitance value of the capacitance CA (n), and Cra is the capacitance value of the coupling capacitance CRSTA (n).

On the other hand, when the connecting transistor SWa (n) is turned on, the feedthrough amount ΔV is ((Cra + Crb) / (Cfd1 + Cfd2)) × Vrst. As described above, Cfd2 is the capacitance value of the capacitance CB (n), and Crb is the capacitance value of the coupling capacitance CRSTB (n).

In the first embodiment, Crb is extremely small. Assuming that Crb is 0, the feedthrough amount ΔV when the connecting transistor SWa (n) is on is (Cra / (Cfd1 + Cfd2)). Here, the capacitance value Cra is constant regardless of whether the connected transistor SWa (n) is turned on or off. Therefore, in the first embodiment, the feedthrough amount ΔV becomes smaller when the connection transistor SWa (n) is turned on. Therefore, the potential VDARK is higher than when the connecting transistor SWa (n) is off.

On the other hand, in the present embodiment, Crb is larger than that of the first embodiment. Therefore, the feedthrough amount ΔV is larger than that of the first embodiment, and the potential VDARK can be lowered.

In order to maintain good linearity of the output from the amplification transistor AMP (n), it is necessary to operate the amplification transistor AMP (n) in the saturation region. That is, it is necessary to make the drain-source voltage Vds larger than the saturation voltage Vdsat. The drain-source voltage Vds is the difference between the drain voltage Vd and the source voltage Vs, and is expressed as Vd-Vs. Here, from FIG. 22, the drain voltage Vd is the power supply voltage Vdd. The source voltage Vs is Vg-Vth-√ (2 x Id / β). Vg is the gate voltage, Vth is the threshold value of the amplification transistor AMP (n), Id is the drain current, and β is the element parameter.

From this, it can be seen that as the gate voltage Vg increases, the source voltage Vs increases, that is, the drain-source voltage Vds decreases. At this time, the amplification transistor AMP (n) may not be able to operate in the saturation region. Therefore, it is necessary to keep the potential VDARK after the reset of the node P (n) low. Further, there is a technique of embedding the amplification transistor AMP (n) in order to reduce noise, but when such a technique is applied, the threshold value Vth is lowered, so that the source voltage Vs is further raised. Therefore, it is more important to keep the potential VDARK low.

In the present embodiment, the feedthrough amount ΔV can be increased even when the connection transistor SWa (n) is turned on, and the amplification transistor AMP (n) can be reliably operated in the saturation region. The linearity of the output of the amplification transistor AMP (n) is improved as compared with the first embodiment.

Further, the capacitance values of Cfd2 and Crb can be adjusted, and by appropriately adjusting the capacitance values, the feedthrough amount ΔV can be made substantially the same regardless of whether the connected transistor SWa (n) is turned on or off. In this way, the potential VDARK after the reset of the node P (n) can be made substantially the same regardless of whether the connected transistor SWa (n) is turned on or off.

[7th Embodiment]
FIG. 25 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state image sensor of the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 26 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 25, and corresponds to FIGS. 4 and 5. In FIGS. 25 and 26, the same or corresponding elements as those in FIGS. 3, 4 and 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

Note that, in FIG. 26, three control lines 22 (n), 24 (n), and 27 (n), which are not shown in FIGS. 4 and 5, are specified, but these three control lines 22 ( n), 24 (n), and 27 (n) are not newly added in the present embodiment. That is, although these three control lines 22 (n), 24 (n), and 27 (n) also exist in the other embodiments, they are not shown.

The control line 22 (n) is a control line through which the control signal φSWa (n) is transmitted, as described with reference to FIG. 3 in the first embodiment. The gate of the connecting transistor SWa (n) is commonly connected to the control line 22 (n) line by line, and the control signal φSWa (n) is supplied to the control line 22 (n) from the vertical scanning circuit 21.

The control line 24 (n) is a control line through which the control signal φRST (n) is transmitted, as described with reference to FIG. 3 in the first embodiment. The gate of the reset transistor RST (n) is commonly connected to the control line 24 (n) line by line, to which the control signal φRST (n) is supplied from the vertical scanning circuit 21.

The control line 27 (n) is a control line through which the control signal φSWb (n) is transmitted, as described with reference to FIG. 3 in the first embodiment. The gate of the connecting transistor SWb (n) is commonly connected to the control line 27 (n) line by line, and the control signal φSWb (n) is supplied from the vertical scanning circuit 21 to the control line 27 (n).

As shown in FIGS. 25 and 26, a coupling capacitance CRSTA (n) is formed between the node P (n) and the control line 24 (n). Similarly, a coupling capacitance CSWa (n) is formed between the wiring 72 (n) and the control line 22 (n), and the coupling between the wiring 72 (n) and the control line 27 (n) is coupled. The capacitance CSWb (n) is formed.

The difference between the present embodiment and the first embodiment is described below. In the present embodiment, the circuit configuration of the solid-state image sensor is the same as that of the first embodiment. In the present embodiment, the operations of the connected transistors SWa (n) and SWb (n) in each operation mode are different from those in the first embodiment. Hereinafter, the operation of the connected transistors SWa (n) and SWb (n) in each operation mode will be described with a focus on the pixel block BL (n).

FIG. 27 is a timing chart showing a first operation mode of the solid-state image sensor of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWa (n) is set to H and the connected transistor SWa ( This is the point where n) is turned on (immediately before time t1). After that, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWa (n) to L to turn off the connecting transistor SWa (n). To. Since other points are the same as those in the first embodiment, the description thereof will be omitted.

FIG. 28 is a timing chart showing the operation mode of the second A of the solid-state image sensor of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. 7. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWb (n) is set to H and the connected transistor SWb is turned on. This is the point where (n) is turned on (immediately before time t1). After that, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWb (n) to L to turn off the connecting transistor SWb (n). To. Since other points are the same as those in the first embodiment, the description thereof will be omitted.

FIG. 29 is a timing chart showing the operation mode of the second B of the solid-state image sensor of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWa (n + 1) is set to H and the connected transistor SWa ( This is the point where n + 1) is turned on (immediately before time t1). After that, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWa (n + 1) to L to turn off the connecting transistor SWa (n + 1). To. Since other points are the same as those in the first embodiment, the description thereof will be omitted.

As described above, in the present embodiment, when the node P (n) is reset, the outermost connecting transistor is (temporarily) turned on at substantially the same time. Here, the outermost connecting transistor is a connecting transistor located at the outermost end of the pixel block BL to be connected. For example, when the pixel block BL (n) is not connected, the outermost connecting transistor is either one of the connecting transistors SWa (n) and SWb (n-1). When the pixel block BL (n) and the pixel block BL (n + 1) are connected, the outermost connecting transistor is either one of the connecting transistors SWa (n + 1) and SWb (n-1).

FIG. 30 is a timing chart illustrating how the potential of the node P (n) is reset. In FIG. 30, the control signal φSW is a control signal supplied to the gate of the outermost connecting transistor. For example, when the outermost connecting transistor is the connecting transistor SWb (n-1), the control signal φSW is the control signal φSWb (n-1).

At time t0, the control signal φSW and the control signal φRST (n) supplied to the gate of the outermost connecting transistor are set to H substantially at the same time. As a result, the reset transistor RST (n) on the nth row is once turned on, and the pixel block BL is temporarily connected. At this time, the potential of the node P (n) is temporarily reset to the power supply potential VDD. After that, when the control signal φRST (n) is set to L, the reset transistor RST (n) is turned off. At this time, the potential of the node P (n) is lowered from the power supply potential VDD by the feedthrough amount ΔV1 according to the coupling capacitance by the control line 24 (n). Subsequently, when the control signal φSW is set to L, the outermost connecting transistor is turned off. At this time, the potential of the node P (n) is further lowered by the feedthrough amount ΔV2 to reach the potential VDARK.

As described above, in the present embodiment, by turning on / off the outermost connection switch when the potential of the node P (n) is reset, the potential of the node P (n) is further lowered by the feedthrough amount ΔV2. I'm letting you. Thereby, the potential VDARK can be further suppressed as compared with the first embodiment. Therefore, the same effect as that described in the sixth embodiment can be obtained.

Although the embodiments and modifications of the present invention have been described above, the present invention is not limited thereto.

4 Solid-state image sensor BL pixel block PX pixel PD photodiode TXA, TXB transfer transistor P node AMP amplification transistor SWa, SWb connection transistor

Claims (13)

A first pixel block having a first node to which the photoelectrically converted charge is transferred and a reset unit for resetting the potential of the first node.
A second pixel block with a second node to which the photoelectrically converted charges are transferred, and
A connection unit having a plurality of switches for connecting the first node and the second node, and
It is provided with a control line which is arranged parallel to the first node and outputs a control signal for controlling the reset unit.
The connection portion has at least a first switch, a second switch, and wiring connected to the first switch and the second switch.
The first switch is an image pickup device controlled so as to connect between the first node and the wiring when the potential of the first node is reset by the reset unit. In the image pickup device according to claim 1,
Before SL is the first switch, the distance to the first node, the imaging device located on the shorter position than the distance from the first switch to the second switch. In the image pickup device according to claim 1 or 2.
Before SL control line, the imaging device which is arranged parallel to the wiring. In the image pickup device according to any one of claims 1 to 3.
The second switch is connected to the second node and the wiring when the potential of the first node is reset by the reset unit during the period in which the first node and the wiring are connected by the first switch. An image sensor that is controlled to connect to and from wiring. In the image pickup device according to any one of claims 1 to 4.
The first pixel block has a first photoelectric conversion unit that converts light into electric charges.
The second pixel block, have a second photoelectric converter for converting light into an electric charge,
The electric charge converted by the first photoelectric conversion unit is transferred to the first node, and the electric charge is transferred to the first node.
The second node is an image sensor to which the electric charge converted by the second photoelectric conversion unit is transferred. In the image pickup device according to claim 5,
The first pixel block has a plurality of the first photoelectric conversion units, and has a plurality of the first photoelectric conversion units.
The second pixel block is an image sensor having a plurality of the second photoelectric conversion units. A first pixel block having a first node to which the photoelectrically converted charge is transferred and a reset unit for resetting the potential of the first node.
A second pixel block with a second node to which the photoelectrically converted charges are transferred, and
A connection unit having a plurality of switches for connecting the first node and the second node, and
A control line for outputting a control signal for controlling the reset unit is provided.
The connection portion has at least a first switch, a second switch, and wiring connected to the first switch and the second switch.
The control line is an image sensor arranged in parallel with the wiring. In the image pickup device according to claim 7,
The first switch is an image pickup device arranged at a position where the distance to the first node is shorter than the distance from the first switch to the second switch. In the image pickup device according to claim 7 or 8.
The first switch is an image pickup device controlled so as to connect between the first node and the wiring when the potential of the first node is reset by the reset unit. In the image pickup device according to any one of claims 7 to 9.
The second switch is connected to the second node and the wiring when the potential of the first node is reset by the reset unit during the period in which the first node and the wiring are connected by the first switch. An image sensor that is controlled to connect to and from wiring. In the image pickup device according to any one of claims 7 to 10.
The first pixel block has a first photoelectric conversion unit that converts light into electric charges.
The second pixel block, have a second photoelectric converter for converting light into an electric charge,
The electric charge converted by the first photoelectric conversion unit is transferred to the first node, and the electric charge is transferred to the first node.
The second node is an image sensor to which the electric charge converted by the second photoelectric conversion unit is transferred. In the image pickup device according to claim 11,
The first pixel block has a plurality of the first photoelectric conversion units, and has a plurality of the first photoelectric conversion units.
The second pixel block is an image sensor having a plurality of the second photoelectric conversion units. An image pickup apparatus comprising the image pickup device according to any one of claims 1 to 12.

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