JP4954540B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more preferably to a semiconductor device capable of storing data by using an organic compound in a memory circuit.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, an RFID tag (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, wireless chip), etc., is especially used in the company, on the market. Etc. have begun to be introduced.

  Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip is a memory circuit (also referred to as a memory). ) And a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided.

  In general, as a memory circuit provided in a semiconductor device, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), a mask ROM (Read Only Memory, a Read ROM). Examples include only memory (EEPROM), EEPROM (electrically erasable and programmable read only memory), and flash memory. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  In view of the above circumstances, it is an object of the present invention to provide a memory device and a semiconductor device that are nonvolatile, easy to manufacture, and additionally writable at a low cost.

  In order to solve the above problems, the present invention takes the following measures.

  A semiconductor device of the present invention is provided over a substrate, an element formation layer including a first transistor and a second transistor, a storage element provided over the element formation layer, and a storage element. The memory element has a stacked structure of a first conductive layer, an organic compound layer, and a second conductive layer, and the first conductive layer and the first transistor are electrically connected to each other. The sensor portion and the second transistor are electrically connected to each other.

  In another structure of the semiconductor device of the present invention, an element formation layer including a first transistor, a second transistor, and a third transistor provided on a substrate, and an element formation layer is provided. A memory element, a conductive layer functioning as an antenna, and a sensor portion provided above the memory element, the memory element having a stacked structure of a first conductive layer, an organic compound layer, and a second conductive layer And the first conductive layer and the first transistor are electrically connected, the sensor portion and the second transistor are electrically connected, and the conductive layer functioning as an antenna and the third transistor are electrically connected. It is characterized by being connected. The conductive layer functioning as an antenna is provided in the same layer as the first conductive layer.

  According to another configuration of the semiconductor device of the present invention, the connection between the sensor portion and the second transistor is such that the conductive layer provided in the sensor portion is electrically connected to the source or drain region of the second transistor. Is performed through conductive fine particles.

  Another structure of the semiconductor device of the present invention includes an element formation layer including a first transistor, a second transistor, and a sensor portion provided over a substrate, and a memory element provided over the element formation layer. The memory element has a stacked structure of a first conductive layer, an organic compound layer, and a second conductive layer, and the first conductive layer and the first transistor are electrically connected; The sensor portion and the second transistor are electrically connected.

  According to another structure of the semiconductor device of the present invention, an element formation layer including a first transistor, a second transistor, a third transistor, and a sensor portion provided over a substrate, and an element formation layer is provided. The memory element is provided and a conductive layer functioning as an antenna. The memory element has a stacked structure of a first conductive layer, an organic compound layer, and a second conductive layer. And the first transistor are electrically connected, the sensor portion and the second transistor are electrically connected, and the conductive layer functioning as an antenna is electrically connected to the third transistor. Yes. The conductive layer functioning as an antenna is provided in the same layer as the first conductive layer.

  Another structure of the semiconductor device of the present invention is characterized in that the sensor portion includes a photodiode or a phototransistor.

  According to another configuration of the semiconductor device of the present invention, an element formation layer including a first transistor and a second transistor provided on a substrate, a memory element and a sensor portion provided on the element formation layer are provided. The memory element has a stacked structure of a first conductive layer, a first organic compound layer, and a second conductive layer, and the sensor unit includes a third conductive layer and a second organic compound. The first conductive layer and the first transistor are electrically connected, and the third conductive layer and the second transistor are electrically connected. A semiconductor device characterized by that.

  In another structure of the semiconductor device of the present invention, an element formation layer including a first transistor, a second transistor, and a third transistor provided on a substrate, and an element formation layer is provided. A memory element and a sensor unit, and a conductive layer functioning as an antenna, and the memory element has a stacked structure of a first conductive layer, a first organic compound layer, and a second conductive layer, Has a stacked structure of a third conductive layer, a second organic compound layer, and a fourth conductive layer, the first conductive layer and the first transistor are electrically connected, and the third conductive The layer and the second transistor are electrically connected, and the conductive layer functioning as an antenna and the third transistor are electrically connected. Further, the conductive layer functioning as an antenna is provided in the same layer as the first conductive layer and the third conductive layer.

  Another structure of the semiconductor device of the present invention is characterized in that the first conductive layer and the third conductive layer are provided in the same layer. Further, the first organic compound layer and the second organic compound layer have the same material.

  Another structure of the semiconductor device of the present invention is characterized in that the distance between the first conductive layer and the second conductive layer of the memory element is changed by writing.

  Another structure of the semiconductor device of the present invention is characterized in that the transistor is an organic transistor.

  Another structure of the semiconductor device of the present invention is characterized in that the transistor is provided over a glass substrate or a flexible substrate.

  Another structure of the semiconductor device of the present invention is characterized in that the organic compound layer has a polymer compound.

  Another structure of the semiconductor device of the present invention is characterized in that the resistance of the memory element is irreversibly changed by writing.

  In addition, a method for manufacturing a semiconductor device of the present invention includes forming a plurality of transistors including at least a first transistor and a second transistor over a substrate, and a first conductive layer electrically connected to the first transistor; A second conductive layer electrically connected to the second transistor, and an insulating layer is selectively formed so as to cover the first conductive layer and an end portion of the second conductive layer. A conductive layer functioning as an antenna is formed so as to be electrically connected to the conductive layer, and after forming the conductive layer functioning as an antenna, a spin coating method, a screen printing method, or droplet discharge is performed so as to cover the second conductive layer. A layer having a high molecular compound is formed using a method, and a third conductive layer is formed so as to cover the organic compound layer. In this case, the conductive layer functioning as an antenna can be formed by performing heat treatment on a conductive paste provided by a screen printing method or a droplet discharge method.

  In another method for manufacturing a semiconductor device of the present invention, a plurality of transistors each including at least a first transistor and a second transistor are formed over a substrate, and the semiconductor device functions as an antenna electrically connected to the first transistor. A first conductive layer and a second conductive layer electrically connected to the second transistor are formed, and an insulating layer is selectively formed so as to cover an end portion of the second conductive layer and the first conductive layer A layer having a high molecular compound is formed by spin coating, screen printing, or a droplet discharge method so as to cover the second conductive layer, and a third conductive layer is formed to cover the organic compound layer. It is characterized by forming. In this case, the first conductive layer and the second conductive layer can be formed by a sputtering method or a CVD method.

  By using the present invention, it is possible to obtain a semiconductor device in which data can be written (added) other than during manufacturing and forgery by rewriting can be prevented. In addition, by using the present invention, an inexpensive semiconductor device having a memory element provided with a fine structure can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
In this embodiment, a structural example of a memory circuit including an organic compound layer in a memory element (hereinafter also referred to as an organic memory) will be described with reference to drawings. More specifically, the case where the structure of the memory circuit is a passive matrix type will be described.

  FIG. 1A shows an example of a structure of a semiconductor device according to the present invention. A bit line having a memory cell array 22 in which memory cells 21 are provided in a matrix, a column decoder 26a, a read circuit 26b, and a selector 26c. It has a drive circuit 26, a word line drive circuit 24 having a row decoder 24a and a level shifter 24b, an interface 23 having a write circuit and the like for performing exchanges with the outside. Note that the structure of the memory circuit 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 21 has a structure in which an organic compound layer is provided between a pair of conductive layers (hereinafter, also referred to as “organic memory element”). Here, a word line Wy (1 ≦ y ≦ n) is formed. The first conductive layer, the organic compound layer, and the second conductive layer constituting the bit line Bx (1 ≦ x ≦ m) are stacked. The organic compound layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  An example of a top structure of the memory cell array 22 is illustrated in FIG.

  The memory cell array 22 includes a first conductive layer 27 extending in a first direction, an organic compound layer provided so as to cover the first conductive layer 27, and a second direction different from the first direction (here, , And a second conductive layer 28 extending in the vertical direction. An organic compound layer is provided between the first conductive layer 27 and the second conductive layer 28. The first conductive layer 27 corresponds to the word line Wy, and the second conductive layer 28 corresponds to the bit line Bx.

  Next, a method for manufacturing a memory cell array including an organic memory element will be described with reference to FIGS. Note that FIG. 2 illustrates an example of a cross-sectional structure between A and B in the memory cell array 22 illustrated in FIG.

  First, a first conductive layer 27 is formed by selectively discharging a conductive composition over the substrate 30 (FIG. 2A). Further, the first conductive layer 27 is not limited to the droplet discharge method, and may be formed by using a vapor deposition method, a sputtering method, a CVD method, a spin coating method, a screen printing method, a gravure printing method, or the like. For example, the first conductive layer 27 can be formed by forming a conductive material over the entire surface by a sputtering method or a CVD method and then selectively etching it using a photolithography method.

  Next, an organic compound layer 29 is formed so as to cover the first conductive layer 27 (FIG. 2B). The organic compound layer 29 can be formed using a droplet discharge method, a screen printing method, a gravure printing, a spin coating method, an evaporation method, or the like. Working efficiency can be improved by using these methods.

  Next, a second conductive layer 28 is formed by selectively discharging a conductive composition over the organic compound layer 29 (FIG. 2C). Here, a memory element portion 39 having a plurality of organic memory elements each having a stacked structure of the first conductive layer 27, the organic compound layer 29, and the second conductive layer 28 is formed. Further, the second conductive layer 28 can be formed by other methods as shown in the formation of the first conductive layer. The second conductive layer 28 may be formed using a method different from that of the first conductive layer 27. For example, the first conductive layer 27 is formed on the entire surface with a conductive material by a CVD method or a sputtering method. Then, the first conductive layer 27 can be formed by selective etching, and the second conductive layer 28 can be directly and selectively formed by a droplet discharge method, a screen printing method, or the like. In this case, since it is not necessary to perform etching for forming the second conductive layer 28, damage to the organic compound layer 29 can be suppressed.

  Next, an insulating layer 31 functioning as a protective film is provided so as to cover the second conductive layer 28 (FIG. 2D).

  Through the above steps, a passive matrix memory cell array including an organic memory element can be formed. Next, the material used in each process described above will be specifically described.

  As the substrate 30, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating layer formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic such as PET generally has a lower heat-resistant temperature than the above-mentioned substrate, but it should be used if it can withstand the processing temperature in the manufacturing process. Is possible. Note that the surface of the substrate 30 may be planarized by polishing such as a CMP method.

  As the first conductive layer 27 and the second conductive layer 28, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo) , Iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. A single layer or a stacked structure including one kind of element or an alloy containing a plurality of such elements can be used. Examples of the alloy containing a plurality of the above elements include an alloy containing Al, Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, an alloy containing Al, Ni and C, or Al and An alloy containing Mo can be used. Other conductive polymers whose conductivity has been improved by doping, for example, conductive polyaniline, conductive polypyrrole, conductive polythiophene, polyethylenedioxythiophene (PEDOT) and polystyrene sulfonic acid (PSS) complexes, etc. Can do. A transparent conductive material may be used. In particular, a transparent conductive material is preferably used when data is written by applying an optical action. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added zinc oxide (GZO) can be used. It is. Indium tin oxide containing silicon oxide or indium oxide containing silicon oxide mixed with 2 to 20 wt% zinc oxide (ZnO) may be used. The above material can be formed by a droplet discharge method, an evaporation method, a sputtering method, a CVD method, a spin coating method, a screen printing method, a gravure printing method, or the like. For example, Ag can be selectively formed by a droplet discharge method, or Al can be formed by a vapor deposition method.

  As the organic compound layer 29, a layer made of an organic compound material having conductivity is provided in a single layer or a laminated structure. Specific examples of the organic compound material having conductivity include a polymer compound having carrier transportability.

  Examples of the polymer compound having carrier transportability include poly (p-phenylene vinylene) (PPV), [methoxy-5- (2-ethyl) hexyloxy] -p-phenylene vinylene (MEH-PPV), poly (9,9- Dialkylfluorene) (PAF), poly (9-vinylcarbazole) (PVK), polypyrroles, polythiophenes, polyacetylenes, polypyrenes, polycarbazoles, and the like can be used. Moreover, you may use the oligomer etc. whose polymerization degree is smaller than the said high molecular compound. These materials can be formed by a spin coating method, a droplet discharge method, a screen printing method, a gravure printing method, an evaporation method, or the like.

  As the insulating layer 31, an inorganic material containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like A single-layer structure such as these or a stacked structure thereof can be used. In addition, a single layer or a laminated structure is formed using an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, epoxy, or siloxane. Alternatively, an inorganic material and an organic material may be stacked. A siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The configuration shown in FIG. 2 is merely an example, and the configuration is not limited to this. A case different from the above configuration is shown in FIG.

  In FIG. 2, the organic compound layer 29 is formed on the entire surface so as to cover the first conductive layer 27. However, when there is a concern about the influence of the electric field in the lateral direction between adjacent memory cells, In order to separate the organic compound layer provided in the memory cell, an insulating layer 32 may be provided between the organic compound layers provided in each memory cell (FIG. 3A). That is, the organic compound layer 29 is selectively provided for each memory cell. In this case, the organic compound layer can be efficiently provided by selectively forming each memory cell using a droplet discharge method, a screen printing method, a gravure printing method, or the like.

  In addition, when the organic compound layer 29 is provided so as to cover the first conductive layer 27, the step of the organic compound layer 29 caused by the step between the first conductive layers 27 and the electric field in the lateral direction between the memory cells. In order to prevent the influence, an insulating layer 37 may be provided between the first conductive layers 27 so as to cover an end portion of the first conductive layer 27 (FIG. 3B). In this case, the insulating layer 37 can be selectively formed between the plurality of first conductive layers 27 by using a droplet discharge method.

  In the structure of FIG. 2, a rectifying element may be provided between the first conductive layer 27 and the organic compound layer 29 (FIG. 3C). The rectifying element is typically a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Of course, other configurations of diodes may be used. Here, a case where a PN junction diode including semiconductor layers 34 and 35 is provided between the first conductive layer and the organic compound layer is shown. One of the semiconductor layers 34 and 35 is an N-type semiconductor, and the other is a P-type semiconductor. As described above, by providing an element having a rectifying action, the margin and accuracy of the read and write operations can be improved.

  2 shows a configuration in which the memory element portion 39 having a plurality of organic memory elements is provided on the substrate 30, the present invention is not limited to this. A thin film transistor (TFT) 779 is provided on the substrate 30 and the memory element portion is provided thereabove. 39 (FIG. 3D), or a field effect transistor (FET) 778 that uses the substrate as a transistor channel region using a semiconductor substrate such as Si or an SOI substrate as the substrate 30; A memory element portion 39 may be formed thereabove (FIG. 3E). Note that although the example in which the memory element portion 39 is formed above the thin film transistor 779 or the field effect transistor 778 is shown here, the memory element portion 39 and the thin film transistor 779 or the field effect transistor 778 may be provided together. In this case, the memory element portion 39 and the thin film transistor 779 or the field effect transistor 778 can be provided by being manufactured in separate steps and then bonded together using a conductive film or the like. The thin film transistor 779 or the field effect transistor 778 may have any structure as long as it is a known structure.

  As described above, in this embodiment mode, a polymer material having carrier transportability is formed as an organic compound layer included in a memory element by a droplet discharging method, a printing method such as a screen printing method or a gravure printing method, a spin coating method, or the like. Therefore, a memory device or a semiconductor device that is easy to manufacture and inexpensive can be manufactured. Further, since the memory element portion described in this embodiment can be manufactured with a minute structure, a semiconductor device including a memory circuit having a large capacity can be obtained.

(Embodiment 2)
In this embodiment, a semiconductor device having a structure different from that of Embodiment 1 is described. Specifically, the case where the structure of the memory circuit is an active matrix type will be described.

  FIG. 4A shows an example of a structure of the semiconductor device of the present invention. A bit line having a memory cell array 222 in which memory cells 221 are provided in a matrix, a column decoder 226a, a read circuit 226b, and a selector 226c. It has a driver circuit 226, a word line driver circuit 224 having a row decoder 224a and a level shifter 224b, an interface 223 having a write circuit and the like for performing exchanges with the outside. Note that the structure of the memory circuit 216 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 221 includes at least a transistor 240 and a memory element 241 (organic memory element). The transistor 240 includes a first wiring and a bit line Bx (a word line Wy (1 ≦ y ≦ n)). 1 ≦ x ≦ m) is electrically connected to the second wiring.

  An example of a top structure of the memory cell array 222 is illustrated in FIG.

  The memory cell array 222 includes a first wiring 231 extending in a first direction and a second wiring 232 extending in a second direction (here, a vertical direction) different from the first direction in a matrix. It has been. Here, the second wiring 232 is electrically connected to one of the source and drain regions of the transistor 240, and the first wiring 231 is electrically connected to the gate electrode of the transistor 240. Further, the other of the source and drain regions of the transistor 240 that is not connected to the second wiring 232 is electrically connected to the first conductive layer 243, and the first conductive layer 243, the organic compound layer, and the second An organic memory element 241 is provided by a stacked structure with a conductive layer.

  Next, a method for manufacturing an organic memory having the above structure will be described with reference to FIGS. Note that FIG. 5 illustrates a cross-sectional view taken along line ab in the memory cell array 222 illustrated in FIG. 4B and a cross-sectional structure of a CMOS circuit included in the bit line driver circuit 226.

  First, a plurality of transistors 240 functioning as switching elements of a memory element and a transistor 248 forming a CMOS circuit included in the bit line driver circuit 226 are formed over the substrate 230. After that, a source electrode or a drain electrode is formed so as to be electrically connected to the source region or the drain region of the transistor 240 (FIG. 5A). Note that here, one of the source electrode and the drain electrode of the transistor 240 is used in combination as the first conductive layer 243 included in the memory element. In the case where a material different from that of the first conductive layer 243 and the source or drain electrode is used, after the source or drain electrode is formed, the first conductive layer 243 is electrically connected to the source or drain electrode. The layer 243 may be formed separately. The first conductive layer 243 can be formed by evaporation, sputtering, CVD, droplet discharge, spin coating, screen printing, gravure printing, or the like.

  Next, an insulating layer 249 functioning as a protective film is formed so as to cover the end portion of the first conductive layer 243 and the source and drain electrodes of the transistors 240 and 248 (FIG. 5B). The insulating layer 249 may be formed directly and selectively using, for example, a droplet discharge method, a screen printing method, or a gravure printing method, or may be selected after being formed using a CVD method, a sputtering method, or a spin coating method. Alternatively, the first conductive layer 243 may be exposed by etching.

  Next, an organic compound layer 244 is formed over the first conductive layer 243 (FIG. 5C). Note that the organic compound layer 244 may be formed over the entire surface as shown in FIG. 5C, or may be selectively formed so that the organic compound layer provided in each memory cell is separated. The organic compound layer 244 can be formed by a droplet discharge method, a screen printing method, a gravure printing method, a spin coating method, an evaporation method, or the like. As shown in FIG. 5, when the organic compound layer 244 is provided on the entire surface, the working efficiency can be improved by using a spin coating method or a vapor deposition method. In the case where the organic compound layer 244 is selectively provided, the material utilization efficiency can be improved by using a droplet discharge method, a screen printing method, a gravure printing method, or the like. Even when a spin coating method or a vapor deposition method is used, a mask can be selectively provided in advance, or an organic compound layer can be selectively provided by etching after being formed over the entire surface. The practitioner may select which method is used as appropriate.

  Next, the second conductive layer 245 is formed over the organic compound layer 244 (FIG. 5D). The second conductive layer 245 can be formed by a vapor deposition method, a sputtering method, a CVD method, a droplet discharge method, a spin coating method, a screen printing method, a gravure printing, or the like in the same manner as the first conductive layer. . The first conductive layer 243 and the second conductive layer 245 may be formed using different methods. A memory element 241 (organic memory element) is formed by a stacked structure of the first conductive layer 243, the organic compound layer 244, and the second conductive layer 245.

  Next, an insulating layer 256 functioning as a protective film is provided so as to cover the second conductive layer 245 (FIG. 5E). The insulating layer 256 can be formed with a single layer or a stacked structure using an evaporation method, a sputtering method, a CVD method, a droplet discharge method, a spin coating method, a screen printing method, a gravure printing, or the like.

  Through the above steps, a semiconductor device having an active matrix memory circuit can be formed. Next, the material used in each process will be specifically described.

  As the substrate 230, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating layer formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic such as PET generally has a lower heat-resistant temperature than the above-mentioned substrate, but it should be used if it can withstand the processing temperature in the manufacturing process. Is possible. Note that the surface of the substrate 230 may be planarized by polishing such as a CMP method.

  The transistor 240 may have any structure as long as it can function as a switching element. For example, a thin film transistor (TFT) may be formed over the substrate 230 using glass or a flexible substrate as the substrate 230, or the substrate may be used as a channel region of the transistor using a semiconductor substrate such as Si or an SOI substrate. A field effect transistor (FET) may be formed. An organic transistor using an organic material may be formed in the channel region of the transistor. FIG. 5 shows an example in which a planar thin film transistor is provided over an insulating substrate; however, a transistor having a staggered structure, an inverted staggered structure, or the like can also be formed.

  Further, any structure of the semiconductor layer included in the transistor 240 or the transistor 248 may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) can be formed. As a structure of the transistor, either a p-channel type or an n-channel type can be used, and a circuit can be a CMOS circuit using only a p-channel type, only an n-channel type, or both. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source and drain regions or the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  As the first conductive layer 243 or the second conductive layer 245, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo) , Iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. A single layer or a stacked structure including one kind of element or an alloy containing a plurality of such elements can be used. Examples of the alloy containing a plurality of the elements include an alloy containing Al, Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, an alloy containing Al, Ni and C, or Al and Mo. An alloy or the like can be used. In addition, known conductive polymers whose conductivity has been improved by doping, such as conductive polyaniline, conductive polypyrrole, conductive polythiophene, polyethylenedioxythiophene (PEDOT) and polystyrene sulfonic acid (PSS) complex, etc. are also used. be able to. A transparent conductive material may be used. In particular, a transparent conductive material is preferably used when data is written by applying an optical action. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added zinc oxide (GZO) can be used. It is. Indium tin oxide containing silicon oxide or indium oxide containing silicon oxide and further mixed with 2 to 20 wt% zinc oxide (ZnO) may be used. The material can be formed by a droplet discharge method, an evaporation method, a sputtering method, a CVD method, a spin coating method, screen printing, gravure printing, or the like. For example, Ag can be formed by a droplet discharge method, or Al can be formed by a vapor deposition method.

  As the organic compound layer 244, a material similar to that of the organic compound layer 29 described in Embodiment 1 can be used. For example, indium tin oxide containing silicon oxide is used as the first conductive layer 243, poly (9-vinylcarbazole) (PVK) is provided as an organic compound layer over the first conductive layer 243, and the organic compound layer A memory element can be formed by providing Ag as the second conductive layer 245 by a droplet discharge method.

  The insulating layers 249 and 256 include oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). A single layer or a stacked layer is formed using an inorganic material or an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, epoxy, or siloxane. Alternatively, an inorganic material and an organic material may be stacked. Materials such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, epoxy, and siloxane can be efficiently formed by using a droplet discharge method, a printing method, or a spin coating method.

  In the above structure, a rectifying element may be provided between the first conductive layer 243 and the organic compound layer 244 or between the organic compound layer 244 and the second conductive layer 245. The element having the rectifying property may have any of the structures described in the above embodiment modes.

  Further, the structure of the semiconductor layer described in this embodiment is not limited to that described above. For example, the insulating layer 250 may be provided so as to cover the source and drain electrodes of the transistor 240, and the first conductive layer 243 may be provided over the insulating layer 250 (FIG. 6). In this case, the organic compound layer 244 can be formed over the entire surface so as to cover the first conductive layer 243 by using a spin coating method or an evaporation method (FIG. 6B). Further, when there is a concern about the step of the organic compound layer 244 or the influence of the electric field in the lateral direction between adjacent memory cells, insulation is performed to separate the organic compound layer provided in each memory cell. A layer 249 may be provided (FIG. 6C). 6C illustrates an example in which the organic compound layer 244 is selectively provided in each memory cell by using a droplet discharge method, a printing method, or the like. However, as illustrated in FIG. Alternatively, the organic compound layer 244 may be provided.

  In this manner, by providing the first conductive layer 243 so as to be electrically connected to the source or drain electrode through the insulating layer 250, the first conductive layer 243 is formed in the same layer as the source electrode and the drain electrode. The arrangement of the first conductive layer 243 can be freely determined as compared with the case where it is provided. That is, in the structure illustrated in FIG. 5, the memory element 241 needs to be provided in a region where the source or drain electrode of the transistor 240 is avoided, but by providing the memory element 241 via the insulating layer 250, for example, the transistor The storage element 241 can be formed above 240. As a result, the memory cell 221 can be more highly integrated (FIG. 6A).

  In addition, as another structure different from the above structure, the memory element 241 can be formed by disposing the first conductive layer 243 and the second conductive layer 245 in the same layer. A configuration example in this case will be described with reference to FIG.

  In FIG. 5 or FIG. 6, the memory element 241 is formed by stacking the organic compound layer 244 with the first conductive layer 243 and the second conductive layer 245 interposed between the top and the bottom. The memory element 241 is formed by providing the conductive layer 243 and the second conductive layer 245 in the same layer and sandwiching the organic compound layer 244 in the horizontal direction (FIGS. 19A and 19B). In this case, the first conductive layer 243 functions as a source or drain electrode of the transistor 240, and the second conductive layer 245 is also formed in the same layer as the source or drain electrode. In the case where the first conductive layer 243 and the second conductive layer 245 can be formed using the same material, the first conductive layer 243 and the second conductive layer 245 can be formed at the same time. The number of manufacturing steps can be reduced. Note that here, an example in which the organic compound layer 244 is provided over the entire surface is described; however, the present invention is not limited thereto, and the organic compound layer 244 can also be selectively formed.

  Alternatively, the insulating layer 250 may be provided so as to cover the source and drain electrodes of the transistor 240, and the first conductive layer 243 and the second conductive layer 245 may be provided over the insulating layer 250 (FIG. 19 ( C)). This is effective when, for example, the first conductive layer 243 is provided with a light-transmitting material such as ITO, that is, when the source and drain electrodes of the transistor and the first conductive layer 243 are formed with different materials. It is. In addition, since the first conductive layer 243 and the second conductive layer 245 are formed through the insulating layer 250, the first conductive layer and the second conductive layer can be freely arranged. The element 241 can be provided in an integrated manner. Also in this case, when the materials of the first conductive layer 243 and the second conductive layer 245 are the same, the manufacturing steps can be reduced by forming them simultaneously.

  Note that in the structure in FIG. 19, the first conductive layer 243 and the second conductive layer 245 are not necessarily provided in the same layer. For example, in the structure of FIG. 19C, the second conductive layer 245 is formed above the organic compound layer 244, and the first conductive layer 243 and the second conductive layer are obliquely interposed through the organic compound layer 244. It is good also as a structure which 245 arrange | positions. With such a configuration, even when there is a contaminant such as dust on the first electrode, the influence can be prevented.

  Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 3)
In this embodiment, an example of a semiconductor device different from that in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 7A illustrates a semiconductor device having an organic memory that is formed using a passive matrix type, in which an element formation layer 351 including a plurality of transistors 451 is provided over a substrate 350, and a plurality of elements are formed above the element formation layer 351. A memory element portion 352 including an organic memory element and an antenna portion 353 are provided. Note that here, the case where the memory element portion 352 or the antenna portion 353 is provided above the element formation layer 351 is shown; however, the present invention is not limited to this structure, and the memory element portion 352 or the antenna portion 353 is disposed below the element formation layer 351. Or in the same layer.

  As the substrate 350, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating layer formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic such as PET generally has a lower heat-resistant temperature than the above-mentioned substrate, but it should be used if it can withstand the processing temperature in the manufacturing process. Is possible. Note that the surface of the substrate 230 may be planarized by polishing such as a CMP method.

  The plurality of organic memory elements included in the memory element portion 352 are provided by stacking a first conductive layer 361, an organic compound layer 362, and a second conductive layer 363 and covering the second conductive layer 363 for protection. An insulating layer 366 that functions as a film is formed. Here, an insulating layer 364 is provided between each memory cell (between a plurality of organic memory elements), and an organic compound layer 362 is provided for each memory cell. However, the organic compound layer 362 includes a first conductive layer 361. You may form in the whole surface so that it may cover. Note that the memory element portion 352 can be formed using the material or the manufacturing method described in the above embodiment modes.

  Further, in the memory element portion 352, as shown in the above embodiment mode, rectification is performed between the first conductive layer 361 and the organic compound layer 362 or between the organic compound layer 362 and the second conductive layer 363. A device having a property may be provided.

  The antenna portion 353 is provided with a conductive layer 355 that functions as an antenna. Here, the conductive layer 355 is provided in the same layer as the first conductive layer 361, and the conductive layer 355 and the first conductive layer 361 may be formed using the same material. The conductive layer 355 may be formed over the insulating layer 364 or the insulating layer 366. In the case of being provided over the insulating layer 364, the second conductive layer 363 can be formed using the same material.

  The conductive layer 355 functioning as an antenna is connected to a transistor that forms a waveform shaping circuit or a rectifier circuit. Here, the conductive layer 355 functioning as an antenna is electrically connected to any of the plurality of transistors 451. Further, data sent from the outside without contact is processed by a waveform shaping circuit or a rectifier circuit, and then data is exchanged with an organic memory element (data writing or reading) through a reading circuit or a writing circuit. .

  As a material of the conductive layer 355, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum ( A kind of element selected from Al), manganese (Mn), titanium (Ti) or the like, or an alloy containing a plurality of such elements can be used. The conductive layer 355 can be formed by an evaporation method, a sputtering method, a CVD method, a droplet discharge method, a screen printing method, gravure printing, or the like.

  The element formation layer 351 includes at least a transistor. With the transistor, a variety of integrated circuits such as a CPU (central processing unit), a memory, or a microprocessor can be provided. In this embodiment, the transistor 451 included in the element formation layer 351 can be a p-channel TFT or an n-channel TFT. In addition, any structure of a semiconductor layer included in the transistor 451 may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  The transistor 451 included in the element formation layer 351 may be an organic transistor in which a channel region of the transistor is formed using an organic material. In this case, the element formation layer 351 having an organic transistor can be formed using a direct printing method, a droplet discharge method, or the like over a flexible substrate such as plastic as the substrate 350. At this time, as described above, the memory element portion 352 is also formed using a droplet discharge method, a screen printing method, a gravure printing method, or the like, whereby a semiconductor device can be manufactured at lower cost.

  FIG. 7B illustrates an example of a semiconductor device including an active matrix organic memory. Note that FIG. 7B will be described with respect to portions different from those in FIG.

  In the semiconductor device illustrated in FIG. 7B, an element formation layer 351 including transistors 451 and 354 is provided over a substrate 350, and a memory element portion 356 and an antenna portion 353 are provided above the element formation layer 351. Note that here, the transistor 354 functioning as a switching element of the memory element portion 356 is provided in the same layer as the transistor 451, and the memory element portion 356 and the antenna portion 353 are provided above the element formation layer 351. The transistor 354 may be provided above or below the element formation layer 351 without being limited to this structure, and the memory element portion 356 and the antenna portion 353 may be provided below the element formation layer 351 or in the same layer. is there.

  The plurality of organic memory elements included in the memory element portion 356 includes a first conductive layer 371, an organic compound layer 372, and a second conductive layer 373 that are stacked so as to cover the second conductive layer 373. An insulating layer 376 is formed as a protective film. Here, the insulating layer 374 is formed so as to cover the end portion of the first conductive layer 371, and the organic compound layer 372 is selectively formed in each memory cell, but the first conductive layer 371 and You may form in the whole surface so that the insulating layer 374 may be covered. Note that the memory element portion 356 can be formed using the material or the manufacturing method described in the above embodiment modes. In the memory element portion 356, as described above, a rectifying element is provided between the first conductive layer 371 and the organic compound layer 372 or between the organic compound layer 372 and the second conductive layer 373. May be provided.

  The conductive layer 355 provided in the antenna portion 353 may be formed in the same layer as the first conductive layer 371 or may be formed over the insulating layer 374 or the insulating layer 376. In the case where the conductive layer 355 is provided over the same layer as the first conductive layer 371 or the second conductive layer 373, the conductive layer 355 is formed using the same material as the first conductive layer 371 or the second conductive layer 373, respectively. You can also The conductive layer 355 functioning as an antenna is connected to a transistor that forms a waveform shaping circuit or a rectifier circuit. Here, the conductive layer 355 functioning as an antenna is electrically connected to a transistor 451 included in a waveform shaping circuit or a rectifier circuit. Further, data sent from the outside without contact is processed by a waveform shaping circuit or a rectifier circuit, and then data is exchanged with an organic memory element (data writing or reading) through a reading circuit or a writing circuit. .

  The transistor 354 provided in the element formation layer 351 functions as a switching element when data is written to or read from an organic memory element included in the memory element portion 356. Therefore, the transistor 354 is preferably provided using either a p-channel TFT or an n-channel TFT. The semiconductor layer included in the transistor 354 may have any structure, for example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel type You may form with either type | mold. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Further, as described above, the element formation layer 351, the memory element portion 356, and the antenna portion 353 can be formed by vapor deposition, sputtering, CVD, droplet discharge, screen printing, gravure printing, or the like. . Note that a different method may be used depending on each place. For example, the transistor 451 that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like over a substrate and then crystallizing it by heat treatment. After that, a transistor 354 that functions as a switching element is provided above the element formation layer 351. An organic transistor can be provided by a droplet discharge method, a screen printing method, a gravure printing method, or the like.

  Note that in the memory element portion 356 illustrated in FIG. 7B, the first conductive layer 371 is connected to the source or drain electrode of the transistor 354 in the element formation layer 351 through an insulating layer. As shown in FIG. 5, it can be formed in the same layer as the source or drain electrode of the transistor. In FIG. 7B, the organic compound layer 372 is selectively provided for each memory cell, but may be formed over the entire surface as shown in FIG. When an organic compound layer is provided for each memory cell, it is preferable to use a droplet discharge method, a screen printing method or a gravure printing method, and when an organic compound layer is provided on the entire surface, a spin coating method or a vapor deposition method is preferably used.

  Next, a structure example of a semiconductor device in which a terminal portion is provided on a substrate provided with a plurality of elements and a memory element and an antenna provided on another terminal is connected to the terminal portion is described with reference to FIG. I will explain. Note that FIG. 8 will be described with respect to parts different from FIG.

  FIG. 8A illustrates a semiconductor device having a passive matrix organic memory, in which an element formation layer 351 including a plurality of transistors 451 is provided over a substrate 350, and an organic memory element is provided above the element formation layer 351. And an antenna portion 357 provided over the substrate 365 is provided so as to be connected to the transistor 451 in the element formation layer 351. Note that although the case where the memory element portion 352 or the antenna portion 357 is provided above the element formation layer 351 is shown here, the present invention is not limited to this structure, and the memory element portion 352 is provided below the element formation layer 351 or in the same layer. Alternatively, the antenna portion 357 can be provided below the element formation layer 351.

  The organic memory element included in the memory element portion 352 is provided by stacking a first conductive layer 361, an organic compound layer 362, and a second conductive layer 363. In the case where there is a concern about the step of the organic compound layer 362 or the influence of the electric field in the lateral direction in adjacent memory cells, an insulating layer for separating the organic compound layer may be provided for each memory cell. Note that the memory element portion 352 can be formed using the material or the manufacturing method described in the above embodiment modes.

  Further, the substrate over which the element formation layer 351 and the memory element portion 352 are formed and the substrate 365 over which the antenna portion 357 is provided are attached to each other with an adhesive resin 375. The element formation layer 351 and the conductive layer 358 are electrically connected through conductive fine particles 359 included in the resin 375. In addition, a substrate on which the element formation layer 351 and the memory element portion 352 are formed using a conductive adhesive such as silver paste, copper paste, or carbon paste, or a method of performing solder bonding, and a substrate on which the antenna portion 357 is provided 365 may be bonded together.

  FIG. 8B illustrates a semiconductor device provided with an active matrix organic memory. An element formation layer 351 including transistors 451 and 354 is provided over a substrate 350, and an organic layer is formed above the element formation layer 351. A memory element portion 356 having a plurality of memory elements is provided, and an antenna portion 357 provided on the substrate 365 is provided so as to be connected to the element formation layer. Note that here, a case where the transistor 354 is provided in the same layer as the transistor 451 in the element formation layer 351 and the antenna portion 357 is provided above the element formation layer 351 is shown; however, the present invention is not limited to this structure, and the memory element portion 356 is provided. Can be provided below the element formation layer 351 or in the same layer, or the antenna portion 357 can be provided below the element formation layer 351.

  The organic memory element included in the memory element portion 356 is provided by stacking a first conductive layer 371, an organic compound layer 372, and a second conductive layer 373. In the case where there is a concern about the influence of the electric field in the lateral direction in adjacent memory cells, an insulating layer may be provided to separate adjacent organic compound layers. Note that the memory element portion 356 can be formed using the material or the manufacturing method described in the above embodiment modes.

  8B, the substrate provided with the element formation layer 351 and the memory element portion 356 and the substrate provided with the antenna portion 357 are provided by bonding with a resin 375 containing conductive fine particles 359. be able to.

  Thus, a semiconductor device including an organic memory and an antenna can be formed. In this embodiment, a thin film transistor is formed over the substrate 350 as the transistors 354 and 451. However, a field effect transistor in which a semiconductor substrate such as Si is used as the substrate 350 and the substrate is used as a channel portion. You may provide by forming (FET). Alternatively, an SOI substrate may be used as the substrate 350 and may be provided over the substrate. In this case, the SOI substrate can be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

Note that this embodiment can be freely combined with the above embodiment.
(Embodiment 4)
In this embodiment, a method for manufacturing a semiconductor device of the present invention including a thin film transistor, a memory element, and an antenna will be described with reference to drawings.

  First, the separation layer 702 is formed over one surface of the substrate 701 (FIG. 21A). As the substrate 701, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like may be used. With such a substrate 701, there is no significant limitation on the area and shape thereof. For example, if the substrate 701 is a rectangular substrate having a side of 1 meter or more and a rectangular shape, productivity is remarkably improved. Can be made. Such an advantage is a great advantage compared to the case of using a circular silicon substrate. Note that although the separation layer 702 is provided over the entire surface of the substrate 701 in this step, the separation layer 702 may be selectively provided using a photolithography method after being provided over the entire surface of the substrate 701 as needed. Good. In addition, although the separation layer 702 is formed so as to be in contact with the substrate 701, an insulating layer serving as a base is formed so as to be in contact with the substrate 701 as necessary, and the separation layer 702 is formed so as to be in contact with the insulation layer. May be.

  The release layer 702 is formed by a known means (sputtering method, plasma CVD method, etc.) tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt An element selected from (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si) A layer formed of an alloy material or a compound material containing an element as a main component is formed as a single layer or a stacked layer. The structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layer 702 has a single-layer structure, for example, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. The oxide of tungsten may be expressed as tungsten oxide.

  In the case where the separation layer 702 has a stacked structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and an oxide or nitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as a second layer Forming an oxide, oxynitride or nitride oxide.

Note that in the case where a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 702, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After a layer containing tungsten is formed, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed thereon. A layer may be formed. The oxide of tungsten is represented by WOx, X is 2 to 3, X is 2 (WO ₂ ), X is 2.5 (W ₂ O ₅ ), and X is 2.75. (W ₄ O ₁₁ ) and X is 3 (WO ₃ ). In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. Note that the best etching rate is a layer containing tungsten oxide (WOx, 0 <X <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere. In the case where the separation layer is provided with a stacked structure including a metal layer and a layer containing a metal oxide, a metal oxide film may be formed on the metal layer by performing plasma treatment on the metal layer after the metal layer is formed. . When plasma treatment is performed, a metal oxide film, a metal oxynitride film, or the like can be formed over the metal film by performing the treatment in an oxygen atmosphere, a nitrogen atmosphere, an N ₂ O atmosphere, or the like.

  Next, an insulating layer 703 serving as a base is formed so as to cover the separation layer 702. The insulating layer 703 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a known means (such as a sputtering method or a plasma CVD method). The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. In the case where the insulating layer serving as a base has a two-layer structure, for example, a silicon nitride oxide layer may be formed as the first layer and a silicon oxynitride layer may be formed as the second layer. When the underlying insulating layer has a three-layer structure, a silicon oxide layer is formed as the first insulating layer, a silicon nitride oxide layer is formed as the second insulating layer, and oxynitriding is performed as the third insulating layer A silicon layer may be formed. Alternatively, a silicon oxynitride layer may be formed as the first insulating layer, a silicon nitride oxide layer may be formed as the second insulating layer, and a silicon oxynitride layer may be formed as the third insulating layer. The insulating layer serving as a base functions as a blocking film that prevents impurities from entering from the substrate 701.

  Next, an amorphous semiconductor layer 704 (eg, a layer containing amorphous silicon) is formed over the insulating layer 703. The amorphous semiconductor layer 704 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, or the like). Subsequently, the amorphous semiconductor layer 704 is subjected to a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, crystallization A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a promoting metal element and a laser crystallization method). After that, the obtained crystalline semiconductor layer is etched into a desired shape to form crystalline semiconductor layers 706 to 710 (FIG. 21B).

An example of a manufacturing process of the crystalline semiconductor layers 706 to 710 will be briefly described below. First, an amorphous semiconductor layer having a thickness of 66 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 706 to 710 are formed by a photolithography method. In the case of forming a crystalline semiconductor layer by a laser crystallization method, a continuous wave or pulsed gas laser or solid state laser is used. As the gas laser, excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, or the like is used. As the solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, or YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is used.

  In addition, when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, it is possible to crystallize at a low temperature for a short time and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method that can contain argon at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

  Next, a gate insulating layer 705 is formed to cover the crystalline semiconductor layers 706 to 710. The gate insulating layer 705 is formed as a single layer or a stack of layers containing silicon oxide or silicon nitride by a known means (plasma CVD method or sputtering method). Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

  Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 705. The first conductive layer is formed with a thickness of 20 to 100 nm by a known means (plasma CVD method or sputtering method). The second conductive layer is formed with a thickness of 100 to 400 nm by a known means. The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive layer and the second conductive layer include a tantalum nitride layer and a tungsten layer, a tungsten nitride layer and a tungsten layer, a molybdenum nitride layer and a molybdenum layer, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum layer, an aluminum layer, and a molybdenum layer may be employed.

  Next, a resist mask is formed using a photolithography method, etching treatment for forming a gate electrode and a gate line is performed, and conductive layers 716 to 725 functioning as gate electrodes (referred to as gate electrode layers) Form).

  Next, a resist mask is formed by photolithography, and an impurity element imparting N-type is added to the crystalline semiconductor layers 706 and 708 to 710 at a low concentration by ion doping or ion implantation. N-type impurity regions 711 and 713 to 715 and channel formation regions 780 and 782 to 784 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

  Next, a resist mask is formed by photolithography, and an impurity element imparting P-type conductivity is added to the crystalline semiconductor layer 707 to form a P-type impurity region 712 and a channel formation region 781. For example, boron (B) is used as the impurity element imparting P-type.

  Next, an insulating layer is formed so as to cover the gate insulating layer 705 and the conductive layers 716 to 725. The insulating layer may be a single layer or a layer containing an inorganic material such as silicon, silicon oxide or silicon nitride, or an organic material such as an organic resin by a known means (plasma CVD method or sputtering method). It is formed by stacking. Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (also referred to as sidewalls) 739 to 743 that are in contact with the side surfaces of the conductive layers 716 to 725 (see FIG. 21 (C)). At the same time as the formation of the insulating layers 739 to 743, insulating layers 734 to 738 obtained by etching the insulating layer 705 are formed. The insulating layers 739 to 743 are used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

  Next, an impurity element imparting n-type conductivity is added to the crystalline semiconductor layers 706 and 708 to 710 using a mask made of a resist formed by a photolithography method and the insulating layers 739 to 743 as masks. First N-type impurity regions (also referred to as LDD regions) 727, 729, 731, 733 and second N-type impurity regions 726, 728, 730, 732 are formed. The concentration of the impurity element contained in the first N-type impurity regions (also referred to as source and drain regions) 727, 729, 731, and 733 is higher than the concentration of the impurity elements in the second N-type impurity regions 726, 728, 730, and 732. Is also low. Through the above steps, N-type thin film transistors 744 and 746 to 748 and a P-type thin film transistor 745 are completed.

  In order to form the LDD region, there is a method using an insulating layer of a sidewall as a mask. The technique using the sidewall insulating layer as a mask makes it easy to control the width of the LDD region, and the LDD region can be reliably formed.

  Subsequently, an insulating layer is formed as a single layer or a stacked layer so as to cover the thin film transistors 744 to 748 (FIG. 22A). The insulating layer covering the thin film transistors 744 to 748 is formed by a known means (SOG method, droplet discharge method, etc.), an inorganic material such as silicon oxide or silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy. It is formed of a single layer or a laminated layer using an organic material such as siloxane. For example, when the insulating layer covering the thin film transistors 744 to 748 has a three-layer structure, a layer containing silicon oxide is formed as the first insulating layer 749, and a layer containing resin is formed as the second insulating layer 750, A layer containing silicon nitride is preferably formed as the third insulating layer 751.

  Note that before the insulating layers 749 to 751 are formed or after one or more thin films of the insulating layers 749 to 751 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  Next, the insulating layers 749 to 751 are etched using photolithography to form contact holes that expose the N-type impurity regions 726 and 728 to 732 and the P-type impurity region 712. Subsequently, a conductive layer is formed so as to fill the contact hole, and the conductive layer is patterned to form conductive layers 752 to 761 functioning as source / drain wirings.

  The conductive layers 752 to 761 are made of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by known means (plasma CVD method or sputtering method), or an alloy containing these elements as a main component. The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. For example, the conductive layers 752 to 761 employ a laminated structure of a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer, and a laminated structure of a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride layer, and a barrier layer. Good. Note that the barrier layer corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are optimal materials for forming the conductive layers 752 to 761 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier layer containing titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, and the crystalline semiconductor layer is excellent. Contact can be made.

  Next, an insulating layer 762 is formed so as to cover the conductive layers 752 to 761 (FIG. 22B). The insulating layer 762 is formed as a single layer or a stacked layer using an inorganic material or an organic material by a known means (SOG method, droplet discharge method, or the like). The insulating layer 762 is preferably formed with a thickness of 0.75 to 3 μm.

  Subsequently, the insulating layer 762 is etched by photolithography to form contact holes that expose the conductive layers 757, 759, and 761. Subsequently, a conductive layer is formed so as to fill the contact hole. The conductive layer is formed of a conductive material using a known means (plasma CVD method or sputtering method). Next, the conductive layer is patterned to form conductive layers 763 to 765. Note that the conductive layers 763 and 764 serve as one of a pair of conductive layers included in the memory element. Therefore, the conductive layers 763 to 765 are preferably formed as a single layer or a stacked layer using titanium, or an alloy material or compound material containing titanium as a main component. Since titanium has a low resistance value, it leads to a reduction in the size of the memory element, and high integration can be realized. In the etching step for forming the conductive layers 763 to 765, wet etching may be performed in order to prevent damage to the thin film transistors 744 to 748, and the etching agent may be hydrogen fluoride (HF) or Ammonia hydrogen peroxide may be used.

  Next, an insulating layer 766 is formed so as to cover the conductive layers 763 to 765. The insulating layer 766 is formed as a single layer or a stacked layer using an inorganic material or an organic material by a known means (SOG method, droplet discharge method, or the like). The insulating layer 766 is preferably formed with a thickness of 0.75 μm to 3 μm. Subsequently, the insulating layer 766 is etched by photolithography to form contact holes 767 to 769 that expose the conductive layers 763 to 765.

  Next, a conductive layer 786 which functions as an antenna is formed in contact with the conductive layer 765 (FIG. 23A). The conductive layer 786 is formed using a conductive material by a known method (plasma CVD method, sputtering method, printing method, droplet discharge method). Preferably, the conductive layer 786 is an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component. It is formed by layer or lamination. Specifically, the conductive layer 786 is formed by a screen printing method using a paste containing silver, and then heat-treated at 50 to 350 degrees. Alternatively, an aluminum layer is formed by a sputtering method, and the aluminum layer is formed by patterning. For the pattern processing of the aluminum layer, wet etching processing may be used, and after the wet etching processing, heat treatment at 200 to 300 degrees may be performed.

  Next, an organic compound layer 787 is formed so as to be in contact with the conductive layers 763 and 764 (FIG. 23B). The organic compound layer 787 is formed by a droplet discharge method, a spin coating method, a screen printing method, or the like. Subsequently, a conductive layer 771 is formed so as to be in contact with the organic compound layer 787. The conductive layer 771 is formed by a known means (a sputtering method or a vapor deposition method).

  Through the above steps, a memory element 789 including a stack of the conductive layer 763, the organic compound layer 787, and the conductive layer 771, and a memory element 790 including a stack of the conductive layer 764, the organic compound layer 787, and the conductive layer 771 are completed. To do.

  Note that the above manufacturing process is characterized in that the organic compound layer 787 is formed after the step of forming the conductive layer 786 functioning as an antenna because the heat resistance of the organic compound layer 787 is not strong.

  Next, an insulating layer 772 functioning as a protective layer is formed by a known means (SOG method, droplet discharge method, or the like) so as to cover the memory elements 789 and 790 and the conductive layer 786 functioning as an antenna. The insulating layer 772 is formed of a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or an organic material, and preferably formed of an epoxy resin.

Next, the thin film integrated circuit 791 is peeled from the substrate 701. Here, after the openings 773 and 774 are formed by irradiation with laser light (for example, UV light) (FIG. 24A), the thin film integrated circuit 791 can be peeled from the substrate 701 using physical force. it can. Further, after the openings 773 and 774 are formed, before the thin film integrated circuit 791 is peeled from the substrate 701, an etching agent is introduced into the openings 773 and 774 and the peeling layer 702 is removed (FIG. 24B). ) May be peeled off. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the thin film integrated circuit 791 is peeled from the substrate 701. Note that the peeling layer 702 may be partially left without being completely removed. By doing so, it is possible to suppress the consumption of the etching agent and shorten the processing time required for removing the release layer. Further, the thin film integrated circuit 791 can be held on the substrate 701 even after the peeling layer 702 is removed.

  The substrate 701 from which the thin film integrated circuit 791 is peeled is preferably reused for cost reduction. The insulating layer 772 is formed so that the thin film integrated circuit 791 is not scattered after the peeling layer 702 is removed. Since the thin film integrated circuit 791 is small and thin, the thin film integrated circuit 791 is likely to be scattered after being removed from the substrate 701 after the peeling layer 702 is removed. However, by forming the insulating layer 772 over the thin film integrated circuit 791, the thin film integrated circuit 791 is weighted and scattering from the substrate 701 can be prevented. In addition, although the thin film integrated circuit 791 is thin and light, the insulating layer 772 is formed, so that a certain shape of strength can be secured without forming a wound shape.

  Next, one surface of the thin film integrated circuit 791 is adhered to the first base body 776 and completely peeled from the substrate 701 (FIG. 25). Subsequently, the other surface of the thin film integrated circuit 791 is bonded to the second substrate 775, and then one or both of heat treatment and pressure treatment are performed, so that the thin film integrated circuit 791 is bonded to the first substrate 776 and the first substrate 776. Sealing with the second substrate 775 is performed. The first substrate 776 and the second substrate 775 are a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, a paper made of a fibrous material, a base film (polyester, polyamide, inorganic vapor deposition film, A laminated film of a paper or the like) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.) can be used. The film is subjected to heat treatment and pressure treatment by thermocompression bonding. When the heat treatment and pressure treatment are performed, the film is either an adhesive layer provided on the outermost surface of the film or the A layer (not an adhesive layer) provided in the outer layer is melted by heat treatment and bonded by pressure. In addition, an adhesive layer may be provided on the surfaces of the first base body 776 and the second base body 775, or the adhesive layer may not be provided. As the adhesive layer, a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive can be used.

  Through the above steps, a semiconductor device including a memory element and an antenna can be manufactured. In addition, a flexible semiconductor device can be obtained through the above steps.

Note that this embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 5)
In this embodiment, a method for manufacturing a semiconductor device, which is different from that in the above embodiment, will be described.

  First, conductive layers 401a and 401b functioning as wirings and electrodes are formed by selectively discharging a conductive composition from a nozzle 410 over a substrate 400 (FIG. 11A). Note that a base insulating layer may be provided over the substrate 400 as a protective film in advance. Alternatively, the base insulating layer may be irradiated with a short pulse laser such as a picosecond laser or a femtosecond laser to form a recess on the surface. Then, when the composition is discharged, the positions where the conductive layers 401a and 401b are disposed can be accurately controlled.

  Next, the conductive layer 402 is formed by selectively discharging a conductive composition from the nozzle 410 (FIG. 11B). Note that the conductive layer 402 may be formed at the same time as the conductive layer 401b. In particular, the conductive layer 402 is preferably provided at the same time when the materials of the conductive layer 401b and the conductive layer 402 are the same.

  Next, the semiconductor layer 403 is formed so as to cover the conductive layers 401 a and 401 b by selectively discharging a composition, and the insulating layer 404 is formed so as to cover the semiconductor layer 403. After that, a conductive layer functioning as a gate electrode (hereinafter referred to as a gate electrode 405) is formed between the conductive layers 401a and 401b (FIG. 11C). Since a concave portion is formed between the conductive layers 401a and 401b, the position can be controlled when the gate electrode 405 is provided by discharging the composition.

  Next, an insulating composition 406 is formed by selectively discharging an insulating composition so as to cover the conductive layers 401a and 401b, the semiconductor layer 403, the insulating layer 404, and the gate electrode 405 (FIG. 11D). .

  Next, the organic compound layer 407 is formed so as to be in contact with the conductive layer 402 by selectively discharging the composition, and the conductive layer 408 is formed over the organic compound layer 407. Note that the organic compound layer 407 may be provided over the entire surface or may be selectively provided so as to be in contact with the conductive layer 402 (FIG. 11E). In this manner, the memory element 409 is formed by a stacked body of the conductive layer 402, the organic compound layer 407, and the conductive layer 408.

  Through the above steps, an active matrix organic memory element can be formed. Although FIG. 11 shows the case where the droplet discharge method is used for all the steps, this embodiment is not limited to this, and in each step, a vapor deposition method, a CVD method, a sputtering method, a spin coating method, a screen printing method is used. Alternatively, it can be formed using other methods such as gravure printing. Moreover, you may combine the method mentioned above using a separate method for every process, ie, the above-mentioned method. For example, the conductive layers 401a and 401b can be formed by a droplet discharge method, the semiconductor layer 403 can be formed by an evaporation method, and the organic compound layer 407 can be formed by a spin coating method. The materials used in each process will be described below.

  As the substrate 400, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating layer formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic such as PET generally has a lower heat-resistant temperature than the above-mentioned substrate, but it should be used if it can withstand the processing temperature in the manufacturing process. Is possible. Note that the surface of the substrate 400 may be planarized by polishing such as a CMP method.

  The conductive layers 401a and 401b are not particularly limited as long as they are conductive materials, and have one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al, or a metal compound. A conductive material can be used. In addition, known conductive polymers whose conductivity has been improved by doping, such as conductive polyaniline, conductive polypyrrole, conductive polythiophene, polyethylenedioxythiophene (PEDOT) and polystyrene sulfonic acid (PSS) complex, etc. are also used. be able to.

  The conductive layer 402 may be formed using a material similar to that of the conductive layers 401a and 401b. In addition, a transparent conductive material may be used. In particular, a transparent conductive material is preferably used when data is written by applying an optical action. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added zinc oxide (GZO) can be used. It is. Indium tin oxide containing silicon oxide or indium oxide containing silicon oxide mixed with 2 to 20 wt% zinc oxide (ZnO) may be used.

  As the semiconductor layer 403, a single element or an alloy of a semiconductor element (silicon, germanium, or the like), an organic semiconductor material, or the like can be used. The organic semiconductor material is an organic compound exhibiting semiconducting electrical properties, and the structure is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Specifically, soluble polymer materials such as polyphenylene vinylene, polythiophene, poly (3-alkylthiophene), and polythiophene derivatives can be used. In addition, other materials such as pentacene and naphthacene may be used. In this specification, a transistor using an organic material such as an organic semiconductor material for a semiconductor layer is referred to as an organic transistor. In this embodiment mode, the organic semiconductor material can be formed by a droplet discharge method, a screen printing method, a gravure printing method, a spin coating method, an evaporation method, or the like.

  As the insulating layer 404 and the insulating layer 406, an inorganic insulating layer such as silicon oxide, silicon nitride, or silicon nitride oxide, an insulating layer such as polyvinylphenol, polyimide, or siloxane can be used. Polyvinylphenol, polyimide, or siloxane can be efficiently formed by using a droplet discharge method, a printing method, or a spin coating method. Siloxanes can be classified according to their structure into, for example, silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, hydrogenated silsesquioxane polymers, hydrogenated alkylsilsesquioxane polymers, and the like. Alternatively, the insulating layer may be formed using a material containing a polymer having an Si—N bond (polysilazane). Alternatively, an insulating layer may be formed by stacking these films.

  The organic compound layer 407 can be formed using any of the organic compound materials described in the above embodiment modes.

  The conductive layer 408 can be formed using any of the materials shown for the conductive layers 401a, 401b, and 402.

  In the above structure, a rectifying element may be provided between the conductive layer 402 and the organic compound layer 407 or between the organic compound layer 407 and the conductive layer 408. As a rectifying element, a transistor or a diode in which a gate electrode and a drain electrode are connected can be provided. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. In this way, by providing a rectifying diode, current flows only in one direction, so that errors are reduced and reading accuracy is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction.

  FIG. 11 shows a top gate (forward stagger) structure in which the gate electrode is located above the source and drain electrodes. Of course, a bottom gate (reverse stagger) structure in which the gate electrode is located below the source and drain electrodes is shown. It is also possible to provide it. FIG. 13A shows the case where a bottom gate structure is provided.

  In FIG. 13A, a gate electrode 425, an insulating layer 424, a semiconductor layer 423, conductive layers 421a and 421b functioning as a source or drain electrode, an insulating layer 426, an organic compound layer 427, and a conductive layer 428 are sequentially formed over a substrate 400. It is formed by stacking. Further, the material and the formation method can be performed using the same material and method as those in FIG. Note that in this case as well, a rectifying element may be provided between the conductive layer 421b and the organic compound layer 427 or between the organic compound layer 427 and the conductive layer 428.

  Next, a case different from the above configuration will be described with reference to FIG. Specifically, the case where a memory element is provided below a transistor is described.

  First, the conductive layer 411 and the organic compound layer 412 are stacked over the substrate 400 (FIG. 12A). The conductive layer 411 and the organic compound layer can be formed by any of the above-described methods.

  Next, an insulating composition 413 is formed by selectively discharging an insulating composition (FIG. 12B). Note that at this time, the insulating layer 413 is provided to avoid a region to be a memory element.

  Next, a conductive composition is selectively discharged over the insulating layer 413, so that conductive layers 414a and 414b functioning as wirings or electrodes are selectively formed (FIG. 12C). In this case, a recess may be formed in advance by irradiating a laser beam at a position where the conductive layers 414a and 414b of the insulating layer 413 are provided.

  Next, a conductive layer 415 is formed so as to be connected to the conductive layer 414b (FIG. 12D). Note that the conductive layer 415 is provided over the organic compound layer 412. Then, a memory element 419 having a stacked structure of the conductive layer 411, the organic compound layer 412, and the conductive layer 415 is obtained. In addition, since the conductive layer 415 is provided in the recess, the position can be easily controlled when a droplet discharge method or the like is used. Note that the conductive layer 415 may be formed at the same time as the conductive layers 414a and 414b.

  Next, a semiconductor layer 416 is formed so as to cover the conductive layers 414a and 414b. After that, an insulating layer 417 is formed so as to cover the semiconductor layer 416, and a gate electrode 418 is formed between the conductive layer 414a and the conductive layer 414b (FIG. 12E). Since a recess is provided between the conductive layer 414a and the conductive layer 414b, the position can be easily controlled when the gate electrode 418 is provided by a droplet discharge method or the like.

  Through the above steps, an organic memory in which the memory element 419 is disposed below the transistor can be formed. Note that FIG. 12 shows the case where the droplet discharge method is used in all the steps, but the present invention is not limited to this, and in each step, a vapor deposition method, a CVD method, a sputtering method, a spin coating method, screen printing, and gravure printing are used. It is also possible to form it using other methods such as a printing method. Moreover, it can also carry out combining the said method for every process. In particular, a material formed over the entire surface of the substrate such as the conductive layer 411 or the organic compound layer 412 is preferably formed using a spin coating method.

  In FIG. 12, any of the materials shown in the description with reference to FIG. 11 can be used for the conductive layers 411, 413a, 413b, and 419, the insulating layers 413 and 417, and the semiconductor layer 416. The organic compound layer 412 can also be formed using any of the materials described in the above embodiment modes.

  Next, an organic memory whose structure is partly different from that of FIG. 12 is illustrated in FIG.

  In a highly integrated memory element, there may be a concern about the influence of a horizontal electric field between adjacent memory cells. Therefore, as shown in FIG. 13B, an organic compound layer provided in each adjacent memory element 419 may be separated. Here, after the conductive layer 411 is formed over the substrate 400, an organic compound layer is selectively formed. In FIG. 13B, an organic compound layer 422 included in each memory element 419 is formed.

  In FIG. 13B, an organic compound layer 421 is provided. This is provided so that the position can be easily controlled when the conductive layers 414a and 414b are formed over the insulating layer 413 by a droplet discharge method or the like. That is, by providing the organic compound layer 421, a recess can be formed in advance at a position where the conductive layers 414a and 414b are provided. Note that the organic compound layer 421 is not necessarily provided when another method such as an evaporation method or a sputtering method is used or when flatness is considered. In this case, as described above, it is preferable to form a concave portion by previously irradiating the laser beam at a position where the conductive layers 414a and 414b of the insulating layer 413 are provided. Further, by providing the organic compound layer 421 with a conductive material, a dual gate structure in which the semiconductor layer 423 is sandwiched from above and below can be obtained.

  12 and 13B, a rectifying element may be provided between the conductive layer and the organic compound layer included in the memory element 419 as described above.

  Thus, by providing the memory element and the transistor with an organic compound, an organic memory and a semiconductor device including the organic memory can be manufactured at low cost with a simple process. Further, by providing the transistor with an organic compound, an organic memory and a semiconductor device including the organic memory can be manufactured directly over a flexible substrate.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 6)
In this embodiment, the case where the semiconductor device described in any of the above embodiments is applied to a display device including a pixel portion will be described with reference to drawings.

  First, FIGS. 26A and 26B illustrate the case where the pixel portion is an active matrix type and the memory element portion is a passive matrix type. Note that a cross-sectional view taken along a line AB in FIG. 26A corresponds to FIG.

  A light emitting element 94 is provided in the pixel portion 81, and the light emitting element 94 includes a first conductive layer 91, an organic compound layer 92, and a second conductive layer 93. The first conductive layer 91, the organic compound layer 92, and the second conductive layer 93 are stacked. The first conductive layer 91 included in the light emitting element 94 is connected to the conductive layer 76 that functions as a source or drain electrode of the driving transistor 85. Further, an insulating layer 79 functioning as a partition is provided between adjacent light emitting elements 94.

  The driver circuit portion 82 is provided with an element formation layer including a plurality of transistors 86. The element formation layer constitutes a drive circuit that controls the operation of the pixel portion 81 and the memory cell 83. Examples of the drive circuit that controls the operation of the pixel unit 81 include a shift register, a decoder, a buffer, a sampling circuit, and a latch. The drive circuit that controls the operation of the memory cell 83 is, for example, a decoder, a sense amplifier, a selector, a buffer, a read circuit, a write circuit, or the like.

  A memory element 98 is provided in the memory cell 83. The memory element 98 has a first conductive layer 95 that functions as the word line Wy, an organic compound layer 96, and a second conductive that functions as the bit arrangement Bx. Layer 97. The first conductive layer 95, the organic compound layer 96, and the second conductive layer 97 are stacked. In the structure of FIG. 26B, the memory cell 98 can be provided above the driver circuit portion 82 by forming the memory element 98 over the insulating layer 79. With such a configuration, the area of the pixel portion 81 can be increased.

  In addition, a connection film 84 is provided on the substrate 80, and specifically, the connection film 84 corresponds to a flexible printed circuit (FPC) or the like. A signal for controlling the operation of a plurality of elements constituting the pixel portion 81 and the memory cell 83 and a power supply potential are input from the outside through the connection film 84.

  Note that data is read from the memory element 98 included in the memory cell 83 by applying an electrical action. Specifically, data is read by applying a voltage between the first conductive layer 95 and the second conductive layer 97 of the memory element 98 and reading the resistance value of the memory element 98. When such data reading is performed, the memory element 98 may emit light depending on the material used for the organic compound layer 96. Therefore, when the organic compound layer 92 included in the light-emitting element 94 and the organic compound layer 96 included in the memory element 98 are formed of the same material, a housing such as a black matrix so that the light emission of the memory element 98 is not visually recognized. It is good to arrange. Alternatively, only the light-emitting element 94 may emit light by providing the organic compound layer 92 included in the light-emitting element 94 and the organic compound layer 96 included in the memory element 98 using different materials.

  Next, FIG. 26C illustrates the case where both the pixel portion and the memory element portion are provided in an active matrix type.

  A light emitting element 94 is provided in the pixel portion 81, and the light emitting element 94 includes a first conductive layer 91, an organic compound layer 92, and a second conductive layer 93. The first conductive layer 91, the organic compound layer 92, and the second conductive layer 93 are stacked. The first conductive layer 91 included in the light-emitting element 94 is connected to the conductive layer 76 functioning as a source or drain wiring of the driving transistor 85 through the insulating layer 77. Further, an insulating layer 78 functioning as a partition is provided between the adjacent light emitting elements 94.

  The driver circuit portion 82 is provided with an element formation layer including a plurality of transistors 86. The element formation layer constitutes a drive circuit that controls the operation of the pixel portion 81 and the memory cell 83. Examples of the drive circuit that controls the operation of the pixel unit 81 include a shift register, a decoder, a buffer, a sampling circuit, and a latch. The drive circuit that controls the operation of the memory cell 83 is, for example, a decoder, a sense amplifier, a selector, a buffer, a read circuit, a write circuit, or the like.

  The memory cell 83 is provided with a memory element 98, and the memory element 98 includes a first conductive layer 88, an organic compound layer 89, and a second conductive layer 90. The first conductive layer 88, the organic compound layer 89, and the second conductive layer 90 are stacked. The first conductive layer 88 included in the memory element 98 is connected to a conductive layer 99 functioning as a source / drain wiring of the switching transistor 87 through an insulating layer 77. In addition, an insulating layer 78 functioning as a partition is provided between adjacent memory elements 98. In the structure illustrated in FIG. 26C, the first conductive layer 91 may be provided in the same layer as the conductive layer 76 functioning as a source or drain electrode without providing the insulating layer 77. The conductive layer 88 may be provided in the same layer as the conductive layer 99 functioning as the source or drain electrode of the switching transistor 87.

  In the above configuration, the light emitted from the light emitting element 94 employs a bottom emission structure toward the substrate 80 side. However, a top emission structure toward the opposite side of the substrate 80 may be employed. You may employ | adopt the structure of the double injection which has the structure of both injection | emission and bottom injection.

  In the above structure, the organic compound layers 96, 92, and 89 can be manufactured by a droplet discharge method, a spin coating method, a screen printing method, a gravure printing method, an evaporation method, or the like. FIGS. 26B and 26C show an example in which the organic compound layers 96, 92, and 89 are selectively formed. This is formed by a droplet discharge method, a screen printing method, a gravure printing method, or the like. be able to. In this case, since an organic compound layer can be selectively provided in each pixel or each memory cell, the material utilization efficiency can be improved. Further, the organic compound layers 96, 92, and 89 can be provided using different materials.

  On the other hand, FIGS. 27A and 27B show the case where the organic compound layers 96, 92, and 89 are formed by using a spin coating method or a vapor deposition method. In FIG. 27, the organic compound layers 96, 92 and 89 are formed of the same material. By using the spin coating method, the working efficiency can be greatly improved.

  The light-emitting device having the above structure includes a memory circuit including a memory element portion having a structure in which an organic compound layer is sandwiched between a pair of conductive layers. Since the structure of the memory element portion is the same as or almost the same as the structure of the light-emitting element, the number of manufacturing steps does not increase, and the structure is simple, so that the manufacturing is simple and an inexpensive display device is provided. be able to. In addition, since it is easy to reduce the area of the memory cell, high integration is easy, and a display device having a large-capacity memory circuit can be provided.

  The display device of the present invention is characterized in that a plurality of pixels for displaying an image and a memory circuit are provided over the same substrate. With the above features, the number of IC chips connected to the outside can be reduced, so that a display device that is small, thin, and lightweight can be provided.

  Note that this embodiment mode can be freely combined with the above embodiment modes. That is, the materials and structures in the semiconductor device described in the above embodiment can be freely combined in this embodiment.

(Embodiment 7)
In this embodiment mode, reading or writing of data in the semiconductor device having the above structure is described.

  Data can be written into the memory circuit by an optical action or an electrical action. First, an operation when data is written by electrical action will be described (FIG. 4). Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 221 in the y-th row and the x-th column will be described. When data “1” is written to the memory cell 221, first, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223. Specifically, a predetermined voltage V22 is applied to the word line Wy connected to the memory cell 221 by the row decoder 224a. Further, the bit line Bx connected to the memory cell 221 is connected to the read circuit 226b by the column decoder 226a and the selector 226c. Then, the write voltage V21 is output from the read circuit 226b to the bit line Bx.

  Thus, the transistor 240 constituting the memory cell is turned on, the common electrode and the bit line are electrically connected to the organic memory element 241, and a voltage of approximately Vw = Vcom−V21 is applied. By appropriately selecting the voltage Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that when data “1” is written to the organic memory element 241, the distance between the pair of conductive layers provided with the organic compound layer interposed therebetween may change. Specifically, the distance L between the pair of conductive layers is changed by physically or electrically changing the organic compound layer in a stacked structure in which the organic compound layer is provided between the pair of conductive layers. For example, in the structure shown in FIG. 3A, data “1” is written between the first conductive layer 27 and the second conductive layer 28 to change the organic compound layer 29 physically or electrically. As a result, the distance L between the first conductive layer 27 and the second conductive layer 28 changes.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written in the memory cell 221, it is not necessary to apply an electrical action to the memory cell 221. In the circuit operation, for example, as in the case of writing “1”, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223, but from the read circuit 226b to the bit line Bx. The output potential is set to the same level as Vcom or the bit line Bx is set in a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 241 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

  Next, a case where data is written by applying an optical action will be described.

  When data is written by applying an optical action, the organic compound layer 29 is irradiated with laser light from the light-transmitting conductive layer side (here, the second conductive layer 28) (FIG. 9 ( A), (B)). Here, the organic compound layer 29 included in a desired portion of the organic memory element is selectively irradiated with laser light using the laser irradiation apparatus 1001 to destroy the organic compound layer 29. Since the destroyed organic compound layer is carbonized and insulated, when an organic memory element including the destroyed organic compound layer and an organic memory element including an unbroken organic compound layer are compared, the first The electrical resistance between the conductive layer and the second conductive layer is greatly increased. As described above, data is written by utilizing the change in the electrical resistance between the two conductive layers provided with the organic compound layer 29 sandwiched by the laser light irradiation. For example, when an organic memory element including an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, the laser light is selectively applied to a desired portion of the organic compound layer. The electrical resistance is increased by irradiating and destroying.

When laser light is irradiated, the change in the electrical resistance of the organic memory element depends on the size of the memory cell 21, but by irradiation with the laser light with a beam spot diameter reduced to μm or nm using an optical system such as a lens. Realize. For example, when a laser beam having a diameter of 1 μm passes at a speed of 10 m / sec, the time for which the organic memory element included in one memory cell 21 is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, for example, the laser power is preferably 10 mW and the power density is 10 kW / mm ² . In the case of selectively irradiating laser light, it is preferable to use a pulsed laser irradiation apparatus.

  Here, an example of a laser irradiation apparatus will be briefly described with reference to FIG. A laser irradiation apparatus 1001 includes a computer (hereinafter, referred to as a PC) 1002 that executes various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004 of the laser oscillator 1003, and laser light. An optical system (ND filter) 1005 for attenuating light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser light, and a lens and an optical path for reducing the cross section of the laser light An optical system 1007 composed of a mirror or the like for changing the position, a moving mechanism 1009 having an X-axis stage and a Y-axis stage, a D / A converter 1010 for digital-to-analog conversion of control data output from the PC, Acousto-optic modulator 1 according to the analog voltage output from the D / A converter A driver 1011 for controlling 06, a driver 1012 for outputting a driving signal for driving the movement mechanism 1009 is provided with an auto-focus mechanism 1013 for focusing the laser beam on the irradiated object.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Laser oscillators include excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO. Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the fundamental wave or the second to fifth harmonics.

  Next, an irradiation method using a laser irradiation apparatus will be described. When the substrate 30 provided with the organic compound layer is mounted on the moving mechanism 1009, the PC 1002 detects the position of the organic compound layer to be irradiated with the laser light by a camera (not shown). Next, the PC 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data.

  Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007 and condensed by the lens, and then the substrate 30 is irradiated with the laser light.

  At this time, according to the movement data generated by the PC 1002, the movement mechanism 1009 is controlled to move in the X direction and the Y direction. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the organic compound layer provided on the substrate 30 can be selectively irradiated with the laser light. Note that, here, an example in which the moving mechanism 1009 is moved and laser light irradiation is performed is shown; however, the laser light may be moved in the X direction and the Y direction by adjusting the optical system 1007.

  Next, an operation when data is read by electrical action will be described. Data is read using the fact that the electrical characteristics of the organic memory element 241 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the reading circuit 226b, for example, a bit line driver circuit 226 using the resistance element 246 and the differential amplifier 247 illustrated in FIG. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 248 may be used instead of the resistance element 246, and a clocked inverter 229 may be used instead of the differential amplifier (FIG. 10B). Of course, the circuit configuration is not limited to that shown in FIGS.

  When data is read from the memory cell 221 at the y-th row and the x-th column, first, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223. Specifically, a predetermined voltage V24 is applied to the word line Wy connected to the memory cell 221 by the row decoder 224a. Further, the bit line Bx connected to the memory cell 221 is connected to the terminal P of the read circuit 226b by the column decoder 226a and the selector 226c. As a result, the potential Vp of the terminal P is determined by resistance division by Vcom and V0 applied to one end of the resistance element 246 by the resistance element 246 (resistance value Rr) and the organic memory element 241 (resistance value R0 or R1). Value. Therefore, when the memory cell 221 has data “0”, Vp0 = Vcom + (V0−Vcom) * R0 / (R0 + Rr). When the memory cell 221 has data “1”, Vp1 = Vcom + (V0−Vcom) * R1 / (R1 + Rr). As a result, in FIG. 10A, Vref is selected to be between Vp0 and Vp1, and in FIG. 10B, the changing point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, the output potential Vout becomes Lo / Hi (or Hi / Lo) according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is Hi, and when the memory cell data is “1”, Vp1 = 0.3V and Lo is output as Vout. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value and the resistance division of the organic memory element. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  An organic memory having the above-described structure and a semiconductor device including the organic memory are nonvolatile memories, and therefore, it is not necessary to incorporate a battery for holding data, and a small, thin, and lightweight semiconductor device is provided. Can do. Further, by using the organic compound material described in any of the above embodiments as an organic compound layer, a memory element in which data can be written (added) but data cannot be rewritten can be obtained. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

  Note that in this embodiment, a passive matrix organic memory with a simple structure of a memory circuit and a semiconductor device including the organic memory are described as examples. However, an active matrix memory circuit is provided. Even in this case, data can be written or read in the same manner.

  Here, in the case of the active matrix type, a case where data in the memory element portion is read by an electric action will be described with reference to FIG.

  FIG. 20 illustrates a current-voltage characteristic 941 of a memory element unit in which data “0” is written in the memory element unit, a current-voltage characteristic 942 in which data data “1” is written, and a resistance element 246. In this example, a transistor is used as the resistance element 246. The horizontal axis indicates the potential of the node α. Further, a case where 3 V is applied between the first conductive layer 243 and the second conductive layer 245 as an operation voltage when reading data will be described.

  In FIG. 20, in a memory cell having a memory element portion in which data of “0” is written, an intersection 944 between the current-voltage characteristic 941 of the memory element part and the current-voltage characteristic 943 of the transistor is an operating point. The potential of the node α is V1 (V). The potential of the node α is supplied to the differential amplifier 247, and the data stored in the memory cell is determined as “0” in the differential amplifier 247.

  On the other hand, in a memory cell having a memory element portion in which data of “1” is written, an intersection 945 between the current-voltage characteristic 942 of the memory element part and the current-voltage characteristic 943 of the transistor serves as an operating point. The potential of α is V2 (V) (V1> V2). The potential of the node α is supplied to the differential amplifier 247, and the data stored in the memory cell is determined as “1” in the differential amplifier 247.

  Thus, by reading the resistance-divided potential according to the resistance value of the organic memory element 241, the data stored in the memory cell can be determined.

  Note that this embodiment mode can be freely combined with the structures of the organic memory and the semiconductor device including the organic memory described in the above embodiment modes.

(Embodiment 8)
In this embodiment, the case where the semiconductor device of the present invention is used as an RFID tag capable of transmitting and receiving data without contact will be described with reference to FIGS.

  The RFID tag 20 has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, a memory 6, A data bus 17 and an antenna 18 (antenna coil) are included (FIG. 14A).

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit in the semiconductor device based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory 6. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data.

  Further, the memory 6 is formed by any of the configurations of the organic memory shown in the above embodiment. Note that the RFID tag is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and cryptographic processing dedicated hardware are added.

  The RFID tag may be of a type in which power supply voltage is supplied to each circuit by radio waves without mounting a power supply (battery), or power supply (battery) is supplied to each circuit instead of an antenna. It may be a type that is mounted, or may be a type that supplies a power supply voltage by radio waves and a power source.

  When the semiconductor device of the present invention is used for an RFID tag or the like, the point of performing contactless communication, the point that multiple reading is possible, the point that data can be written, the point that it can be processed into various shapes, and the selection Depending on the frequency to be used, there are advantages such as wide directivity and wide recognition range. RFID tags can be used for IC tags that can identify individual information about people and objects by wireless communication without contact, labels that can be attached to target objects by label processing, wristbands for events and amusements, etc. Can be applied. Further, the RFID tag may be molded using a resin material, or may be directly fixed to a metal that hinders wireless communication. Furthermore, the RFID tag can be used for system operation such as an entrance / exit management system and a payment system.

  Next, one mode when the semiconductor device is actually used as an RFID tag will be described. A reader / writer 320 is provided on the side surface of the portable terminal including the display portion 321, and an RFID tag 323 is provided on the side surface of the article 322 (FIG. 14B). When the reader / writer 320 is held over the RFID tag 323 included in the item 322, the display unit 321 displays information about the product, such as a description of the product, such as the raw material and origin of the product, the inspection result for each production process, and the history of the distribution process. The In addition, when the product 326 is conveyed by a belt conveyor, the product 326 can be inspected using the reader / writer 324 and the RFID tag 325 provided on the product 326 (FIG. 14C). In this manner, by using the RFID tag in the system, information can be easily acquired, and high functionality and high added value are realized.

  Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 9)
In this embodiment, a semiconductor device provided with a sensor capable of measuring various information such as temperature and pressure in the above structure will be described with reference to FIGS.

  FIG. 28A illustrates an example of a structure in the case where a sensor portion is provided in the semiconductor device described in the above embodiment. An element formation layer 351 including transistors 451 and 354 is provided over a substrate 350, and a memory element portion 356 and an antenna portion 353 are provided above the element formation layer. A sensor unit 950 is provided above the memory element unit 356. Note that the memory element portion 356 and the transistors 451 and 354 can be formed using any of the structures described in the above embodiments. For example, the structure shown in FIG. 19 may be used as the memory element portion 356.

  The sensor unit 950 can detect temperature, humidity, illuminance, gas, gravity, pressure, sound, vibration, acceleration, and other characteristics by physical or chemical means. The sensor unit 950 includes a sensor and a sensor circuit that controls the sensor, and the sensor is formed of a resistance element, a photoelectric conversion element, a thermoelectromotive force element, a transistor, a thermistor, a diode, or the like.

  The sensor portion 950 is connected to the transistor 451 included in the element formation layer 351, and is bonded here with an adhesive resin 954. The sensor portion 950 and the transistor 451 include conductive particles 952 in which a conductive layer 953 electrically connected to the sensor portion 950 and a conductive layer 951 electrically connected to the source or drain region of the transistor are included in the resin 954. It is electrically connected via.

  The sensor unit 950 is not limited to the above configuration and may be arranged in any manner. For example, the memory element portion 356 may be provided in the same layer or the transistor 451 may be provided. In addition, the sensor portion 950 can be provided below the substrate 350. In the case where the transistor 451 or the memory element portion 356 is provided in the same layer as the transistor 451 or the memory element portion 356, the manufacturing process can be simplified and cost can be reduced.

  In addition to the above method, the sensor unit 950 and the transistor 451 may be connected with a conductive adhesive such as silver paste, copper paste, or carbon paste, a solder bonding method, a TCP (tape carrier package) method, It can carry out using well-known methods, such as a wire bonding method.

  In the above structure, an example in which a sensor portion is formed separately from the semiconductor device and then pasted is shown; however, the sensor portion can be directly formed in the semiconductor device. This case will be described with reference to FIG.

  In FIG. 29A, a photosensor is provided in the same layer as the element formation layer 351 including the transistors 354 and 451. Here, a photodiode 461 including a P-type impurity region, an intrinsic semiconductor region, and an N-type impurity region is provided as an optical sensor. Since the current value of the diode 461 changes when irradiated with light, light can be detected by measuring the change in the current value with the transistor 462 connected to the photodiode 461. The photodiode 461 includes a P-type impurity region and an intrinsic semiconductor region and a P-type impurity region, an N-type impurity region and an intrinsic semiconductor region and an N-type impurity region, or a junction between a P-type impurity region and an N-type impurity region. You may comprise from structure. Further, a phototransistor may be provided instead of the photodiode. For example, in the case where the transistors 354 and 451 are provided using thin film transistors, it is preferable to provide a photodiode and a phototransistor at the same time because the process can be simplified and the cost can be reduced.

  In FIG. 29B, a temperature sensor 472 is provided in the same layer as the memory element portion 356. Here, an organic compound layer 482 is provided as a temperature sensor between a pair of conductive layers. The organic compound layer 482 has a property that the resistance value changes depending on the ambient temperature. Specifically, when the room temperature is a normal temperature, the resistance value decreases when the temperature is higher than the room temperature, and the resistance value increases when the temperature is lower than the room temperature. Therefore, a change in temperature can be detected by measuring a voltage value when a constant current value is passed between the pair of conductive layers.

  In FIG. 29B, the memory element portion 356 and the temperature sensor 472 are both provided by sequentially stacking a first conductive layer, an organic compound layer, and a second conductive layer provided in the same layer. Therefore, the same material can be used. Specifically, the first conductive layer of the memory element portion 356 and the first conductive layer in the temperature sensor 472 or the second conductive layer of the memory element portion 356 and the second conductive layer in the temperature sensor 472 are made of the same material. Can be formed. In addition, the organic compound layer of the memory element portion 356 and the organic compound layer of the temperature sensor 472 can be provided using the same material. In the case where the organic compound layer of the memory element unit 356 and the organic compound layer of the temperature sensor 472 are provided using the same material, when the change in the resistance value of the organic compound layer is detected by the temperature sensor 472, the memory element unit 356 Since the resistance value of the organic compound layer in the memory cell similarly changes, it is preferable to provide a circuit that corrects a change in voltage caused by a change in the resistance value of the organic compound layer when reading data stored in the memory element portion 356. . Of course, it is not necessary to provide all of the first conductive layer, the organic compound layer, and the second conductive layer with the same material. For example, only the first conductive layer may be formed with the same material. Only the conductive layer may be formed of the same material. Further, as shown in the above embodiment mode, the first conductive layer and the conductive layer functioning as an antenna may be formed in the same layer. 29 is not limited to the optical sensor and the temperature sensor, and other sensors described above can be formed. In the case where the temperature sensor 472 and the memory element portion 356 are provided in the same configuration, for example, the temperature sensor 472 can be formed with the structure shown in FIG.

  Next, FIG. 28B illustrates a structure of an RFID tag 900 including an element formation layer 901, a memory circuit portion 904, a sensor 908, and an antenna 902. The sensor unit 906 detects temperature, humidity, illuminance, gas, gravity, pressure, sound, vibration, acceleration, and other characteristics by physical or chemical means. The sensor unit 906 includes a sensor 908 and a sensor circuit 909 that controls the sensor 908. The sensor 908 is formed of a resistance element, a photoelectric conversion element, a thermoelectromotive element, a transistor, a thermistor, a diode, or the like. The sensor circuit 909 detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the arithmetic processing circuit unit 903.

  The element formation layer 901 includes an arithmetic processing circuit portion 903, a communication circuit portion 905, and a power supply circuit portion 907. In addition, the memory circuit portion 904 can be provided in the element formation layer 901. The memory circuit portion 904 can record information received from the outside via the sensor portion 906 and the antenna 902 as needed. The memory circuit unit 904 is configured by being divided into a first memory circuit unit 910 that stores a signal detected by the sensor unit 906 and a second memory circuit unit 911 that records information written from the reader / writer device. You can also.

  The first memory circuit portion 910 is preferably configured by a flash memory or the like that allows sequential writing and records data in order to record information detected by the sensor portion 906. In addition, it is preferable to apply a memory element that can be written only once.

  The communication circuit unit 905 includes a demodulation circuit 912 and a modulation circuit 913. The demodulation circuit 912 demodulates a signal input via the antenna 902 and outputs the demodulated signal to the arithmetic processing circuit unit 903. The signal includes a signal for controlling the sensor unit 906 and information stored in the storage circuit unit 904. In addition, a signal output from the sensor circuit 909 and information read from the storage circuit unit 904 are output to the modulation circuit 913 through the arithmetic processing circuit unit 903. The modulation circuit 913 modulates this signal into a signal capable of wireless communication, and outputs the signal to an external device via the antenna 902.

  Electric power necessary for operating the arithmetic processing circuit unit 903, the sensor unit 906, the storage circuit unit 904, and the communication circuit unit 905 is supplied via the antenna 902. Moreover, it is good also as a structure which incorporated the power supply (battery) depending on the usage form.

  In this manner, by providing a sensor capable of detecting information such as temperature and pressure in the semiconductor device described in the above embodiment mode, various information detected from the sensor can be stored and managed in the memory element portion. It becomes. For example, a semiconductor device having a gas sensor can be provided in the food to manage the state of the food. Specifically, a semiconductor device having a gas sensor is provided in a perishable food or the like to detect spoilage gas emitted from the food. The stored data is periodically read by a reader / writer provided on the side of the display shelf or the belt conveyor, so that the freshness of the food can be managed and the food that has started to be spoiled can be selected.

  In addition, a semiconductor device having a sensor such as a temperature sensor or a pressure sensor is provided on the surface or inside of the human body, and the biological information such as the pulse rate, heart rate, body temperature, blood pressure, electrocardiogram, electromyogram, etc. Can be stored in a storage element portion provided in the storage area. Since the semiconductor device of the present invention is thin and small, it can read biological information without restraining the human body. In addition, by regularly reading the recorded information with a reader / writer, it is possible to manage the health and exercise state of the human body and prevent or predict diseases. In addition, a home medical monitoring system or the like can be obtained by obtaining biological information read by a reader / writer using a network such as the Internet. It is possible to record and manage various information by embedding a semiconductor device provided with a sensor not only in the human body but also in animals such as livestock.

  Note that this embodiment can be freely combined with the above embodiment. That is, it can be implemented in combination with any structure of the semiconductor device described in the above embodiment mode.

(Embodiment 10)
The semiconductor device of the present invention has a wide range of uses, but can be used, for example, in electronic devices that store and display information. As an electronic device, for example, it can be used in a television receiver, a portable information terminal such as a mobile phone, a digital camera, a video camera, a navigation system, and the like. The case where the semiconductor device of the present invention is applied to a mobile phone will be described with reference to FIG.

  The cellular phone includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705. The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is attached to and detached from the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  The semiconductor device of the present invention is characterized in that it is small, thin, and lightweight. With the above characteristics, a limited space inside the housings 2700 and 2706 of the electronic device can be used effectively. In addition, the semiconductor device of the present invention is characterized by having a memory circuit with a simple structure, and by the above characteristics, an electronic device using the semiconductor device having a memory circuit highly integrated is provided at low cost. Can do. Furthermore, the semiconductor device of the present invention is characterized in that it has a nonvolatile memory circuit that can be additionally written, and an electronic device that realizes high functionality and high added value by the above characteristics. Can do. In addition, the semiconductor device of the present invention can be provided with a transistor in which a channel portion is a single crystal semiconductor layer having favorable mobility and response speed. In this case, high-speed operation is possible and the operating frequency is improved. An electronic device using the semiconductor device can be provided.

  The semiconductor device of the present invention can also be used as an RFID tag. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles It can be used in foods, clothing, health supplies, daily necessities, medicines, electronic devices and the like. These examples will be described with reference to FIG.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like (see FIG. 16A). The certificate refers to a driver's license, a resident card, etc. (see FIG. 16B). Bearer bonds refer to stamps, gift tickets, various gift certificates, and the like (see FIG. 16C). Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like (see FIG. 16D). Books refer to books, books, and the like (see FIG. 16E). The recording media refer to DVD software, video tapes, and the like (see FIG. 16F). The vehicles refer to vehicles such as bicycles, ships, and the like (see FIG. 16G). Personal belongings refer to bags, glasses, and the like (see FIG. 16H). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  Forgery can be prevented by providing RFID tags on bills, coins, securities, certificates, bearer bonds, and the like. In addition, it is possible to improve the efficiency of inspection systems and rental store systems by providing RFID tags for personal items such as packaging containers, books, and recording media, foods, daily necessities, and electronic devices. it can. By providing RFID tags on vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. The RFID tag is provided by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Further, when writing (additional writing) is performed by applying an optical action later, it is preferable to form the transparent element so that light can be applied to the portion of the memory element provided on the chip. Furthermore, forgery can be effectively prevented by using a memory element in which data once written cannot be rewritten. In addition, problems such as privacy after a user purchases a product can be solved by providing a system for erasing data in a storage element provided in the RFID tag.

  In this way, by providing RFID tags on packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. In addition, forgery and theft can be prevented by providing an RFID tag in vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding an RFID tag equipped with a sensor in a living creature such as livestock, it is possible to easily manage the current health condition such as the body temperature as well as the year of birth, gender or type.

  As described above, the semiconductor device of the present invention can be provided and used for any article that stores data. Note that this embodiment can be freely combined with the above embodiment.

  In this embodiment, a result of writing data by providing an organic memory element on a substrate and applying an electrical action to the organic memory element will be described.

  An organic memory element is an element in which a first conductive layer, an organic compound layer, and a second conductive layer are stacked in this order on a substrate. Note that a compound of silicon oxide and indium tin oxide was used for the first conductive layer. The organic compound layer was formed by spin coating of methoxy-5- (2-ethyl) hexyloxy] -p-phenylene vinylene (sometimes abbreviated as MEH-PPV). The second conductive layer was provided with aluminum by a vapor deposition method.

FIG. 17 shows measurement results of current-voltage characteristics before data is written by an electrical action and after data is written by an electrical action in the organic memory element having the above configuration. In FIG. 17, the horizontal axis indicates the voltage value (V), and the vertical axis indicates the current density (mA / cm ² ). In FIG. 17, a plot 861a shows a current-voltage characteristic before writing data by applying an electrical action, and a plot 861b shows a current-voltage characteristic after writing data by applying an electrical action.

From FIG. 17, it can be seen that there is a large change in the current-voltage characteristics of the organic memory element before and after data writing. For example, the current density before writing is 7.4 × 10 ⁻⁶ mA / cm ² at an applied voltage of 1 V, whereas the current density of the organic memory element after writing data is 1.1 × 10 ² mA / cm ^2. Thus, there is an 8-digit change in the current value before data writing and after data writing. That is, after the data is written, the resistance value of the organic memory element is greatly reduced.

  As described above, the resistance value of the organic memory element has changed before and after the data writing, and the change in the resistance value of the organic memory element is read by the voltage value or the current value. The function of a memory circuit can be incorporated in the semiconductor device of the present invention.

  In addition, a description will be given of a result of manufacturing an organic memory element using a material different from the above structure and writing data to the organic memory element by an electric action.

  An organic memory element is an element in which a first conductive layer, an organic compound layer, and a second conductive layer are stacked in this order on a substrate. Note that a compound of silicon oxide and indium tin oxide was used for the first conductive layer. The organic compound layer was formed by spin coating of poly (9-vinylcarbazole) (sometimes abbreviated as PVK). The second conductive layer was provided with aluminum by a vapor deposition method.

FIG. 18 shows measurement results of current-voltage characteristics before writing data by an electrical action and after writing data by an electrical action in the organic memory element having the above configuration. In FIG. 18, the horizontal axis indicates the voltage value (V), and the vertical axis indicates the current density (mA / cm ² ). In FIG. 18, a plot 862a shows a current-voltage characteristic before writing data by applying an electrical action, and a plot 862b shows a current-voltage characteristic after writing data by applying an electrical action.

As shown in FIG. 18, there is a large change in the current-voltage characteristics of the organic memory element before data writing and after data writing. For example, the current density is 2.3 × 10 ⁻¹ mA / cm ² before writing at an applied voltage of 1 V, whereas the current density of the organic memory element after writing data is 2.6 × 10 ² mA / cm ^2. Thus, there is a three-digit change in the current value before data writing and after data writing. That is, after the data is written, the resistance value of the organic memory element is greatly reduced.

  As described above, the resistance value of the organic memory element has changed before and after the data writing, and the change in the resistance value of the organic memory element is read by the voltage value or the current value. It can function as a memory circuit.

  In this embodiment, current-voltage characteristics of an organic memory element in which a second conductive layer is formed by a droplet discharge method (inkjet method) are shown. Here, writing was performed by applying a voltage to the organic memory element to short-circuit the organic memory element. In FIGS. 30A and 30B, the horizontal axis represents the voltage applied to the organic memory element, and the vertical axis represents the current density flowing through the organic memory element.

Here, ITO containing silicon oxide was formed as a first conductive layer over a glass substrate by a sputtering method. Next, PVK (poly (9-polyvinylcarbazole)) was applied by spin coating, and then heated at 100 ° C. for 10 minutes to form an organic compound layer having a thickness of 30 nm. Next, a composition containing Ag was discharged onto the organic compound layer by a droplet discharge method, and heated in a nitrogen atmosphere at 200 ° C. for 1 hour to form a second conductive layer. FIG. 30A shows the current-voltage characteristics of the organic memory element at this time. The write voltage here was 4.2 V, and the write current density was 5.8 mA / cm ² .

  In FIG. 30A, a plot 5001 shows a current-voltage characteristic before writing of the organic memory element, and a plot 5002 shows a current-voltage characteristic after writing of the organic memory. It can be seen that an ohmic current flows after writing. That is, it is possible to short-circuit the organic memory element with an applied voltage of 4 to 5V.

On the other hand, FIG. 30B is a reference example of the organic memory element shown in FIG. 30A and shows current-voltage characteristics of an organic memory element formed using an aluminum layer by a vapor deposition method as the second conductive layer. . The write voltage here was 1.9 V, and the write current density was 0.26 mA / cm ² .

  In FIG. 30B, a plot 5011 shows a current-voltage characteristic before writing of the organic memory element, and a plot 5012 shows a current-voltage characteristic of the organic memory element after writing. 30A and 30B, the organic memory element in which the second conductive layer is formed by the droplet discharge method applies a voltage in the same manner as the organic memory element in which the second conductive layer is formed by the vapor deposition method. By doing so, it is possible to short-circuit and write.

  In this example, the measurement result of the current-voltage characteristic when the organic memory element is heated is shown in FIG. Here, the organic compound layer of the organic memory element was formed using PVK having a glass transition point of 200 ° C.

  ITO containing silicon oxide formed by sputtering on a glass substrate is formed as a first conductive layer, PVK having a thickness of 17 nm is applied on the first conductive layer by spin coating, and heated at 120 ° C. for 90 minutes. Then, an organic compound layer was formed, and a second conductive layer formed of an aluminum layer was formed on the organic compound layer by vapor deposition to form an organic memory element. At this time, the thickness of the first conductive layer was 110 nm, and the thickness of the second conductive layer was 200 nm. The size of the element in the horizontal plane was 2 mm × 2 mm. The measurement result of the current-voltage characteristic of the organic memory element at this time is shown by a circled plot in FIG.

  Next, after heating the organic memory element at 120 ° C. for 10 minutes, the measurement result of the current-voltage characteristics of the organic memory element at room temperature is shown as a square plot in FIG. Similarly, after the organic memory element was heated at 160 ° C. for 10 minutes, the measurement result of the current-voltage characteristic of the organic memory element at room temperature was measured, and the triangular plot in FIG. 31 shows the result. Similarly, after heating the organic memory element at 200 ° C. for 10 minutes, the measurement result of the current-voltage characteristics of the organic memory element at room temperature is shown by a rhombus plot in FIG.

  Furthermore, the measurement results of the current-voltage characteristics after writing each element are shown by cross marks.

  In the organic memory element before writing, the writing voltage gradually decreases as the heating temperature is increased, and the writing voltage can be reduced.

  In this embodiment, write voltages and currents of organic memory elements having different sizes will be described with reference to Table 1 and FIG. Here, writing was performed by applying a voltage to the organic memory element to short-circuit the organic memory element.

  A first conductive layer made of titanium is formed on a substrate by sputtering, and PVK (poly (9-vinylcarbazole)) is applied on the first conductive layer by spin coating and heated to form an organic layer having a thickness of 8 nm. A compound layer was formed, and a second conductive layer formed of an aluminum layer was formed on the organic compound layer by vapor deposition to form an organic memory element. At this time, organic memory elements having a size of 100 μm × 100 μm, 40 μm × 40 μm, 20 μm × 20 μm, 10 μm × 10 μm in the horizontal plane of the organic memory element were formed, and current-voltage characteristics were measured.

  Here, the organic memory element having a size of 100 μm × 100 μm in the horizontal plane is Sample 1, the organic memory element having 40 μm × 40 μm is Sample 2, the organic memory element having 20 μm × 20 μm is Sample 3-6, and 10 μm × 10 μm. These organic memory elements are designated as Samples 7 to 10, and Table 1 shows the write voltage, write current, and read current of the organic memory elements of Samples 1 to 10. Reading was performed by applying 2.5 V to the element before writing and 0.5 V to the element after writing.

  Moreover, the current-voltage characteristics of Samples 8 to 10 are shown in FIGS. A triangle (triangle mark) indicates before writing, and a circle (circle) indicates after writing.

It was possible to perform writing at 8.5 V to 10.1 V, respectively. Further, the read current value before and after the writing had a difference of 10 ⁷ or more at the reading voltage of 1 V, and it was found that the characteristics sufficient for the memory were exhibited. The current value at the time of writing was 10 μA, and it was found that data could be written to the organic memory element with low power.

FIG. 6 illustrates a structural example of a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 10 shows an example of writing data to a semiconductor device of the present invention with a laser. 8A and 8B illustrate a method for driving a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 11 shows a usage pattern of a semiconductor device of the invention. FIG. 11 shows a usage pattern of a semiconductor device of the invention. FIG. 11 shows a usage pattern of a semiconductor device of the invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 is a diagram showing reading of data stored in a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. 10A and 10B illustrate a structural example of a method for manufacturing a semiconductor device of the present invention. FIG. 10 illustrates a structural example in which a semiconductor device of the present invention is provided in a display device. FIG. 10 illustrates a structural example in which a semiconductor device of the present invention is provided in a display device. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 illustrates a structural example of a semiconductor device of the present invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention.

Explanation of symbols

6 Memory 11 Power supply circuit 12 Clock generation circuit 13 Data demodulation / modulation circuit 14 Control circuit 15 Interface circuit 16 Storage circuit 17 Data bus 18 Antenna 19 Reader / writer 20 RFID tag 21 Memory cell 22 Memory cell array 23 Interface 24 Word line drive circuit 24a Row Decoder 24b Level shifter 26 Bit line drive circuit 26a Column decoder 26b Read circuit 26c Selector 27 First conductive layer 28 Second conductive layer 29 Organic compound layer 30 Substrate 31 Insulating layer 32 Insulating layer 34 Semiconductor layer 35 Semiconductor layer 37 Insulating layer 38 Organic compound layer 39 Memory element part 46 Resistive element 47 Differential amplifier 76 Conductive layer 77 Insulating layer 78 Insulating layer 79 Insulating layer 80 Substrate 81 Pixel part 82 Drive circuit part 83 Memory cell 84 Connection film 85 Driving transistor Star 86 Transistor 87 Transistor 88 First conductive layer 89 Organic compound layer 90 Second conductive layer 91 First conductive layer 92 Organic compound layer 93 Second conductive layer 94 Light emitting element 95 First conductive layer 96 Organic compound layer 97 Second conductive layer 98 Memory element 99 Conductive layer 221 Memory cell 222 Memory cell array 226 Bit line driver circuit 226a Column decoder 226b Read circuit 226c Selector 224 Word line driver circuit 224a Row decoder 224b Level shifter 223 Interface 216 Memory circuit 231 First Wiring 232 second wiring 240 transistor 248 transistor 241 storage element 241 organic memory element 230 substrate 243 first conductive layer 244 organic compound layer 245 second conductive layer 246 resistance element 247 differential amplifier 256 insulating layer 2 9 Insulating layer 250 Insulating layer 251 Element forming layer 321 Display unit 320 Reader / writer 322 Product 323 RFID tag 326 Product 324 Reader / writer 325 RFID tag 350 Substrate 351 Element forming layer 352 Memory element unit 353 Antenna unit 354 Transistor 355 Conductive layer 356 Memory element Part 357 antenna part 358 conductive layer 359 conductive fine particle 361 first conductive layer 362 organic compound layer 363 second conductive layer 364 insulating layer 365 substrate 366 insulating layer 371 first conductive layer 372 organic compound layer 373 second conductive Layer 374 insulating layer 375 resin 376 insulating layer 400 substrate 401a conductive layer 401b conductive layer 402 conductive layer 403 semiconductor layer 404 insulating layer 405 gate electrode 406 insulating layer 407 organic compound layer 408 conductive layer 409 storage element 410 nozzle 411 conductive Layer 412 Organic compound layer 413 Insulating layer 414a Conductive layer 414b Conductive layer 415 Conductive layer 416 Semiconductor layer 417 Insulating layer 418 Gate electrode 419 Memory element 421 Organic compound layer 421a Conductive layer 421b Conductive layer 422 Organic compound layer 423 Semiconductor layer 424 Insulating layer 425 Gate electrode 426 Insulating layer 427 Organic compound layer 428 Conductive layer 451 Transistor 462 Transistor 482 Organic compound layer 701 Substrate 702 Release layer 703 Insulating layer 704 Amorphous semiconductor layer 705 Insulating layer 706 Crystalline semiconductor layer 707 Crystalline semiconductor layer 708 Crystalline Semiconductor layer 709 Crystalline semiconductor layer 710 Crystalline semiconductor layer 711 N-type impurity region 712 P-type impurity region 713 N-type impurity region 714 N-type impurity region 715 N-type impurity region 716 Conductive layer 717 Conductive layer 718 Conductive layer 719 Conductive layer 720 Conductive layer 721 Conductive layer 722 Conductive layer 723 Conductive layer 724 Conductive layer 725 Conductive layer 726 N-type impurity region 727 N-type impurity region 728 N-type impurity region 729 N-type impurity region 730 N-type impurity region 731 N-type impurity region 731 732 N-type impurity region 733 N-type impurity region 734 Insulating layer 735 Insulating layer 736 Insulating layer 737 Insulating layer 738 Insulating layer 739 Insulating layer 740 Insulating layer 741 Insulating layer 742 Insulating layer 743 Insulating layer 744 Thin film transistor 745 Thin film transistor 746 Thin film transistor 747 Thin film transistor 748 Thin film transistor 749 insulating layer 750 insulating layer 751 insulating layer 752 conductive layer 753 conductive layer 754 conductive layer 755 conductive layer 756 conductive layer 757 conductive layer 758 conductive layer 759 conductive layer 760 conductive layer 761 conductive layer 762 insulating layer 7 3 conductive layer 764 conductive layer 765 conductive layer 766 insulating layer 767 contact hole 768 contact hole 769 contact hole 771 conductive layer 772 insulating layer 773 opening 774 opening 775 second substrate 776 first substrate 778 field effect transistor 779 thin film transistor 780 Channel formation region 781 Channel formation region 782 Channel formation region 783 Channel formation region 784 Channel formation region 785 P-type impurity region 786 Conductive layer 787 Organic compound layer 789 Memory element 790 Memory element 791 Thin film integrated circuit 900 RFID tag 901 Element formation layer 902 Antenna 906 Sensor part 941 Current-voltage characteristic 942 Current-voltage characteristic 943 Current-voltage characteristic 944 Intersection 945 Intersection 950 Sensor part 951 Conductive layer 952 Conductive fine particle 953 Conductive layer 9 4 Resin 1001 Laser Irradiation Device 1002 Computer 1003 Laser Oscillator 1004 Power Supply 1005 Optical System 1006 Acoustooptic Modulator 1007 Optical System 1009 Moving Mechanism 1010 D / A Converter 1011 Driver 1012 Driver 1013 Autofocus Mechanism 2700 Housing 2706 Housing 2701 Panel 2702 Housing 2703 Printed wiring board 2704 Operation button 2705 Battery 2708 Connection film 2709 Pixel area 861a Plot 861b Plot 862a Plot 862b Plot 5001 Plot 5002 Plot 5011 Plot 5012 Plot

Claims (8)

An element formation layer including a first transistor and a second transistor provided over a substrate;
A storage element provided on the element formation layer;
A sensor unit provided on the storage element,
The memory element has a stacked structure of a first conductive layer, an organic compound layer on the first conductive layer, and a second conductive layer on the organic compound layer,
Insulating layer is provided to cover the end of Oite the first conductive layer under the organic compound layer,
The first conductive layer is electrically connected to the first transistor;
The organic compound layer has a polymer compound,
The semiconductor device is characterized in that the sensor portion is electrically connected to the second transistor. An element formation layer including a first transistor, a second transistor, and a sensor portion provided on a substrate;
A storage element provided on the element formation layer,
The memory element has a stacked structure of a first conductive layer, an organic compound layer on the first conductive layer, and a second conductive layer on the organic compound layer,
Insulating layer is provided to cover the end of Oite the first conductive layer under the organic compound layer,
The first conductive layer is electrically connected to the first transistor;
The organic compound layer has a polymer compound,
The semiconductor device is characterized in that the sensor portion is electrically connected to the second transistor. An element formation layer including a first transistor and a second transistor provided over a substrate;
A storage element and a sensor unit provided on the element formation layer,
The memory element has a stacked structure of a first conductive layer, a first organic compound layer on the first conductive layer, and a second conductive layer on the first organic compound layer;
A first insulating layer covering the one end of Oite the first conductive layer is provided under the first organic compound layer,
The sensor unit has a stacked structure of a third conductive layer, a second organic compound layer on the third conductive layer, and a fourth conductive layer on the second organic compound layer,
A second insulating layer covering the one end of Oite the third conductive layer is provided under the second organic compound layer,
The first conductive layer is electrically connected to the first transistor;
The third conductive layer is electrically connected to the second transistor;
The semiconductor device, wherein the first organic compound layer and the second organic compound layer have the same polymer compound. In claim 3 ,
The first organic compound layer and the second organic compound layer are provided in the same process. In claim 3 or claim 4 ,
At least one of the first conductive layer and the third conductive layer, or the second conductive layer and the fourth conductive layer has the same material provided in the same step. . In any one of Claims 1 thru | or 5 ,
The semiconductor device is characterized in that the substrate is a glass substrate or a flexible substrate. In any one of Claims 1 thru | or 6 ,
A resistance of the memory element is irreversibly changed by writing. In any one of Claims 1 thru | or 7 ,
In the semiconductor device, the distance between the first conductive layer and the second conductive layer is changed by writing in the memory element.

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