JP4950780B2 - Bit error rate measuring device - Google Patents

Description

  The present invention relates to a bit error rate measuring apparatus, and more particularly to a bit error rate measuring apparatus for measuring a bit error rate of a burst test signal.

As a conventional bit error rate measuring device, a bit test signal transmitted by a measurement object that has received a burst test signal having a pseudo random pattern generated by a data generator is received, and a bit error rate of the burst test signal Receives a burst gate signal representing the measurement interval and a trigger signal synchronized with the period of the burst test signal from the data generator, and adjusts the phase of the burst gate signal based on the phase difference between the signal under test and the trigger signal In some cases, the phase of the burst gate signal is appropriately and automatically delayed with respect to the phase of the signal under test (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-284603

  However, the conventional bit error rate measuring device needs to measure in advance the amount of deviation between the phase of the burst test signal and the phase of the burst gate signal that has passed through the system under test when measuring the bit error rate. In addition, when resetting the delay amount of the burst gate signal, there is a problem that the measurement of the bit error rate must be interrupted.

  The present invention has been made to solve the conventional problems, and provides a bit error rate measuring apparatus capable of measuring the bit error rate of a burst test signal without measuring a delay amount in advance. Objective.

  A bit error rate measuring apparatus according to the present invention measures a bit error rate of a signal under test by comparing a burst signal under test with a reference pattern corresponding to the signal under test. A termination detecting means for detecting an end of an error rate measurement period to be measured based on a bit error rate of the signal under test, a burst length and a period of the signal under test, Based on the end of the error rate measurement period, the end of the error rate measurement period ends, an internal gate signal generating means for generating an internal gate signal representing an error determination period, the signal under test and the reference pattern A synchronization determination circuit that determines the establishment of synchronization based on a first threshold, and that the synchronization between the signal under test and the reference pattern is detected within the error determination period. The has a measurement result output means for outputting a bit error in the error rate measurement period as the measurement result, a structure having a it is.

  With this configuration, the bit error rate measuring device of the present invention can measure the bit error rate of the burst test signal without measuring the delay amount in advance.

  The termination detection means calculates the bit error rate for each bit group consisting of a predetermined number of bits during the error rate measurement period, and the bit error rate for each bit group is equal to or greater than a second threshold value. A position obtained by subtracting the time of at least one bit group from the tip of the earliest bit group may be the end of the error rate measurement period.

  In addition, the termination detection means detects the termination of the error rate measurement period before the maximum synchronization loss detection time from when the synchronization determination circuit detects that the signal under test is out of synchronization with the reference pattern. May be detected.

  The internal gate signal generation means may generate the internal gate signal such that the length of the error determination period is equal to the length of the signal under test.

  The bit error rate measuring apparatus of the present invention receives the signal from the synchronization determination circuit and the internal gate signal, and the bit error rate is equal to or higher than the first threshold within the error determination period and after synchronization is established. Gate control means for detecting that the signal under test and the reference pattern are out of synchronization may be provided based on whether or not.

  Further, the gate control means further receives a signal from the termination detection means, and the synchronization between the signal under test and the reference pattern is lost within the error determination period and after synchronization is established, or the error rate Until the period when the bit error rate of the bit group that is a predetermined number before the end of the measurement period is equal to or greater than the second threshold continues for a predetermined number of times, the same internal gate signal is transmitted to the internal gate in each period. The signal generation unit may generate the signal.

  Further, the bit error rate measuring device of the present invention represents the burst length and period of the signal under test, and from the rising edge of the input burst gate signal that has been input for a predetermined time with respect to the signal under test, From the first time until it is detected that synchronization between the signal under test and the reference pattern is established, and from the end of the error rate measurement period detected by the end detection means, the rising edge of the input burst gate signal is detected. A third time obtained by subtracting the second time from the first time is calculated from a second time from when the first time elapses until the first time elapses, and the input burst gate signal is calculated as the first time. A phase adjustment unit that outputs a signal delayed by a time of 3 as the internal gate signal may be provided.

  The device test system of the present invention includes a burst test signal generation device that generates a burst test signal, and the bit error rate measurement device that receives the signal under test output by a measurement object that has received the burst test signal. It has the composition provided.

  With this configuration, the device test system of the present invention adjusts the phase of the burst gate signal based on the bit error rate measured by the bit error rate measurement unit, so that the burst test signal is not measured in advance. Can be measured.

  The present invention can provide a bit error rate measuring apparatus that can measure the bit error rate of a burst test signal without interrupting the measurement of the bit error rate and without measuring the delay amount in advance.

  Furthermore, the bit error rate measuring device of the present invention can perform phase automatic adjustment of the input burst gate signal and reset the phase even during the bit error measurement.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
A device test system according to a first embodiment of the present invention is shown in FIG.

  The device test system 1 includes an input / output device 2, a burst test signal generation device 4 that generates a burst test signal for testing the measurement object 3, and an object transmitted by the measurement object 3 that has received the burst test signal. And a bit error rate measuring device 5 for measuring the bit error rate of the test signal.

  Note that the measurement object 3 in the present embodiment includes an OLT (Optical Line Terminal), a repeater, a transmission optical fiber, and a transmission installed in a station of a communication carrier in the PON (Passive Optical Network) system. There are cables.

  Here, in addition to the OLT, the PON system is an ONU (Optical) that is installed in a telephone pole / roadside near a user, a building, a user's house, etc. and converts an optical signal from the OLT into a signal that conforms to a user's standard. Network Unit), and an optical fiber star coupler that connects one OLT and a plurality of ONUs in a one-to-many manner, and is used in an optical fiber access network.

  The OLT upstream test method used in the PON system is standardized by IEEE, and two types of burst test signals with an average light power difference of about 10 dB are alternately and repeatedly transmitted from two ONUs. Thus, it is tested whether the OLT can correctly receive a burst test signal having a small optical power.

  The object to be measured 3 is one that inputs an optical signal and outputs an electrical signal, such as an OLT, one that inputs and outputs an optical signal, such as a relay device or a transmission optical fiber, and an electrical signal, such as a transmission cable. There is something to output.

  When the measurement object 3 is for inputting an optical signal, an E / O converter is provided so as to be built in or externally attached to the output side of the burst test signal generation device 4.

  When the measurement object 3 outputs an optical signal, an O / E converter is provided on the input side of the bit error rate measuring device 5 so as to be built in or externally attached. The output electrical signal is input to the bit error rate measuring unit 31 described later as a signal under test.

  The input / output device 2 includes an input device 10 configured by a keyboard, a pointing device, and the like, a display device 11, and a CPU (Central Processing Unit) 12 that executes a program for controlling the device test system 1. Yes. The input / output device 2 may be configured by a computer device externally attached to the device test system 1.

  The burst test signal generation device 4 periodically and repeatedly generates a burst storage signal having a pattern stored in the pattern storage 20 and a pattern storage 20 that stores a pattern of the burst test signal to be transmitted to the measurement object 3. A test signal generation unit 21 and a gate signal generation unit 22 that generates a burst gate signal representing a section in which the burst test signal has a pattern are provided.

  In the present embodiment, the pattern storage unit 20 is configured by a storage medium such as a RAM (Random Access Memory), and the test signal generation unit 21 and the gate signal generation unit 22 are programmed FPGA (Field Programmable Gate Array). It is constructed integrally.

  Note that the gate signal generation unit 22 may be configured to be built in the bit error rate measurement device 5 or externally attached to the burst test signal generation device 4 or the bit error rate measurement device 5.

  The bit error rate measuring device 5 includes a reference pattern storage unit 30 that stores a reference pattern corresponding to the pattern stored in the pattern storage unit 20, a bit error rate measurement unit 31 that measures the bit error rate of the signal under test, And an error rate measurement period signal representing an error rate measurement period as a bit error rate measurement target, and a phase adjustment unit 32 for adjusting the phase of an internal gate signal representing an error determination period. Here, the error determination period refers to a period including the error rate measurement period that has the same termination as the error rate measurement period.

  In the present embodiment, the reference pattern storage unit 30 is configured by a storage medium such as a RAM, and the bit error rate measurement unit 31 and the phase adjustment unit 32 are integrally configured by a programmed FPGA.

  The bit error rate measurement unit 31 compares the pattern of the signal under test received from the measurement object 3 with the reference pattern when the internal gate signal adjusted by the phase adjustment unit 32 represents the error determination period, The bit error rate is measured by the input / output device 2 in a predetermined time unit or a predetermined number of bits.

  As shown in FIG. 2, the bit error rate measurement unit 31 compares the pattern of the signal under test with the reference pattern during the error determination period and measures the bit error rate, and the synchronization determination circuit 51. And an AND circuit 52.

  When the bit error rate measured by the bit error rate measurement circuit 50 is equal to or less than the first threshold value S1 set by the input / output device 2, the synchronization determination circuit 51 continues for a predetermined time Tx. It is determined that synchronization has been established, and a status signal “1” is output to the counter 61 and an AND circuit 68 described later.

  In addition, the synchronization determination circuit 51 performs synchronization when the state in which the bit error rate measured by the bit error rate measurement circuit 50 is higher than the first threshold value S1 continues for a predetermined time Ty (Tx <Ty). The status signal “0” is output to the counter 61 and the AND circuit 68.

  The synchronization method determined by the synchronization determination circuit 51 includes a frame synchronization method for detecting a frame to establish synchronization, a PRBS synchronization method for receiving a pseudo-random pattern, and a pattern synchronization method for establishing synchronization without detecting a frame. Etc. For example, in the case of the frame synchronization method, the synchronization determination circuit 51 outputs a signal indicating synchronization establishment to a frame detection circuit and a reference pattern generation circuit (not shown in FIG. 2).

  The AND circuit 52 outputs the bit error rate in the error rate measurement period among the bit error rates measured by the bit error rate measurement circuit 50 as a measurement result to the CPU 12 and an error rate monitoring circuit 69 of the phase adjustment unit 32 described later. It has become.

  The phase adjustment unit 32 includes counters 60 to 64, selectors 65 and 66, a set-reset flip-flop (hereinafter simply referred to as “SR-FF”) 67, an AND circuit 68, an error rate monitoring circuit 69, and a gate. And a control circuit 70.

  The counter 60 starts counting when receiving an instruction to start measurement input to the input / output device 2 and counts the rising edge of the input burst gate signal.

  The counter 61 starts counting at the rising edge of the input burst gate signal, and stops counting when the status signal output from the synchronization determination circuit 51 changes from “0” to “1”. The time T1 from the rise of the signal to the rise of the status signal is measured.

  When the count value of the counter 60 is less than 2, the selector 65 selects the time T1 measured by the counter 61. When the count value of the counter 60 is 2 or more, the selector 65 starts from the time T1 to a time described later. A time (T1-T2) obtained by subtracting T2 is selected.

  When the count value of the counter 60 is less than 2, the selector 66 selects 0 time, and when the count value of the counter 60 is 2 or more, the selector 66 subtracts the time T2 from the time T1 (T1- T2) is selected.

  The counter 62 starts counting at the rising edge of the input burst gate signal. When the time selected by the selector 66 elapses, the counter 62 outputs a carry “1” indicating that the count has exceeded to the SR-FF 67. Yes.

  The counter 63 starts counting at the falling edge of the input burst gate signal. When the time selected by the selector 65 elapses, the counter 63 outputs a carry “1” indicating that the count has exceeded to the SR-FF 67. ing.

  The SR-FF 67 is set (low → high) when the carry 62 is output by the counter 62, and is reset (high → low) when the carry 63 is output by the counter 63. In this set / reset state, an internal gate signal representing an error determination period is generated.

  The AND circuit 68 performs a logical product of the internal gate signal output from the SR-FF 67 and the status signal output from the synchronization determination circuit 51, thereby converting the error rate measurement period signal representing the error rate measurement period into a bit error. The data is output to the AND circuit 52 of the rate measuring unit 31.

  The error rate monitoring circuit 69 monitors the bit error rate of the error rate measurement period output from the AND circuit 52 of the bit error rate measuring unit 31 in units of a predetermined number of bits, for example, in units of 64 bits, and performs a bit in units of 64 bits. While the error rate is equal to or greater than the second threshold value S2, a signal indicating that the bit error rate is equal to or greater than S2 is output to the counter 64 and the gate control circuit 70. Here, the second threshold value is set to a value slightly smaller than the mark rate of the signal under test. In the present embodiment, the mark ratio of the signal under test is set to 1/2, and the second threshold is set to 3/7.

  The counter 64 is a time obtained by adding a predetermined number N times of the time of the bit group consisting of 64 bits to the time when the signal indicating that the bit error rate from the error rate monitoring circuit 69 is S2 or more is output. T2 is measured. Here, the predetermined number N is at least 1 or more, and is 4 in the present embodiment. Even for a bit group whose bit error rate does not exceed S2, a period in which the signal under test does not exist may be included in the period of the bit group, so the predetermined number N must be 1 or more.

  The gate control circuit 70 determines whether or not the status signal is “0” after the status signal is changed from “0” to “1” (synchronization is established) during the error determination period indicated by the internal gate signal. Based on the above, it is detected that the synchronization is lost within the error determination period.

Further, the gate control circuit 70 has a register for holding the value of the signal output from the error rate monitoring circuit 69 for a predetermined number _NG of bit groups, and the predetermined number _NG from the fall of the internal gate signal. It is determined whether or not the bit error rate of the previous bit group is S2 or more. Here, the predetermined number _NG is at least 1 or more, and is 2 in the present embodiment.

  In addition, the gate control circuit 70 detects that the synchronization is lost after the synchronization is established within the error determination period, or the bit error rate of the bit group two before the falling edge of the internal gate signal is S2 or more. When the period is detected continuously for a predetermined number of times C, the counters 61 and 64 are operated, and the counters 61 and 64 are caused to remeasure the times T1 and T2, so that the times T1 and T2 are remeasured. The SR-FF 67 is made to newly generate an internal gate signal. Here, the predetermined number of times C is 4 in the present embodiment.

  On the other hand, if the period is not detected four times in succession, the gate control circuit 70 stops the counters 61 and 64 and sends the internal gate signal to the SR-FF 67 based on the measured times T1 and T2. It is supposed to be generated.

  Note that the gate control circuit 70 may detect that the synchronization is lost after the establishment of synchronization within the error determination period every unit time, and output the detection result to the CPU 12.

  The operation of the device test system 1 configured as described above will be described with reference to FIG.

In the burst test signal generation device 4, a burst test signal having a pattern stored in the pattern storage unit 20 is repeatedly generated by the test signal generation unit 21. Further, the input burst gate signal representing the measurement section (T _G ) having the same time length as the burst length of the signal under test (T _T ) is gated at the same timing as the output timing of the burst test signal that is repeatedly output. The signal generation unit 22 outputs the signal to the phase adjustment unit 32 of the bit error rate measurement device 5.

  The burst test signal is converted into a signal under test via a measurement object 3 such as an OLT in the PON system, and then input to the bit error rate measuring unit 31 of the bit error rate measuring device 5 as an electric signal. . Therefore, the input burst gate signal (c) generated by the gate signal generator 22 is input to the bit error rate measuring device 5 prior to the signal under test (a).

  Here, when the state in which the bit error rate measured by the bit error rate measurement circuit 50 is equal to or less than the first threshold value S1 continues for the time Tx, the status signal (b) “1” is generated by the synchronization determination circuit 51. When the state in which the bit error rate is higher than the first threshold value S1 continues for the time Ty, the synchronization determination circuit 51 generates the status signal (b) “0”.

  The counter 61 measures the time T1 from the rising edge of the input burst gate signal (c) to the rising edge of the status signal (b).

  Measurement was performed by the counter 61 in the first period from the rise of the first input burst gate signal to the rise of the second input burst gate signal after the measurement start instruction input to the input / output device 2 was input. The time T1 is selected by the selector 65, and the time 0 is selected by the selector 66.

  In this case, the SR-FF 67 is set at the rising edge of the input burst gate signal (c), and is reset when the time T1 has elapsed from the falling edge of the input burst gate signal (c). The internal gate signal (d) representing the set / reset state of the signal is output from the SR-FF 67 to the bit error rate measuring circuit 50.

  Next, the error rate measurement period signal (e), which is the result of the logical product of the internal gate signal (d) output from the SR-FF 67 and the status signal (b) output from the synchronization determination circuit 51, is the AND circuit 68. Is output by.

  Here, if the bit error rate measured by the bit error rate measurement circuit 50 is higher than the second threshold value S2 while the error rate measurement period signal (e) output by the AND circuit 68 is high, an error occurs. The counter 64 measures a time T2 obtained by adding the time of four bit groups from the time determined by the rate monitoring circuit 69.

  For example, as shown in FIG. 4, the pattern of the signal under test (a) ends at time t2, and the bit error rate of the bit group is higher than the second threshold value S2 between time t3 and time t4. Is determined by the error rate monitoring circuit 69, the counter 64 measures the time T2 from the time t1 to the time t4 obtained by subtracting the time corresponding to the four bit groups from the time t3. Note that in the signal under test (a) shown in FIG. 4, one rectangle indicates one bit group, that is, a 64-bit section, and a hatched section indicates a section where a pattern exists. Show.

  If the time from the rise of the status signal (b) to the fall of the internal gate signal (d) is not a natural number multiple of the time corresponding to 64 bits of the signal under test (a), the interval indicated by the last rectangle However, the bit error rate per bit number may be measured and compared with the second threshold value S2.

  In FIG. 4, time t1 is the end of the error rate measurement period. The end point may be a time obtained by subtracting the time for at least one bit group from the time t3, and the subtracted time does not have to be a natural number multiple of the time for 64 bits.

  In FIG. 3, after the rise of the second input burst gate signal after the measurement start instruction is input to the input / output device 2, that is, after the next cycle, the time (T1−) obtained by subtracting the time T2 from the time T1. T2) is selected by the selector 65 and the selector 66.

  In this case, the SR-FF 67 is set when the time (T1-T2) has elapsed from the rise of the input burst gate signal (c), and the time (T1-T2) from the fall of the input burst gate signal (c). When T2) elapses, the reset state is entered, and the internal gate signal (d) is output from the SR-FF 67.

  Thus, the phase adjustment between the input burst gate signal and the signal under test by the phase adjustment unit 32 is completed in two cycles, and the error rate measurement period signal (e) in the second and subsequent cycles is at a high level. The bit error rate of the signal under test is transmitted to the CPU 12 as a measurement result and displayed on the display device 11.

  Also, from this state, it is detected that synchronization has been lost after synchronization is established within the error determination period, or the bit error rate of the bit group two before the falling edge of the internal gate signal is S2 or more. Until the gate control circuit 70 detects four consecutive times, the times T1 and T2 are maintained, and the phases of the internal gate signal (d) and the error rate measurement period signal (e) are fixed.

  On the other hand, when the period is detected four times in succession by the gate control circuit 70, the times T1 and T2 are remeasured in the same manner as when measured last time, and the internal gate signal (d) and the error rate measurement period are measured. The phase of the signal (e) is readjusted.

  For the burst gate signal in the first cycle, the input burst gate signal rises from the set interval until the time T1 elapses after the input burst gate signal rises and from the end of the signal under test. Synchronization is not established in a total of two sections, from the time when the time T1 elapses until the time T1 elapses. Therefore, the result of bit error measurement in the two sections is not included in the calculation of the bit error rate to be displayed on the display device 11 via the CPU 12.

  In the present invention, when the signal under test is a burst signal repeatedly input, the input interval of the signal under test is not limited to a uniform one. The signal under test and the input burst gate signal have the same phase difference between those having the same order n after the measurement start instruction is input, and the rising timing of the nth input burst gate signal is It must be the same as or behind the time position at the end of the (n-1) th signal under test.

In addition, when measuring the bit error rate of a part of the signal under test, for example, only the payload, the time _TG from the rising edge to the falling edge of the input burst gate signal is set equal to the payload length and the payload of the burst test signal is set. Only the pattern to be set is stored in the reference pattern storage unit 30.

  In the present embodiment, an example in which a relay device, a transmission cable, or the like is applied as the measurement object 3 has been described. By providing an electric-optical converter or an optical-electrical converter on the input side of the apparatus 5, an optical module, an optical cable, or the like can be applied as the measurement object 3, and in particular, an OLT test or light in the PON system. This is suitable for a round-trip experiment.

In this embodiment, the input burst gate signal is input to the phase adjustment unit 32. However, when the phase adjustment unit 32 can obtain the length _TG and the period of the input burst gate signal. A burst gate signal equivalent to the input burst gate signal may be generated inside the phase adjustment unit 32.

(Second Embodiment)
A device test system according to the second embodiment of the present invention is shown in FIG. In the present embodiment, the same components as those of the device test system 1 in the first embodiment of the present invention are denoted by the same reference numerals, and description thereof is omitted.

  As illustrated in FIG. 5, the device test system 100 includes an input / output device 2, a burst test signal generation device 104 that generates a burst test signal for testing the measurement object 3, and a measurement target that has received the burst test signal. A bit error rate measuring device 105 for measuring the bit error rate of the signal under test transmitted by the object 3.

  The burst test signal generation device 104 is configured by removing the gate signal generation unit 22 from the burst test signal generation device 4 described in the first embodiment of the present invention.

  The bit error rate measuring device 105 adjusts the phase of the reference pattern storage unit 30, the bit error rate measuring unit 31 that measures the bit error rate of the signal under test, the error rate measurement period signal, and the first internal gate signal. And a phase adjustment unit 132. Here, the first internal gate signal represents the first error determination period including the error rate measurement period that has the same termination as the error rate measurement period.

  As shown in FIG. 6, the phase adjustment unit 132 includes counters 162 and 163, selectors 165, 166, and 171, SR-FF 167, AND circuit 68, error rate monitoring circuit 69, gate control circuit 70, And a termination detection circuit 172 that detects the termination of the first error determination period.

The selector 165 includes a _T C _-T T -64 minus the time _{T T} and the first bit group content length 64 of the burst length of the signal under test from the period _{T C} of the test signal, the period of the test signal T and a T _C -T _T obtained by subtracting the time T _T of burst length of the signal under test from _C, to select on the basis of the count end value set in the counter 162 the selection signal output from the gate control circuit 70 It has become.

  The selector 166 outputs, from the gate control circuit 70, a signal representing the timing at which the counter 162 starts counting from the termination signal representing the termination detected by the termination detection circuit 172 and the first internal gate signal having the opposite phase. The selection is made based on the selection signal.

  The counter 162 starts counting at the end of the first error determination period, and outputs a carry “1” indicating that the count has exceeded at the beginning of the next first error determination period to the SR-FF 67. It has become.

Counter 163 starts counting at the beginning of the first error determination period, when the time T _T of burst length of the test signal has passed, SR-FF 67 a carry "1" indicating that the count is over To output.

  The SR-FF 167 enters a set state when a carry “1” is output by the counter 162, and enters a reset state when a carry “1” is output by the counter 163. In this set / reset state, the SR-FF 167 A first internal gate signal representing an error determination period is generated.

  The selector 171 uses the first internal gate signal generated by the SR-FF 167 and the level “1” as a gate control circuit for the second internal gate signal as the internal gate signal output to the bit error rate measuring unit 31. The selection is made on the basis of the selection signal output from 70. The termination detection circuit 172 detects the termination of the first error determination period based on the signal output from the error rate monitoring circuit 69.

  In the first embodiment of the present invention, the gate control circuit 70 is provided so as to switch the operation and stop of the counters 61 and 64. However, in the present embodiment, the gate control circuit 70 is a selector. 165, 166 and 171 are provided to switch the selection.

Specifically, the gate control circuit 70 determines that the bit error rate of the bit group that is a predetermined number _NG before the cycle in which the synchronization is lost within the error determination period or the falling edge of the second internal gate signal. When a period equal to or greater than S2 is continuously detected C a predetermined number of times or at the start of the test, the selector 165 selects T _C -T _T -64, the selector 166 selects the termination signal, and the selector 171 selects the level “1”. "It is supposed to let you choose.

  Further, the gate control circuit 70 causes the selectors 165, 166, and 171 to select the other after the end of the first error determination period is detected by the end detection circuit 172.

  The operation of the device test system 100 configured as described above will be described with reference to FIG.

First, in a state where the selector 165 selects T _C -T _T -64, the selector 166 selects the termination signal (f), and the selector 171 selects the level “1”, the termination detection circuit 172 selects the first When the end of the error determination period is detected at time t1, SR-FF 167 is set at time t2 when time T _C -T _T -64 has elapsed (g), and the first internal gate signal (x) Becomes "1".

Here, according to the selection signal (h) output by the gate control circuit 70, the selector 165 selects T _C -T _T at the time t3, and the selector 166 has the first internal gate signal (x) having the reverse phase. And the selector 171 selects the first internal gate signal (x).

The first internal gate signal at time t4 to time T _T measured by the counter 163 has elapsed from the time t2 (x) becomes "0". Later, the first internal gate signal of the first error determination time period _{T T} and period _{T C} (x) is generated by the SR-FF167, the second internal gate signal (d) bit error as an internal gate signal It is output to the rate measuring unit 31.

(Third embodiment)
A device test system according to the third embodiment of the present invention is shown in FIG. In the present embodiment, the same components as those of the device test system 100 in the second embodiment of the present invention are denoted by the same reference numerals, and description thereof is omitted.

  As illustrated in FIG. 8, the device test system 200 includes an input / output device 2, a burst test signal generation device 104 that generates a burst test signal for testing the measurement object 3, and a measurement target that has received the burst test signal. A bit error rate measuring device 205 for measuring the bit error rate of the signal under test transmitted by the object 3.

  As shown in FIG. 9, the bit error rate measuring device 205 is different from the bit error rate measuring device 105 constituting the device test system 100 in the second embodiment of the present invention in place of the phase adjusting unit 132. An adjustment unit 232 is provided.

  The phase adjustment unit 232 includes counters 271 and 272, a subtracter 273, and an SR-FF 274. The counter 271 calculates a period S in which the status signal obtained from the bit error rate measuring unit 31 is “1”.

The subtractor 273 calculates a time (S−T _L ) obtained by subtracting the maximum synchronization loss detection time _TL set by the CPU 12 from the period S calculated by the counter 271. Here, the maximum loss of synchronization detection time _TL can be determined in advance as 1 / (S1 * R) using the first threshold value S1 and the bit rate R of the signal under test.

The counter 272 indicates that the count has exceeded when the time (S−T _L ) calculated by the subtractor 273 has elapsed since the status signal obtained from the bit error rate measurement unit 31 has become “1”. Is output to the SR-FF 274.

  The SR-FF 274 enters a set state when the status signal obtained from the bit error rate measuring unit 31 becomes “1”, and enters a reset state when a carry “1” is output from the counter 272. An error rate measurement period signal indicating an error rate measurement period is generated in the reset state.

  In the present embodiment, the bit error rate measurement circuit 50 is configured to always compare the pattern of the signal under test with the reference pattern.

  The operation of the device test system 200 configured as described above will be described with reference to FIG.

The SR-FF 174 enters the set state when the status signal (b) obtained from the bit error rate measuring unit 31 is “1” with respect to the signal under test (a), and the status signal (b) is “ The reset state is entered when the time (S−T _L ) calculated by the subtractor 273 has elapsed since 1 ″. Thereby, the error rate measurement period signal is generated by the SR-FF 174.

(Fourth embodiment)
A device test system according to a fourth embodiment of the present invention is shown in FIG. In the present embodiment, the same components as those of the device test system 100 in the second embodiment of the present invention are denoted by the same reference numerals, and description thereof is omitted.

  As illustrated in FIG. 11, the device test system 300 includes an input / output device 2, a burst test signal generation device 104 that generates a burst test signal for testing the measurement object 3, and a measurement target that has received the burst test signal. A bit error rate measuring device 305 for measuring the bit error rate of the signal under test transmitted by the object 3.

  As shown in FIG. 12, the bit error rate measuring apparatus 305 is different from the bit error rate measuring apparatus 105 constituting the device test system 100 according to the second embodiment of the present invention in place of the phase adjustment unit 132. An adjustment unit 332 is provided. The phase adjustment unit 332 includes counters 321 and 322 and an SR-FF 324.

When the maximum synchronization establishment detection time T _S set by the CPU 12 has elapsed since the status signal became “1”, the counter 321 counts the carry “1” indicating that the count has been exceeded with the counters 322 and SR. -It outputs to FF324. Here, the maximum synchronization establishment detection time T _S can be determined in advance using the first threshold S 1 and the bit rate of the signal under test.

The counter 322 is obtained by subtracting the maximum synchronization establishment detection time T _S and the maximum synchronization loss detection time T _L from the time T _{T corresponding} to the burst length of the signal under test from the time when the carry “1” is output from the counter 321. _{When m} has elapsed, a carry “1” indicating that the count has been exceeded is output to the SR-FF 324.

Here, the maximum loss of synchronization detection time _TL can be determined in advance as 1 / (S1 * R) using the first threshold value S1 and the bit rate R of the signal under test. Further, since the time T _{T corresponding to} the burst length of the signal under test and the maximum synchronization establishment detection time T _S are also determined in advance, the time T _m can also be determined in advance.

  The SR-FF 324 enters a set state when a carry “1” is output from the counter 321, and enters a reset state when a carry “1” is output from the counter 322. In this set / reset state, the error rate measurement is performed. An error rate measurement period signal representing the period is generated.

  In the present embodiment, the bit error rate measurement circuit 50 is configured to always compare the pattern of the signal under test with the reference pattern.

  The operation of the device test system 300 configured as described above will be described with reference to FIG.

SR-Ff324, to the signal under test (a), when the maximum synchronization establishment detection time T _S has elapsed since the status signal obtained from the bit error rate measuring section 31 (b) is set to "1" It becomes a set state, in the reset state when the time T _m from a set state has elapsed. Thereby, the error rate measurement period signal is generated by the SR-FF 324.

In this embodiment, the error rate measurement period is determined based on the status signal (b), T _T , T _S , and T _L for each period, but the period of the signal under test (a) is known. In this case, an error rate measurement period signal (e) after the desired period may be generated based on the status signal (b) having a desired period.

The block diagram of the device test system in the 1st form of this invention 1 is a block diagram of a bit error rate measuring unit and a phase adjusting unit of a bit error rate measuring device constituting a device test system according to a first embodiment of the present invention. Timing chart for explaining operations of the bit error rate measuring unit and the phase adjusting unit of the bit error rate measuring device constituting the device test system according to the first embodiment of the present invention Timing chart for explaining the termination detection operation of the phase adjustment unit of the bit error rate measuring device constituting the device test system according to the first embodiment of the present invention The block diagram of the device test system in the 2nd form of this invention The block diagram of the bit error rate measurement part of the bit error rate measurement apparatus which comprises the device test system in the 2nd form of this invention, and a phase adjustment part Timing chart for explaining operations of the bit error rate measuring unit and the phase adjusting unit of the bit error rate measuring device constituting the device test system according to the second embodiment of the present invention The block diagram of the device test system in the 3rd form of this invention The block diagram of the bit error rate measurement part of the bit error rate measurement apparatus which comprises the device test system in the 3rd form of this invention, and a phase adjustment part Timing chart for explaining operations of the bit error rate measuring unit and the phase adjusting unit of the bit error rate measuring device constituting the device test system according to the third embodiment of the present invention The block diagram of the device test system in the 4th form of this invention The block diagram of the bit error rate measurement part of the bit error rate measurement apparatus which comprises the device test system in the 4th form of this invention, and a phase adjustment part Timing chart for explaining operations of the bit error rate measuring unit and the phase adjusting unit of the bit error rate measuring device constituting the device test system in the fourth mode of the present invention

Explanation of symbols

1, 100, 200, 300 Device test system 2 Input / output device 3 Measurement object 4, 104 Burst test signal generator 5, 105, 205, 305 Bit error rate measurement device 10 Input device 11 Display device 12 CPU
20 pattern storage unit 21 test signal generation unit 22 gate signal generation unit 30 reference pattern storage unit 31 bit error rate measurement unit 32, 132, 232, 332 phase adjustment unit 50 bit error rate measurement circuit 51 synchronization determination circuit 52 AND circuit 60, 61, 62, 63, 64, 162, 163, 271, 272, 321, 322, 721 Counter 65, 66, 165, 166, 171 Selector 67, 167, 174, 274, 324 SR-FF
68 AND circuit 69 Error rate monitoring circuit 70 Gate control circuit 172 Termination detection circuit 273 Subtractor

Claims (8)

A bit error rate measuring device for measuring a bit error rate of the signal under test by comparing a burst signal under test with a reference pattern corresponding to the signal under test,
End detection means (64, 69) for detecting the end of an error rate measurement period to be measured based on the bit error rate of the signal under test;
Internal gate signal generation means for generating an internal gate signal representing an error determination period, based on the burst length and period of the signal under test and the end of the error rate measurement period. (67)
A synchronization determination circuit (51) for determining establishment of synchronization between the signal under test and the reference pattern based on a first threshold (S1);
Measurement result output means (52) for outputting, as a measurement result, a bit error in the error rate measurement period in which it is detected that synchronization between the signal under test and the reference pattern is established within the error determination period; A bit error rate measuring apparatus comprising:   The termination detection unit calculates the bit error rate for each bit group including a predetermined number of bits during the error rate measurement period, and the bit error rate for each bit group becomes equal to or greater than a second threshold (S2). 2. The bit error rate measuring device according to claim 1, wherein a position obtained by subtracting the time of at least one bit group from the tip of the earliest bit group is the end of the error rate measuring period. . The termination detection means detects the error rate measurement period before the maximum synchronization loss detection time (T _L ) from when the synchronization determination circuit detects that the signal under test is out of synchronization with the reference pattern. The bit error rate measuring device according to claim 1, wherein the bit error rate measuring device is detected as an end of the bit error rate.   4. The internal gate signal generating means generates the internal gate signal so that an error determination period has a length equal to the length of the signal under test. Bit error rate measurement device.   In response to the signal from the synchronization determination circuit and the internal gate signal, based on whether the bit error rate is equal to or higher than the first threshold (S1) within the error determination period and after synchronization is established, 5. The bit error rate measuring apparatus according to claim 1, further comprising gate control means (70) for detecting that the signal under test and the reference pattern are out of synchronization. . The gate control means further receives a signal from the termination detection means, and the synchronization between the signal under test and the reference pattern is lost within the error determination period and after synchronization is established, or the error rate measurement period Until the cycle in which the bit error rate of the bit group that is a predetermined number (N _G ) before the end of is equal to or greater than the second threshold value (S2) continues for a predetermined number of times (C), it is the same in each cycle. 6. The bit error rate measuring apparatus according to claim 5, wherein the internal gate signal is generated by the internal gate signal generation means.   Represents the burst length and period of the signal under test, and establishes synchronization between the signal under test and the reference pattern from the rising edge of the input burst gate signal that is input with a certain time advance with respect to the signal under test A first time (T1) until it is detected and the end of the error rate measurement period detected by the end detection means, and the first time elapses from the fall of the input burst gate signal. A third time (T1-T2) obtained by subtracting the second time from the first time is calculated from the second time (T2) until the time when the input burst gate signal is input. 7. A bit error rate measuring device according to claim 1, further comprising: a phase adjusting unit (32) for outputting a signal delayed by a time of (2) as the internal gate signal. . A burst test signal generator (4) for generating a burst test signal;
The bit error rate measuring device (5) according to any one of claims 1 to 7, further comprising: a signal under test output from a measurement object (3) that has received the burst test signal. Device testing system.

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