JP4946210B2 - Solid-state imaging device and imaging apparatus using the same - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  In recent years, imaging devices such as video cameras and electronic still cameras have been widely used. These cameras use a CCD solid-state image sensor, or an XY address solid-state image sensor such as an amplification type or a CMOS type in which a pixel amplifier is arranged in each pixel. In such a solid-state imaging device, a plurality of pixels are arranged in a matrix, and photoelectric conversion is performed at each pixel to generate a signal charge. A generated signal charge or an electrical signal corresponding to the signal charge is output from a scanning circuit under the instruction of a control unit such as a timing generator, and solid-state imaging is performed via a CCD or a signal line according to the driving signal. Output from the device to the outside.

  In such a solid-state imaging device, a vertical scanning circuit and a horizontal scanning circuit are mounted to sequentially read out pixel outputs. The vertical scanning circuit may be configured to enable random row selection using a decoder circuit using a memory or the like, but is generally configured using a vertical shift register. This is because when the vertical shift register is used, the circuit configuration is simplified and the cost can be reduced as compared with the case where a decoder circuit using a memory or the like is used.

  The vertical shift register used in the conventional solid-state imaging device is generally composed of a plurality of unit circuits connected in cascade, and a driving clock signal (for example, two-phase) supplied to each unit circuit. The clock signal) is always supplied in common to all unit circuits. That is, the unit circuits in all stages are always driven by the same drive clock signal. The unit circuit at each stage transmits a signal corresponding to an input signal to the unit circuit as an output signal from the unit circuit by a shift operation according to the drive clock signal. As this unit circuit, for example, a D-type flip-flop is used.

  By the way, in such a solid-state imaging device, a solid-state imaging device that performs a rolling electronic shutter as an electronic shutter operation is known (for example, Patent Document 1 below). The rolling electronic shutter is one of the characteristic driving methods in the solid-state imaging device of the XY address system. When the pixel rows are sequentially selected by the vertical shift register, as a start pulse of the vertical shift register, First, a first pulse (a row selection pulse for reset pulse) is applied, and a second pulse (a row selection pulse for a readout pulse) is applied with a delay of a desired electronic shutter period (exposure period) with respect to the first pulse. . When a rolling electronic shutter sequentially scans a reset pulse and a readout pulse applied to a pixel row for each row, a time interval between the reset pulse and a subsequent readout pulse is set to a time interval according to a desired exposure period. It is a technique to do.

  In addition, in a solid-state imaging device, it may be necessary to capture an image at a high frame rate for an electronic viewfinder or high-speed continuous shooting. In such a case, thinning-out readout is required without reading out signals of all pixels from the solid-state imaging device.

Patent Document 2 below discloses a solid-state imaging device that can perform thinning readout. In the solid-state imaging device disclosed in Patent Document 2, the vertical scanning circuit uses a vertical shift register that sequentially selects each row group including a plurality of rows and a selection signal from among the row groups selected by the vertical shift register. Accordingly, a selection circuit that arbitrarily selects a desired row and outputs an image signal is configured.
JP 2005-269098 A JP 2000-4406 A

  However, the solid-state imaging device disclosed in Patent Document 1 can perform a rolling electronic shutter, but cannot perform thinning readout. On the other hand, the solid-state imaging device disclosed in Patent Document 2 can perform thinning readout, but cannot perform a rolling electronic shutter.

  Therefore, as a result of research, the present inventor has conducted both selection of the row of the reset pulse and selection of the row of the readout pulse as one vertical shift register (a unit circuit in all stages is always driven by the same drive clock signal). The first pulse (reset pulse row selection pulse) is given first as a start pulse of the vertical shift register, and the first pulse is delayed by a desired electronic shutter period (exposure period). By providing a second pulse (a row selection pulse for a read pulse), a driving clock for the vertical shift register is realized so that a vertical shift pulse is shifted by a plurality of stages in each horizontal blanking period while realizing a rolling electronic shutter. Give a signal multiple times (for example, skipping two rows and reading every three rows, By providing) a drive clock signal of three times the vertical shift register in the flat blanking period, that it is possible to perform the thinning read, found. This method will be described later as a comparative example.

  By the way, in the solid-state imaging device, a plurality of optical black pixels (OB pixels) for generating a black level signal in addition to an effective pixel for photoelectrically converting incident light to generate a signal corresponding to the incident light are effective pixel regions. It is provided in the vicinity. Then, by using the signal of the OB pixel, signal processing such as so-called black level clamping processing is performed to improve the image quality.

  However, according to the technique found by the present inventor described above, the row of OB pixels is handled in exactly the same way as the row of effective pixels, so that not only the rows of effective pixels are thinned but also the rows of OB pixels. It has also been found that the number of OB pixels to be read is reduced. As a result, with the above-described method, a correct black reference level cannot be obtained with high accuracy, and the image quality deteriorates.

  The present invention has been made in view of such circumstances, and can perform thinning readout while performing a rolling electronic shutter with a simple configuration, and can read out rows of optical black pixels without thinning out. It is an object of the present invention to provide an imaging apparatus capable of suppressing deterioration in image quality and an electronic camera using the same.

In order to solve the above-described problem, the solid-state imaging device according to the first aspect of the present invention selects a plurality of pixels arranged two-dimensionally and a row of the plurality of pixels, and each pixel in the selected row. A vertical scanning circuit for outputting a reset pulse for an electronic shutter operation or a reading pulse for a signal reading operation, and a horizontal scanning circuit for outputting a pixel column selection pulse for selecting a column of the plurality of pixels. , With. The plurality of pixels include an optical black pixel that generates a black level signal in addition to an effective pixel that photoelectrically converts incident light to generate a signal corresponding to the incident light. The vertical scanning circuit generates a vertical shift pulse for selecting a row of the plurality of pixels and outputs the vertical shift register, and the reset pulse or each pixel in the selected row based on the vertical shift pulse. A vertical drive circuit for outputting the readout pulse. The vertical shift register includes a plurality of stages of unit circuits that are provided corresponding to the plurality of pixel rows and connected in cascade. The vertical shift register has a first input unit to which a first drive clock signal supplied to each unit circuit corresponding to each row of the optical black pixels in the plurality of unit circuits is input. And a second drive clock signal supplied to each unit circuit corresponding to each row including the effective pixel in the unit circuits of the plurality of stages , and electrically from the first input unit. And an independent second input unit .

An imaging device according to a second aspect of the present invention includes the solid-state imaging device according to the first aspect and a control unit. Wherein, as the vertical shift pulses, as a second pulse following the first pulse and the first pulse that precedes is output, it supplies the start pulse to the vertical shift register. The controller drives the vertical drive so that the vertical drive circuit outputs the reset pulse based on the first pulse and the vertical drive circuit outputs the read pulse based on the second pulse. Control the circuit. In the thinning-out readout mode, the control unit performs the first shift so that the vertical shift pulse is shifted by one stage in each horizontal blanking period in the unit circuits of the respective stages corresponding to the rows of the optical black pixels. The driving clock signal is supplied to the first input section, and the vertical shift pulse is shifted by a plurality of stages in each horizontal blanking period in the unit circuit of each stage corresponding to the row including the effective pixel. In addition, the second drive clock signal is supplied to the second input section.

  The imaging device according to a third aspect of the present invention is the imaging device according to the second aspect, wherein the control unit generates the first drive clock signal based on the second drive clock signal and the gate control signal. The gate circuit is mounted on the solid-state image sensor or provided outside the solid-state image sensor.

  According to the present invention, it is possible to perform thinning readout while performing a rolling electronic shutter with a simple configuration, and furthermore, it is possible to read out optical black pixel rows without thinning out and to suppress deterioration in image quality. An imaging device and an imaging device using the imaging device can be provided.

  Hereinafter, a solid-state imaging device and an imaging device using the same according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to the first embodiment of the present invention. A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 2a for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 3 is arranged.

  The solid-state imaging device 3 is driven by a command from the imaging control unit 4 and outputs an image signal. In the electronic viewfinder mode or in the high-speed continuous shooting mode, the imaging control unit 4 controls the solid-state imaging device 3 so as to perform thinning readout while performing the rolling electronic shutter. This operation will be described in detail later. Further, at the time of normal main photographing or the like, the imaging control unit 4 controls the solid-state imaging device 3 so as to obtain an image signal of all pixels not depending on thinning while performing a rolling electronic shutter, for example. Each image signal is subjected to signal processing such as black level clamping processing by the signal processing unit 5, is A / D converted by the A / D conversion unit 6, and is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected to a lens control unit 2a, an imaging control unit 4, a microprocessor 9, a monitor display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. The microprocessor 9 is connected to an operation unit 9a such as a release button. A recording medium 11a is detachably attached to the recording unit 11 described above.

  When an electronic viewfinder mode, high-speed continuous shooting, or the like is instructed by the operation of the operation unit 9a, the microprocessor 9 in the electronic camera 1 drives the imaging control unit 4 accordingly. The imaging control unit 4 controls the solid-state imaging device 3 so as to perform thinning readout while performing a rolling electronic shutter. At this time, the focus and the aperture are appropriately adjusted by the lens control unit 2a. The thinned image signal obtained from the solid-state imaging device 3 is stored in the memory 7. The microprocessor 9 causes the monitor display unit 10 to display an image of the thinned image signal in the electronic viewfinder mode. In the case of high-speed continuous shooting or normal main shooting, the microprocessor 9 stores the thinned image signal or the non-thinned image signal in the memory 7 and then based on a command from the operation unit 9a. The image processing unit 13 or the image compression unit 12 performs a desired process as necessary, and outputs the processed signal to the recording unit 11 and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 3 in FIG. FIG. 2 also shows the imaging control unit 4. FIG. 3 is a circuit diagram showing the pixel 11 in FIG. FIG. 4 is a circuit diagram showing the vertical drive circuit 16 in FIG. FIG. 5 is a circuit diagram showing the read circuit 19 in FIG. FIG. 6 is a circuit diagram showing the vertical shift register 14 in FIG.

  The solid-state image sensor 3 is configured as a CMOS solid-state image sensor. Although not shown in the drawing, the imaging control unit 4 is configured by a timing generator or the like, and supplies drive pulses and the like to each unit of the solid-state imaging device 3 as described later.

  As shown in FIG. 2, the solid-state imaging device 3 includes pixels 11 arranged in a two-dimensional matrix in n rows and m columns, a vertical shift register 14 and a vertical drive circuit 16 constituting a vertical scanning circuit, and a horizontal A horizontal shift register 18 constituting a scanning circuit and a readout circuit 19 are provided. Most of the pixels 11 are effective pixels that photoelectrically convert incident light to generate a signal corresponding to the incident light, but the remaining pixels 11 are optical black pixels (OB pixels) that generate a black level signal. It has become. In the present embodiment, the pixels 11 from the first row to the fourth row are all OB pixels, and the remaining pixels 11 are all effective pixels. However, the arrangement of the OB pixels is not limited to this example. For example, the first predetermined number of rows from the first row and the last predetermined number of rows up to the n-th row are defined as OB pixel regions, and the remaining rows sandwiched between these OB pixel regions are effective pixel regions. It is good.

  In this embodiment, each pixel 11 includes a selection transistor Ta, a source follower amplification transistor Tb, a reset transistor Tc, a transfer transistor Td, and a photodiode PD, as shown in FIG. . These transistors Ta to Td are assumed to be N channel MOS transistors. Therefore, the transistors Ta, Tc, and Td are turned on when their gates become H level. In FIG. 3, Vcc is a power source.

  In this embodiment, each pixel 11 has the circuit configuration shown in FIG. 3 regardless of whether the pixel is an effective pixel or an OB pixel, but the photodiode PD is not shielded from light by the effective pixel. On the other hand, in the OB pixel, the photodiode PD is shielded by the light shielding film.

  As shown in FIGS. 2 and 3, the gates of the selection transistors Ta of the pixels 11 are commonly connected to the selection line 20 for each row. The gate of the reset transistor Tc of the pixel 11 is commonly connected to the reset line 21 for each row. The gates of the transfer transistors Td of the pixels 11 are commonly connected to the transfer line 22 for each row. The sources of the amplification transistors Tb of the pixels 11 are commonly connected to the vertical signal lines 32-1 to 32-m for each column. As shown in FIG. 2, source follower read constant current sources 33-1 to 33-m are connected to the vertical signal lines 32-1 to 32-m. 3 indicates the pixel 11 in the n-th row and the first column.

  Selection pulses φsel1 to φseln as readout pulses are transferred to the selection lines 20 of each row of the pixels 11, reset pulses φrst1 to φrstn are transferred to the reset lines 21 of each row of the pixels 11, and transferred to the transfer lines 22 of each row of the pixels 11. Pulses φtx 1 to φtxn are supplied from the vertical drive circuit 16. Each pixel 11 in the row to which the reset driving pulse is supplied starts signal accumulation immediately after that, and starts an electronic shutter operation. Each pixel 11 in the row to which the driving pulse for reading is supplied performs a signal reading operation to the corresponding vertical signal line 32-1 to 32-m.

  Specifically, the reset driving pulse is a pulse that is sent to φtx to completely transfer the PD charge, and then the φrst pulse is set to H level to perform a reset operation. At this time, φsel remains at the L level. Thereby, the charge reset operation in the pixel PD is performed without performing the readout operation.

  On the other hand, the read pulse is a signal for reading out pixel information by setting the φsel pulse to the H level and connecting the vertical signal line to the pixel and then sending a pulse to φtx to completely transfer the charge of the PD. Thereafter, φsel is returned to the L level, the φrst pulse is set to the H level, and the pixel is reset.

  As described above, φtx and φrst are common, and the reset pulse and the read pulse can be switched only by the difference between whether or not φsel is inserted.

  The vertical shift register 14 receives a vertical start pulse φSTV, two-phase clock signals φV1 and φV2 as a first drive clock signal, and a two-phase clock signal φV3 as a second drive clock signal from the imaging control unit 4. , ΦV4 are received, and according to these, vertical shift pulses φSV1 to φSVn are output for each row of the pixels 11 as a signal for defining a row selection period and timing by H level. The configuration of the vertical shift register 14 will be described in detail later.

  As shown in FIG. 4, the vertical driving circuit 16 includes unit circuits 60 provided for each row of the pixels 11. Each unit circuit 60 includes an AND gate 61, a level shift circuit 62, a NAND gate 63, and an AND gate 64. Each unit circuit 60 includes two selection pulses φSEL-odd and φSEL-even that are the sources of the selection pulses φsel1 to φseln, a reset pulse φRST that is a source of the reset pulses φrst1 to φrstn, and a transfer pulse φtx1 A transfer pulse φTX that is the basis of φtxn is received from the imaging control unit 4 as a drive pulse.

  Each unit circuit 60 takes the AND of the vertical shift pulse and transfer pulse φTX in the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register 14 by the AND gate 61, and level-shifts the output level thereof. By changing the level to a required level by the circuit 62, a transfer pulse of the row (for example, φtx2 if the row is the second row) is generated and supplied to the transfer line 22 of the row. Each unit circuit 60 takes the NAND of the vertical shift pulse and reset pulse φRST of the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register 14 by the NAND gate 63, thereby resetting the reset pulse of the row. (For example, if the row is the second row, φrst2) is created, and this is supplied to the reset line 21 of the row.

  In the present embodiment, as shown in FIG. 4, the selection pulse φSEL-odd is input to the AND gate 64 of the odd-numbered unit circuit 60, while the selection pulse φSEL-even is input to the AND gate 64 of the even-numbered unit circuit 60. Is entered. Thus, in the present embodiment, the selection pulses are selected from the selection pulse φSEL-odd for controlling the selection transistor Ta of the odd-numbered row pixels 11 and the selection pulse φSEL-even for controlling the selection transistor Ta of the even-numbered row pixels 11. Divided into two systems. Each unit circuit 60 uses an AND gate 64 to select a vertical shift pulse and a selection pulse in the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register 14 (if the row is an odd row, the selection pulse φSEL-odd, If the row is an even row, an AND operation with the selection pulse φSEL-even) is taken to create a selection pulse for that row (for example, φsel2 if the row is the second row), Supply to the selection line 20.

  The horizontal shift register 18 receives the horizontal start pulse φSTH and the two-phase drive clock signals φH1 and φH2 from the imaging control unit 4, and in accordance with these, as a signal defining the period and timing for selecting a column, Horizontal shift pulses φSH1 to φSHm are output. Although not shown in the drawing, the horizontal shift register 18 is composed of a plurality of stages (m stages in the present embodiment) connected in cascade as in the vertical shift register 14. Unlike the register 14, the unit circuits of all stages are always driven by the same two-phase clock signals φH1 and φH2. Thus, unlike the horizontal shift register 14, the horizontal shift register 18 uses a normal shift register.

The readout circuit 19 is the same as the readout circuit employed in, for example, the solid-state imaging device disclosed in FIG. 5 of JP-A-8-295991. Briefly, as shown in FIG. 5, the readout circuit 19 includes a Sig signal horizontal readout line 38, a Dark signal horizontal readout line 39, output amplifiers 38a and 39a, a Sig signal readout pulse line 41a, and a Dark signal readout pulse. line 42a, MOS transistors _T HS1 horizontal read _{selection, T HS2, T HS3, T} HD1, T HD2, T HD3, Sig signal transfer MOS transistors _{T S1, T S2, T S3} , Dark signal transfer MOS transistor _{T D1} , T _D2 , T _D3 , Sig signal storage capacitors C _S1 , C _S2 , C _S3 , Dark signal storage capacitors C _D1 , C _D2 , C _D3 , and the like. C _HS and C _HD indicate the parasitic capacitances of the Sig signal horizontal readout line 38 and the Dark signal horizontal readout line 39, respectively. The readout circuit 19 operates according to drive pulses φRH, φTS, and φTD supplied from the imaging control unit 4.

  Here, the configuration of the vertical shift register 14 will be described in detail with reference to FIG. In the present embodiment, the vertical shift register 14 includes n-stage unit circuits 70 connected in cascade. Specifically, the output unit f of each unit circuit 70 in the previous stage is connected to the input unit a of each unit circuit 70 in the subsequent stage, so that the n unit circuits 70 are cascaded. The vertical start pulse φSTV is input to the input part a of the unit circuit 70 in the first stage. The outputs of the unit circuits 70 in each stage (output signals output from the output unit f) are vertical shift pulses φSV1 to φSVn for each row of the pixels 11. For example, the output of the unit circuit 70 in the second stage is the vertical shift pulse φSV2 in the second row of the pixels 11.

  The unit circuit 70 in each stage transmits a signal corresponding to the input signal input to the unit circuit 70 as an output signal from the unit circuit 70 by a shift operation according to the drive clock signal input to the unit circuit 70. . In the present embodiment, a dynamic or static D flip-flop is used as the unit circuit 70 in each stage. However, the unit circuit 70 is not limited to the D-type flip-flop, and the unit circuits 70 in all stages do not necessarily have the same configuration. In the present embodiment, the unit circuit 70 in each stage is driven by a two-phase clock signal as a drive clock signal, but the drive clock signal does not necessarily have two phases.

  In the present embodiment, as shown in FIG. 6, the unit circuit 70 in each stage includes an input unit a to which the input signal is input, an output unit f to which the output signal is output, and driving of one phase. A clock input section b to which a clock signal is input, a clock input section c to which the driving clock signal of the other phase is input, a clock input section d to which an inverted signal of the driving clock signal of the one phase is input, A clock input unit e to which an inverted signal of the driving clock signal of the other phase is input.

  In the present embodiment, the vertical shift register 14 includes unit circuits 70 (first to fourth stages) corresponding to OB pixel rows (first to fourth lines) in the n-stage unit circuits 70, respectively. In FIG. 6, a group of these unit circuits 70 is indicated by a symbol BV1), and the first drive clock signals φV1 and φV2 supplied to the unit circuit 70 and the n-stage unit circuits 70 Of these, unit circuits 70 (each unit circuit 70 in the fifth to nth stages) corresponding to each row of effective pixels (the fifth to nth rows). In FIG. The second drive clock signals φV3 and φV4 supplied to (BV2) are supplied independently of each other.

  Specifically, in the present embodiment, the clock input portion b of each unit circuit 70 of the group BV1 is connected in common independently of the group BV2, and the clock of one phase of the first drive clock signal. Signal φV1 is input. The clock input section c of each unit circuit 70 of the group BV1 is connected in common independently of the group BV2, and receives the clock signal φV2 of the other phase of the first drive clock signals. The clock input portions d of the unit circuits 70 of the group BV1 are connected in common independently of the group BV2, and an inverted signal of the clock signal φV1 is input through the not gate 91. The clock input units e of the unit circuits 70 of the group BV1 are connected in common independently of the group BV2, and an inverted signal of the clock signal φV2 is input via the knot gate 92.

  Similarly, the clock input part b of each unit circuit 70 of the group BV2 is commonly connected independently of the group BV1, and the clock signal φV3 of one phase of the second drive clock signal is input. The clock input section c of each unit circuit 70 of the group BV2 is commonly connected independently from the group BV1, and the clock signal φV4 of the other phase of the second drive clock signals is input. The clock input section d of each unit circuit 70 of the group BV2 is connected in common independently of the group BV1 and an inverted signal of the clock signal φV3 is input through the not gate 93. The clock input units e of the unit circuits 70 of the group BV2 are connected in common independently of the group BV1, and an inverted signal of the clock signal φV4 is input via the not gate 94.

  Next, an operation example of the solid-state imaging device according to the present embodiment will be described focusing on the operation of the vertical shift register 14.

  FIG. 7 is a timing chart showing each signal input to the vertical shift register 14 at the time of thinning readout at the time of the rolling electronic shutter. FIG. 8 is a timing chart showing main signals input to and output from the vertical shift register 14 and the vertical drive circuit 16 in the state after the first pulse φSTV-1 of the vertical start pulse φSTV in FIG. FIG. 9 is a timing chart showing main signals input to and output from the vertical shift register 14 and the vertical drive circuit 16 in the state after the second pulse φSTV-2 of the vertical start pulse φSTV in FIG. 8 and 9 show signals up to the 13th row.

  7 to 9, the vertical start pulse φSTV is determined at the falling edge of the drive clock signal φV1, and the vertical shift pulses φSV1 to φSVn are determined based on the falling edge of the corresponding drive clock signal φV2 or the corresponding drive clock signal φV4. It is determined at the rising edge of the first pulse in the horizontal period.

  When performing the rolling electronic shutter, the imaging control unit 4 gives the preceding first pulse (row selection pulse for reset pulse) φSTV-1 as the vertical start pulse φSTV of the vertical shift register 14 as shown in FIG. Then, the subsequent second pulse (row selection pulse for reading pulse) φSTV-2 is given with a delay of time T100 having the same length as the desired electronic shutter period (exposure period) with respect to the first pulse φSTV-1.

  In order to perform the rolling electronic shutter, a reset operation is performed for the first pulse φSTV-1, and a selection operation is performed for the second pulse φSTV-2. In this embodiment, for this purpose, as described above, the selection pulse is divided into two systems of the selection pulse φSEL-odd and the selection pulse φSEL-even, and the timing for applying the vertical start pulse φSTV is controlled as described below. Yes.

  As shown in FIGS. 8 and 9, pulses are alternately input to φSEL-odd and φSEL-even. Here, as shown in FIG. 8, the first pulse φSTV-1 is input as the vertical start pulse φSTV at the timing when φSV1 and φSEL-even overlap. In this case, φsel of each row remains low, and only the reset operation is performed on the row selected by the vertical shift pulse by the first pulse φSTV-1 without performing the read operation from the pixel 11. On the other hand, as shown in FIG. 9, the second pulse φSTV-2 is input as the vertical start pulse φSTV at the timing when φSV1 and φSEL-odd overlap. In this case, the read operation is performed on the row selected by the vertical shift pulse by the second pulse φφSTV-2.

  By changing the interval T100 between the first pulse φSTV-1 and the second pulse φSTV-2, it is possible to adjust the accumulation time of the electronic shutter (which has the same length as the interval T100). In this embodiment, the control of the reset operation and the read operation is switched according to the even / odd timing of the vertical start pulse φSTV. Therefore, the interval T100 between the first pulse φSTV-1 and the second pulse φSTV-2. Is set to an odd number of lines.

  Then, in order to perform thinning readout while performing such a rolling electronic shutter, the imaging control unit 4 in the thinning readout mode, each unit circuit 70 of the group BV1 (four stages from the first stage corresponding to each row of OB pixels). The first drive clock signals φV1 and φV2 are supplied to the unit circuit 70 of the eye so that the vertical shift pulse is shifted by one stage in each horizontal blanking period in each unit circuit 70 of the group BV1. Further, the imaging control unit 4 compares each unit circuit 70 of the group BV2 (unit circuit 70 of the fifth to nth stages corresponding to each row of effective pixels) in each unit circuit 70 of the group BV2. Second drive clock signals φV3 and φV4 are supplied so that the vertical shift pulse is shifted by a plurality of stages in the horizontal blanking period.

  Specifically, in this embodiment, as shown in FIGS. 7 to 9, the imaging control unit 4 generates the clock signals φV1 and φV2 once (one pulse) corresponding to one horizontal blanking period. And the clock signals φV3 and V4 are supplied three times (three pulses). The reason why the clock signals φV3 and V4 are supplied three times is because FIGS. 7 to 9 show an example of thinning-out reading in which two rows are skipped and reading is performed every three rows. However, thinning readout is not limited to every three rows.

  As a result, effective pixels are read every three rows, while OB pixels are read row by row. As can be understood from FIGS. 7 to 9, the accumulation time is maintained at a constant length determined by the time T <b> 100 regardless of whether the row is a valid pixel row or an OB pixel row.

  As described above, according to the present embodiment, the vertical scanning circuit is configured by using the vertical shift register 14, thereby simplifying the circuit configuration and reducing the cost, and performing thinning readout while performing the rolling electronic shutter. In addition, it is possible to read out rows of OB pixels without thinning out and suppress deterioration in image quality.

  When all pixels are read out during the rolling electronic shutter, the same signals as the clock signals φV1 and φV2 in FIGS. 7 to 9 may be given as the clock signals φV3 and φV4.

  Note that φtx and φrst are driven in the same way as an image sensor using a general 4-TrCMOS pixel.

  Here, the comparative example compared with this Embodiment is demonstrated. This comparative example has been devised as a result of research by the present inventor. In this embodiment, the vertical shift register 14 is driven by the same drive clock signal so that the unit circuits 70 of all stages are always driven. It is transformed into Specifically, in this comparative example, for example, in FIG. 6, the lines connected to the clock signals φV1 and φV2 and the knot gates 91 and 92 are removed, and the clock input portions b are connected to each other for the unit circuits 70 in all stages. The clock input units c are connected in common, the clock input units d are connected in common, the clock input units e are connected in common, and the unit circuits 70 in all stages are connected to the drive clock signal φV3. Drive only by φV4.

  In this comparative example, when thinning readout is performed at the time of the rolling electronic shutter, the same signals as those shown in FIGS. 7 to 9 (except for the clock signals φV1 and φV2) may be supplied from the imaging control unit 4. This situation is the same as the clock signals φV3 and φV4 shown in FIGS. 7 to 9 (corresponding to one horizontal blanking period) as the clock signals φV1 and φV2 in a state where the present embodiment is not modified as in the comparative example. This is equivalent to the state in which the three-pulse signal) is supplied.

  In this comparative example, in this case, reading is performed every three rows regardless of whether the row is an effective pixel row or an OB pixel. Therefore, the rows of effective pixels are read out every three rows and thinned out. However, not only the rows of effective pixels but also rows of OB pixels are read out every three rows and thinned out. Therefore, in this comparative example, the number of OB pixels to be read is reduced. For this reason, the correct black reference level cannot be obtained with high accuracy, and the image quality is degraded.

  On the other hand, in the present embodiment, as described above, the vertical shift register 14 includes the first drive clock signals φV1 and φV2 for driving the unit circuit 70 of the group BV1 corresponding to the OB pixel region, and the effective pixel region. The second drive clock signals φV3 and φV4 for driving the unit circuits 70 of the group BV2 corresponding to are able to be supplied independently of each other. Therefore, according to the present embodiment, the first drive clock signals φV1 and φV2 and the second drive clock signals φV3 and φV4 can be supplied as shown in FIGS. Effective pixels are read out every three rows, while OB pixels can be read out row by row. Therefore, according to the present embodiment, a correct black reference level can be obtained with high accuracy, and image quality does not deteriorate.

In this embodiment, as described above, the control of the reset operation and the read operation is switched according to the even / odd timing of applying the vertical start pulse φSTV. Therefore, when thinning readout is performed during the rolling electronic shutter, every odd row Read to. For example, in the case of a Bayer array that is widely used as an on-chip color filter array of a solid-state imaging device, readout is performed every odd number of rows, so that R / Gr rows and Gb / B rows are alternately read. However, color information can also be obtained appropriately. Note that the switching between the reset operation and the control of the read operation is not limited to the method described above.

  [Second Embodiment]

  FIG. 10 is a circuit diagram showing a main part of the solid-state imaging device 3 of the electronic camera as the imaging device according to the second embodiment of the present invention. FIG. 11 is a timing chart showing each signal input to the vertical shift register 14 and the like at the time of thinning readout at the time of the rolling electronic shutter in this embodiment, and corresponds to FIG. 10 and 11, the same or corresponding elements as those in FIGS. 2 and 7 are denoted by the same reference numerals, and redundant description thereof is omitted.

  This embodiment differs from the first embodiment in that a gate circuit 90 is added and mounted on the solid-state imaging device 3, and the imaging control unit 4 replaces the first drive clock signals φV1 and φV2. The only point is that the gate control signal φg is supplied to the solid-state imaging device 3.

  The gate circuit 90 generates first drive clock signals φV1 and φV2 based on the second drive clock signals φV3 and φV4 and the gate control signal φg, and supplies both signals φV1 and φV2 to the vertical shift register 14. In the present embodiment, gate circuit 90 takes AND of clock signal φV3 and gate control signal φg to generate clock signal φV1, and AND of clock signal φV4 and gate control signal φg. An AND gate 92 for generating the clock signal φV2.

  As shown in FIG. 11, the gate control signal φg selectively selects the first pulse of the plurality of pulses corresponding to the horizontal blanking period of each of the clock signals φV3 and φV4.

  The gate circuit 90 constitutes a control unit that controls the vertical shift register 14 and the like together with the imaging control unit 4. It goes without saying that such a gate circuit 90 may be provided on the imaging control unit 4 side and provided outside the solid-state imaging device 3 instead of being mounted on the solid-state imaging device 3.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, in each of the above embodiments, the vertical shift register 14 is a two-phase drive, but a one-phase drive may be used.

  In each of the embodiments described above, the OB pixels are arranged in the first scanning side row of the vertical shift register. However, for example, the OB pixels are arranged in an L shape in both the row and the column. You may do it. In this case, since the OB pixels on the column side are irrelevant to the rolling electronic shutter operation, the horizontal shift register remains the same as before. Only the vertical shift register needs to be divided into groups as in each embodiment.

  Alternatively, the OB may be arranged on all four sides of the pixel. In this case, when the vertical shift register is divided into three groups of an OB pixel area on the first scanning side, an area including effective pixels, and an OB pixel area on the last scanning side, and thinning readout is performed. Even so, the OB pixel may be read without being thinned out.

  Further, as the OB pixel, the case where the photodiode PD is shielded by the light shielding film has been described. However, for example, a pixel structure in which the PD itself is not formed may be used.

  In addition, when thinning out also in the horizontal direction and reading, the drive clock signals φH1 and φH2 supplied from the imaging control unit 4 to the horizontal shift register 18 are pulsed one by one in a non-thinned column, A plurality of pulses may be input.

1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 3 is a circuit diagram showing a pixel in FIG. 2. FIG. 3 is a circuit diagram showing a vertical drive circuit in FIG. 2. FIG. 3 is a circuit diagram showing a readout circuit in FIG. 2. FIG. 3 is a circuit diagram showing a vertical shift register in FIG. 2. 4 is a timing chart showing each signal input to the vertical shift register at the time of thinning readout at the time of a rolling electronic shutter in the first embodiment of the present invention. FIG. 8 is a timing chart showing main signals input to and output from the vertical shift register and the vertical drive circuit in a state after the first pulse φSTV-1 of the vertical start pulse φSTV in FIG. 7. 8 is a timing chart showing main signals input to and output from the vertical shift register and the vertical drive circuit in a state after the second pulse φSTV-2 of the vertical start pulse φSTV in FIG. 7. It is a circuit diagram which shows the principal part of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention. 9 is a timing chart showing signals input to a vertical shift register or the like at the time of thinning readout at the time of a rolling electronic shutter in the second embodiment of the present invention.

Explanation of symbols

1 Electronic Camera 4 Imaging Control Unit 11 Pixel 14 Vertical Shift Register 16 Vertical Drive Circuit 18 Horizontal Shift Register 70 Unit Circuit φV1, φV2 First Drive Clock Signal φV3, φV4 Second Drive Clock Signal

Claims (3)

A plurality of pixels arranged two-dimensionally;
A vertical scanning circuit that outputs a reset pulse for an electronic shutter operation or a readout pulse for a signal readout operation to each pixel of the selected row while selecting a row of the plurality of pixels;
A horizontal scanning circuit that outputs a pixel column selection pulse for selecting the plurality of pixel columns;
With
The plurality of pixels include an optical black pixel that generates a black level signal in addition to an effective pixel that photoelectrically converts incident light to generate a signal corresponding to the incident light,
The vertical scanning circuit generates a vertical shift pulse for selecting a row of the plurality of pixels and outputs the vertical shift register, and the reset pulse or each pixel in the selected row based on the vertical shift pulse. A vertical drive circuit for outputting the readout pulse,
The vertical shift register includes a plurality of stages of unit circuits that are provided corresponding to the plurality of pixel rows and connected in cascade,
The vertical shift register has a first input unit to which a first drive clock signal supplied to each unit circuit corresponding to each row of the optical black pixels in the plurality of unit circuits is input. And a second drive clock signal supplied to each unit circuit corresponding to each row including the effective pixel in the unit circuits of the plurality of stages, and electrically from the first input unit. An independent second input,
A solid-state imaging device. An imaging apparatus comprising the solid-state imaging device according to claim 1 and a control unit,
Wherein, as the vertical shift pulses, as a second pulse following the first pulse and the first pulse that precedes is output, supplies the start pulse to the vertical shift register,
The controller drives the vertical drive so that the vertical drive circuit outputs the reset pulse based on the first pulse and the vertical drive circuit outputs the read pulse based on the second pulse. Control the circuit,
In the thinning-out readout mode, the control unit performs the first shift so that the vertical shift pulse is shifted by one stage in each horizontal blanking period in the unit circuits of the respective stages corresponding to the rows of the optical black pixels. The driving clock signal is supplied to the first input section, and the vertical shift pulse is shifted by a plurality of stages in each horizontal blanking period in the unit circuit of each stage corresponding to the row including the effective pixel. And supplying the second drive clock signal to the second input unit.
An imaging apparatus characterized by that. The control unit includes a gate circuit that generates the first drive clock signal based on the second drive clock signal and a gate control signal;
The image pickup apparatus according to claim 2, wherein the gate circuit is mounted on the solid-state image sensor or provided outside the solid-state image sensor.

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