JP4941125B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to arithmetic processing.

For example, in a semiconductor test apparatus that tests a liquid crystal driver IC as a test object (hereinafter referred to as a DUT), as described in Patent Document 1, an output voltage of each pin of the DUT is converted into a digital signal by an A / D converter. The output data stored in the memory is temporarily stored in the memory, and the output data stored in the memory is taken into the digital signal processing unit. The magnitude of the absolute value of the output voltage of each pin and the magnitude of the output voltage variation between the pins Etc. are calculated to determine whether the DUT is acceptable or not.
JP 2001-13218 A

  By the way, in recent semiconductor test apparatuses, a plurality of DUTs can be simultaneously tested in order to increase the test efficiency per unit time of the test apparatus and reduce the test cost ratio as the cost of the DUT.

  FIG. 3 is a block diagram showing an example of such a conventional semiconductor test apparatus. In FIG. 3, a plurality of n DUTs 10 are connected to a plurality of n measurement modules 30 each composed of a plurality of m-channel measurement cards 20.

  Each measurement card 20 includes an A / D converter 21, a capture memory 22, a DSP (Digital Signal Processor) 23, a local memory 24, and the like. Specifically, the output terminal of the A / D converter 21 is connected to the input terminal of the capture memory 22. The capture memory 22, DSP 23, and local memory 24 are connected to each other via an internal bus 25.

  Each measurement module 30 is provided with a DMA controller 31 common to each measurement card 20.

  Each measurement module 30 is connected to a tester controller (hereinafter referred to as TSC) 50 via a bus 40.

  The TSC 50 has a PC (personal computer) function, and the CPU 51 and the RAM 52 are connected via an internal bus 53. The RAM 52 stores a predetermined test program for executing the test of the DUT 10, measurement data of each test item, a pass / fail result of the test, and the like. Henceforth, TSC50 is described also as PC50.

  The calculation processing for the previous measurement data is only performed by the DSP 23 mounted on each measurement card 20, but the calculation by the PC 50 is accompanied by the improvement of the processing speed of the CPU 51, the lower price of the RAM 52, and the increase in capacity. In some cases, the processing can be shortened compared to the processing time of the DSP 23. Still, the arithmetic processing by the DSP 23 has an advantage over the PC 50 in the area of a small number of data and a multi-parallel DUT. Therefore, the semiconductor test apparatus is configured such that the calculation can be performed by either the PC 50 or the DSP 23, and the user can specify each test by the test program.

  The operation of FIG. 3 will be described. The analog output signal of each pin of the DUT 10 is converted into a digital signal by the A / D converter 21 and stored in the capture memory 22. The output data of the DUT 10 stored in the capture memory 22 is read into the DSP 23 or the CPU 51 of the TSC 50 based on an instruction described in a test program according to the model of the DUT 10 output from the TSC 50, and the predetermined data as described above. The arithmetic processing is performed.

  When calculation processing in the DSP 23 is specified by the test program output from the TSC 50, the DSP 23 of each measurement card 20 performs parallel calculation processing as shown in FIG. 4 and stores the calculation result in the local memory 24. Output to. That is, since the A / D converter 21, the capture memory 22, the DSP 23, and the local memory 24 exist for each DUT 10, a series of processes from A / D conversion to calculation by the DSP 23 in each measurement card 20 can be performed in parallel. it can.

  When arithmetic processing in the PC (TSC) 50 is specified by the test program output from the TSC 50, the DMA controller 31 of each measurement module 30 stores the output data of the DUT 10 stored in each capture memory 22 in the RAM 52 of the TSC 50. Store for transfer. The CPU 51 of the TSC 50 sequentially performs predetermined arithmetic processing on the output data of the DUT 10 transferred and stored in the RAM 52 as shown in FIG. That is, since there is only one PC (TSC) 50 in the semiconductor test apparatus, parallel processing can be performed from A / D conversion to data capture into the capture memory 22 in each measurement card 20, but data transfer from the capture memory 22 is possible. And PC calculation becomes sequential processing.

  FIG. 6 is a characteristic comparison diagram of the DSP operation and the PC operation. (A) shows the relationship between the number of operation data per device and the processing time, and (B) shows the number of parallel DUTs and processing in a certain number of data. Shows the relationship of time. Since the processing time for the number of operation data per device is linked to the drive clock, and the CPU 50 is considerably faster than the DSP 23, it can be said that the PC operation is superior to the DSP operation.

  However, as the number of parallel DUTs increases, a DSP operation that can be processed in parallel is more advantageous as an overall processing speed. Depending on the device program, a test including measurement and calculation several hundred to several thousand times is performed for one device, and the number of calculation data also varies greatly from hundreds to tens of thousands of data.

  Therefore, for each DUT test item, the user determines which of the PC and DSP should be used for calculation based on the number of parallel DUTs and the number of operation data, and specifies and describes in a series of test programs. In the case of a test in which these judgments are difficult, the determination is made after actually obtaining calculation time data.

  However, according to the conventional configuration, since the user determines and decides whether to perform the calculation by PC or DSP for each individual test item based on the number of parallel DUTs and the number of calculation data, There is a problem that the optimization process takes a considerable amount of time.

  Further, in the semiconductor test apparatus, for the DUT that fails during execution of the test program, the subsequent measurement is stopped and the test is continued for the passing DUT, so that the number of parallel DUTs changes dynamically. Thus, no matter how much the user optimizes the calculation time in advance, it cannot cope with a change in processing time due to a dynamic change in the number of parallel DUTs.

  The present invention solves such problems, and its purpose is to dynamically switch between PC and DSP as arithmetic processing means according to the test result of the DUT accompanying the progress of the test program, An object of the present invention is to realize a semiconductor test apparatus that can eliminate the need for the user to set the optimization of the calculation time.

In order to solve the above-mentioned problem, the invention described in claim 1
A plurality of measurement modules comprising a measurement card of a plurality of channels provided with a DSP having a calculation processing function for measurement data, and a tester controller having a PC function having a calculation processing function for measurement data and controlling these measurement modules in an integrated manner. A semiconductor test apparatus configured to simultaneously test a plurality of DUTs,
The tester controller is provided with switching selection means for switching and selecting DSP or PC as arithmetic processing means for the measurement data based on the arithmetic processing prediction time corresponding to the test condition at that time.

  According to a second aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the switching selection unit obtains an arithmetic processing predicted time based on the number of parallel DUTs and the number of predicted arithmetic data to be tested at that time. It is characterized by that.

  According to a third aspect of the present invention, in the semiconductor test apparatus according to the first or second aspect, the DUT is an analog LSI including a liquid crystal driver IC.

  According to the present invention, either a PC or a DSP can be dynamically switched as an arithmetic processing unit in accordance with a test result of a DUT accompanying the progress of a test program, and a calculation time optimization setting operation by a user can be eliminated. A semiconductor test apparatus can be realized.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main part of an embodiment of the present invention, and the same reference numerals are given to the parts common to FIG. In FIG. 1, a parallel DUT number confirmation unit 54, a calculation data number confirmation unit 55, a processing time database 56, and a DSP / PC calculation switching unit 57 are connected to an internal bus 53 of a PC (TSC) 50.

  The parallel DUT number confirming unit 54 confirms the number of parallel DUTs 10 to be subjected to the next test item based on the pass / fail result of each test item of the DUT 10 associated with the execution of a predetermined test program.

  The calculation data number confirmation unit 55 confirms the predicted calculation data number obtained by executing the next test item.

  In the processing time database 56, for each test item, the relationship between the number of parallel DUTs 10 to be executed, the calculation processing prediction time by the DSP 23 based on the number of prediction calculation data obtained, and the calculation processing prediction time by the PC 50 is shown in a table. It is stored in the form.

  The DSP / PC computation switching unit 57 searches the processing time database 56 based on the number of parallel DUTs and the number of computation data confirmed by the parallel DUT number confirmation unit 54 and the computation data number confirmation unit 55, so that the DSP 23 that satisfies the condition is retrieved. The calculation processing predicted time by the PC 50 and the calculation processing predicted time by the PC 50 are obtained, and the shorter calculation processing prediction time is designated as the calculation processing means for the next test item.

  As a result, according to the test result of the DUT 10 accompanying the progress of the test program, a means having a short calculation processing prediction time is dynamically selected from the PC 50 and the DSP 23, and the calculation processing of each test item is performed for the test item. Since it is executed by the arithmetic processing means having a high processing speed under the conditions, the semiconductor test apparatus can perform a series of tests on the DUT 10 in the shortest time. As a result, the conventional operation time optimization setting operation by the user becomes unnecessary.

  FIG. 2 is a flowchart showing an example of the flow of switching control of arithmetic processing means in the semiconductor test apparatus configured as shown in FIG. In FIG. 2, the semiconductor test apparatus 50 sequentially executes tests for four DUTs according to the test program as test item 1, test item 2, test item 3,..., Arithmetic processing means for each test item. Are switched and selected by the DSP / PC computation switching unit 57 according to the conditions at that time.

  In test item 1, the number of parallel DUTs is 4 and the number of operation data is “many”, and the DSP / PC operation switching unit 57 selects the DSP as the operation processing means. The measurement data of the four DUTs are taken into the corresponding measurement modules, respectively, and predetermined arithmetic processing is performed in each DSP. As a result of the arithmetic processing, the first, third, and fourth DUTs are determined to be PASS, and the process proceeds to the test item 2. The second DUT is determined to be FAIL, and the tests after the test item 2 are stopped.

  In test item 2, the number of parallel DUTs is 3 and the number of operation data is “many”, and DSP / PC operation switching unit 57 selects the DSP as the operation processing means in the same manner as test item 1. The measurement data of the three DUTs are taken into the corresponding measurement modules, respectively, and predetermined arithmetic processing is performed in each DSP. As a result of the arithmetic processing, the first and third DUTs are determined to be PASS, and the process proceeds to the test of test item 3. The fourth DUT is determined to be FAIL, and the tests after test item 3 are stopped.

  In test item 3, the number of parallel DUTs is 2 and the number of operation data is “small”, and the DSP / PC operation switching unit 57 selects PC as the operation processing means. The measurement data of the two DUTs is taken into the RAM 52 via the DMA controller 31, and a predetermined calculation process is performed by the CPU 51. As a result of the arithmetic processing, the first and third DUTs are determined to be PASS, and the test item 4 is advanced to the test.

  As described above, based on the test result of the test item at each stage of the DUT 10, as a calculation processing means for the next test item, a means having a short calculation processing prediction time is dynamically selected from the PC 50 and the DSP 23 under the condition of the test item. Therefore, the semiconductor test apparatus can perform a series of tests on the DUT 10 in the shortest time, and can increase the test efficiency per unit time of the test apparatus and reduce the test cost ratio as the cost of the DUT.

  In the above embodiment, the case where the DUT is a liquid crystal driver IC has been described. However, the present invention is not limited to this, and the present invention is also effective for testing various analog LSIs.

  As described above, according to the present invention, it is possible to realize a semiconductor test apparatus capable of increasing the test efficiency per unit time without performing the optimization setting operation of the calculation time by the user.

It is a block diagram which shows the principal part of the embodiment of this invention. 2 is a flowchart showing an example of a flow of switching control of arithmetic processing means in the semiconductor test apparatus of FIG. It is a block diagram which shows an example of the conventional semiconductor test apparatus. It is a flowchart which shows an example of the flow of DSP calculation. It is a flowchart which shows an example of the flow of PC calculation. It is a characteristic comparative example figure of DSP calculation and PC calculation.

Explanation of symbols

20 Measurement Card 21 A / D Converter 22 Capture Memory 23 DSP
24 Local memory 25 Internal bus 30 Measurement module 31 DMA controller 40 Bus 50 Tester controller (TSC)
51 CPU
52 RAM
53 Internal Bus 54 Parallel DUT Number Confirmation Unit 55 Operation Data Number Confirmation Unit 56 Processing Time Database 57 DSP / PC Operation Switching Unit

Claims (3)

A plurality of measurement modules comprising a measurement card of a plurality of channels provided with a DSP having a calculation processing function for measurement data, and a tester controller having a PC function having a calculation processing function for measurement data and controlling these measurement modules in an integrated manner. A semiconductor test apparatus configured to simultaneously test a plurality of DUTs,
A semiconductor test apparatus, wherein the tester controller is provided with a switching selection means for switching and selecting a DSP or a PC as an arithmetic processing means for measurement data based on an arithmetic processing prediction time corresponding to a test condition at that time.   2. The semiconductor test apparatus according to claim 1, wherein the switching selection unit obtains an arithmetic processing prediction time based on the number of parallel DUTs and the number of prediction arithmetic data to be tested at that time.   The semiconductor test apparatus according to claim 1, wherein the DUT is an analog LSI including a liquid crystal driver IC.

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