JP4939838B2 - Storage device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device capable of storing data by using an organic compound for a memory circuit and a capacitor.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, RFID (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, wireless chip), etc. are especially used in the company, market, etc. Has begun to be introduced.

  Many of these semiconductor devices have a circuit using a semiconductor substrate such as silicon (Si) (hereinafter also referred to as an IC (Integrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter also referred to as a memory). And a control circuit. In addition, development of a semiconductor device including a control circuit, a memory circuit, and the like having an organic thin film transistor (hereinafter also referred to as TFT) using an organic compound, an organic memory, and the like is actively performed.

For example, there is Patent Document 1 as an example using an organic memory. Further, for example, there is Patent Document 2 as an example of RFID.
Japanese Unexamined Patent Publication No. 7-22669 JP 2000-299440 A

  However, as a capacitor used in a circuit included in the semiconductor device, a capacitor formed between a semiconductor layer and a gate electrode by connecting a source electrode and a drain electrode of a transistor formed over a substrate is often used. In this case, there is an advantage that it can be formed at the same time as other transistors, but on the other hand, there is a problem that the ratio of the area of the capacitance to the area of the semiconductor device is large and the reduction is difficult.

  Further, when an attempt is made to increase the capacity in order to improve the rectification capability and the boosting function, the increase in the capacity using the semiconductor layer and the gate electrode directly leads to an increase in the area of the semiconductor device. However, it is particularly desirable to reduce the size of a semiconductor device used for RFID as much as possible, and a reduction in capacity element or an increase in capacitance in the semiconductor device is expected.

  SUMMARY OF THE INVENTION The present invention has been made in view of this point, and reduces the area of a capacitive element in a circuit in a semiconductor device to reduce the size of a semiconductor device on which the capacitive element and an organic memory are mounted. The purpose is to improve the function by increasing the capacitance in the circuit without increasing the area of the device. Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. By using the present invention, a semiconductor device such as an integrated circuit having a multilayer wiring layer or a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be manufactured.

  One embodiment of the present invention includes a memory portion and a peripheral circuit electrically connected to the memory portion over the same substrate, the memory portion including a bit line extending in a first direction, A word line extending in a second direction perpendicular to the direction of 1, a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line A plurality of memory elements each having a stacked structure are provided, and the peripheral circuit includes a capacitor element having a dielectric made of the same material as the layer containing the organic compound.

  One embodiment of the present invention includes a memory portion, a circuit that controls the memory portion, and a power supply circuit on the same substrate, and the memory portion includes a bit line extending in a first direction, A word line extending in a second direction perpendicular to the direction of 1, a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line A plurality of memory elements having a stacked structure are provided, and the power supply circuit includes a capacitor element having a dielectric made of the same material as that of the layer containing the organic compound.

  One embodiment of the present invention includes a memory portion, a circuit that controls the memory portion, and a transmission / reception circuit over the same substrate, the memory portion including a bit line extending in a first direction, A word line extending in a second direction perpendicular to the direction of 1, a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line A plurality of memory elements each having a stacked structure are provided, and the transmission / reception circuit includes a capacitor element having a dielectric made of the same material as the layer containing the organic compound.

  One embodiment of the present invention includes a memory portion and a peripheral circuit electrically connected to the memory portion over the same substrate, the memory portion including a memory cell including a transistor and a memory element, and a plurality of the memory cells. A memory cell array including a memory cell, wherein the memory element includes a first conductive layer electrically connected to a source or drain region of the transistor, and an organic compound provided on the first conductive layer A layer and a second conductive layer provided on the organic compound layer, and the peripheral circuit includes a capacitive element having a dielectric made of the same material as the layer containing the organic compound. It is a feature.

  One embodiment of the present invention includes a memory portion, a circuit that controls the memory portion, and a power supply circuit over the same substrate. The memory portion includes a memory cell that includes a transistor and a memory element, and a plurality of the memory cells. A memory cell array including a memory cell, wherein the memory element includes a first conductive layer electrically connected to a source or drain region of the transistor, and an organic compound provided on the first conductive layer And a second conductive layer provided on the organic compound layer, and the power supply circuit includes a capacitive element having a dielectric made of the same material as the layer containing the organic compound. It is a feature.

  One embodiment of the present invention includes a memory portion, a circuit that controls the memory portion, and a transmission / reception circuit over the same substrate. The memory portion includes a memory cell that includes a transistor and a memory element, and a plurality of the memory cells. A memory cell array including a memory cell, wherein the memory element includes a first conductive layer electrically connected to a source or drain region of the transistor, and an organic compound provided on the first conductive layer A layer and a second conductive layer provided on the organic compound layer, and the transmission / reception circuit includes a capacitive element having a dielectric made of the same material as the layer containing the organic compound. It is a feature.

  In the above structure, the first capacitor element that uses the same material as the layer containing the organic compound as a dielectric and the second capacitor element that uses a semiconductor as a dielectric may be provided over the same substrate. Note that it is desirable that the first capacitor element using the same material as the layer containing the organic compound as a dielectric and the second capacitor element using the semiconductor as a dielectric are connected in parallel. Further, the same material as that of the second conductive layer may be used for one electrode of the first capacitor element using the same material as that of the layer containing the organic compound as a dielectric.

  Note that in the above structure, a rectifying element is provided between the first conductive layer and the layer containing the organic compound or between the layer containing the organic compound and the second conductive layer. As the rectifying element, there is a transistor in which a gate electrode and a drain electrode are connected.

  One of the present invention is a method for manufacturing a memory portion having a memory element over an insulating surface, a peripheral circuit electrically connected to the memory portion, and a semiconductor device in which the peripheral circuit has a capacitor, A first conductive layer, a layer containing an organic compound, and a second conductive layer are formed on an insulating surface in order from the bottom, and the layer containing the organic compound is used as a dielectric layer of the capacitor element. It is said.

  In one embodiment of the present invention, a memory portion including a transistor over a substrate having an insulating surface, a first capacitor element, a peripheral circuit electrically connected to the memory portion, and the peripheral circuit include A method for manufacturing a semiconductor device having a second capacitor element, in which a first semiconductor layer and a second semiconductor layer are formed over a substrate having an insulating surface, the transistor having the first semiconductor layer, A first capacitor layer having two semiconductor layers, a first conductive layer electrically connected to the transistor, and a layer containing an organic compound over the first conductive layer, A second conductive layer is formed on the layer containing the organic compound overlapping with the conductive layer, and the layer containing the organic compound is used as a dielectric layer of the second capacitor element.

  In the above structure, it is preferable that the first capacitor element and the second capacitor element are connected in parallel. Further, the same material as that of the second conductive layer may be used for one electrode of the capacitor.

  Note that in the above structure, an element having a rectifying property is provided between the first conductive layer and the layer containing the organic compound or between the layer containing the organic compound and the second conductive layer. Also good. As the rectifying element, there is a transistor in which a gate electrode and a drain electrode are connected.

  Note that an organic memory is a memory in which a layer having an organic compound is interposed between a pair of conductive layers. The present invention is characterized by using a capacitor element that is made of the same material as that of the layer containing an organic compound used in an organic memory. A peripheral circuit in this specification refers to a circuit including at least a capacitor such as a resonance circuit, a power supply circuit, a booster circuit, a DA converter, and a protection circuit. In addition to a capacitor element using the same material as the layer containing the organic compound as a dielectric, a capacitor element using a semiconductor as a dielectric may be provided on the same substrate. In this case, it is desirable that the capacitive element using the same material as the layer containing the organic compound as a dielectric and the capacitive element using a semiconductor as a dielectric are connected in parallel.

  According to the present invention, it is possible to obtain a semiconductor device equipped with an organic memory that can be formed inexpensively and easily without using a special process and without increasing the number of processes.

  In a capacitive element using the same semiconductor layer as that of a conventional transistor as a dielectric, an effective capacitance can be obtained only in an area where the gate insulating film and the semiconductor layer overlap. In contrast, a capacitor using a layer containing an organic compound used in an organic memory can be formed directly on an element such as a transistor or a wiring, and most of the area required for placement can contribute to the capacitance. The area of the capacitor element in the circuit can be reduced.

  Further, by selectively using a material having a high dielectric constant for the layer containing the organic compound according to the present invention, the capacitance value per unit area of the capacitor can be improved.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a memory element in which a layer containing an organic compound is installed between two conductive layers, and a capacitor element in which a layer containing the same organic compound as the memory element is installed between two conductive layers; A configuration example of a semiconductor device including the above will be described with reference to the drawings.

  As shown in FIG. 1, the semiconductor device according to the present invention includes a memory element 108 and a capacitor 109 formed over a substrate 100.

  A memory element 108 illustrated in FIG. 1 is formed by stacking a first conductive layer 101, a layer 104 containing an organic compound, and a second conductive layer 106. The capacitor 109 is formed by stacking a layer 105 containing an organic compound using the same material as the first conductive layer 102 and the memory element portion and a second conductive layer 107. The partition layers 110a, 110b, and 110c function to prevent the first conductive layer 101 and the second conductive layer 106, or the first conductive layer 102 and the second conductive layer 107 from being in direct contact with each other.

The first conductive layers 101, 102, and 103, the layers 104 and 105 containing an organic compound, the second conductive layers 106 and 107, and the partition layers 110a, 110b, and 110c can be formed by the same process. it can. Accordingly, the memory element 108 and the capacitor 109 can be formed at the same time in the same process.

  In the above structure, a highly conductive element, compound, or the like is used for the first conductive layers 101, 102, and 103 and the second conductive layers 106 and 107. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements Thus, a single layer or a laminated structure can be used. Examples of the alloy containing a plurality of the above elements include an alloy Al containing Al and Ti, an alloy containing Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, and Al, Ni and C. An alloy containing Al or an alloy containing Al and Mo can be used. The above material can be formed by vapor deposition, sputtering, CVD, printing, or droplet discharge. For example, Ag can be formed by a droplet discharge method, or Al can be formed by a vapor deposition method.

  Further, one or both of the first conductive layers 101, 102, and 103 and the second conductive layers 106 and 107 may be provided so as to have a light-transmitting property. The light-transmitting conductive layer is formed using a transparent conductive material, or is formed with a thickness that allows light to pass even if it is not a transparent conductive material. Examples of transparent conductive materials include indium tin oxide (ITO, Indium Tin Oxide), zinc oxide (ZnO), indium zinc oxide (IZO), and other light-transmitting oxides such as gallium-doped zinc oxide (GZO). A conductive material can be used. Indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide mixed with 2 to 20 wt% zinc oxide (ZnO) may be used.

  The layers 104 and 105 containing an organic compound are formed of an organic compound, an organic compound whose conductivity is changed by an electric action, or a layer formed by mixing an organic compound and an inorganic compound. The layers 104 and 105 containing an organic compound may be provided as a single layer or a stack of a plurality of layers. Alternatively, a layer formed of an organic compound whose conductivity is changed by an electric action may be stacked.

  Examples of the organic compound that can form the layers 104 and 105 containing an organic compound include organic resins such as polyimide, acrylic, polyamide, benzocyclobutene, and epoxy.

Further, as an organic compound that can constitute the layers 104 and 105 containing an organic compound and whose conductivity is changed by an electric action, an organic compound material having a hole transporting property or an organic compound material having an electron transporting property can be used. Etc.

As an organic compound material having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper lid Phthalocyanine compounds such as Russianine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound material having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used.

In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

  As a manufacturing method, an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like can be used. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering. Alternatively, a coating method, a droplet discharge method, a printing method (a method of selectively forming a pattern shape such as screen printing or offset printing), or the like can also be used.

  Further, by using a material having a high dielectric constant for the layers 104 and 105 containing an organic compound, the capacitance value per unit area of the capacitor 109 can be improved.

  As the partition layers 110a, 110b, and 110c, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, or polyimide ( Polyimide), aromatic polyamide, heat-resistant polymer such as polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Further, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A TOF film or an SOG film obtained by a coating method can also be used.

  Further, after a conductive layer, an insulating layer, or the like is formed by discharging a composition by a droplet discharge method, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, the surface of the roller-like object may be scanned to reduce unevenness, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

  An example in which a memory element portion and a capacitor element are formed using a plurality of organic compound layers is shown in FIG.

  In FIG. 13, in the memory element 108, a layer 113 containing a first organic compound is formed on the first conductive layer 101, and a layer containing the first organic compound is formed on the layer 113 containing the first organic compound layer. A layer 114 containing a second organic compound is formed so as to cover 113, and a second conductive layer 106 is formed on the layer 114 containing a second organic compound. In the capacitor 109, the layer 115 containing the first organic compound is formed over the first conductive layer 102, and the layer 115 containing the first organic compound is covered on the layer 115 containing the first organic compound. A layer 116 containing a second organic compound is formed in a shape, and the second conductive layer 107 is formed over the layer 116 containing the second organic compound.

  When either the memory element or the capacitor is stacked, a second layer containing an organic compound is selectively provided between the first layer containing an organic compound and the second conductive layer. It may be formed.

  In the above structure of this embodiment, a rectifying element may be provided between the first conductive layer 101 of the memory element 108 and the layer 104 containing an organic compound. The rectifying element is a transistor or a diode in which a gate electrode and a drain electrode are connected. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that the element having a rectifying property may be provided between the layer 104 containing an organic compound and the second conductive layer 106.

  As described above, the partition layers 110a, 110b, and 110c prevent the first conductive layer 101 and the second conductive layer 106, or the first conductive layer 102 and the second conductive layer 107 from being in direct contact with each other. In the case where the first conductive layer has a sufficiently thin film thickness and there is no possibility that the layer containing an organic compound is torn in a region where there is a step such as an end, part or all of the partition layers 110a, 110b, and 110c Can be excluded.

  A structural example of a semiconductor device which does not use a partition layer is shown in FIG. In FIG. 2A, the memory element 108 is formed so that the entire surface of the first conductive layer 101 is covered with a layer 104 containing an organic compound, and further the second conductive layer 106 is covered. Similarly, the capacitor 109 is formed so that the first conductive layer 102 is covered with a layer 105 containing an organic compound, and the second conductive layer 107 is further covered. By not forming the partition layer, it contributes to simplification of the process.

  Note that the second conductive layers 106 and 107 are usually electrically separated from each other, but when one of the electrodes of the memory element portion and one end of the capacitor can be used at the same potential, The second conductive layers 106 and 107 may be connected.

  A structural example of a semiconductor device having such a structure is shown in FIG. In FIG. 2B, a layer containing an organic compound which forms the memory element 108 and the capacitor 109 and the second conductive layer are used in common. In the memory element 108, the first conductive layer 101 and the organic layer are organic. The capacitor element 109 has a stacked structure of the layer 112 including the compound and the second conductive layer 111, and the capacitor 109 has a stacked structure of the first conductive layer 102, the layer 112 including the organic compound, and the second conductive layer 111. In the case where one of the electrodes of the memory element portion and one end of the capacitor can be used at the same potential, such a configuration may be adopted.

  With such a configuration, it is possible to simultaneously form the memory element and the capacitor element over the same substrate without increasing the number of processes.

(Embodiment 2)
In this embodiment, a memory element in which a layer containing an organic compound is installed between two conductive layers, and a capacitor element in which a layer containing the same organic compound as the memory element is installed between two conductive layers; A configuration example different from that of the first embodiment will be described with reference to the drawings with respect to a configuration example of the semiconductor device including the above.

  Although FIG. 1 illustrates a structure in which the memory element 108 and the capacitor 109 are provided over the substrate 100, the present invention is not limited thereto, and as illustrated in FIG. 3, the transistor group 200 is provided over the substrate 100 and the memory element 108 is provided thereover. Alternatively, the capacitor 109 may be formed. FIG. 3 shows a structure in which the capacitor 109 is formed immediately above the transistor group 200 and one end of the electrode is connected to the wiring 150. Thus, the capacitor 109 functions as a capacitor between the transistor group 200 and the wiring 150.

  The transistor group 200 is provided with a thin film transistor (TFT) in FIG. 3, but this is an example, and any configuration may be used as long as it is a known one. For example, a CMOS transistor or a field effect transistor can be used. Further, any structure of the semiconductor layer included in the transistor group 200 may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or Either n channel type may be used.

  Further, the channel formation region of the transistor used may be a single gate structure formed by one, a double gate structure formed by two, or a triple gate structure formed by three. By using the present invention in combination with a single gate structure, a further miniaturized semiconductor device can be obtained. In addition, by combining the present invention with a double gate or triple gate structure, variation in off-state current can be further reduced, and a highly reliable semiconductor device can be obtained.

  Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source and drain regions and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Note that here, an example in which the memory element 108 and the capacitor 109 are formed over the transistor group 200 is described; however, the memory element 108, the capacitor 109, and the transistor group 200 are manufactured in separate steps, and a conductive film or the like is formed. You may stick together using.

  FIG. 3 shows an example in which the capacitor 109 is formed and connected immediately above the transistor group 200, but what is connected to the capacitor is not limited to the transistor, and may be a wiring. FIG. 4 shows an example in which a capacitive element is formed and connected immediately above the wiring.

  In FIG. 4, the capacitor 109 is formed immediately above the wiring 250, and the second conductive layer of the capacitor 109 is connected to the wiring 150 through the first conductive layer 103. Thus, the capacitor 109 functions as a capacitor between the wiring 150 and the wiring 250.

  Further, the region for forming the capacitor element does not need to be on the directly connected transistor or wiring, and can be arbitrarily determined. FIG. 5 is a diagram illustrating an example in which the memory element 108 and the capacitor 109 are formed over the transistor 300 and the transistor group 310. In FIG. 5, the capacitor 109 is formed immediately above the transistor group 310 that is not connected to the capacitor 109.

  Similarly, a capacitor element can be formed immediately above a wiring that is not directly connected to the capacitor element. FIG. 6 is a diagram showing an example in which the memory element 108 and the capacitor 109 are formed over the wirings 150, 350, 351, 352, and 353. In FIG. 6, the capacitor 109 is formed immediately above the wirings 351, 352, and 353 that are not connected to the capacitor 109.

  By adopting the configuration as shown in FIGS. 5 and 6, the capacitive element of the present invention can be formed directly above circuits and wirings that are not directly connected.

  As described above, by configuring the capacitor element as in the embodiment of the present invention, all or part of the conventional capacitor element using the semiconductor layer and the gate electrode can be reduced and arranged on a circuit or a wiring. It becomes possible. As a result, the area of the semiconductor device can be reduced.

(Embodiment 3)
In this embodiment, a memory element in which a layer containing an organic compound is installed between two conductive layers, and a capacitor element in which a layer containing the same organic compound as the memory element is installed between two conductive layers; A configuration example different from the first embodiment and the second embodiment will be described with reference to the drawings with respect to one configuration example of the semiconductor device including the above.

  The capacity element according to the present invention can be increased in capacity by combining with the existing capacity element. FIG. 7 shows an example in which a conventional capacitive element using a semiconductor layer and a gate metal is combined with the capacitive element of the present invention.

  In the example shown in FIG. 7, an existing capacitor element 400 is formed over a substrate 100, and a memory element 108 and a capacitor element 109 are formed thereover. The capacitive element 400 is a conventionally used capacitive element, and functions as a capacitive element using a capacitance between the semiconductor layer and the gate electrode by being connected to the source electrode layer and the drain electrode layer of the TFT.

  Further, by connecting the wiring 150 and the gate electrode in the existing capacitive element 400, the capacitance of the existing capacitive element 400 and the capacitance of the capacitive element 109 are connected between the wiring 150 and the drain / source electrode of the existing capacitive element 400. The capacity is added.

  By adopting such a configuration, a capacitor element and a conventional capacitor element using a semiconductor layer and a gate electrode can be used at the same time. Therefore, the capacity can be increased without increasing the chip area as compared with the conventional case, and the function of the circuit can be improved.

  In addition, it is possible to selectively use the capacitor element to be used depending on the voltage applied to the element. For example, an existing capacitor element is used for a region where a high voltage is generated and the capacitor element according to the present invention is damaged, and a capacitor element according to the present invention is used for a capacitor in a region that handles other low voltages. In addition, the capacitor used may be changed depending on the region.

  Furthermore, by combining with the above embodiment mode, it is possible to improve the function while reducing the chip area by greatly increasing the number of capacitors according to the present invention while reducing the number of conventional capacitors.

(Embodiment 4)
In this embodiment, a structure example of an RFID chip in which the capacitor and the organic memory described in the above embodiment are formed and an antenna is mounted will be described with reference to drawings.

  The RFID chip described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic wave in which a pair of coils are arranged to face each other and communicate by mutual induction. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

  First, a configuration example of an RFID chip in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to the drawings.

  FIG. 8 is a diagram showing an outline of the RFID chip. As shown in FIG. 8, an antenna circuit 1101, a clock generation circuit 1104, a power supply circuit 1105, a control circuit 1112, and a memory circuit 1113 are provided over a substrate 1100. The antenna circuit 1101 includes an antenna 1102 and a resonance capacitor 1103, and the power supply circuit 1105 includes a smoothing circuit 1106 and a booster circuit 1107. Further, the smoothing circuit 1106 includes a diode 1108 that rectifies an AC signal and a smoothing capacitor 1109, and the booster circuit 1107 includes a diode group 1110 and a capacitor element group 1111 for boosting a voltage. Although not shown, in addition to these circuits, a data modulation / demodulation circuit, a sensor, an interface circuit, and the like may be included.

  According to the present invention, part or all of the resonance capacitor 1103, the smoothing capacitor 1109, and the capacitor element group 1111 can be replaced with a capacitor element using a conductive layer and an organic compound constituting an organic memory as in the above embodiment. .

  However, when the structure of the present invention is applied to a region where a high voltage that can destroy the memory element is applied as in the last stage of the capacitor element group 1111, the conductive layer and the organic compound that form the organic memory are used. Therefore, it is necessary to take measures so that the capacitor element is not destroyed. For example, locally increase the film thickness of the insulating layer of the corresponding capacitive element, replace the insulating layer of the corresponding capacitive element with another insulating layer, or add another insulating layer, etc. .

  Of course, it may be replaced with a conventional capacitive element, and the replacement of the capacitive element in accordance with the use region is not limited to the above example, and is applied to all the capacitive elements in the circuit including the capacitive element in the chip. It goes without saying that it is possible.

  FIG. 9A is a top view of an RFID chip having a memory device formed of an active matrix type. A conductive layer used as an upper electrode of a memory element and an upper electrode in a capacitor element of the present invention and a conductive layer functioning as an antenna. It is the figure which looked at the position where a layer is formed from the upper surface. In FIG. 9A, a memory 1001, an antenna circuit 1005, and a power supply circuit 1009 are provided over a substrate 1000. Although not shown, in addition to these circuits, a control circuit and a clock generation circuit may be included, and a data modulation / demodulation circuit, a sensor, an interface circuit, and the like may be included.

  The memory 1001 has a memory cell array 1003 configured by arranging a plurality of memory cells 1002, and a conductive layer 1004 is formed so as to cover the memory cell array 1003. The antenna circuit 1005 includes an antenna 1006 and a resonance capacitor 1007, and a conductive layer 1008 is formed in a shape covering the resonance capacitor 1007. The power supply circuit 1009 includes a smoothing circuit 1010 and a booster circuit 1013. The smoothing circuit 1010 further includes a smoothing circuit 1012, and the conductive layer 1011 is formed so as to cover the smoothing circuit 1012. The booster circuit 1013 includes capacitors 1015, 1017, 1019, 1021, and 1023, and conductive layers 1014, 1016, 1018, 1020, and 1022 are formed so as to cover the capacitors.

  The conductive layers 1004, 1008, 1011, 1014, 1016, 1018, 1020, and 1022 are all the same material and are simultaneously formed in the same process.

  Note that although the antenna 1006 has a shape surrounding the resonant capacitor 1007 and the power supply circuit 1009, this is merely an example, and the actual shape of the antenna is not limited thereto. In addition, the configuration such as the number, shape, and arrangement of the formed capacitors is an example, and the actual configuration of the capacitors is not limited to this.

  FIG. 9B illustrates an example of a structure of a memory device formed of an active matrix type. A memory cell array 1003 in which memory cells 1002 are provided in a matrix, a bit line driver circuit 1076 having a column decoder 1076a, a read circuit 1076b, and a selector 1076c, a word line driver circuit 1074 having a row decoder 1074a and a level shifter 1074b, a write circuit, etc. It has an interface 1073 for exchanging with the outside. Note that the structure of the memory 1001 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 1002 includes a first wiring that forms a word line Wy (1 ≦ y ≦ n), a second wiring that forms a bit line Bx (1 ≦ x ≦ m), a transistor 1060, and a memory element 1065. And have. The memory element 1065 has a structure in which an organic compound layer is sandwiched between a pair of conductive layers.

  In FIG. 9A, FIG. 10 shows a cross-sectional configuration between AB. FIG. 10 shows a semiconductor device having a memory device formed of an active matrix type. A transistor portion 530 having transistors 510a and 510b over a substrate 500, a transistor portion 540 having transistors 520a and 520b, a transistor portion 560 having transistors 550a and 550b, and insulating layers 501a, 501b, 508, 509, 511, and 516 514, an element formation layer 535 including a storage element portion 525, a capacitor element 570 formed using the same material as the storage element, and a conductive layer 543 functioning as an antenna are provided above the element formation layer 535. Yes.

  Note that the case where the memory element portion 525, the capacitor element 570, and the conductive layer 543 functioning as an antenna are provided above the element formation layer 535 is described here; however, the present invention is not limited to this structure, and the memory element portion 525 and the capacitor element 570 are provided. The conductive layer 543 functioning as an antenna can be provided in a layer below the element formation layer 535.

  The memory element unit 525 includes memory elements 515a and 515b. The memory element 515a includes a partition layer (insulating layer) 507a, a partition layer (insulating layer) 507b, a layer 512 containing an organic compound, and a second conductive layer 513 over the first conductive layer 506a. . The memory element 515b is provided by stacking a partition layer (insulating layer) 507b, a partition layer (insulating layer) 507c, a layer 512 containing an organic compound, and a second conductive layer 513 over the first conductive layer 506b. Yes. In addition, an insulating layer 514 that covers the second conductive layer 513 and functions as a protective film is formed.

  The first conductive layer 506a and the first conductive layer 506b in which the plurality of memory elements 515a and 515b are formed are connected to the source electrode layer or the drain electrode layer of each of the transistors 510a and 510b. That is, each memory element is connected to one transistor. A layer 512 containing an organic compound is formed over the entire surface so as to cover the first conductive layers 506a and 506b and the partition layers (insulating layers) 507a, 507b, and 507c, but is selectively formed in each memory cell. It may be. Note that the memory elements 515a and 515b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  By applying voltage to the first conductive layers 506a and 506b and the second conductive layer 513, current flows in the layer 512 containing an organic compound. Therefore, the temperature of the layer 512 containing an organic compound is increased and fluidized by Joule heat, and the composition having fluidity moves without maintaining a solid state shape. Accordingly, the thickness of the layer 512 containing an organic compound becomes nonuniform, the layer 512 containing an organic compound is deformed, and the first conductive layers 506a and 506b and the second conductive layer 513 are short-circuited. Therefore, the conductivity of the memory element before and after voltage application changes.

  Data is read by reading the change in conductivity in each memory element. An example of the reading method will be described with reference to FIG.

  FIG. 12A is a schematic diagram of an active matrix storage element and its drive circuit, a word line drive circuit 724, a bit line drive circuit 726, and a storage element portion in which the bit line Bx and the word line Wy are connected. 721. The bit line driver circuit 726 includes a column decoder 726a, a read circuit 726b, and a selector 726c. In addition, the reading circuit 726 b includes a sense amplifier 747 and a resistance element 746. Note that the structure shown here is merely an example, and other circuits such as an output circuit and a buffer may be provided, or a write circuit may be provided in the bit line driver circuit.

  FIG. 12B illustrates a current-voltage characteristic 701 of the memory element unit in which data “0” is written in the memory element unit, and a current-voltage characteristic 702 of the memory element unit in which data “1” is written. , Current-voltage characteristics 703 of the resistance element 746 are shown. Here, a case where a transistor is used as the resistance element 746 is shown. A case where 3 V is applied between the first conductive layer 506a and the second conductive layer 513 as an operation voltage when reading data is described.

  In FIG. 12, in a memory cell having a memory element portion in which data of “0” is written, an intersection 704 between the current-voltage characteristic 701 of the memory element portion and the current-voltage characteristic 703 of the transistor is an operating point. The potential of the node α is V2 (V). The potential of the node α is supplied to the sense amplifier 747, and the data stored in the memory cell is determined as “0” in the sense amplifier 747.

  On the other hand, in a memory cell having a memory element portion in which data of “1” has been written, an intersection point 705 between the current-voltage characteristic 702 of the memory element portion and the current-voltage characteristic 703 of the transistor serves as an operating point. The potential of α is V1 (V) (V1> V2). The potential of the node α is supplied to the sense amplifier 747, and the data stored in the memory cell is determined as “1” in the sense amplifier 747.

  In this manner, data stored in the memory cell can be determined by reading the resistance-divided potential according to the resistance value of the memory element portion 721.

  In the memory element 515a, a rectifying element may be provided between the first conductive layer 506a and the layer 512 containing an organic compound, or between the layer 512 containing an organic compound and the second conductive layer 513. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction. The same applies to the memory element 515b.

  The capacitor 570 includes a partition layer (insulating layer) 507d, a partition layer (insulating layer) 507e, and an organic compound over the first conductive layer 561 formed using the same layer as the first conductive layers 506a and 506b. A layer 562 containing an organic compound formed of the same layer as the layer 512 and a second conductive layer 563 formed of the same layer as the second conductive layer 513 are stacked. In addition, an insulating layer 514 that covers the second conductive layer 563 and functions as a protective film is formed. Further, the second conductive layer 563 is connected to the wiring 565 through the conductive layer 564 separated from the first conductive layer 561, and is connected to another circuit through the wiring 565. With such a structure, it is possible to dispose a capacitor element directly above a transistor or a wiring.

  The conductive layer 543 functioning as an antenna is provided over the conductive layer 542 formed using the same layer as the second conductive layer 513. Note that a conductive layer functioning as an antenna may be formed using the same layer as the second conductive layer 513. The conductive layer 542 is provided over the conductive layer 541 formed using the same layer as the first conductive layers 506a and 506b. The conductive layer 541 is connected to the source electrode layer or the drain electrode layer of the transistor 520a.

  As a material of the conductive layer 543 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 543 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  The transistors 510a, 510b, 520a, 520b, 550a, and 550b included in the element formation layer 535 can be provided using p-channel TFTs, n-channel TFTs, or a CMOS in which these are combined. In addition, any structure of the semiconductor layers included in the transistors 510a, 510b, 520a, 520b, 550a, and 550b may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) is formed. Alternatively, the p-channel type or the n-channel type may be used. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source and drain regions and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  In the transistors 510a, 510b, 520a, 520b, 550a, and 550b included in the element formation layer 535, various semiconductors such as an amorphous semiconductor, a crystalline semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor are used as a semiconductor layer. The semiconductor layer to be formed may be an organic transistor formed of an organic compound. In this case, the element formation layer 535 including an organic transistor can be formed using a direct printing method, a droplet discharge method, or the like over a flexible substrate such as a plastic as the substrate 500. By using a printing method, a droplet discharge method, or the like, a semiconductor device can be manufactured at lower cost.

  In addition, the element formation layer 535, the memory elements 515a and 515b, the capacitor 570, and the conductive layer 543 functioning as an antenna are formed by evaporation, sputtering, CVD, printing, droplet discharge, or the like as described above. can do. Note that a different method may be used for each region. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by printing or An organic transistor can be provided by a droplet discharge method.

  Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

  Next, a structure example of a semiconductor device in the case where a terminal portion is provided over a substrate provided with a plurality of elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is described with reference to FIG. I will explain.

  FIG. 11 illustrates a semiconductor device having an active matrix memory device. A transistor portion 630 having transistors 610a and 610b over a substrate 600, a transistor portion 640 having transistors 620a and 620b, a transistor portion 660 having transistors 650a and 650b, and insulating layers 601a, 601b, 608, 609, and 611 , 616 and 614 are provided. Further, a storage element portion 625 and a capacitor element 670 formed using a material for the storage element are provided above the element formation layer 635. Further, a conductive layer 643 functioning as an antenna provided over the substrate 646 is provided so as to be connected to the element formation layer 635.

  Note that here, the case where the memory element portion 625 or the conductive layer 643 functioning as an antenna is provided above the element formation layer 635 is shown; however, the structure is not limited thereto, and the memory element portion 625, the capacitor element 670, and the antenna function. The conductive layer 643 can be provided below the element formation layer 635.

  The memory element portion 625 includes memory elements 615a and 615b. The memory element 615a has a partition layer (insulating layer) 607a, a partition layer (insulating layer) 607b, and a layer 612 containing an organic compound over the first conductive layer 606a. The memory element 615b includes a partition layer (insulating layer) 607b, a partition layer (insulating layer) 607c, and a layer 612 containing an organic compound over the first conductive layer 606b. The second conductive layer 613 is provided in a stacked manner. In addition, an insulating layer 614 that covers the second conductive layer 613 and functions as a protective film is formed.

  In addition, the first conductive layer 606a and the first conductive layer 606b in which the plurality of memory elements 615a and 615b are formed are connected to the source electrode layer or the drain electrode layer of each of the transistors 610a and 610b. That is, each memory element is connected to one transistor. A layer 612 containing an organic compound is formed over the entire surface so as to cover the first conductive layers 606a and 606b and the partition layers (insulating layers) 607a, 607b, and 607c, but is selectively formed in each memory cell. It may be. Note that the memory elements 615a and 615b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  By applying a voltage to the first conductive layers 606 a and 606 b and the second conductive layer 613, a current flows through the layer 612 containing an organic compound. Therefore, the temperature of the layer 612 containing an organic compound is increased by Joule heat to be fluidized, and the fluid composition moves without maintaining a solid state shape. Therefore, the thickness of the layer 612 containing an organic compound becomes nonuniform, the layer 612 containing an organic compound is deformed, and the first conductive layers 606a and 606b and the second conductive layer 613 are short-circuited. Therefore, the conductivity of the memory element before and after voltage application changes.

  As described above, data is read by reading the change in conductivity in each memory element.

  In the memory element 615a, a rectifying element may be provided between the first conductive layer 606a and the layer 612 containing an organic compound, or between the layer 612 containing an organic compound and the second conductive layer 613. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction. The same applies to the memory element 615b.

  The capacitor 670 includes a partition layer (insulating layer) 607d, a partition layer (insulating layer) 607e, and an organic compound over the first conductive layer 661 formed using the same layer as the first conductive layers 606a and 606b. A layer 662 containing an organic compound formed of the same layer as the layer 612 and a second conductive layer 663 formed of the same layer as the second conductive layer 613 are provided. In addition, an insulating layer 614 that covers the second conductive layer 663 and functions as a protective film is formed. Further, the second conductive layer 663 is connected to the wiring 665 through the conductive layer 664 separated from the first conductive layer 661 and is connected to another circuit through the wiring 665. With such a structure, it is possible to dispose a capacitor element directly above a transistor or a wiring.

  The substrate 600 including the element formation layer 635, the memory element portion 625, and the capacitor 670, and the substrate 646 provided with the conductive layer 643 functioning as an antenna are attached to each other with an adhesive resin 645. The element formation layer 635 and the conductive layer 643 are electrically connected through conductive fine particles 644 contained in the resin 645. In addition, using a conductive adhesive such as a silver paste, a copper paste, or a carbon paste, or a solder bonding method, a substrate 600 including the element formation layer 635, the memory element portion 625, and the capacitor 670, and a conductive material that functions as an antenna. The substrate 646 provided with the layer 643 may be attached.

  As a material of the conductive layer 643 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 643, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  In this manner, an RFID chip including a memory device and an antenna in which a capacitor element is provided immediately above a wiring or a transistor can be formed. In this embodiment mode, an element formation layer can be provided by forming a thin film transistor over a substrate, or by forming a field effect transistor over a substrate using a semiconductor substrate such as Si as the substrate. A layer may be provided. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

  Further, the memory element portion and the capacitor may be provided over a substrate provided with a conductive layer functioning as an antenna. A sensor connected to the transistor may be provided.

  Note that although an application example in the case of an active matrix memory has been described in this embodiment, the present invention can be similarly applied to a passive matrix memory manufactured by a known method.

  FIG. 17A is a top view of an RFID chip having a memory device configured with a passive matrix type. The conductive layer used as the upper electrode of the memory element and the upper electrode in the capacitor of the present invention and the conductive layer functioning as an antenna It is the figure which looked at the position where and are formed from the upper surface. In FIG. 17A, a memory 1201, an antenna circuit 1005, and a power supply circuit 1009 are provided over a substrate 1000. Although not shown, in addition to these circuits, a control circuit and a clock generation circuit may be included, and a data modulation / demodulation circuit, a sensor, an interface circuit, and the like may be included.

  The memory 1201 has a memory cell array 1203 configured by arranging a plurality of memory cells 1202, and conductive layers 1204 are formed by the number of rows of memory cells so as to extend over one column of memory cells. The conductive layer 1204 is formed at the same time using the same material and the same process as the conductive layers 1008, 1011, 1014, 1016, 1018, 1020, and 1022.

  Note that in FIG. 17A, the conductive layer 1204 is formed in a shape that extends over one column of memory cells; however, the shape is not limited to this, and may be formed in a shape that extends over one row of memory cells.

  FIG. 17B illustrates an example of a structure of a passive matrix memory device. A memory cell array 1203 in which memory cells 1202 are provided in a matrix, a bit line driver circuit 1226 having a column decoder 1226a, a read circuit 1226b, and a selector 1226c, a word line driver circuit 1224 having a row decoder 1224a and a level shifter 1224b, a write circuit, etc. And an interface 1223 for exchanging with the outside. Note that the structure of the memory 1201 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 1202 includes a first conductive layer constituting the word line Wy (1 ≦ y ≦ n), a second conductive layer constituting the bit line Bx (1 ≦ x ≦ m), and a layer containing an organic compound And have. The layer containing an organic compound is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  In FIG. 17A, FIG. 18 shows a cross-sectional configuration between AB. FIG. 18 illustrates a semiconductor device having a memory device formed of a passive matrix type. Over the substrate 1500, a transistor portion 1540 including transistors 1520a and 1520b, a transistor portion 1560 including transistors 1550a and 1550b, and an element formation layer 1535 including insulating layers 1501a and 1501b, 1508, 1509, 1511, 1516, and 1514 are provided. Over the element formation layer 1535, a memory element portion 1525, a capacitor 1570 formed using the same material as the memory element, and a conductive layer 1543 functioning as an antenna are provided.

  Note that the case where the memory element portion 1525, the capacitor 1570, and the conductive layer 1543 functioning as an antenna are provided above the element formation layer 1535 is described here; however, the present invention is not limited to this structure, and the memory element portion 1525 and the capacitor 1570 are provided. The conductive layer 1543 functioning as an antenna can be provided in a layer below the element formation layer 1535.

  The memory element unit 1525 includes memory elements 1515a and 1515b. The memory element 1515a is formed by stacking a partition wall (insulating layer) 1507a, a partition wall (insulating layer) 1507b, a layer 1512a containing an organic compound, and a second conductive layer 1513a over a first conductive layer 1506. In the memory element 1515b, a partition wall (insulating layer) 1507b, a partition wall (insulating layer) 1507c, an organic compound layer 1512b, and a second conductive layer 1513b are stacked over the first conductive layer 1506. In addition, an insulating layer 1514 functioning as a protective film is formed so as to cover the second conductive layers 1513a and 1513b. In addition, the first conductive layer 1506 in which the plurality of memory elements 1515 a and 1515 b are formed is connected to the wiring 1530. That is, the first conductive layer 1506 functions as a word line, and the second conductive layers 1513a and 1513b function as bit lines.

  Needless to say, the first conductive layer may be used as a bit line and the second conductive layer may be used as a word line. FIG. 19 shows a configuration example formed in such a manner. In FIG. 19, the first conductive layers 1600a and 1600b are used as bit lines, and the second conductive layer 1601 is used as a word line. The layer 1602 containing an organic compound formed between the first conductive layers 1600a and 1600b and the second conductive layer 1601 may be separated for each memory element.

  Note that the element formation layer 1535, the memory element portion 1525, the capacitor 1570, and the conductive layer 1543 functioning as an antenna can be formed using the material or the manufacturing method described in the above embodiment modes.

  In addition, the RFID chip manufactured in this embodiment mode is peeled off from a substrate by a publicly known peeling process, and is bonded onto a flexible substrate, so that the semiconductor device can be provided over a flexible substrate. Can be obtained. Flexible substrate means film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of fibrous material, substrate film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and adhesiveness It corresponds to a laminated film with a synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment, and when the heat treatment and pressure treatment are performed, the film is provided on the adhesive layer provided on the outermost surface of the film or on the outermost layer. The layer (not the adhesive layer) is melted by heat treatment and bonded by pressure. Further, an adhesive layer may be provided on the substrate, or an adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

  By applying the capacitive element and the organic memory of the present invention as in this embodiment, the capacitive element can be formed immediately above the wiring or the transistor, and the capacitive element can be formed simultaneously with the formation of the organic memory. . As described above, by forming a capacitor element directly above a wiring or a transistor, an RFID chip including a memory device and an antenna satisfying both of the reduction in area and the improvement in characteristics due to an increase in capacitance is provided. The

(Embodiment 5)
In this embodiment, a method for manufacturing a semiconductor device of the present invention including a thin film transistor, a memory element, a capacitor, and an antenna will be described with reference to FIGS.

  First, insulating layers 2001 and 2002 to be a base are formed over a substrate 2000 (FIG. 14A). As the substrate 2000, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like may be used. With such a substrate 2000, the area and shape of the substrate 2000 are not greatly limited. For example, if the substrate 2000 has a side of 1 meter or more and has a rectangular shape, the productivity is remarkably improved. Can be made. Such an advantage is a great advantage compared to the case of using a circular silicon substrate. Further, when a separation layer is used between the substrate 2000 and the insulating layer 2001, a layer having a thin film transistor can be transferred to a substrate over which a conductive film or the like is formed. As a result, the conductive film connected to the thin film transistor And the connection with the conductive film on the transfer destination substrate can be simplified.

  Next, the insulating layer 2001 is formed as a silicon oxynitride layer as a first layer, and the insulating layer 2002 is formed as a second layer from a silicon oxynitride layer. As the insulating layers 2001 and 2002, a layer containing silicon oxide or silicon nitride is formed by a known means (such as sputtering or plasma CVD). The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The base insulating layer may be a single layer or a stacked layer. For example, when the base insulating layer has a three-layer structure, a silicon oxide layer is formed as the first insulating layer, and the second insulating layer is formed. And a silicon oxynitride layer is preferably formed as a third insulating layer. Alternatively, a silicon oxynitride layer may be formed as the first insulating layer, a silicon nitride oxide layer may be formed as the second insulating layer, and a silicon oxynitride layer may be formed as the third insulating layer. The insulating layer serving as a base functions as a blocking film that prevents intrusion of impurities from the substrate 2000.

  Next, an amorphous semiconductor layer 2003 (eg, a layer containing amorphous silicon) is formed over the insulating layer 2002 (FIG. 14B). The amorphous semiconductor layer 2003 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Subsequently, the amorphous semiconductor layer 2003 is subjected to a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, crystallization A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a promoting metal element and a laser crystallization method). After that, the obtained crystalline semiconductor layer is patterned into a desired shape to form crystalline semiconductor layers 2004 to 2009 (FIG. 14C).

An example of a manufacturing process of the crystalline semiconductor layers 2004 to 2009 will be briefly described below. First, an amorphous semiconductor layer having a thickness of 66 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 2004 to 2009 are formed by a patterning process using a photolithography method. In the case of forming a crystalline semiconductor layer by a laser crystallization method, a continuous wave or pulsed gas laser or solid state laser is used. As the gas laser, excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, or the like is used. As the solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, or YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is used.

  In addition, when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, it is possible to crystallize at a low temperature for a short time and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method that can contain argon at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

  Next, a gate insulating layer 2010 is formed to cover the crystalline semiconductor layers 2004 to 2009 (FIG. 14D). The gate insulating layer 2010 is formed by a known method (plasma CVD method or sputtering method) by forming a single layer or a stacked layer containing a silicon oxide or a silicon nitride. Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

  Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 2010. The first conductive layer is formed with a thickness of 20 to 100 nm by a known means (plasma CVD method or sputtering method). The second conductive layer is formed with a thickness of 100 to 400 nm by a known means. The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of combinations of the first conductive layer and the second conductive layer include a tantalum nitride (TaN) layer and a tungsten (W) layer, a tungsten nitride (WN) layer and a tungsten layer, a molybdenum nitride (MoN) layer and molybdenum. (Mo) layer etc. are mentioned. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. Moreover, it is not limited to a two-layer structure, and may be a laminated structure of two or more layers or a single-layer structure. Note that in the case of a three-layer structure, a stacked structure of a molybdenum layer, an aluminum layer, and a molybdenum layer is preferably employed.

  In this embodiment, a single drain transistor without an LDD is used. However, this is an example, and any structure may be used as long as it is a known transistor.

  Next, a resist mask is formed by photolithography, and an etching process is performed to form a gate electrode and a gate line, so that a conductive layer functioning as a gate electrode (sometimes referred to as a gate electrode layer) 2011-2016 is formed (FIG. 15A).

  Next, a mask made of a resist is formed by photolithography, and desired impurity regions 2017b to 2022b of N type or P type are formed on the crystalline semiconductor layers 2004 to 2009 by ion doping or ion implantation. Channel formation regions 2017a to 2022a are formed (FIG. 15B). For example, when N-type is imparted, an element belonging to Group 15 may be used as the impurity element imparting N-type. For example, an impurity element is added using phosphorus (P) or arsenic (As) to form an N-type impurity region. Next, in the case of imparting P-type, a resist mask is formed by photolithography, and an impurity element imparting P-type, for example, boron (B) is added to a desired crystalline semiconductor layer, and P A type impurity region is formed.

  Next, insulating layers 2023 and 2024 are formed so as to cover the gate insulating layer 2010 and the conductive layers 2011 to 2016 (FIG. 15C). The insulating layers 2023 and 2024 are formed by known means (SOG method, droplet discharge method, etc.), inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, siloxane, etc. It is made of an organic material. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The insulating layer covering the conductive layer may be a single layer or a stacked layer. In the case of a three-layer structure, a layer containing silicon oxide is formed in the first insulating layer, and a resin is applied to the second insulating layer. A layer including silicon nitride may be formed, and a layer including silicon nitride may be formed as the third insulating layer.

  Note that before the insulating layers 2023 and 2024 are formed, or after one or more thin films of the insulating layers 2023 and 2024 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  Next, the insulating layers 2023 and 2024 are etched by photolithography to form contact holes that expose the impurity regions 2017b to 2022b. Subsequently, a conductive layer is formed so as to fill the contact hole, and the conductive layer is patterned to form conductive layers 2025 to 2037 functioning as source / drain wirings (FIG. 15D).

  The conductive layers 2025 to 2037 are formed of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by known means (plasma CVD method or sputtering method), or an alloy containing these elements as a main component. The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive layers 2025 to 2037 include, for example, a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer, and a stacked layer of a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride (TiN) layer, and a barrier layer. A structure should be adopted. Note that the barrier layer corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are suitable materials for forming the conductive layers 2025 to 2037 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier layer made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, and the crystalline semiconductor layer is excellent. Contact can be made.

  Next, insulating layers 2038 and 2039 are formed so as to cover the conductive layers 2025 to 2037 (FIG. 16A). The insulating layers 2038 and 2039 are formed as a single layer or stacked layers using an inorganic material or an organic material by a known means (SOG method, droplet discharge method, or the like).

  Subsequently, the insulating layers 2038 and 2039 are etched by photolithography to form contact holes that expose the conductive layers 2025 to 2037. Subsequently, a conductive layer is formed so as to fill the contact hole. The conductive layer is formed of a conductive material using a known means (plasma CVD method or sputtering method). Next, the conductive layer is patterned to form conductive layers 2040 to 2044 (FIG. 16A). Note that the conductive layers 2040 and 2041 serve as one of a pair of conductive layers included in the memory element. Therefore, the conductive layers 2040 to 2044 are preferably formed as a single layer or stacked layers using titanium, or an alloy material or compound material containing titanium as a main component. Since titanium has a low resistance value, it leads to a reduction in the size of the memory element, and high integration can be realized. In the photolithography process for forming the conductive layers 2040 to 2044, wet etching is preferably performed in order to prevent damage to the lower layer thin film transistor, and hydrogen fluoride (HF) or ammonia excess is used as an etchant. Use water.

  Next, an insulating layer is formed so as to cover the conductive layers 2040 to 2044, and the insulating layer is etched by photolithography to form contact holes that expose the conductive layers 2040 to 2044. A partition layer (insulating layer) ) 2045-2049 are formed. The partition layers 2045 to 2049 are formed as a single layer or a stacked layer using an inorganic material or an organic material by a known means (SOG method, droplet discharge method, or the like). The partition layers 2045 to 2049 are preferably formed with a thickness of 0.75 to 3 μm.

  Next, layers 2050 and 2051 containing an organic compound are formed so as to be in contact with the conductive layers 2040, 2041, and 2043 (FIG. 16B). For the layers 2050 and 2051 containing an organic compound, a droplet discharge method, a printing method, a spin coating method, or the like can be used. In particular, the work efficiency can be improved by using a spin coating method. When the spin coating method is used, a mask is provided in advance, or an organic compound layer can be selectively provided by using a photolithography process or the like after being formed over the entire surface. Further, by using a droplet discharge method or a printing method, the material utilization efficiency can be improved.

  Subsequently, the conductive layers 2052 and 2054 are formed so as to be in contact with the layers 2050 and 2051 containing an organic compound, and the conductive layer 2053 is formed so as to be in contact with the conductive layer 2042. The conductive layers 2052 to 2054 can be formed by a known means (plasma CVD method, sputtering method, printing method, droplet discharge method).

  Next, a conductive layer 2055 functioning as an antenna is formed in contact with the conductive layer 2053 (FIG. 16B). The conductive layer 2055 is formed using a conductive material by a known method (plasma CVD method, sputtering method, printing method, droplet discharge method). Preferably, the conductive layer 2055 is made of an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component. It is formed by layer or lamination. Specifically, the conductive layer 2055 is formed using a paste containing silver by a screen printing method, and then heat-treated at 50 to 350 degrees. Alternatively, an aluminum layer is formed by a sputtering method, and the aluminum layer is formed by patterning. For the pattern processing of the aluminum layer, wet etching processing may be used, and after the wet etching processing, heat treatment at 200 to 300 degrees may be performed.

  Next, an insulating layer 2056 functioning as a protective film is provided so as to cover the conductive layers 2052 to 2055 (FIG. 16B). The insulating layer 2056 can be formed with a single layer or a stacked structure by a droplet discharge method, a printing method, a spin coating method, or the like.

  Through the above steps, the memory element portion including a stack of the conductive layer 2040, the layer 2050 including the organic compound, and the conductive layer 2052, and the memory including the stack of the conductive layer 2041, the layer 2050 including the organic compound, and the conductive layer 2052. An element portion and a capacitor formed using a stack of the conductive layer 2043, the layer 2051 containing an organic compound, and the conductive layer 2054 can be completed, and an active matrix storage element and a circuit including the capacitor are formed. A semiconductor device can be formed.

  By producing the capacitor and the organic memory of the present invention as in this embodiment, the capacitor can be formed immediately above the wiring or the transistor, and the capacitor can be formed simultaneously with the formation of the organic memory. . As described above, by forming a capacitor element directly above a wiring or a transistor, an RFID chip including a memory device and an antenna satisfying both of the reduction in area and the improvement in characteristics due to an increase in capacitance is provided. The

  In this example, an application example of an RFID chip formed using the embodiment will be described with reference to the drawings. A method for manufacturing a transistor, which is different from that in the above embodiment, will be described.

  FIG. 20 shows a configuration of a semiconductor device using the present invention which transmits and receives signals using wireless communication. This semiconductor device 2501 has a function of performing wireless communication with a reader / writer device 2509. The reader / writer device 2509 is connected via a communication line and has a function of performing data communication with the semiconductor device 2501 under the control of a computer or as a computer terminal. The reader / writer device 2509 may be configured to communicate with the semiconductor device 2501 independently of the network.

  The semiconductor device 2501 includes a resonance circuit 2502, a power supply circuit 2503, a clock generation circuit 2504, a demodulation circuit 2505, a control circuit 2506, a memory unit 2507, and an encoding and modulation circuit 2508. The resonance circuit 2502 and the power supply circuit 2503 are configured by analog circuits, and the control circuit 2506 and the memory unit 2507 are configured by digital circuits. The clock generation circuit 2504, the demodulation circuit 2505, and the encoding and modulation circuit 2508 have an analog portion and a digital portion.

  These circuits include transistors. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 21 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 21 shows n-channel transistors 2201 and 2202, a capacitor element 2204, a resistor element 2205, and a p-channel transistor 2203. Each transistor includes a semiconductor layer 2305, a gate insulating layer 2308, and a gate electrode 2309. The gate electrode 2309 is formed with a stacked structure of a first conductive layer 2303 and a second conductive layer 2302. 22A to 22D are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 21, and can be referred to.

  In FIG. 21, an n-channel transistor 2201 includes an impurity region 2306 for forming a source and drain region for forming a contact with a wiring 2304 in the semiconductor layer 2305 and a concentration of impurities in the channel length direction (carrier flow direction). A lightly doped impurity region 2307 is formed. The impurity region 2307 is also called a low concentration drain (LDD). In the case where the n-channel transistor 2201 is formed, phosphorus or the like is added to the impurity region 2306 and the impurity region 2307 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 22A, in the gate electrode 2309 of the n-channel transistor 2201, the first conductive layer 2303 is formed so as to spread on both sides of the second conductive layer 2302. In this case, the first conductive layer 2303 is formed thinner than the second conductive layer. The thickness of the first conductive layer 2303 is formed to allow the ion species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 2307 is formed so as to overlap with the first conductive layer 2303 of the gate electrode 2309. That is, an LDD region overlapping with the gate electrode 2309 is formed. In this structure, an impurity region 2307 is formed in a self-aligned manner in the gate electrode 2309 by adding one conductivity type impurity through the first conductive layer 2303 using the second conductive layer 2302 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  A transistor having LDDs on both sides of a channel formation region is applied to a transistor constituting a rectifying TFT of the power supply circuit 2503 in FIG. 20 or a transmission gate (also referred to as an analog switch) used in a logic circuit. In these TFTs, since both positive and negative voltages are applied to the source / drain electrodes, it is preferable to provide LDDs on both sides of the channel formation region.

  In FIG. 21, an n-channel transistor 2202 includes an impurity region 2306 that forms a source and a drain region in a semiconductor layer 2305 and an impurity region 2307 that is doped at a lower concentration than the impurity concentration in the semiconductor layer 2305. . The impurity region 2307 is provided on one side of the channel formation region so as to be in contact with the impurity region 2306. As shown in FIG. 22B, in the gate electrode 2309 of the n-channel transistor 2202, the first conductive layer 2303 is formed so as to spread on one side of the second conductive layer 2302. In this case as well, an LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 2303 using the second conductive layer 2302 as a mask.

  A transistor having an LDD on one side of the channel formation region may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 21, the capacitor 2204 is formed by sandwiching a gate insulating layer 2308 between a first conductive layer 2303 and a semiconductor layer 2305. A semiconductor layer 2305 that forms the capacitor 2204 includes an impurity region 2310 and an impurity region 2311. The impurity region 2311 is formed in the semiconductor layer 2305 so as to overlap with the first conductive layer 2303. Further, the impurity region 2310 forms a contact with the wiring 2304. Since the impurity region 2311 can be doped with one conductivity type impurity through the first conductive layer 2303, the impurity concentration in the impurity region 2310 and the impurity region 2311 can be the same or different. It is. In any case, since the semiconductor layer 2305 functions as an electrode in the capacitor 2204, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as illustrated in FIG. 22C, the first conductive layer 2303 can function sufficiently as an electrode by using the second conductive layer 2302 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 2303 and the second conductive layer 2302 are combined, the capacitor 2204 can be formed in a self-aligning manner.

  In FIG. 20, the capacitor is used as a storage capacitor included in the power supply circuit 2503 or a resonance capacitor included in the resonance circuit 2502. However, all of these capacitive elements can be replaced with the capacitive elements of the present invention. It may be replaced or used together as necessary.

  In FIG. 21, the resistance element 2205 is formed of a first conductive layer 2303. Since the first conductive layer 2303 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element is used as a resistance load included in the modulation circuit 2508 in FIG. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 21, a p-channel transistor 2203 includes an impurity region 2312 in a semiconductor layer 2305. The impurity region 2312 forms source and drain regions that form a contact with the wiring 2304. The gate electrode 2309 has a structure in which the first conductive layer 2303 and the second conductive layer 2302 overlap each other. The p-channel transistor 2203 is a single drain transistor without an LDD. In the case of forming the p-channel transistor 2203, boron or the like is added to the impurity region 2312 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 2312, an n-channel transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 2305 and the gate insulating layer 2308 is excited by microwaves, has an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by plasma treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and the treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), whereby the interface between the semiconductor layer 2305 and the gate insulating layer 2308 The defect level of can be reduced. By performing this treatment on the gate insulating layer 2308, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 2308. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 2305 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 2308 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 2204. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 21 and 22, elements having various structures can be formed by combining conductive layers having different thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 22A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  In the case of FIGS. 21 and 22, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same patterning process using a photomask or reticle provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  Note that this embodiment can be freely combined with Embodiments 1 to 5 described above.

  An example of constituting a static RAM (SRAM) as one of the elements constituting the semiconductor device shown in FIG. 20 will be described with reference to FIGS.

  The semiconductor layers 10 and 11 illustrated in FIG. 23A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. The semiconductor layer is etched using the mask pattern to form island-shaped semiconductor layers 10 and 11 having a specific shape including the source and drain regions of the TFT and the channel formation region. The semiconductor layers 10 and 11 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layers 10 and 11 shown in FIG. 23A includes a mask pattern 30 shown in FIG. The mask pattern 30 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, the mask pattern 30 shown in FIG. 23B is manufactured as a light shielding portion. The mask pattern 30 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that is bent over a plurality of steps so that the corner portion does not become a right angle. In this photomask pattern, for example, the corners of the pattern and one side of the right triangle are deleted to a size of 10 mm or less.

  The shape of the mask pattern 30 shown in FIG. 23B is reflected in the semiconductor layers 10 and 11 shown in FIG. In that case, a shape similar to the mask pattern 30 may be transferred, or the corner of the mask pattern 30 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 30 may be provided.

  On the semiconductor layers 10 and 11, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as shown in FIG. 24A, gate wirings 12, 13, and 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layers 10 and 11. The gate wiring 14 is formed corresponding to the semiconductor layers 10 and 11. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  The photomask for forming this gate wiring is provided with a mask pattern 31 shown in FIG. The mask pattern 31 is a corner, and one side of a right triangle is 10 μm or less, or less than 1/2 of the line width of the wiring, and the corner is deleted to a size of 1/5 or more of the line width. Yes. The shape of the mask pattern 31 shown in FIG. 24B is reflected in the gate wirings 12, 13, and 14 shown in FIG. In that case, a shape similar to the mask pattern 31 may be transferred, or the corner of the mask pattern 31 may be transferred so as to be further rounded. That is, the gate wirings 12, 13, and 14 may be provided with rounded portions that have a smoother pattern shape than the mask pattern 31. That is, the corners of the gate wirings 12, 13, and 14 are ½ or less of the line width, and the corners are rounded to 1/5 or more. The convex portion suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave portion wash away that even if it is fine powder, it tends to gather at the corners. As a result, the yield can be expected to be greatly improved.

  The interlayer insulating layer is a layer formed next to the gate wirings 12, 13 and 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material using polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 12, 13, and 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

  Openings are formed in predetermined positions in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 25A, wirings 15 to 20 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 32 shown in FIG. As shown in the top view of FIG. 25 (B), the wiring layer is each corner portion bent in an L shape, and one side of a right triangle is 10 μm or less, or 1/2 or less of the line width of the wiring, The corners are deleted to a size of 1/5 or more of the line width, and the corners are rounded. That is, the outer periphery of the wiring layer at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring layer corresponding to the right isosceles triangular portion formed by is removed. When removed, two obtuse angle parts are newly formed in the wiring layer. By appropriately setting the mask design and etching conditions, a curve that touches both the first straight line and the second straight line is formed at each obtuse angle part. It is preferable to etch the wiring layer as described above. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. In such wiring, the convex part suppresses the generation of fine powder due to abnormal discharge when dry etching with plasma, and the concave part is easy to collect even in the case of cleaning even if it is fine powder. Wash away. As a result, the yield can be expected to be greatly improved. It can be expected that the corner portion of the wiring is electrically conducted by taking a round. In addition, a large number of parallel wires are very convenient for washing away dust.

  In FIG. 25A, n-channel transistors 21 to 24 and p-channel transistors 25 and 26 are formed. The n-channel transistor 23 and the p-channel transistor 25, and the n-channel transistor 24 and the p-channel transistor 26 constitute an inverter. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  Note that this embodiment can be freely combined with the above-described first to fifth embodiments and the first embodiment.

  In this example, application examples of a semiconductor device formed using the embodiment will be described with reference to drawings.

  According to the present invention, a semiconductor device that functions as a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refers to checks, securities, promissory notes, and the like, and can be provided with a processor chip 800 (see FIG. 26A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a processor chip 801 (see FIG. 26B). Personal belongings refer to bags, glasses, and the like, and can be provided with a processor chip 802 (see FIG. 26C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a processor chip 803 (see FIG. 26D). Books refer to books, magazines, and the like, and can be provided with a processor chip 804 (see FIG. 26E). A recording medium refers to DVD software, video tape, or the like, and can be provided with a processor chip 805 (see FIG. 26F). A vehicle refers to a vehicle such as a bicycle, a ship, or the like, and can be provided with a processor chip 806 (see FIG. 26G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  In addition, a processor chip having features of further miniaturization and / or higher functionality according to the present invention is mounted on a printed circuit board, attached to a surface, or embedded and fixed to an article. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the processor chip of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the processor chip of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Next, one mode of an electronic device mounted with a semiconductor device having a capacitor element according to the present invention will be described with reference to the drawings. The electronic device illustrated in FIG. 27 is a mobile phone, which includes housings 900 and 906, a panel 901, a housing 902, a printed wiring board 903, operation buttons 904, and a battery 905. The panel 901 is detachably incorporated in the housing 902, and the housing 902 is fitted on the printed wiring board 903. The shape and size of the housing 902 are changed as appropriate in accordance with the electronic device in which the panel 901 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 903, and the capacitive element according to the present invention can be applied as one of them. The plurality of semiconductor devices mounted on the printed wiring board 903 have any one of functions such as a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, and a transmission / reception circuit.

  The panel 901 is connected to the printed wiring board 903 via the connection film 908. The panel 901, the housing 902, and the printed wiring board 903 are housed in the housings 900 and 906 together with the operation buttons 904 and the battery 905. A pixel region 909 included in the panel 901 is arranged so as to be visible from an opening window provided in the housing 900.

  As described above, a semiconductor device to which the capacitor element of the present invention is applied is characterized in that it is small, thin, and lightweight, and the above-described feature makes it possible to effectively use a limited space inside the casings 900 and 906 of electronic devices. Can be used.

  Note that the housings 900 and 906 are examples of the external shape of a mobile phone, and the electronic device according to this embodiment can be transformed into various modes depending on functions and uses.

It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is a schematic diagram of an RFID chip. It is a schematic diagram of an RFID chip equipped with an active matrix memory. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is a schematic diagram of reading of an active matrix type memory. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed the process of forming the circuit of this invention. It is sectional drawing which showed the process of forming the circuit of this invention. It is sectional drawing which showed the process of forming the circuit of this invention. It is a schematic diagram of an RFID chip equipped with a passive matrix memory. It is sectional drawing which showed embodiment of this invention. It is sectional drawing which showed embodiment of this invention. It is a figure which shows the structure of the semiconductor device using this invention. It is a figure which shows the cross section of the circuit using this invention. It is a figure which shows the upper surface of the circuit using this invention. It is a figure which shows the upper surface and mask pattern of a circuit using this invention. It is a figure which shows the upper surface and mask pattern of a circuit using this invention. It is a figure which shows the upper surface and mask pattern of a circuit using this invention. It is the figure which showed the example of application of this invention. It is the figure which showed the example of application of this invention.

Claims (5)

On the same substrate, it has a memory part, a bit line drive circuit part, and a peripheral circuit part,
The memory unit includes a plurality of memory elements having a stacked structure of a first conductive layer constituting a bit line, an organic compound layer, and a second conductive layer constituting a word line,
The peripheral circuit section includes a capacitive element that uses the same material as the organic compound layer as a dielectric,
The material of the organic compound layer is an organic compound material having a hole transporting property, or an organic compound material having an electron transporting property,
The storage element has a function of storing a change in conductivity caused by applying a voltage between the first conductive layer and the second conductive layer;
The bit line driver circuit unit has a function of determining data corresponding to the change in conductivity by reading the change in conductivity. On the same substrate, it has a memory part, a bit line drive circuit part, and a peripheral circuit part,
The memory unit includes a plurality of memory elements having a stacked structure of a first conductive layer constituting a bit line, an organic compound layer, and a second conductive layer constituting a word line,
The peripheral circuit section includes a capacitor element having the same material as the organic compound layer as a dielectric, a transistor, and a wiring,
The capacitive element is formed above the transistor or the wiring,
The material of the organic compound layer is an organic compound material having a hole transporting property, or an organic compound material having an electron transporting property,
The storage element has a function of storing a change in conductivity caused by applying a voltage between the first conductive layer and the second conductive layer;
The bit line driver circuit unit has a function of determining data corresponding to the change in conductivity by reading the change in conductivity. On the same substrate, it has a memory part, a bit line drive circuit part, and a peripheral circuit part,
The memory unit includes a plurality of memory cells each including a transistor and a memory element.
The memory element has a stacked structure of a first conductive layer electrically connected to a source or drain of the transistor, an organic compound layer, and a second conductive layer,
The peripheral circuit section includes a capacitive element that uses the same material as the organic compound layer as a dielectric,
The material of the organic compound layer is an organic compound material having a hole transporting property, or an organic compound material having an electron transporting property,
The storage element has a function of storing a change in conductivity caused by applying a voltage between the first conductive layer and the second conductive layer;
The bit line driver circuit unit has a function of determining data corresponding to the change in conductivity by reading the change in conductivity. On the same substrate, it has a memory part, a bit line drive circuit part, and a peripheral circuit part,
The memory unit includes a plurality of memory cells including a first transistor and a memory element,
The memory element has a stacked structure of a first conductive layer electrically connected to a source or a drain of the first transistor, an organic compound layer, and a second conductive layer,
The peripheral circuit section includes a capacitive element that uses the same material as the organic compound layer as a dielectric, a second transistor, and a wiring.
The capacitive element is formed above the second transistor or the wiring,
The material of the organic compound layer is an organic compound material having a hole transporting property, or an organic compound material having an electron transporting property,
The storage element has a function of storing a change in conductivity caused by applying a voltage between the first conductive layer and the second conductive layer;
The bit line driver circuit unit has a function of determining data corresponding to the change in conductivity by reading the change in conductivity. In any one of Claims 1 thru | or 4 ,
The memory device, wherein the peripheral circuit portion includes a resonance circuit, a power supply circuit, a booster circuit, a DA converter, or a protection circuit.

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