JP4895394B2 - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration of processing efficiency of a processor and to shorten a time required for image processing when transferring an image processing parameter to be written by the processor to a main memory page by page to a register by a DMAC (direct memory access controller) and performing image processing of a plurality of continuous pages with an image processing module on the basis of the image processor parameter. <P>SOLUTION: At ST1, the image processing parameter is stored in the main memory. At ST2, descriptors for a parameter DMAC, data read DMAC, and data write DMAC are created on the main memory. At ST3, an address of the descriptor is set to a descriptor pointer register. At ST4, an image processing controller is started. At ST5, it is determined whether or not there is a next page and, when there is, operation from ST1 to ST4 is repeated in succession. After the operation for a final page is finished, processing is completed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention is based on the image processing parameters set in the register relates to an image processing equipment for performing image processing on the image data by the image processing means.

  In the digital multi-function peripheral, various image processing is performed on the image data read by the scanner, and the image is output by the printer. Typical image processing includes γ conversion processing, filter processing, color correction processing, gradation processing, and the like.

  When performing these image processes, unprocessed image data on the main memory is transferred to each image processing module under the control of the DMAC (Direct Memory Access Controller), and image processed image data is transferred under the control of the DMAC. Then, transfer from the image processing module to main memory.

  In addition, in order to execute each image processing in the set image quality mode, each image processing module has a built-in register for holding image processing parameters. In general, since these parameters are set in a register by a CPU (Central Processing Unit), the load on the CPU is heavy, and the time from writing the parameter to the register until the end of image processing also becomes longer.

  Therefore, the CPU stores the image processing parameters in the main memory in advance, transfers the image processing parameters in the main memory to the register by the parameter transfer DMAC, and interlocks with the DMAC for image data transfer. An image processing apparatus that reduces the load on the CPU and shortens the time until the end of image processing has been proposed (see Patent Document 1).

FIG. 11 is a functional block diagram of the image processing apparatus.
The image processing apparatus includes a control unit 101 realized by a microcomputer including a CPU, a ROM (Read Only Memory), and a RAM (Random Access Memory), an image processing module 102, and a memory 103.

  The image processing module 102 is realized by, for example, an application specific integrated circuit (ASIC), and includes a register 104, a parameter DMAC105, a data read DMAC106, and data that directly transfer data without using a CPU. It consists of a write DMAC 107, and each DMAC performs image processing in conjunction with each other.

  First, in steps S101 to 103, the control unit 101 writes the descriptor information for each DMAC of the data read DMAC 106 and the data write DMAC 107 and the descriptor information for the image processing parameter of the parameter DMAC 105 in the memory 103.

  In step S104, the control unit 101 writes register information to the image processing module 102 and sets necessary registers. In step S105, the control unit 101 activates the image processing module 102 using the activation register. When activated by the control unit 101, the image processing module 102 simultaneously sends activation signals EXEC from the register 104 to the parameter DMAC 105, the data read DMAC 106, and the data write DMAC 107, respectively. Accordingly, the parameter DMAC 105, the data read DMAC 106, and the data write DMAC 107 are activated simultaneously.

  In step S106, the data read DMAC 106 that has received the activation signal EXEC from the register 104 reads and acquires the descriptor information for the data read DMAC from the memory 103, and sets it in the internal register. In step S107, the parameter DMAC 105 that has received the activation signal EXEC from the register 104 reads and acquires the descriptor information for the image processing parameter from the address of the memory 103 designated by the setting in the register, and sets it in the internal register. In step S108, the data write DMAC 107 that has received the activation signal EXEC from the register 104 reads and acquires the descriptor information for the data write DMAC from the memory 103, and sets it in the internal register. The processes in steps S106 to S108 are performed simultaneously, whereby the parameter DMAC 105, the data read DMAC 106, and the data write DMAC 107 simultaneously read and acquire the descriptor information set in the memory 103.

  Next, in step S109, the parameter DMAC 105 sends an end notification indicating that the image processing parameter descriptor information has been set in the internal register to the data read DMAC 106 and ended. In step S110, the data read DMAC 106 confirms that the descriptor information for the image processing parameter is set in the internal register of the parameter DMAC 105 based on the end notification, and from the memory 103 based on the descriptor information acquired in step S105. The image processing module 102 reads the image data and performs image processing on the image data.

  In step S111, the data write DMAC 107 sequentially writes the image data after the image processing by the image processing module 102 to the memory 103 based on the descriptor information acquired in step S108.

  In step S112, the data read DMAC 106 sends an end notification indicating that all image data has been read to the data write DMAC 107. In step S113, the data write DMAC 107 writes all the image processed image data in the memory 103, and after confirming that the end notification is received from the data read DMAC 106, the control unit 101 indicates the end of the image processing. The control unit 101 performs a termination interrupt process based on the termination notification.

  In this way, the controller 101 does not directly set the descriptor information in the internal register for setting the descriptor information for the image processing parameter of the parameter DMAC 105, but stores the descriptor information in the memory 103 and then performs image processing by DMA processing. Since the module 102 reads, it is possible to reduce the load on the CPU of the control unit 101 and shorten the image processing time.

  However, in this image processing apparatus, when performing processing of a plurality of continuous pages, each DMAC needs to set descriptor information in an internal register for each page, and the control unit 101 completes image processing for each page. The setting will be repeated and the activation will be repeated. Therefore, when the number of pages increases, there is a problem that the processing efficiency of the software decreases due to an increase in the number of processes in which the CPU of the control unit 101 waits for an interrupt.

JP 2007-188434 A

  The present invention has been made to solve such a problem, and an object of the present invention is to read image processing parameters written to the main memory for each page by the processor using the DMAC, set the registers, and set the registers. That is, when performing image data processing of a plurality of continuous pages by the image processing means based on the image processing parameters, the reduction in the processing efficiency of the processor is suppressed and the time required for the image processing is shortened.

The present invention relates to a register in which image processing parameters are set, a first DMAC that reads out image processing parameters in a main memory and sets them in the register, and image processing parameters set in the registers by the first DMAC And an image processing means for performing image processing on the image data, and an activation that activates the first DMAC based on an activation signal output after the processor writes the image processing parameters to the main memory for each page A control unit, a second DMAC that is activated by the activation control unit, reads image data on the main memory and transfers the image data to the image processing unit, and is activated by the activation control unit and processed by the image processing unit and a third DMAC to transfer image data to the main memory were describes the operation of each of the second DMAC, third DMAC Of Isukuriputa, the head of the descriptor for each page has an expanded region of the common information in the page, has other descriptor for each descriptor specific information, when processing image data of a plurality consecutive pages The image processing apparatus is characterized in that writing of image processing parameters for each page and output of a start signal by the processor are performed without waiting for completion of processing of each page of the first DMAC and the image processing means. .

According to the present invention, image processing parameters written to the main memory for each page by the processor are read by the DMAC and set in the register, and a plurality of continuous pages are processed by the image processing unit based on the image processing parameters set in the register. When performing image data processing, it is possible to suppress a decrease in the processing efficiency of the processor and to shorten the time required for the image processing. In addition, it is possible to eliminate the need to hold information common to each page in a register while suppressing an increase in the memory area for descriptors when one page is constituted by a large number of descriptors.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of an image processing apparatus according to an embodiment of the present invention. The image processing apparatus includes an engine 1000 and a controller 2000.

  The engine 1000 includes a scanner 1100, a scanner image processing ASIC 1200, a plotter 1300, a plotter control ASIC 1400, a RAM 1500, an engine CPU 1600, a flash memory 1700, and an engine ASIC 1800, and reads a document and outputs an image.

  A scanner 1100 is a unit that reads a document, and outputs document image data during a scanner operation, a copy operation, and a FAX transmission operation. The scanner image processing ASIC 1200 generates and outputs image data obtained by correcting the image data read by the scanner 1100, and image separation data in which a character portion / photograph portion and chromatic / achromatic color in a document are determined.

  The plotter 1300 forms an image on a sheet based on the image data output from the plotter control ASIC 1400 and outputs the image. The plotter control ASIC 1400 outputs image data input from the engine ASIC 1800 to the plotter 1300 in accordance with the synchronization signal from the plotter 1300.

  The RAM 1500 is a working memory for the engine CPU 1600 to perform engine control, and is used by the engine CPU 1600 for a variable storage area during program execution. The engine CPU 1600 performs overall control of the engine 1000 such as scanner control, paper conveyance, image formation, and fixing. The flash memory 1700 is a rewritable nonvolatile memory for storing programs used when the engine CPU 1600 executes various controls.

  The engine ASIC 1800 includes a video output unit 1810, an arbiter 1820, a communication buffer 1830, a resolution conversion unit 1840, and a compression / decompression unit 1850, and interfaces data between the controller 2000 and the engine CPU 1600, and between the controller 2000 and the plotter control ASIC 1400. .

  The video output unit 1810 reads image data of an image to be output from a main memory 2400, which will be described later, performs mask processing, composition processing, format conversion, and the like, and outputs them to the plotter control ASIC 1400. The arbiter 1820 arbitrates access from each module in the engine ASIC 1800 to the controller CPU 2300 described later. The communication buffer 1830 is a buffer for communication between the engine CPU 1600 and the controller CPU 2300. The resolution conversion unit 1840 converts low-resolution image data on the main memory 2400 to high-resolution image data suitable for the plotter 1300 during printer operation and FAX operation, and converts the converted image data to the main memory 2400. Output. The compression / decompression unit 1850 compresses the image data and sends it to the main memory 2400 in order to reduce the image data area on the main memory 2400, and decompresses the compressed image data output from the main memory 2400.

  The controller 2000 is a control device that controls the entire image processing apparatus and executes various applications, and includes a controller ASIC 2100, a hard disk 2200, a controller CPU 2300, and a main memory 2400.

  The controller ASIC 2100 includes a video input unit 2110, an arbiter 2120, a distribution image processing unit 2140, an image processing controller 2150, and a hard disk I / F (interface) 2160, and a main memory 2400 for image data input from the engine 1000. Transfer, image processing during copying, read / write control to the hard disk 2200, etc.

  The video input unit 2110 compresses the image data output from the scanner image processing ASIC 1200 and transfers it to the main memory 2400. The arbiter 2120 arbitrates access from each module in the controller ASIC 2100 to the controller CPU 2300. The distribution image processing unit 2140 performs image data conversion processing in order to distribute the image data on the main memory 2400 via the network, and outputs the converted image data to the main memory 2400. The image processing controller 2150 expands the compressed image data on the main memory 2400, performs filter processing, color conversion processing, gradation processing, and the like, and transfers them to the main memory 2400. The hard disk I / F 2160 performs read / write control to the hard disk 2200.

  The hard disk 2200 is a storage device used for storing various image data and for a temporary storage area of the controller CPU 2300. The controller CPU 2300 includes a memory controller, PCI (Peripheral Component Interconnect) Express (registered trademark), and a general-purpose interface for PCI, securing the area of the main memory 2400 and read / write control, as well as printer image drawing, copying, scanner, FAX, Execute various applications such as distribution. The main memory 2400 is a working memory for the controller CPU 2300 to execute various applications, and is used by the controller CPU 2300 for various data temporary storage areas, DMAC descriptor areas, and the like.

FIG. 2 is a diagram illustrating a configuration example of the image processing controller 2150 and a data flow with the main memory 2400.
The image processing controller 2150 includes an image processing module group 2151, a register control unit 2152, a data read DMAC 2153, a parameter DMAC 2154, and first to fourth data write DMACs 2155 to 2158.

  The parameter DMAC 2154 reads the image processing parameter 2402 previously loaded on the main memory 2400 and sets it in a parameter register (not shown) in the register control unit 2152. The data read DMAC 2153 reads out pixel sequential RGB image data and separated data X (input image data 2401) from the main memory 2400 and sends them to the image processing module group 2151. The image processing module group 2151 is a collection of modules that perform various image processing on input image data, and includes a γ conversion module, a filter module, a color correction module, a gradation processing module, and the like. The first to fourth data write DMACs 2155 to 2158 output the CMYK plane sequential image data after image processing sent from the image processing module group 2151 to the main memory 2400 (output image data 2403 to 2406).

  The register control unit 2152 holds parameters used when each image processing module in the image processing module group 2151 performs image processing. It also has an EXEC register for instructing each DMAC to start, an interrupt status register that holds the interrupt status, a descriptor pointer register for each DMAC, etc., to start each DMAC and output an interrupt signal to the controller CPU 2300 Do.

  FIG. 3 is a diagram illustrating examples of descriptors for data read DMAC and data write DMAC. Here, A is the first descriptor 2411 of each page, and B is the other descriptor 2412. The first descriptor 2411 and the other descriptors 2412 of each page, that is, all descriptors have the following entries.

  The address of the next descriptor is set in NDP (Next Descriptor Pointer). If the image area for one page cannot be secured continuously on the main memory 2400, the image area is secured in a jump, a descriptor is created for each area, and the address of the next descriptor is written here. By doing so, it is possible to continuously perform processing on the skipped image area.

  In SA (start address), the head address for inputting or outputting data is set. In the case of data read DMAC, image data is read from this address, and in the case of data write DMAC, image data is written from this address.

  In LINE, the number of lines in the sub-scanning direction of the two-dimensional image or the number of data of one-dimensional data is set. In MODE, the type of transfer data, interrupt, and repeat are set.

  In addition to the above entries, the descriptor 2411 at the top of the page has a common information entry in the page. In MWIDTH (memory width), the width on the memory in the main scanning direction of the two-dimensional image is set. The DMAC reads or writes (outputs) image data for one line using this value as a unit. In IWIDTH (image width), the width of the two-dimensional image in the main scanning direction is set. Set operation mode such as rotation in CTRL (control). In FILL (fill pattern), the value to be written when the memory is cleared is set.

  With such a configuration, it is possible to eliminate the need to hold information common to each page in a register while suppressing an increase in the memory area for descriptors when one page is configured with a large number of descriptors.

FIG. 4 is a diagram illustrating an example of the descriptor for the parameter DMAC.
The parameter DMAC descriptor 2413 has an entry of a start address (SA) of a parameter set in each image processing module. In the SA for the γ conversion parameter, a start address of a parameter such as a table value used for γ conversion is set. In the filter parameter SA, a start address of a parameter such as a filter coefficient used for smoothing or edge enhancement is set. In the color correction parameter SA, a start address of a parameter such as a masking coefficient used when converting from RGB to CMYK is set. In the gradation processing parameter SA, a start address of a parameter such as a dither table used for gradation processing is set.

FIG. 5 is a diagram illustrating a configuration example of registers in the register control unit 2152 of the image processing controller 2150.
The EXEC register shown in A of this figure is a register for starting the image processing controller 2150. The interrupt status register holds interrupt information such as an end interrupt of each DMAC of the image processing controller 2150 and an error. In the interrupt mask register, mask control for each interrupt of the image processing controller 2150 is set. An operation mode of the image processing controller 2150 is set in the operation mode register.

  In the parameters DMAC DP1 to DMAC DPn, the address (descriptor pointer) of the image processing parameter descriptor of each page (1 to n pages) is set when a plurality of pages are set.

  In the data read DMAC DP1 to the data read DMAC DPn, the address of the first descriptor of the input image data of each page is set when setting a plurality of pages.

  In the data write DMAC1 DP1 to the data write DMAC1 DPn, the address of the first descriptor of the output image data of each page for the first data write DMAC2155 is set when setting a plurality of pages. Similarly, the address of the first descriptor of the output image data of each page for the second data write DMAC2156 is set in the data write DMAC2 DP1 to the data write DMAC2 DPn, and the data write DMAC3 DP1 to the data write DMAC3 DPn The address of the first descriptor of the output image data of each page for the third write DMAC2157 is set, and the output image data of each page for the fourth write DMAC2158 is set in the data write DMAC4 DP1 to the data write DMAC4 DPn. Set the address of the first descriptor.

  Each register shown in B of this figure is set by a parameter DMAC2154. The γ conversion parameters hold parameters such as table values used for γ conversion, the filter parameters hold parameters such as filter coefficients used for smoothing and edge enhancement, and the color correction parameters are RGB Parameters such as masking coefficients used when converting from CMYK to CMYK, and parameters for tone processing hold parameters such as a dither table used when tone processing is performed.

FIG. 6 is a diagram showing a software control flow of the controller CPU 2300.
First, in step ST1, image processing parameters are prepared on the main memory 2400. This is realized by storing it in a storage device such as a ROM or a hard disk 2200 and loading it into the main memory 2400.

  Next, descriptors for the parameter DMAC 2154, the data read DMAC 2153, and the first to fourth data write DMACs 2155 to 2158 are created on the main memory 2400 in step ST2. Next, the address of the created descriptor is set in the descriptor pointer register in the register control unit 2152 in step ST3. When these settings are completed, the image processing controller 2150 is activated by writing 1 to the EXEC register in the register control unit 2152 in step ST4.

  Next, at step ST5, it is determined whether or not there is a next page. If there is (ST5: yes), the operations of steps ST1 to ST4 are repeated. When the process reaches the last page (ST5: no), the process ends. The controller CPU 2300 can perform another task until all the processing of the image processing controller 2150 described later is completed.

FIG. 7 is a diagram showing an operation flow of the image processing controller 2150.
The image processing controller 2150 continues the idle state in step ST11 until it is activated (EXEC) by the software of the controller CPU 2300. When the activation is applied (step ST11: yes), the operation flow branches into two steps ST12 and ST15 and proceeds in parallel.

  In one step ST12 branched, the counter of the number of activations held in the register control unit 2152 is incremented. Thereafter, when the activation is again applied (step ST13: yes), the activation number counter is incremented again. If not set (step ST13: no) and the counter value is larger than 0 (step ST14: yes), it waits for activation. If it is not set and the value of the counter becomes 0, the process proceeds to step ST25, an operation completion interrupt signal is output to the controller CPU 2300, and the process ends.

  In the other branched step ST15, the descriptor for the parameter DMAC 2154 is read from the main memory 2400. When reading of the descriptor is completed, the image processing parameter 2402 on the main memory 2400 is read out and set in the register in the register control unit 2152 in step ST16. When the parameter setting by the parameter DMAC2154 is completed, in step ST17, the data read DMAC2153 and the first to fourth data write DMAC2155 to 2158 read the descriptor 2411 with the extension area at the head of the page from the main memory 2400.

  When the data read DMAC 2153 finishes reading the descriptor, the data read DMAC 2153 reads the image data from the main memory 2400 according to the contents of the descriptor, and outputs it to the image processing module group 2151. The image processing module group 2151 performs image processing according to the parameters set in the register in the register control unit 2152 and outputs the processed image data to each data write DMAC. Each data write DMAC outputs image data from the image processing module group 2151 to the main memory 2400. These are the processes of step ST18.

  In step ST19, it is determined whether or not there is a next area, that is, whether or not an image area for one page is divided on the main memory 2400. If there is no next area, the process proceeds to step ST23, and the counter for the number of activations is decremented.

  On the other hand, if there is a next area, the process proceeds to step ST20, and the data read DMAC 2153 and the first to fourth data write DMACs 2155 to 2158 read the descriptor 2412 having no extension area from the main memory 2400.

  When the reading of the descriptor is completed, the data read DMAC 2153 reads the image data of the divided area from the main memory 2400 according to the contents of the descriptor, and outputs it to the image processing module group 2151. The image processing module group 2151 performs image processing according to the parameters set in the register in the register control unit 2152 and outputs the processed image data to the data write DMACs 2155 to 2158. Each data write DMAC 2155 to 2158 outputs the image data from the image processing module group 2151 to the main memory 2400. These are the processes of step ST21.

  After the processing of the second area is completed in step ST21, it is determined in step ST22 whether or not there is another area. If yes (ST22: yes), the process returns to ST20 and the page is divided. S20 and S21 are repeated until the image processing for all areas is completed.

  When there is no next area (ST22: no), the activation counter is decremented in step ST23. After decrementing, it is determined in step ST24 whether or not the counter value is greater than 0. If it is greater, the next page has been set and started, so the process returns to ST15 and the next page is processed. Do. If the counter value is 0, the next page has not been activated, so the process proceeds to ST25, an operation completion interrupt is output, and the operation is terminated.

  FIG. 8 is a diagram illustrating an arrangement example of descriptors, parameters, and image areas on the main memory 2400. In this example, the number of pages is 2, and the image area of each page is divided into two. Hereinafter, the divided area is referred to as a band. In this figure, A is the first page and B is the second page.

  PD1 of A in this figure is a descriptor of the first page for parameter DMAC2154, and this descriptor pointer is PDP1. P1 is a parameter for the first page, and parameters for γ conversion, filter, color correction, and gradation processing are loaded in this area. This start address is PSA1.

  DRD1_1 is a descriptor of the first band of the first page for the data read DMAC2153, and this descriptor pointer is DRDP1_1. Since this descriptor is the descriptor at the head of the page, it has an extension area. DR1_1 is an image area of the first band of the first page for data read DMAC, and original image data to be subjected to image processing is loaded into this area. This start address is DRSA1_1.

  DRD1_2 is a descriptor of the second band of the first page for the data read DMAC2153, and this descriptor pointer is DRDP1_2. Since this descriptor is not the descriptor at the head of the page, it does not have an extension area. DR1_2 is an image area of the second band of the first page for the data read DMAC2153, and original image data to be subjected to image processing is loaded in this area. This start address is DRSA1_2.

  DWD1_1 is a first band descriptor of the first page for the first to fourth data writes DMAC2155 to 2158, and this descriptor pointer is DWDP1_1. Since this descriptor is the descriptor at the head of the page, it has an extension area. DW1_1 is an image area of the first band of the first page for the first to fourth data write DMACCs 2155 to 2158, and image data after image processing is output to this area. This start address is DWSA1_1. Here, for convenience, four descriptors and image areas for four data write DMACs 2155 to 2158 are shown one by one, but actually four are provided.

  DWD1_2 is a second band descriptor of the first page for the first to fourth data write DMACCs 2155 to 2158, and this descriptor pointer is DWDP1_2. Since this descriptor is not the descriptor at the head of the page, it does not have an extension area. DR1_2 is an image area of the second band of the first page for the first to fourth data write DMACs 2155 to 2158, and image data after image processing is written to this area. This start address is DWSA1_2.

  PD2 shown in B of this figure is the descriptor of the second page for parameter DMAC2154, and this descriptor pointer is PDP2. P2 is a parameter for the second page, and parameters for γ conversion, filter, color correction, and gradation processing are loaded in this area. This start address is PSA2.

  DRD2_1 is a descriptor of the first band of the second page for the data read DMAC2153, and this descriptor pointer is DRDP2_1. Since this descriptor is the descriptor at the head of the page, it has an extension area. DR2_1 is an image area of the first band of the second page for the data read DMAC2153, and original image data to be subjected to image processing is loaded into this area. This start address is DRSA2_1.

  DRD2_2 is a descriptor of the second band of the second page for the data read DMAC2153, and this descriptor pointer is DRDP2_2. Since this descriptor is not the descriptor at the head of the page, it does not have an extension area. DR1_2 is an image area of the second band of the second page for the data read DMAC2153, and original image data to be subjected to image processing is loaded in this area. This start address is DRSA2_2.

  DWD2_1 is a first band descriptor of the second page for the first to fourth data write DMACs 2155 to 2158, and this descriptor pointer is DWDP2_1. Since this descriptor is the descriptor at the head of the page, it has an extension area. DW2_1 is an image area of the first band of the second page of the first to fourth data write DMAC2155 to 2158, and image data after image processing is written to this area. This start address is DWSA2_1.

  DWD2_2 is a second band descriptor of the second page for the first to fourth data writes DMAC2155 to 2158, and this descriptor pointer is DWDP2_2. Since this descriptor is not the descriptor at the head of the page, it does not have an extension area. DR2_2 is an image area of the second band of the second page for the first to fourth data write DMACs 2155 to 2158, and the image data after image processing is written in this area. This start address is DWSA2_2.

  9 and 10 are diagrams showing the operation sequence of the controller CPU 2300 and the image processing controller 2150 described above. Here, an example in which the number of pages is two and the image area of each page is divided into two as in FIG. 8 is shown. It is assumed that original image data to be subjected to image processing is already stored in the main memory 2400. The “software” in this figure is the software processing of the controller CPU 2300.

In step S0, the state is an initial state, and the counter for the number of activations of the register control unit 2152 is zero.
Steps S1 to S12 are software processes for the first page. First, in step S1, the parameters of the first page are loaded onto the main memory 2400, and in step S2, the descriptor of the parameters of the first page is created on the main memory 2400. In step S3, PDP1 is set in DP1 for parameter DMAC2154 in register controller 2152. In step S4, the first-band descriptor DRD1_1 of the first page for the data read DMAC 2153 is created on the main memory 2400. In step S5, DRDP1_1 is set in DP1 for data read DMAC 2153 in the register control unit 2152. In step S6, a second-band descriptor DRD1_2 for the first page for the data read DMAC 2153 is created on the main memory 2400. In step S7, DRDP1_2 is set in DP2 for data read DMAC2153 in the register control unit. In step S8, the first-band descriptor DWD1_1 of the first page for the first to fourth data write DMACs 2155 to 2158 is created on the main memory 2400. In step S9, DWDP1_1 is set in DP1 for the first to fourth data write DMACs 2155 to 2158 in the register control unit 2152. In step S10, the second-band descriptor DWD1_2 of the first page for the first to fourth data write DMACs 2155 to 2158 is created on the main memory 2400. In step S11, DWDP1_2 is set in DP2 for the first to fourth data write DMACs 2155 to 2158 in the register control unit 2152. In step S12, 1 is written in the EXEC register in the register control unit 2152 to activate the first page.

  When the register controller 2152 is activated, the activation counter is incremented in step S13, and as a result, the counter value becomes 1.

  The following steps S14 to S25 are software processes for the second page. In step S14, the parameters of the second page are loaded onto the main memory 2400. In step S15, a parameter descriptor for the second page is created on the main memory 2400. In step S16, PDP2 is set in DP2 for parameter DMAC2154 in register controller 2152. In step S17, the first-band descriptor DRD2_1 of the second page for the data read DMAC 2153 is created on the main memory 2400. In step S18, DRDP2_1 is set in DP3 for data read DMAC 2153 in the register control unit 2152. In step S19, a second-band descriptor DRD2_2 for the second page for the data read DMAC 2153 is created on the main memory 2400. In step S20, DRDP2_2 is set in DP4 for data read DMAC 2153 in the register control unit 2152. In step S21, the first-band descriptor DWD2_1 of the second page for the first to fourth data write DMACs 2155 to 2158 is created on the main memory 2400. In step S22, DWDP2_1 is set in DP3 for the first to fourth data write DMACs 2155 to 2158 in the register control unit 2152. In step S23, the second-band descriptor DWD2_2 of the second page for the first to fourth data write DMACs 2155 to 2158 is created on the main memory 2400. In step S24, DWDP2_2 is set in DP4 for the first to fourth data write DMACs 2155 to 2158 in the register control unit 2152. In step S25, 1 is written to the EXEC register in the register control unit 2152 to activate the second page.

  When being activated, the register control unit 2152 increments the activation number counter in step S26, and as a result, the counter value becomes 2.

The following steps S27 to S67 are processing of the image processing controller 2150.
The register control unit 2152 activated in the idle state activates the parameter DMAC2154 in step S27. In step S28, the parameter DMAC2154 reads the descriptor PD1 of the first page in the main memory 2400. In step S29, the parameter P1 of the first page in the main memory 2400 is read. In step S30, the parameter P1 is stored in the register control unit. Set in the register in 2152. The parameter DMAC 2154 sends a transfer end signal to the register control unit 2152 in step S31 when all parameter settings are completed in this way.

  Upon receiving the transfer end signal from the parameter DMAC 2154, the register control unit 2152 activates the data read DMAC 2153 in step S32, and activates the first to fourth data write DMACs 2155 to 2158 in step S33.

  In step S34, the activated data read DMAC 2153 reads the first-band descriptor DRD1_1 of the first page on the main memory 2400. In addition, the activated first to fourth data write DMACs 2155 to 2158 read out the descriptor DWD1_1 of the first band of the first page on the main memory 2400 in step S35. In step S36, the data read DMAC 2153 reads the first band image data DR1_1 of the first page on the main memory 2400, and outputs it to the image processing module group 2151.

  In step S37, the image processing module group 2151 performs image processing set by parameters on the image data input from the data read DMAC 2153, and outputs the image data to the first to fourth data write DMACs 2155 to 2158. In step S38, the first to fourth data write DMACs 2155 to 2158 output the image data DW1_1 after the image processing of the first band of the first page output from the image processing module group 2151 to the main memory 2400.

  In step S39, the data read DMAC 2153 reads the second-band descriptor DRD1_2 of the first page on the main memory 2400. In step S40, the first to fourth data write DMACs 2155 to 2158 read the second band descriptor DWD1_2 of the first page on the main memory 2400. In step S41, the data read DMAC 2153 reads the image data DR1_2 of the second band of the first page on the main memory 2400 and outputs it to the image processing module group 2151. When the reading is completed, a transfer end signal is output to the register control unit 2152 in step S44.

  In step S42, the image processing module group 2151 performs image processing set by parameters for the image data input from the data read DMAC 2153, and outputs the image data to the first to fourth data write DMACs 2155 to 2158. In step S43, the first to fourth data write DMACs 2155 to 2158 output the image data DW1_2 after the second band image processing of the first page output from the image processing module group 2153 to the main memory 2400. When the output ends, a transfer end signal is output to the register control unit 2152 in step S45.

  Upon receiving the transfer end signal from the first to fourth data write DMACs 2155 to 2158, the register control unit 2152 decrements the activation number counter in step S46. As a result, the counter value becomes 1. Since the value of the counter after decrement is not 0, the register control unit 2152 activates the parameter DMAC2154 again in step S47.

  The activated parameter DMAC2154 reads the descriptor PD2 of the second page on the main memory 2400 in step S48, reads the parameter P2 of the second page on the main memory 2400 in step S49, and sets the parameter P2 in step S50. Set to a register in the register control unit 2152. When all parameter settings are completed, a transfer end signal is output to the register control unit 2152 in step S51.

  Upon receiving the transfer end signal from the parameter DMA 2154C, the register control unit 2152 activates the data read DMAC 2153 in step S52, and activates the first to fourth data write DMACs 2155 to 2158 in step S53.

  The activated data read DMAC 2153 reads the first-band descriptor DRD2_1 of the second page on the main memory 2400 in step S54. The activated first to fourth data write DMACs 2155 to 2158 read the second band descriptor DWD2_1 of the second page on the main memory 2400 in step S55. In step S56, the data read DMAC 2153 reads the image data DR2_1 for the first band of the second page on the main memory 2400 and outputs it to the image processing module group 2151.

  In step S57, the image processing module group 2151 performs image processing set by parameters on the image data input from the data read DMAC 2153, and outputs the image data to the first to fourth data write DMACs 2155 to 2158. In step S58, the first to fourth data write DMACs 2155 to 2158 output the image data DW2_1 after the image processing for the first band of the second page output from the image processing module group 2151 to the main memory 2400.

  In step S59, the data read DMAC 2153 reads the second-band descriptor DRD2_2 of the second page on the main memory 2400. In step S60, the first to fourth data write DMACs 2155 to 2158 are read on the main memory 2400. Read out the descriptor DWD2_2 in the second band of the second page. In step S61, the data read DMAC 2153 reads the image data DR2_2 of the second band of the second page on the main memory 2400 and outputs it to the image processing module group 2151. When the reading is completed, a transfer end signal is output to the register control unit 2152 in step S64.

  In step S62, the image processing module group 2151 performs image processing set by parameters on the image data input from the data read DMAC 2153, and outputs the image data to the first to fourth data write DMACs 2155 to 2158. In step S63, the first to fourth data write DMACs 2155 to 2158 output the image data DW2_2 after the image processing of the second band of the second page output from the image processing module group 2151 to the main memory 2400. When the output ends, a transfer end signal is output to the register control unit 2152 in step S65.

  Upon receiving the transfer end signal from the first to fourth data write DMACs 2155 to 2158, the register control unit 2152 decrements the activation number counter in step S66, and the counter value becomes zero. The register control unit 2152 outputs a transfer end interrupt signal to the CPU controller 2300 in step S67 because the counter of the number of activations has become 0.

As described above in detail, according to the embodiment of the present invention, the following effects (1) to (3) can be obtained.
(1) The register control unit 2152 has a plurality of descriptor registers for the data read DMAC 2153 and the first to fourth data write DMACs 2155 to 2158, the image processing controller 2150 has a counter for the number of activations, and the image processing ends. Thereafter, if the activation counter is not 0, the parameter DMAC2154 is activated again, and when the parameter transfer by the parameter DMAC2154 is completed, the activation of the data read DMAC2153 and the first to fourth data write DMAC2155 to 2158 is repeated. As a result, the controller CPU 2300 eliminates the restriction of writing parameters and descriptors to the main memory 2400 after image processing for one page, and can write multiple pages at a time. Can be improved.
(2) Among the descriptors for the data read DMAC 2153 and the first to fourth data write DMACs 2155 to 2158, only the first descriptor of the page has an extension area to be held. The number of page registers can be reduced, and an increase in hardware scale can be suppressed.
(3) Since the end interrupt is issued when the processing of all pages is completed and the value of the activation counter reaches 0, the number of interrupt processing is reduced, so that the software processing efficiency can be improved.

1 is a block diagram illustrating an overall configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration example of an image processing controller in FIG. 1 and a data flow to and from a main memory. FIG. 3 is a diagram illustrating an example of descriptors of the data read DMAC and the data write DMAC in FIG. 2. It is a figure which shows the example of the descriptor of the parameter DMAC of FIG. FIG. 3 is a diagram illustrating a configuration example of a register in a register control unit of the image processing controller in FIG. 2. It is a figure which shows the software control flow of the controller CPU of FIG. It is a figure which shows the operation | movement flow of the image processing controller of FIG. FIG. 3 is a diagram illustrating an arrangement example of descriptors, parameters, and image areas on the main memory in FIG. 2. FIG. 3 is a first half of a diagram illustrating an operation sequence of the controller CPU and the image processing controller of FIG. 2. FIG. 3 is the latter half of the diagram showing the operation sequence of the controller CPU and image processing controller of FIG. 2. It is a functional block diagram of the conventional image processing apparatus.

Explanation of symbols

  2150 ... Image processing controller, 2152 ... Register controller, 2153 ... Data read DMAC, 2154 ... Parameter DMAC, 2155 to 2158 ... First to fourth data write DMAC, 2300 ... -Controller CPU, 2400 ... Main memory.

Claims (2)

A register in which image processing parameters are set;
A first DMAC that reads image processing parameters on the main memory and sets them in the register;
Image processing means for performing image processing on image data based on image processing parameters set in the register by the first DMAC;
Activation control means for activating the first DMAC based on an activation signal that is output after the processor writes the image processing parameters to the main memory for each page ;
A second DMAC that is activated by the activation control means, reads image data on the main memory, and transfers the image data to the image processing means;
A third DMAC that is activated by the activation control means and transfers the image data processed by the image processing means to the main memory ;
Of the descriptors describing the operations of the second DMAC and the third DMAC, the descriptor at the head of each page has an extended area of information common to the page, and the other descriptors are unique to each descriptor. Have information,
When processing a plurality of consecutive pages of image data, the processor does not wait for the end of processing of each page of the first DMAC and image processing means to write the image processing parameters of each page and output the start signal. And an image processing apparatus. The image processing apparatus according to claim 1.
A counter that increments upon input of the activation signal and decrements based on completion of image processing for one page; and a means for interrupting a completion notification to the processor when the value of the counter decreases to 0. An image processing apparatus.

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