JP4886558B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus capable of storing a stop factor of the information processing apparatus.

  In an information processing apparatus used in an industrial or public field, when a failure occurs, it is very effective for early failure recovery to save the cause of the failure and use it for cause analysis.

  2. Description of the Related Art Conventionally, an information processing apparatus has a built-in program called POST (Power On Self Test) that automatically diagnoses and initializes connected hardware at startup, and diagnoses system configurations such as memory and keyboard. The display function is provided.

  When executing POST, the plurality of tasks are sequentially executed in accordance with a task table held in the BIOS of the system.

  In recent PC server BIOS, a specific command called IPMI (Intelligent Management Platform) is used to notify the task number to a processor called BMC (Baseband Management Controller).

  At the same time, the BMC timer is set (to reboot if the timer is not reset after the set time has elapsed). If it hangs up during POST, the system is restored by rebooting after the set time has elapsed. Since the BMC holds the task number at the time of rebooting, it is recorded as log data.

  As described above, the conventional fault diagnosis method always requires a dedicated processor such as BMC. There are systems where BMC does not exist, but in this case, it is possible to reboot when the system hangs up, but the function is limited such that it is not possible to record which task number is hung.

  Therefore, a technique for providing a PC server that can monitor a POST activation failure without a specific processor such as a BMC is disclosed (for example, see Patent Document 1).

  Further, in the conventional information processing apparatus, as a storage device of the stop factor of the apparatus and a storage method of the stop factor, the cause of the stop request is stored in an external storage device such as an HDD as a file by software such as an application or a driver. It was something to save. (For example, refer to Patent Document 2).

As another method, normally, logging data is a file and data stored in an external storage device. (For example, refer to Patent Document 3.)
Japanese Patent Laying-Open No. 2004-302731 (FIG. 1, page 1) Japanese Patent Laid-Open No. 10-260870 (FIG. 1, page 1) Japanese Patent Laid-Open No. 7-319741 (FIG. 2, page 1)

  In the conventional system stop factor saving method, logging data is saved as a file in an external storage device such as an HDD. Therefore, logging data cannot be saved in situations where the software such as the basic software and application driver cannot be operated. There's a problem.

  For this reason, when an abnormal stop occurs in a situation where the basic software such as the system is starting up and software such as an application driver cannot be operated, it is impossible to save the cause of the stop.

  If the logging data of the system stop factor is not saved, it may take a very long time to investigate the cause of the system failure, or it may not be possible to investigate the cause of the stop factor with a low occurrence frequency.

  By the way, in addition to the system abnormality detected by the POST diagnosis, the cause of the stop of the arithmetic processing unit of the information processing apparatus is a malfunction caused by an erroneous operation or noise of the power switch or the system reset switch, an overheating of an electronic component in operation, The system may stop due to a drop in the power supply voltage.

  Therefore, the present invention provides an information processing apparatus capable of reliably storing a stop factor signal generated during any of normal processing, start-up processing, and stop processing in a nonvolatile memory. For the purpose.

In order to achieve the above object, an information processing apparatus according to claim 1 of the present invention is an information processing apparatus including an arithmetic processing unit and a stop factor processing unit of the arithmetic processing device, wherein the arithmetic processing unit includes: Yes a central processing unit comprising an abnormality detection circuit for detecting an abnormality of the processing unit itself, and the system reset switch of said central processing unit, and a power supply unit of the arithmetic processing unit, and a power switch of the power supply unit The central processing unit controls a reset delay circuit that delays an output signal of the system reset switch and an output signal of the reset delay circuit and diagnoses an abnormality of the central processing unit itself. A CPU control circuit including the abnormality detection circuit to be output to the outside, and a main memo of the CPU control circuit connected via a bus of the CPU control circuit And an input / output interface circuit connected via the bus, wherein the power supply unit is a power supply off-delay circuit for off-delaying the output signal of the power switch, and an output signal of the power supply off-delay circuit. A power supply circuit that controls the output of the power supply and a voltage drop detection circuit that detects a drop in the output of the power supply circuit, wherein the stop factor processing unit is the power switch, the system reset switch, and the voltage drop detection circuit From the stop factor signal from the, further input the stop factor signal output from the abnormality detection circuit,
Has a stop cause storage control unit for displaying together and stores these stopping cause signal, a nonvolatile memory for storing the stop factor signal, and a display unit that displays the stop factor signal, said information processing apparatus Is characterized in that the stop factor signal generated during any of the normal process, the start process, and the stop process is stored in an identifiable manner.

  The timing to guarantee that the power ON / OFF signal, the system reset switch signal and the abnormality detection signal of the central processing unit are reliably written, or the voltage that guarantees the operation is reliably supplied, and the generated stop factor signal is canceled. An information processing apparatus capable of reliably storing and displaying a stop factor signal generated during a normal process, an activation process, or a stop process of the information processing apparatus is provided. I can do it.

  Hereinafter, description will be given with reference to the drawings.

  An information processing apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an information processing apparatus according to the present invention.

  The information processing apparatus according to the present invention includes an arithmetic processing unit 1, a stop factor processing unit 2, and a peripheral device 3. The peripheral processing device 3 is appropriately changed according to system requirements.

  The arithmetic processing unit 1 includes a central arithmetic processing unit 11, a power supply unit 12, a power switch 13 and a system reset switch 14.

  Next, the configuration of each unit will be described. The central processing unit 11 receives a signal from the CPU control circuit 11a that controls this processing unit and the system reset switch 14, and delays this signal by a predetermined time to be supplied to the CPU control circuit 11a. A circuit 11b, a main memory 11c directly accessed by the CPU control circuit 11a, an input / output interface circuit 11d of a peripheral device controlled by the CPU control circuit 11a, a CPU control circuit bus 11e for connecting these components, and an expansion bus 11f It consists of.

  Further, the CPU control circuit 11a is provided with an abnormality detection circuit 11a1 for detecting a temperature abnormality of an electronic component including the CPU and a control operation abnormality of the CPU control circuit 11a by the CPU control circuit 11a itself. This control operation abnormality is configured such that, for example, an expansion bus error, a memory access error, or the like is detected by its own CPU control circuit.

  The output of the abnormality detection circuit 11a is transmitted to the power supply circuit 12a and a later-described stop factor storage control unit 21 via the expansion bus 11f.

  Next, the power supply unit 12 includes a power supply circuit 12a that supplies power to each unit of the arithmetic processing unit 1 and the stop factor processing unit 2, a voltage drop detection circuit 12b that monitors an output abnormality of the power supply circuit 12a, a power switch 13 includes a power supply off delay circuit 12c that receives the 13 signals and delays the timing when the output of the power supply circuit 12a is turned off.

  Further, the stop factor processing unit 2 receives signals from the power switch 13, the system reset switch 14, and the voltage drop detection circuit 12b, and also receives a stop factor signal from the abnormality detection circuit 11a1 via the expansion bus 11. The stop factor storage control unit 21 that executes control for storage and display, the nonvolatile memory 22 that stores the stop factor signal by controlling the write / read operation by the stop factor storage control unit 21, and the display unit 23 It consists of.

  The non-volatile memory 22 is configured by a ROM or a flash memory, and the display unit 23 may be a display such as an LED that can determine a stop factor signal.

  The peripheral device 3 includes an external storage device, an input / output device, a communication device, and the like (not shown).

  Next, the operation of the information processing apparatus configured as described above will be described. When the power switch 13 of the information processing apparatus is turned on, a built-in POST is executed, a system abnormality is automatically diagnosed, and basic software and application software are started up.

  Then, the power switch 13 or the system reset switch 14 after the start of the information processing apparatus is erroneously operated for some reason, malfunctions due to noise, an abnormal temperature of an electronic component in operation, or a decrease in supply power voltage Etc. may occur.

  When the abnormality detection circuit 11a exceeds a predetermined abnormality determination level, an abnormality such as a temperature abnormality of the electronic component being operated or a drop in the supply power supply voltage is detected and a stop factor signal is generated.

  Further, the stop factor signal detected by the abnormality detection circuit 11a such as an extended bus error or a memory access error is input by assigning the signal detected in advance to the stop factor storage control circuit 21. As long as the voltage supplied to is normal, it is correctly identified and stored in the nonvolatile memory 22.

  However, when the power switch 13 is erroneously operated or malfunctioned for some reason, the power circuit 12a is shut down, and when the output of the power circuit 12a falls below the normal value range, the stop factor signal It is conceivable that none of these are stored in the nonvolatile memory 22.

  However, in the configuration of the present invention, a power off delay circuit 12c is provided between the power switch 13 and the power circuit 12a, and a reset delay circuit 11b is provided between the system reset switch 14 and the CPU control circuit 11a. Even if the switch signal is input, the stop factor signal is delayed by the time to be written in the nonvolatile memory 22, so that it is reliably stored before the output from the power supply circuit 12a is lowered, and then the reset processing operation is started. .

  At this time, the abnormality detection set value of the voltage drop detection circuit 12b needs to be set as a set value in the range of the operable lower limit.

  With such a configuration, a stop factor signal during stop processing of the information processing apparatus due to an erroneous operation or malfunction can be identified and stored in the nonvolatile memory 22, and the factor can be displayed on the display unit 22.

  If the output signal of the POST diagnosis is input to the stop factor storage control unit 21 via the expansion bus 11f, the POST signal can be stored and displayed at the same time.

  FIG. 2 is a configuration diagram of the information processing apparatus according to the second embodiment of this invention. Regarding the respective parts of this embodiment, the same parts as those of the information processing apparatus of the first embodiment of FIG.

  The difference between the second embodiment and the first embodiment is that, in the first embodiment, the voltage supplied from the power supply unit 12 is guaranteed until the timing at which the stop factor signal is reliably stored in the nonvolatile memory 22. The signals are delayed from the power switch 13 and the system reset switch 14, but in the second embodiment, the secondary battery 12c is mounted in the power supply unit 12, and the central information processing unit 11 and the stop factor processing unit 2 are installed. Thus, the stop factor signal is surely stored in the non-volatile memory 22 even if the output of the power supply circuit 12a is lowered by always supplying a voltage.

  According to the second embodiment, since the secondary battery is provided, there is no possibility of malfunction of the storage process of the abnormal stop factor signal due to a decrease in the power of the stop factor processing unit 2, and the start process, the normal process, and the stop It is possible to identify, store, and display a stop factor signal of the information processing apparatus due to an erroneous operation or an erroneous signal during any processing.

  The present invention is not limited to the above-described embodiment, and includes a stop factor signal detection unit, a memory writing unit that identifies and writes the stop factor signal, and a unit that guarantees the write timing. Any modifications can be made without departing from the spirit of the present invention.

The block diagram of Example 1 of the information processing apparatus of this invention. The block diagram of Example 2 of the information processing apparatus of this invention.

Explanation of symbols

1 arithmetic processing unit 2 stop factor processing unit 3 peripheral device 11 central processing unit 11a CPU control circuit 11b reset delay circuit 11c main memory 11d input / output interface circuit 11e CPU control circuit bus 11f expansion bus 12 power supply unit 12a power supply circuit 12b voltage drop Detection circuit 12c Secondary battery 13 Power switch 14 System reset switch 21 Stop factor storage control unit 22 Non-volatile memory 23 Display unit

Claims (2)

An information processing device comprising an arithmetic processing unit and a stop factor processing unit of the arithmetic processing device,
The arithmetic processing unit includes a central arithmetic processing unit including an abnormality detection circuit that detects an abnormality of the arithmetic processing unit itself, a system reset switch of the central arithmetic processing unit, a power source unit of the arithmetic processing unit, and the power source unit And a power switch
The central processing unit is configured to delay the output signal of the system reset switch, and to control a reset operation using the output signal of the reset delay circuit and diagnose an abnormality of the central processing unit itself to the outside. C including the abnormality detection circuit to output
A PU control circuit, a main memory of the CPU control circuit connected via a bus of the CPU control circuit, and an input / output interface circuit connected via the bus;
The power supply unit detects a decrease in the output of the power supply circuit, a power supply off delay circuit that off-delays the output signal of the power switch, a power supply circuit that controls its output with the output signal of the power supply off-delay circuit, and A voltage drop detection circuit,
The stop factor processing unit inputs a stop factor signal from the power switch, the system reset switch, and the voltage drop detection circuit, and further inputs a stop factor signal output from the abnormality detection circuit. displaying a stop cause storage control unit for displaying together with storing the signal, and non-volatile memory for storing the stop factor signal, the stop signal
A display unit ,
An information processing apparatus characterized in that the stop factor signal generated during any one of a normal process, a start process, and a stop process is stored in an identifiable manner. 2. The information processing according to claim 1, wherein delay times of the power off delay circuit and the reset delay circuit are delayed more than a time required for writing the stop factor signal to the nonvolatile memory . apparatus.

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