JP4879530B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor element such as a thin film transistor (hereinafter referred to as a thin film transistor (TFT)), and a method for manufacturing a semiconductor device having a circuit including such a semiconductor element. The present invention relates to an electro-optical device represented by a luminescence display device, an EC display device, etc. Also, an electrical device for improving processing speed, such as a central processing unit (CPU), formed using TFTs, The present invention also relates to an electro-optical device and an electronic apparatus in which the electric device is mounted as a component.

  In recent years, a technology for manufacturing a semiconductor element such as a TFT on a substrate has greatly advanced, and application development to, for example, an active matrix type display device has been advanced. In particular, a TFT using a crystalline semiconductor film has higher field effect mobility (also referred to as mobility) than a TFT using a conventional amorphous semiconductor film, and thus can operate at high speed.

  By the way, as a substrate used for a semiconductor device, a glass substrate is considered promising rather than a single crystal silicon substrate in terms of cost. However, when forming a semiconductor element on a glass substrate, the semiconductor element must be manufactured at a temperature at which the glass substrate does not melt.

  In order to obtain a crystalline semiconductor film used for a semiconductor element, it is necessary to crystallize an amorphous semiconductor material or to crystallize an amorphous component contained in the semiconductor material to further improve crystallinity. Is required (see, for example, Patent Document 1).

  In order to obtain a crystalline semiconductor film, a technique is known in which a catalyst element for promoting crystallization is added to an amorphous semiconductor film and then crystallized by heating. However, when the crystalline semiconductor film obtained by such a method is used, there is a possibility that the TFT characteristics are remarkably deteriorated by the catalytic element contained in the film. In particular, the off current of the TFT may increase.

  Therefore, in order to suppress such deterioration of TFT characteristics, it is necessary to remove (getter) the catalyst element in the crystalline semiconductor film.

  In order to getter the catalytic element, there is a method using a semiconductor film doped with phosphorus. For example, a silicon film is newly formed as an upper layer and heat treatment is performed, or phosphorus is added to a part of the semiconductor film to form a region with high phosphorus concentration, and then heat treatment is performed, so that a portion with high phosphorus concentration is obtained. A catalyst element in a semiconductor film is moved to getter the catalyst element in the film (see, for example, Patent Document 2).

  3A to 3D and FIGS. 4A to 4B show a conventional TFT manufacturing process. First, the gate electrode 1001, the gate insulating film 1002, and the amorphous semiconductor film 1003 are formed over the substrate 1000.

  Next, a solution 1004 containing a catalytic element is applied over the amorphous semiconductor film 1003 by a spin coating method (FIG. 3A).

  After application of the solution containing the catalytic element, the amorphous semiconductor film 1003 is crystallized by first heat treatment to form a crystalline semiconductor film 1005 (FIG. 3B).

  Further, a semiconductor film 1006 containing an element selected from Group 15 (typically phosphorus (P), arsenic (As), antimony (Sb)) is formed over the crystalline semiconductor film 1005, and the second Heat treatment is performed. By the second heat treatment, the catalytic element in the crystalline semiconductor film 1005 moves to the semiconductor film 1006 containing an element selected from Group 15, that is, the catalytic element is gettered (FIG. 3C).

  Next, an island-shaped stacked film is formed using the crystalline semiconductor film 1005 and the semiconductor film 1006 containing an element selected from Group 15 (FIG. 3D). Further, a conductive film 1007 is formed so as to cover the island-shaped stacked film (FIG. 3E). Next, part of the conductive film is removed using a mask, so that the source or drain electrode 1008 is formed (FIG. 4A).

  Next, using the source or drain electrode 1008 as a mask, the semiconductor film 1006 containing an element selected from Group 15 of the island-shaped stacked film is completely removed, and part of the crystalline semiconductor film 1005 is removed to remove the film thickness. Is made thinner (FIG. 4B).

Through the above steps, an inverted staggered TFT having a source or drain region 1009 and a channel formation region 1010 is formed.
JP-A-11-160734 JP-A-11-97706

  In the conventional method, two heat treatment steps of (1) heat treatment for crystallization and (2) heat treatment for catalytic element gettering are necessary. In the manufacturing process of a semiconductor element, an increase in the number of steps directly leads to a high cost and a decrease in yield.

  Therefore, the object of the present invention is to enable gettering of the catalytic element simultaneously with crystallization and to reduce the heat treatment process.

  According to the present invention, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, an amorphous semiconductor film is formed on the gate insulating film, and 15A is formed on the amorphous semiconductor film. A semiconductor film containing an element selected from the group is formed, and an island-shaped amorphous semiconductor film and an island-shaped semiconductor film are formed using the amorphous semiconductor film and the semiconductor film including an element selected from the group 15, respectively. Forming a source electrode or a drain electrode on the island-shaped semiconductor film, using the source electrode or the drain electrode as a mask, removing a part of the island-shaped semiconductor film to form a source region or a drain region; And reducing the thickness of the island-shaped amorphous semiconductor film and exposing a part thereof to promote crystallization of the island-shaped amorphous semiconductor film in the exposed region of the island-shaped amorphous semiconductor film. Introducing a catalytic element, the source region or drain And heating the island region and the island-shaped amorphous semiconductor film to crystallize the island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film, and gettering the catalytic element to the source or drain region The present invention relates to a method for manufacturing a semiconductor device.

  According to the present invention, when a crystalline semiconductor film is formed using a catalyst that promotes crystallization, and a semiconductor device is manufactured using the film, the heating process of crystallization and gettering can be performed at one time. The manufacturing process can be reduced.

  In the present invention, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, an amorphous semiconductor film is formed on the gate insulating film, and the amorphous semiconductor film is formed on the amorphous semiconductor film. A semiconductor film containing an element selected from Group 15 is formed, and the amorphous semiconductor film and the semiconductor film containing an element selected from Group 15 are used to form an island-shaped amorphous semiconductor film and an island-shaped semiconductor film, respectively. A source electrode or a drain electrode is formed on the island-shaped semiconductor film, and a part of the island-shaped semiconductor film is removed using the source electrode or the drain electrode as a mask to form a source region or a drain region. And reducing the film thickness of the island-shaped amorphous semiconductor film and exposing a part thereof, forming a mask covering the exposed region of the source or drain electrode and the island-shaped amorphous semiconductor film, The island-shaped amorphous semiconductor film Etching the mask on the exposed region to form a window, exposing a part of the island-shaped amorphous semiconductor film, and part of the island-shaped amorphous semiconductor film through the window, A catalyst element that promotes crystallization of the island-shaped amorphous semiconductor film is introduced, the source region or drain region and the island-shaped amorphous semiconductor film are heated, and the island-shaped amorphous semiconductor film is crystallized to form islands. The present invention relates to a method for manufacturing a semiconductor device, wherein a crystalline semiconductor film is formed and the catalytic element is gettered to the source region or the drain region.

  By providing the window for adding the catalytic element, the catalytic element to be added can be further reduced, and the lateral growth region where the crystal grows in the direction parallel to the substrate can be increased.

  In the present invention, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, an amorphous semiconductor film is formed on the gate insulating film, and the amorphous semiconductor film is formed on the amorphous semiconductor film. A semiconductor film containing an element selected from Group 15 is formed, and the amorphous semiconductor film and the semiconductor film containing an element selected from Group 15 are used to form an island-shaped amorphous semiconductor film and an island-shaped semiconductor film, respectively. A source electrode or a drain electrode is formed on the island-shaped semiconductor film, and a part of the island-shaped semiconductor film is removed using the source electrode or the drain electrode as a mask to form a source region or a drain region. And reducing the film thickness of the island-shaped amorphous semiconductor film and exposing a part thereof to promote crystallization of the island-shaped amorphous semiconductor film in the exposed region of the island-shaped amorphous semiconductor film. Introducing the catalytic element, the source region or A rain region and the island-shaped amorphous semiconductor film are heated, and the island-shaped amorphous semiconductor film is crystallized to form an island-shaped crystalline semiconductor film, and the catalytic element is gettered to the source region or the drain region. The present invention relates to a method for manufacturing a semiconductor device, wherein a wiring electrically connected to the source electrode or the drain electrode is formed.

  In the present invention, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, an amorphous semiconductor film is formed on the gate insulating film, and the amorphous semiconductor film is formed on the amorphous semiconductor film. A semiconductor film containing an element selected from Group 15 is formed, and the amorphous semiconductor film and the semiconductor film containing an element selected from Group 15 are used to form an island-shaped amorphous semiconductor film and an island-shaped semiconductor film, respectively. Forming a mask over the island-shaped semiconductor film, using the mask to remove a part of the island-shaped semiconductor film to form a source region or a drain region, and to form the island-shaped amorphous semiconductor Reducing the thickness of the film and exposing a part thereof, and introducing a catalytic element that promotes crystallization of the island-shaped amorphous semiconductor film into the exposed region of the island-shaped amorphous semiconductor film; Heating the region or drain region and the island-shaped amorphous semiconductor film; The island-shaped amorphous semiconductor film is crystallized to form an island-shaped crystalline semiconductor film, and the catalyst element is gettered to the source region or the drain region and electrically connected to the source region or the drain region. The present invention relates to a method for manufacturing a semiconductor device, characterized in that the step is formed.

  In the present invention, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, an amorphous semiconductor film is formed on the gate insulating film, and the amorphous semiconductor film is formed on the amorphous semiconductor film. A semiconductor film containing an element selected from Group 15 is formed, an element selected from Group 13 is introduced into the semiconductor film containing an element selected from Group 15, and the amorphous semiconductor film and Groups 15 and 13 are introduced. An island-shaped amorphous semiconductor film and an island-shaped semiconductor film are formed using a semiconductor film containing an element selected from the group, and a source electrode or a drain electrode is formed on the island-shaped semiconductor film, and the source Using the electrode or drain electrode as a mask, a part of the island-shaped semiconductor film is removed to form a source region or a drain region, and the thickness of the island-shaped amorphous semiconductor film is reduced and a part is exposed, The island-shaped amorphous semiconductor film exposed A catalyst element for promoting crystallization of the island-shaped amorphous semiconductor film is introduced into the region, the source region or drain region and the island-shaped amorphous semiconductor film are heated, and the island-shaped amorphous semiconductor film is heated The present invention relates to a method for manufacturing a semiconductor device, wherein an island-like crystalline semiconductor film is formed by crystallization and the catalyst element is gettered to the source region or the drain region.

  In the present invention, the wiring may be formed of a low melting point conductive material.

  In the present invention, the wiring may be formed by sputtering, droplet ejection, or CVD.

  In the present invention, the catalyst elements are nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold One element selected from (Au) or a plurality of elements.

  In the present invention, the source electrode or the drain electrode is one element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material containing the element as a main component or It contains compound materials.

  In the present invention, the element selected from group 15 and / or the element selected from group 13 can be activated by the heating.

  According to the present invention, since crystallization and gettering can be performed at the same time, only one heat treatment step is required, which greatly reduces the number of steps. In addition, crystallinity can be improved by crystallization becoming a lateral growth process. By reducing the number of steps, cost increases and yield reduction can be suppressed.

  This embodiment will be described with reference to FIGS. 1A to 1D and FIGS. 2A to 2D.

  First, a conductive film is formed over the substrate 100, and the gate electrode 101 is formed using the conductive film. As the substrate 100, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. It is also possible to use a substrate made of a plastic such as PET, PES, or PEN, or a flexible synthetic resin such as acrylic.

  The gate electrode 101 is formed using a structure in which a single conductive film or two or more conductive films are stacked. As the conductive film, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material or a compound material containing the element as a main component is used. Also good. Alternatively, the gate electrode 101 may be formed using a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P). In this embodiment mode, the gate electrode 101 is formed using tungsten (W) or molybdenum (Mo).

  The gate electrode 101 may be formed integrally with the wiring, or the gate electrode 101 and the gate wiring may be separately formed and electrically connected.

  After forming the gate electrode 101, a gate insulating film 102 is formed over the gate electrode 101 and the substrate 100. As the gate insulating film 102, an insulating film such as a silicon oxide film, a silicon nitride film, a silicon nitride film containing oxygen, or a silicon oxide film containing nitrogen can be used. The gate insulating film 102 also serves to prevent alkali metals such as Na and alkaline earth metals contained in the substrate 100 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. In this embodiment, silicon oxide is deposited by plasma CVD to form the gate insulating film 102.

  Although an example in which a single-layer film is used as the gate insulating film 102 is shown here, a structure in which two or more insulating films are stacked may be used.

  Next, an amorphous semiconductor film 103 is formed over the gate insulating film 102 (FIG. 1A). As the amorphous semiconductor film 103, silicon (Si) or a silicon germanium (SiGe) alloy may be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%. In this embodiment mode, an amorphous silicon film to which an element selected from non-doped or group 13 such as boron (B) is added by a plasma CVD method is formed as the amorphous semiconductor film 103.

  Next, a semiconductor film 104 into which an element selected from Group 15 is introduced is formed over the amorphous semiconductor film 103. The semiconductor film into which an element selected from the group 15 is introduced not only serves as a source region and a drain region in a later process, but also serves as a gettering region for a catalyst element for crystallization (FIG. 1B). ). In the present embodiment, phosphorus (P) is used as an element selected from Group 15.

  Next, the gate insulating film 102, the amorphous semiconductor film 103, and the semiconductor film 104 into which an element selected from the group 15 is introduced are formed in an island shape using a mask. Thus, an island-shaped region 113 including the island-shaped amorphous semiconductor film 111 and the island-shaped semiconductor film 112 is formed (FIG. 1C).

  After that, the conductive film 105 is formed so as to cover the island region 113 (FIG. 1D). When a metal film is used for the conductive film, the silicide is formed by reacting with the island-shaped semiconductor film 112 in a later thermal process, so that conductivity is improved. In addition, since this conductive film is used as a mask when the island-shaped amorphous semiconductor film 111 and the island-shaped semiconductor film 112 are etched in a later step, a material that can have a selection ratio with the island-shaped semiconductor film 112 is preferable.

  As the conductive film 105, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material or a compound material containing the element as a main component, or a single layer You may use what was laminated | stacked. In this embodiment mode, tungsten (W) or molybdenum (Mo) is used as the conductive film.

  Next, a resist mask is formed over the conductive film, and the source or drain electrode 106 is formed using the conductive film (FIG. 2A). Further, the island region 113 is etched using the source or drain electrode 106 as a mask. In this embodiment mode, wet etching is performed using a tetramethylammonium hydroxide (TMAH) aqueous solution. However, the etching time is adjusted so that the island-shaped amorphous semiconductor film 111 is not completely removed. Of course, you may etch using dry etching.

  The source or drain electrode 106 may be formed integrally with the wiring, or the source or drain electrode 106 and the wiring may be separately formed and electrically connected.

  As a result, the entire region of the island-shaped semiconductor film 112 that is not covered with the source or drain electrode 106 is removed, and the source or drain region 107 is formed. Further, the thickness of the island-shaped amorphous semiconductor film 111 is reduced, and the region 114 that is not covered with the source or drain electrode 106 is exposed (FIG. 2B).

  Next, a thin oxide film is formed on the surface of the exposed region 114 of the island-shaped amorphous semiconductor film 111. The oxide film is formed so that a solution containing a catalytic element to be applied in a later step is uniformly applied to the region 114.

  This thin oxide film is formed by oxidation treatment with water (ozone water) in which ozone is dissolved in water, heat treatment in an oxidation atmosphere, or irradiation with UV light. In this embodiment, a thin oxide film is formed by applying ozone water.

  Next, a catalyst element that promotes crystallization of the region 114 semiconductor film is introduced. The introduction method includes a method in which the catalyst element is dispersed in a solution and introduced by a spin coating method, and a method in which the catalyst element is introduced by plasma treatment using an electrode containing the catalyst element (FIG. 2C). ).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  As a method for introducing the catalytic element, a method in which the catalytic element is dispersed in a solution and introduced by a spin coating method, or a method in which the catalytic element is introduced by plasma treatment using an electrode containing the catalytic element is used. Is possible. In this embodiment mode, nickel (Ni) is used as a catalyst element, and a nickel acetic acid solution is applied to the surface of the region 114 by a spin coating method.

  Next, hydrogen in the island-shaped amorphous semiconductor film 111 is released by holding at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming a dangling bond in the island-shaped amorphous semiconductor film 111.

  Then, the island-shaped amorphous semiconductor film 111 is crystallized by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere. With this catalytic element, the crystallization temperature of the island-shaped amorphous semiconductor film 111 can be set to a relatively low temperature of 550 to 600 ° C.

  By this heat treatment, crystallization proceeds in parallel with the substrate from the region where the catalyst element is introduced. Further, the catalytic element moves with crystallization from the added region and is gettered to the source region or the drain region 107. Thus, a crystalline semiconductor film 109 with reduced catalytic elements can be obtained (FIG. 2D).

  An element selected from Group 15 such as phosphorus hardly moves in an environment of 550 to 600 ° C. in the semiconductor film, so that the element selected from Group 15 and the catalytic element are substantially contained in crystalline semiconductor film 109 by heat treatment. Region (channel forming region) 108 that does not exist and a region where an element selected from Group 15 and a catalytic element coexist can be formed (FIG. 2E).

  Further, phosphorus functions as a dopant for the N-channel TFT as it is. In the present embodiment, it has been found that although the catalytic element remains in the source region or the drain region, it hardly affects the element characteristics. It is convenient for the catalytic element to segregate in the source region or the drain region to reduce the resistance of the region.

  In this embodiment mode, an N-channel TFT is manufactured. However, if a P-channel TFT is manufactured, an element selected from Group 13 is introduced into the semiconductor film 104 into which an element selected from Group 15 is introduced. do it.

  As an element selected from Group 13, boron (B) or gallium (Ga) can be used.

  Further, by this heat treatment, an element selected from Group 15 or Group 13 included in the source region or drain region 107 can be activated.

  From the above, an inverted staggered TFT having the source or drain region 107 and the channel formation region 108 can be formed.

  As described above, according to the present invention, conventionally, the heat treatment for crystallization and the heat treatment for gettering had to be performed separately.

  This embodiment will be described with reference to FIGS. 7A to 7C, FIGS. 8A to 8D, and FIGS. 9A to 9C.

  First, as shown in FIG. 7A, gate electrodes 501 to 503 are formed over a substrate 500. As the substrate 500, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. It is also possible to use a substrate made of a plastic such as PET, PES, or PEN, or a flexible synthetic resin such as acrylic.

  The gate electrodes 501 to 503 are formed using a structure in which a single conductive film or two or more conductive films are stacked. In the case where two or more conductive films are stacked, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material containing the element as a main component, or The gate electrodes 501 to 503 may be formed by stacking compound materials. Alternatively, the gate electrode may be formed using a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P).

  In this embodiment, the gate electrodes 501 to 503 are formed as follows. First, as the first conductive film, for example, a tantalum nitride (TaN) film is formed with a thickness of 10 to 50 nm, for example, 30 nm. Then, as the second conductive film, for example, a tungsten (W) film is formed with a thickness of 200 to 400 nm, for example, 370 nm on the first conductive film, and a stacked film of the first conductive film and the second conductive film is formed. Form.

  Next, the first conductive film and the second conductive film are etched to form gate electrodes 501 to 503.

  Next, a gate insulating film 504 is formed over the gate electrodes 501 to 503. For the gate insulating film 504, for example, an insulating film single layer such as silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen, or insulating such as silicon oxide, silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen is used. A stacked film in which a plurality of films are stacked can be used. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. In this embodiment, a silicon oxide film containing nitrogen is formed with a thickness of 10 nm to 400 nm, for example, 50 nm by a plasma CVD method.

  The gate insulating film 504 prevents an alkali metal such as Na or an alkaline earth metal contained in the substrate 500 from diffusing into a semiconductor film manufactured in a later step and adversely affecting the characteristics of the semiconductor element. There is also work.

  Next, an amorphous semiconductor film 505 is formed over the gate insulating film 504. The film thickness of the amorphous semiconductor film 505 is 100 nm to 200 nm. As the semiconductor, not only silicon (Si) but also silicon germanium (SiGe) can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

A semiconductor film 506 into which an element selected from Group 15 is introduced is formed with a thickness of 50 nm to 100 nm over the amorphous semiconductor film 505. The semiconductor film 506 into which an element selected from the group 15 is introduced becomes not only a source region and a drain region in a later process, but also a gettering region for a catalyst element for crystallization. In this embodiment, as the semiconductor film 506, an amorphous silicon film containing phosphorus (P) at a concentration of 1 × 10 ¹⁹ cm ⁻³ to 8 × 10 ¹⁹ cm ⁻³ and formed by a plasma CVD method is used.

Next, the semiconductor film 506 is covered with a mask 507 except for a region which will later become a P-channel TFT 521, and an element selected from Group 13 is introduced (FIG. 7B). In this embodiment, boron (B) is used as an element selected from Group 13, and an ion implantation method is performed so that the concentration in the semiconductor film 506 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²¹ cm ^−3. Alternatively, an ion doping method is used to form a P-type impurity region 508 (FIG. 7C).

  Next, as illustrated in FIG. 8A, an island-shaped region 556 including an island-shaped amorphous semiconductor film 550 and an island-shaped semiconductor film 553 is formed using an amorphous semiconductor film 505 and a semiconductor film 506, An island-shaped region 557 including the crystalline semiconductor film 551 and the island-shaped semiconductor film 554 and an island-shaped region 558 including the island-shaped amorphous semiconductor film 552 and the island-shaped semiconductor film 555 are formed.

  Next, a conductive film 509 is formed so as to cover the island regions 556 to 558 (FIG. 8B). As the conductive film 509, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material or a compound material containing the element as a main component is stacked. May be used.

  Next, electrodes 510 to 514 are formed using the conductive film 509. The electrodes 510 to 514 are respectively connected to the source region or drain region of the TFT, and in particular, the electrode 511 connects the source region or drain region of the N-channel TFT and the source region or drain region of the P-channel TFT ( FIG. 8C).

Next, using the electrodes 510 to 514 as masks, the island-shaped semiconductor films 553 to 555 and the island-shaped amorphous semiconductor films 550 to 552 into which an element selected from Group 15 is introduced are etched. In this embodiment, etching is performed using CF ₄ and O ₂ as an etching gas by a dry etching method. However, the etching time is adjusted so that the island-shaped amorphous semiconductor films 550 to 552 are not completely removed. Needless to say, etching may be performed using wet etching (FIG. 8D).

  Next, a catalytic element is introduced into the regions 560 to 562 which are exposed by etching and are not covered with the electrodes 510 to 514 of the island-shaped amorphous semiconductor films 550 to 552 (FIG. 9A).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  As a method for introducing the catalytic element, a method in which the catalytic element is dispersed in a solution and introduced by a spin coating method, or a method in which the catalytic element is introduced by plasma treatment using an electrode containing the catalytic element is used. Is possible. In this embodiment mode, nickel (Ni) is used as a catalytic element, and a nickel acetic acid solution is applied to a region of the amorphous semiconductor film 505 that is not covered with the electrodes 510 to 514 by a spin coating method.

  Note that in the case where the catalyst element is introduced using a solution containing the catalyst element, before the catalyst element is introduced into the regions 560 to 562, a thin oxide film is formed over the surface of the regions 560 to 562, so The wettability of a solution containing a catalytic element with respect to the crystalline semiconductor films 550 to 552 can be improved. In this embodiment, this thin oxide film is formed by UV irradiation.

  Next, hydrogen in the island-shaped amorphous semiconductor films 550 to 552 is released by maintaining the temperature at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming dangling bonds in the island-shaped amorphous semiconductor films 550 to 552.

  Then, by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere, the island-shaped amorphous semiconductor films 550 to 552 are crystallized to form island-shaped crystalline semiconductor films 520 to 522. By this heat treatment, the catalyst element moves with crystallization from the added region simultaneously with crystallization, and is gettered to the source or drain regions 524, 527, and 530. Thus, island-like crystalline semiconductor films 520 to 522 with reduced catalytic elements can be obtained (FIG. 9B).

  Further, by this heating step, an element selected from Group 15 and Group 13 included in the source region or drain region 524, 527, 530 can be activated.

  From the above, an inverted staggered N-channel TFT 540, a P-channel TFT 541, and an N-channel TFT 542 are formed. Further, the N-channel TFT 540 and the P-channel TFT 541 form a CMOS circuit 543.

  The N-channel TFT 540 includes a channel formation region 525, a source or drain region 524, and an intrinsic region 523. The P-channel TFT 541 includes a channel formation region 528, a source region or drain region 527, and an intrinsic region 526. The N-channel TFT 542 includes a channel formation region 531, a source or drain region 530, and an intrinsic region 529 (FIG. 9C).

  In addition, only a P-channel TFT can be manufactured by the process shown in this embodiment. That is, as shown in FIGS. 7B to 7C, by introducing an element selected from Group 13 into an amorphous semiconductor film containing an element selected from Group 15, a P-type impurity region is obtained. Can be formed. Thereafter, by using the steps shown in FIGS. 8A to 8D and FIGS. 9A to 9C, a P-channel TFT can be manufactured independently.

  In addition, this embodiment can be freely combined with any description of the embodiment mode if necessary.

  In this embodiment, an example in which a catalytic element is added more selectively will be described with reference to FIGS. 5A to 5D and FIGS. 6A to 6B.

  First, based on the steps described in the embodiment, the etching up to the island-shaped region 113 illustrated in FIG. Note that the same portions as those in the embodiment are denoted by the same reference numerals (FIG. 5A).

  Next, a mask 201 is formed so as to cover the exposed region 114 of the source or drain electrode 106 and the island-shaped amorphous semiconductor film 111. As the mask 201, heat treatment is performed in a later step; therefore, a heat resistant material may be used. For example, silicon oxide, silicon nitride, silicon nitride containing oxygen, or silicon oxide containing nitrogen is used. In this embodiment, silicon oxide is used as the mask 201. The mask 201 is provided with a window 200 for introducing a catalytic element on the region 114 by etching.

  Next, a catalytic element that promotes crystallization of the semiconductor film is introduced into the window 200. The introduction method includes a method in which the catalyst element is dispersed in a solution and introduced by a spin coating method, and a method in which the catalyst element is introduced by plasma treatment using an electrode containing the catalyst element (FIG. 5C). ).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  In this embodiment, nickel (Ni) is used as a catalytic element, and a nickel acetic acid solution is applied to the surface of the island-shaped amorphous semiconductor film 111 through the window 200 by a spin coating method.

  When the catalyst element is dispersed in a solution and introduced by spin coating, a thin oxide film is formed on the surface of the region exposed by the window 200 of the island-shaped amorphous semiconductor film 111 before the introduction of the catalyst element. It is preferable to improve the wettability of the island-shaped amorphous semiconductor film 111 to a solution. This thin oxide film is formed by oxidation treatment with water (ozone water) in which ozone is dissolved in water, heat treatment in an oxidation atmosphere, or irradiation with UV light. In this embodiment, a thin oxide film is formed by applying ozone water.

  Next, hydrogen in the island-shaped amorphous semiconductor film 111 is released by holding at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming a dangling bond in the island-shaped amorphous semiconductor film 111.

  Then, the island-shaped amorphous semiconductor film 111 is crystallized by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere. With this catalytic element, the crystallization temperature of the island-shaped amorphous semiconductor film 111 can be set to a relatively low temperature of 550 to 600 ° C.

  By this heat treatment, crystallization proceeds in parallel with the substrate from the region where the catalyst element is introduced. Further, the catalytic element moves from the added region with crystallization and is gettered to the source region or the drain region 203 (FIG. 5D). Thus, a crystalline semiconductor film 202 with reduced catalytic elements can be obtained (FIG. 6A).

  Further, by this heating step, an element selected from Group 15 or Group 13 included in the source region or drain region 203 can be activated.

  Next, it heats at 350-450 degreeC in a hydrogen atmosphere, Preferably it is 410-420 degreeC. Accordingly, the crystalline semiconductor film 202 can be hydrogenated. In other words, dangling bonds existing in the crystalline semiconductor film 202 can be terminated.

  Further, instead of heating in a hydrogen atmosphere, a new silicon nitride film or a silicon nitride film containing oxygen is formed on the mask 201 and heated at 350 to 450 ° C., preferably 410 to 420 ° C. The conductive semiconductor film 202 can be hydrogenated.

  According to this embodiment, an inverted staggered TFT having a channel formation region 204 and a source or drain region 203 can be manufactured (FIG. 6B).

  In this embodiment, the catalytic element introduction window 200 is further formed on the region 114 using the mask 201, so that the catalytic element can be more selectively introduced into the island-shaped amorphous semiconductor film 111. Therefore, since the introduced region is small, the lateral growth region of the crystalline semiconductor film 202 can be increased, and the amount of the catalyst element to be introduced can be reduced.

  Further, this embodiment can be freely combined with any description in Embodiment Mode and Embodiment 1 if necessary.

  For example, when this embodiment is applied to Embodiment 1, a TFT and a CMOS circuit similar to the structure shown in FIG. 9C can be obtained.

  That is, an N-channel TFT 540, a P-channel TFT 541, and an N-channel TFT 542 are formed over the substrate 500. Further, the N-channel TFT 540 and the P-channel TFT 541 form a CMOS circuit 543.

  The N-channel TFT 540 includes a gate electrode 501, a gate insulating film 504, a channel formation region 525, a source or drain region 524, and an intrinsic region 523. The P-channel TFT 541 includes a gate electrode 502, a gate insulating film 504, a channel formation region 528, a source or drain region 527, and an intrinsic region 526. The N-channel TFT 542 includes a gate electrode 503, a gate insulating film 504, a channel formation region 531, a source or drain region 530, and an intrinsic region 529.

  Further, electrodes 510 and 511 are connected to the source region or drain region 524 of the N-channel TFT 540, electrodes 511 and 512 are connected to the source region or drain region 527 of the P-channel TFT 541, and the source of the N-channel TFT 542 is connected. Electrodes 513 and 514 are connected to the region or drain region 530.

  Note that the electrodes 510 to 514 may be formed integrally with the wiring, or the electrode and the wiring may be formed separately and electrically connected.

  In this embodiment, an example in which a wiring connected to a source electrode or a drain electrode is formed using a low-melting-point conductive material is shown in FIGS. 10A to 10D and FIGS. 11A to 11C. Will be described.

  First, formation of the conductive film 105 illustrated in FIG. 1D is performed based on the steps described in the embodiment. Note that the same portions as those in the embodiment are denoted by the same reference numerals (FIG. 10A).

  Next, a resist mask is formed over the conductive film 105, and the source or drain electrode 301 is formed using the conductive film 105. However, since the wiring is formed separately from the source or drain electrode 301 in a later step, only the source or drain electrode 301 is formed in this step (FIG. 10B).

  Next, the island-shaped region 113 is etched using the source or drain electrode 301 as a mask. An etching method similar to that described in the embodiment may be used. Thus, the region 302 of the island-shaped amorphous semiconductor film 111 that is not covered with the source or drain electrode 301 is exposed (FIG. 10C).

  Next, a catalytic element is introduced into the exposed region 302. The catalyst element and the introduction method thereof are the same as those described in the embodiment (FIG. 10D).

  Next, hydrogen in the island-shaped amorphous semiconductor film 111 is released by holding at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming a dangling bond in the island-shaped amorphous semiconductor film 111.

  Then, the island-shaped amorphous semiconductor film 111 is crystallized by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere.

  By this heat treatment, crystallization proceeds in parallel with the substrate from the region where the catalyst element is introduced. Further, the catalyst element moves from the added region with crystallization and is gettered to the source or drain region 303 (FIG. 11A). Thus, a crystalline semiconductor film 305 with reduced catalytic elements is obtained (FIG. 11B).

  Further, by this heating step, an element selected from Group 15 or Group 13 contained in the source region or drain region 303 can be activated.

  After the crystalline semiconductor film 305 is obtained, a wiring 306 connected to the source or drain electrode 301 is formed (FIG. 11C).

  Since the wiring 306 is formed after the heating step, a low melting point conductive material such as aluminum (Al), silver (Ag), or the like can be used for the wiring 306. For the wiring 306, a sputtering method, a droplet discharge method (inkjet), or a CVD method can be used. In particular, when the wiring 306 is formed by a droplet discharge method, it is not necessary to use a photomask, so that the process can be shortened.

  Through the above steps, an inverted staggered TFT having a channel formation region 304 and a source or drain region 303 is formed.

  Further, this embodiment can be freely combined with any description in Embodiment Mode and Embodiment 1 if necessary.

  For example, when this embodiment is applied to Embodiment 1, the TFT and CMOS circuit shown in FIG. 25 can be obtained.

  That is, an N-channel TFT 941, a P-channel TFT 942, and an N-channel TFT 943 are formed over the substrate 900. The N-channel TFT 941 and the P-channel TF 942 form a CMOS circuit 944.

  The N-channel TFT 941 includes a gate electrode 911, a gate insulating film 901, a channel formation region 920, an island-shaped crystalline semiconductor film 915 including an intrinsic region 918, and a source or drain region 919. The P-channel TFT 942 includes a gate electrode 912, a gate insulating film 901, a channel formation region 923, an island-shaped crystalline semiconductor film 916 including an intrinsic region 921, and a source region or a drain region 922. The N-channel TFT 943 includes a gate electrode 913, a gate insulating film 901, a channel formation region 926, an island-shaped crystalline semiconductor film 917 including an intrinsic region 924, and a source or drain region 925.

  Further, electrodes 931 and 932 are connected to the source region or drain region 919 of the N-channel TFT 941, electrodes 933 and 934 are connected to the source region or drain region 922 of the P-channel TFT 942, and the source of the N-channel TFT 943 is connected. Electrodes 935 and 936 are connected to the region or drain region 925.

  Further, a wiring 951 made of a low melting point conductive material is connected to the electrode 931, a wiring 952 to the electrodes 932 and 933, a wiring 953 to the electrode 934, a wiring 954 to the electrode 935, and a wiring 955 to the electrode 936. Has been.

  In this embodiment, another example in which a wiring connected to a source electrode or a drain electrode is formed using a low melting point conductive material is described with reference to FIGS. 12A to 12D and FIGS. A description will be given using B).

  First, based on the steps described in Embodiment Mode and Example 3, the etching up to the island-shaped amorphous semiconductor film 111 and the island-shaped semiconductor film 112 illustrated in FIG. 10C is performed. Note that the same portions as those in Embodiment Mode and Example 3 are denoted by the same reference numerals (FIG. 12A).

  Next, a mask 401 is formed so as to cover the exposed region 302 of the source or drain electrode 106 and the island-shaped amorphous semiconductor film 111. As the mask 401, heat treatment is performed in a later step; therefore, a heat resistant material may be used. For example, silicon oxide, silicon nitride, silicon nitride containing oxygen, or silicon oxide containing nitrogen may be used. In this embodiment, silicon oxide is used as the mask 401. The mask 401 is provided with a window 400 for introducing a catalytic element on the region 302 by etching.

  Next, a catalyst element that promotes crystallization of the semiconductor film is introduced into the window 400. The introduction method includes a method in which the catalyst element is dispersed in a solution and introduced by a spin coating method, and a method in which the catalyst element is introduced by plasma treatment using an electrode containing the catalyst element (FIG. 12C). ).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  As a method for introducing the catalytic element, a method in which the catalytic element is dispersed in a solution and introduced by a spin coating method, or a method in which the catalytic element is introduced by plasma treatment using an electrode containing the catalytic element is used. Is possible. In this embodiment, nickel (Ni) is used as a catalyst element, and a nickel acetic acid solution is applied to the surface of the island-shaped amorphous semiconductor film 111 through the window 400 by a spin coating method.

  When the catalyst element is dispersed in a solution and introduced by spin coating, a thin oxide film is formed on the surface of the region exposed by the window 400 of the island-like amorphous semiconductor film 111 before the introduction of the catalyst element. It is preferable to improve the wettability of the island-shaped amorphous semiconductor film 111 to a solution. This thin oxide film is formed by oxidation treatment with water (ozone water) in which ozone is dissolved in water, heat treatment in an oxidation atmosphere, or irradiation with UV light. In this embodiment, a thin oxide film is formed by applying ozone water.

  Next, hydrogen in the island-shaped amorphous semiconductor film 111 is released by holding at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming a dangling bond in the island-shaped amorphous semiconductor film 111.

  Then, the island-shaped amorphous semiconductor film 111 is crystallized by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere. With this catalytic element, the crystallization temperature of the island-shaped amorphous semiconductor film 111 can be set to a relatively low temperature of 550 to 600 ° C.

  By this heat treatment, crystallization proceeds in parallel with the substrate from the region where the catalyst element is introduced. Further, the catalytic element moves from the added region with crystallization and is gettered to the source region or the drain region 403 (FIG. 12D). Thus, a crystalline semiconductor film 402 with reduced catalytic elements can be obtained (FIG. 13A).

  Further, by this heating step, an element selected from Group 15 or Group 13 included in the source region or drain region 403 can be activated.

  Next, it heats at 350-450 degreeC in a hydrogen atmosphere, Preferably it is 410-420 degreeC. Accordingly, the crystalline semiconductor film 402 can be hydrogenated. In other words, dangling bonds existing in the crystalline semiconductor film 402 can be terminated.

  Further, instead of heating in a hydrogen atmosphere, a new silicon nitride film or a silicon nitride film containing oxygen is formed over the mask 401 and heated at 350 to 450 ° C., preferably 410 to 420 ° C. The conductive semiconductor film 402 can be hydrogenated

  After the crystalline semiconductor film 402 is obtained, a wiring 405 connected to the source or drain electrode 301 is formed (FIG. 13B).

  Since the wiring 405 is formed after the heating process, a low melting point conductive material such as aluminum (Al), silver (Ag), or the like can be used for the wiring 405. For the wiring 405, a sputtering method, a droplet discharge method (inkjet), or a CVD method can be used. In particular, when the wiring 405 is formed by a droplet discharge method, a process can be shortened because a photomask is not necessary.

  Through the above steps, an inverted staggered TFT having a channel formation region 404 and a source region or drain region 403 is formed.

  Further, this embodiment can be freely combined with any description in Embodiment Mode and Embodiment 1 if necessary.

  For example, when this embodiment is applied to Embodiment 1, the TFT and CMOS circuit shown in FIG. 25 can be obtained.

  That is, an N-channel TFT 941, a P-channel TFT 942, and an N-channel TFT 943 are formed over the substrate 900. The N-channel TFT 941 and the P-channel TFT 942 form a CMOS circuit 944.

  The N-channel TFT 941 includes a gate electrode 911, a gate insulating film 901, a channel formation region 920, an island-shaped crystalline semiconductor film 915 including an intrinsic region 918, and a source or drain region 919. The P-channel TFT 942 includes a gate electrode 912, a gate insulating film 901, a channel formation region 923, an island-shaped crystalline semiconductor film 916 including an intrinsic region 921, and a source region or a drain region 922. The N-channel TFT 943 includes a gate electrode 913, a gate insulating film 901, a channel formation region 926, an island-shaped crystalline semiconductor film 917 including an intrinsic region 924, and a source or drain region 925.

  Further, electrodes 931 and 932 are connected to the source region or drain region 919 of the N-channel TFT 941, electrodes 933 and 934 are connected to the source region or drain region 922 of the P-channel TFT 942, and the source of the N-channel TFT 943 is connected. Electrodes 935 and 936 are connected to the region or drain region 925.

  Further, a wiring 951 made of a low melting point conductive material is connected to the electrode 931, a wiring 952 to the electrodes 932 and 933, a wiring 953 to the electrode 934, a wiring 954 to the electrode 935, and a wiring 955 to the electrode 936. Has been.

  In this embodiment, an example in which an inverted stagger TFT is formed by a manufacturing process different from those in Embodiments 1 to 4, FIGS. 14 (A) to 14 (C) and FIGS. 15 (A) to 15 (D), This will be described with reference to FIGS.

  First, based on the steps described in Embodiment Modes, formation up to the island-shaped region 113 including the island-shaped amorphous semiconductor film 111 and the island-shaped semiconductor film 112 illustrated in FIG. Note that the same portions as those in the embodiment are denoted by the same reference numerals (FIG. 14A).

  Next, a resist 601 is selectively formed over the island-shaped region 113 using a photomask (FIG. 14B), and the island-shaped region 113 is etched using the resist 601 as a mask.

  As a result, all regions of the island-shaped semiconductor film 112 that are not covered with the resist 601 are removed. Further, the thickness of the island-shaped amorphous semiconductor film 111 is reduced, and the region 602 that is not covered with the resist 601 is exposed (FIG. 14C).

  Next, a mask 604 is formed so as to cover the gate insulating film 102, the source or drain region, and the exposed region 602. As the mask 604, heat treatment is performed in a later step; therefore, a heat resistant material may be used. For example, silicon oxide, silicon nitride, silicon nitride containing oxygen, or silicon oxide containing nitrogen is used. In this embodiment, silicon oxide is used as the mask 604. The mask 604 is provided with a window 603 for introducing a catalytic element over the region 114 by etching (FIG. 15A).

  Next, a catalyst element that promotes crystallization of the semiconductor film is introduced into the window 603. As the introduction method, there are a method in which the catalyst element is dispersed in a solution and introduced by a spin coating method, and a method in which the catalyst element is introduced by plasma treatment using an electrode containing the catalyst element (FIG. 15B). ).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  As a method for introducing the catalytic element, a method in which the catalytic element is dispersed in a solution and introduced by a spin coating method, or a method in which the catalytic element is introduced by plasma treatment using an electrode containing the catalytic element is used. Is possible. In this embodiment, nickel (Ni) is used as a catalyst element, and a nickel acetic acid solution is applied to the surface of the island-shaped amorphous semiconductor film 111 through the window 603 by spin coating.

  When the catalyst element is dispersed in a solution and introduced by spin coating, a thin oxide film is formed on the surface of the region exposed by the window 603 of the island-like amorphous semiconductor film 111 before the introduction of the catalyst element. It is preferable to improve the wettability of the island-shaped amorphous semiconductor film 111 to a solution. This thin oxide film is formed by oxidation treatment with water (ozone water) in which ozone is dissolved in water, heat treatment in an oxidation atmosphere, or irradiation with UV light. In this embodiment, a thin oxide film is formed by irradiation with UV light.

  Next, hydrogen in the island-shaped amorphous semiconductor film 111 is released by holding at 450 to 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the threshold energy for subsequent crystallization is lowered by intentionally forming a dangling bond in the island-shaped amorphous semiconductor film 111.

  Then, the island-shaped amorphous semiconductor film 111 is crystallized by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere. With this catalytic element, the crystallization temperature of the island-shaped amorphous semiconductor film 111 can be set to a relatively low temperature of 550 to 600 ° C.

  By this heat treatment, crystallization proceeds in parallel with the substrate from the region where the catalyst element is introduced. Further, the catalyst element moves from the added region with crystallization and is gettered to the source region or the drain region 608 (FIG. 15C). Thus, a crystalline semiconductor film 605 with reduced catalytic elements can be obtained (FIG. 15D).

  Further, by this heating step, an element selected from Group 15 or Group 13 included in the source region or drain region 608 can be activated.

  Next, it heats at 350-450 degreeC in a hydrogen atmosphere, Preferably it is 410-420 degreeC. Accordingly, the crystalline semiconductor film 605 can be hydrogenated. In other words, dangling bonds existing in the crystalline semiconductor film 605 can be terminated.

  Further, instead of heating in a hydrogen atmosphere, a new silicon nitride film or a silicon nitride film containing oxygen is formed over the mask 604 and heated at 350 to 450 ° C., preferably 410 to 420 ° C. The conductive semiconductor film 605 can be hydrogenated

  Next, an interlayer insulating film 606 is formed over the gate insulating film 102, the crystalline semiconductor film 605, and the mask 604.

  The interlayer insulating film 606 may be formed using an insulating film containing silicon, for example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, or a stacked film thereof using a plasma CVD method or a sputtering method. Needless to say, the interlayer insulating film 606 is not limited to a silicon oxide film or a silicon nitride film containing nitrogen, or a laminated film thereof, and another insulating film containing silicon may be used as a single layer or a laminated structure.

  As the interlayer insulating film 606, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin may be used.

  Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  Next, a contact hole is formed in the interlayer insulating film 606, a conductive film is formed over the interlayer insulating film 606, and a source electrode or a drain electrode 607 electrically connected to the source region or the drain region 608 is formed using the conductive film. To do. Thus, an inverted staggered TFT having a channel formation region 609 and a source or drain region 608 is manufactured (FIG. 16A).

  Further, the mask 604 may be removed by etching before forming the interlayer insulating film. In this case, the number of steps increases by one, but since the amorphous semiconductor film and the unreacted catalyst element do not remain in the TFT, the reliability of the TFT becomes higher when the mask 604 is removed.

  When the mask 604 is removed, the interlayer insulating film 611 is formed using an inorganic material such as an insulating film containing silicon in order to prevent impurities such as carbon and oxygen from entering the channel formation region 614 and the source or drain region 613. Is more preferable.

  After the interlayer insulating film 611 is formed, a contact hole is formed, and then a conductive film is formed over the interlayer insulating film 611, and a source electrode or a drain electrode 612 that is electrically connected to the source region or the drain region 613 using the conductive film. Form. Thus, an inverted staggered TFT having a channel formation region 614 and a source or drain region 613 is manufactured (FIG. 16B).

  Alternatively, the wiring 621 connected to the source or drain region 622 may be formed without forming the interlayer insulating film after the mask 604 is formed.

  As the wiring 621, a low melting point conductive material such as aluminum (Al), silver (Ag), or the like can be used. For the wiring 621, a sputtering method, a droplet discharge method (inkjet), or a CVD method can be used. In particular, when the wiring 621 is formed by a droplet discharge method, it is not necessary to use a photomask, so that the process can be shortened.

  Through the above steps, an inverted staggered TFT having a channel formation region 623 and a source or drain region 622 is formed (FIG. 16C).

  Further, this embodiment can be freely combined with any description in Embodiment Mode and Embodiment 1 if necessary.

  For example, when the structure shown in FIG. 16A of this embodiment is applied to Embodiment 1, the TFT and CMOS circuit shown in FIG. 26 can be obtained.

  That is, an N-channel TFT 1151, a P-channel TFT 1152, and an N-channel TFT 1153 are formed over the substrate 1101. The N-channel TFT 1151 and the P-channel TFT 1152 form a CMOS circuit 1154.

  The N-channel TFT 1151 includes a gate electrode 1111, a gate insulating film 1102, a channel formation region 1120, an island-shaped crystalline semiconductor film 1115 including an intrinsic region 1118, and a source or drain region 1119. The P-channel TFT 1152 includes a gate electrode 1112, a gate insulating film 1102, a channel formation region 1123, an island-shaped crystalline semiconductor film 1116 including an intrinsic region 1121, and a source region or a drain region 1122. The N-channel TFT 1153 includes a gate electrode 1113, a gate insulating film 1102, a channel formation region 1126, an island-shaped crystalline semiconductor film 1117 including an intrinsic region 1124, and a source or drain region 1125.

  On the TFTs 1151 to 1153, a mask 1141 (corresponding to 604 in FIG. 15A) having windows 1161-1163 (corresponding to 603 in FIG. 15A) for catalyst elements is formed. An interlayer insulating film 1142 (corresponding to 606 in FIG. 15A) is formed over the mask 1141, and wirings 1131 to 1135 are formed over the interlayer insulating film 1142.

  Wirings 1131 and 1132 are connected to the source region or drain region 1119 of the N-channel TFT 1151, wirings 1132 and 1133 are connected to the source region or drain region 1122 of the P-channel TFT 1152, and the source region or Wirings 1134 and 1135 are connected to the drain region 1125.

  In addition, when the structure shown in FIG. 16B of this embodiment is applied to Embodiment 1, the TFT and the CMOS circuit shown in FIG. 27 can be obtained.

  That is, an N-channel TFT 1251, a P-channel TFT 1252, and an N-channel TFT 1253 are formed over the substrate 1201. The N-channel TFT 1251 and the P-channel TFT 1252 form a CMOS circuit 1254.

  The N-channel TFT 1251 includes a gate electrode 1211, a gate insulating film 1202, a channel formation region 1220, an island-shaped crystalline semiconductor film 1215 including an intrinsic region 1218, and a source region or a drain region 1219. The P-channel TFT 1252 includes a gate electrode 1212, a gate insulating film 1202, a channel formation region 1223, an island-shaped crystalline semiconductor film 1216 including an intrinsic region 1221, and a source or drain region 1222. The N-channel TFT 1253 includes a gate electrode 1213, a gate insulating film 1202, a channel formation region 1226, an island-shaped crystalline semiconductor film 1217 including an intrinsic region 1224, and a source or drain region 1225.

  An interlayer insulating film 1241 (corresponding to 611 in FIG. 16B) is formed over the TFTs 1151 to 1153, and wirings 1231 to 1235 are formed over the interlayer insulating film 1241.

  Wirings 1231 and 1232 are connected to the source region or drain region 1219 of the N-channel TFT 1251, and wirings 1232 and 1233 are connected to the source region or drain region 1222 of the P-channel TFT 1252. Wirings 1234 and 1235 are connected to the drain region 1225.

  Further, when the structure shown in FIG. 16C of this embodiment is applied to Embodiment 1, the TFT and the CMOS circuit shown in FIG. 43 can be obtained.

  That is, an N-channel TFT 1941, a P-channel TFT 1942, and an N-channel TFT 1943 are formed over the substrate 1900. The N-channel TFT 1941 and the P-channel TFT 1942 form a CMOS circuit 1944.

  The N-channel TFT 1941 includes a gate electrode 1911, a gate insulating film 1901, a channel formation region 1920, an island-shaped crystalline semiconductor film 1915 including an intrinsic region 1918, and a source or drain region 1919. The P-channel TFT 1942 includes a gate electrode 1912, a gate insulating film 1901, a channel formation region 1923, an island-shaped crystalline semiconductor film 1916 including an intrinsic region 1921, and a source or drain region 1922. The N-channel TFT 1943 includes a gate electrode 1913, a gate insulating film 1901, a channel formation region 1926, an island-shaped crystalline semiconductor film 1917 including an intrinsic region 1924, and a source or drain region 1925.

  In addition, wirings 1931 and 1932 formed of a low melting point conductive material are connected to the source region or drain region 1919 of the N-channel TFT 1941, and wirings 1932 and 1933 are connected to the source region or drain region 1922 of the P-channel TFT 1942. In addition, wirings 1934 and 1935 are connected to the source region or the drain region 1925 of the N-channel TFT 1943.

  In this embodiment, an example of manufacturing a liquid crystal display (LCD) using the present invention will be described with reference to FIGS. 17A to 17B, FIG. 18, FIG. 19, and FIG. 20 (D), FIG. 21 (A) to FIG. 21 (B), FIG. 22 to FIG. 24, and FIG.

  A manufacturing method of a liquid crystal display device described in this embodiment is a method of manufacturing a pixel portion including a pixel TFT and a TFT of a driver circuit portion provided around the pixel portion at the same time. However, in order to simplify the explanation, a CMOS circuit composed of an n-channel TFT and a p-channel TFT, which are basic units for the drive circuit, is illustrated.

  First, based on Embodiment 1, a CMOS circuit 543 including an N-channel TFT 540 and a P-channel TFT 541 and an N-channel TFT 542 shown in FIG. 9C are formed. In this embodiment, the N-channel TFT 542 is used as a pixel TFT, and the CMOS circuit 543 is used as a basic unit of a driver circuit (FIG. 17A).

  Note that the N-channel TFTs 540 and 542 and the P-channel TFT 541 are not limited to those manufactured by the method described in Example 1, and the method described in any of Examples 2 to 5 is used. Can be used.

  Next, a first interlayer insulating film 701 is formed to cover the TFTs 540 to 542.

  As the first interlayer insulating film 701, an insulating film containing silicon, for example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, or a stacked film thereof is formed by plasma CVD or sputtering. Needless to say, the first interlayer insulating film 701 is not limited to a silicon oxide film or silicon nitride film containing nitrogen, or a laminated film thereof, and other insulating films containing silicon may be used as a single layer or a laminated structure. .

  Note that the first interlayer insulating film 701 is formed using a silicon nitride film and a silicon nitride film containing oxygen, heat treatment is performed, and the island-shaped crystalline semiconductor films 520 to 522 are hydrogenated by hydrogen from the first interlayer insulating film 701. May be. That is, dangling bonds existing in the island-like crystalline semiconductor films 520 to 522 can be terminated by hydrogen.

  Next, a second interlayer insulating film 702 that functions as a planarization film is formed over the first interlayer insulating film 701.

  As the second interlayer insulating film 702, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Note that siloxane is composed of a skeleton structure of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. is there. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  In this embodiment, siloxane is formed as the second interlayer insulating film 702 by a spin coating method.

A part of the first interlayer insulating film 701 and the second interlayer insulating film 702 is etched to form a contact hole reaching the electrode 514. In this contact hole formation, carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ), and helium (He) are used as etching gases at flow rates of 50 sccm, 50 sccm, and 30 sccm, respectively.

  Next, a conductive film is formed over the second interlayer insulating film 702. Next, using a photomask, a pixel electrode 703 which is electrically connected to the electrode 514 is formed using a conductive film (FIG. 17B).

In this embodiment, since a transmissive liquid crystal display panel is manufactured, a transparent conductive film such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, zinc oxide (ZnO), and tin oxide (SnO ₂ ) is used. A pixel electrode 703 is formed using the same.

  In the case of manufacturing a reflective liquid crystal display panel, the pixel electrode 703 is made of a light reflective material such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum) by sputtering. It may be formed using a metal material having

  Note that FIG. 19 shows a top view in which a part of the pixel portion 801 is enlarged. FIG. 19 shows a state in which a pixel electrode is being formed, and shows a state in which a pixel electrode is formed in the left pixel, but no pixel electrode is formed in the right pixel. In FIG. 19, a diagram cut along a solid line A-A ′ corresponds to the cross section of the pixel TFT 542 in FIG. 17B, and the same reference numerals are used for portions corresponding to FIG. 17B. In addition, a capacitor wiring 711 is provided, and the storage capacitor is formed using the first interlayer insulating film 701 as a dielectric, the pixel electrode 703, and the capacitor wiring 711 overlapping the pixel electrode.

  In this embodiment, in the region where the pixel electrode 703 and the capacitor wiring 711 overlap, the second interlayer insulating film 702 is etched, and the storage capacitor is formed by the pixel electrode 703, the first interlayer insulating film 701, and the capacitor wiring 711. Yes. However, if the second interlayer insulating film 702 can also be used as a dielectric, the second interlayer insulating film 702 need not be etched. In that case, the first interlayer insulating film 701 and the second interlayer insulating film 702 function as a dielectric.

  In FIG. 19, the gate electrode 503 is connected to a gate wiring 712 formed separately from the gate electrode 503. Further, although the electrode 513 is formed integrally with the source wiring, the electrode 513 and the source wiring may be formed separately and connected to each other.

  Through the above steps, a TFT substrate for a liquid crystal display panel in which the CMOS circuit 543 and the pixel electrode 703 including the inverted staggered pixel TFT 542, the inverted staggered N-channel TFT 540, and the P-channel TFT 541 are formed on the substrate 500 is obtained. Can be completed.

  Next, an alignment film 704 a is formed so as to cover the pixel electrode 703. Note that the alignment film 704a may be formed using a droplet discharge method, a screen printing method, or an offset printing method. Thereafter, a rubbing process is performed on the surface of the alignment film 704a.

  The counter substrate 705 is provided with a color filter composed of a colored layer 706b, a light shielding layer (black matrix) 706a, and an overcoat layer 707, a counter electrode 708 composed of a transparent electrode or a reflective electrode, and an alignment film thereon. 704b is formed. Then, a sealing material 721 having a closed pattern is formed so as to surround a region overlapping with the pixel portion 801 by a droplet discharge method. Here, an example in which a sealing material having a closed pattern is drawn in order to drop the liquid crystal 709 is shown. However, a dip type (in which a liquid crystal is injected by using a capillary phenomenon after providing a sealing pattern having an opening and attaching a TFT substrate) A pumping type) may be used (FIG. 20A).

  Next, the liquid crystal 709 is dropped under reduced pressure so that bubbles do not enter (FIG. 20B), and both the substrates 500 and 705 are attached (FIG. 20C). The liquid crystal is dropped once or a plurality of times in the closed loop seal pattern. As the alignment mode of the liquid crystal, a TN mode in which the alignment of liquid crystal molecules is twisted by 90 ° from the incident light to the emitted light is often used. When a TN mode liquid crystal display device is manufactured, the substrates are bonded so that the rubbing directions of the substrates are orthogonal.

  Note that the distance between the pair of substrates may be maintained by spraying spherical spacers, forming columnar spacers made of resin, or including a filler in the sealing material. The columnar spacer is an organic resin material mainly containing at least one of acrylic, polyimide, polyimide amide, and epoxy, or any one material of silicon oxide, silicon nitride, and silicon oxide containing nitrogen, or a laminate thereof. It is an inorganic material made of a film.

  Next, the substrate is divided. In case of multi-chamfering, each panel is divided. In the case of one-sided chamfering, the dividing step can be omitted by attaching a counter substrate that has been cut in advance (FIG. 20D).

  Then, an FPC (Flexible Printed Circuit) 804 is attached through an anisotropic conductor layer using a known technique. The liquid crystal display device is completed through the above steps. If necessary, an optical film is attached. In the case of a transmissive liquid crystal display device, the polarizing plate is attached to both the active matrix substrate and the counter substrate.

  A cross-sectional view of the liquid crystal display device obtained through the above steps is shown in FIG. 18, a top view thereof is shown in FIG. 21A, and an example of a top view of another liquid crystal display device is shown in FIG.

  In FIG. 21A, reference numeral 500 denotes a substrate, 705 denotes a counter substrate, 801 denotes a pixel portion, 721 denotes a sealant, and 804 denotes an FPC. Note that liquid crystal is discharged by a droplet discharge method, and the pair of substrates 500 and 705 are bonded to each other with a sealant 721 under reduced pressure.

  In FIG. 21B, reference numeral 802 denotes a source signal line driver circuit, 803 denotes a gate signal line driver circuit, 721a denotes a first seal material, and 721b denotes a second seal material. Note that the liquid crystal is discharged by a droplet discharge method, and the pair of substrates 500 and 705 are bonded to each other with the first sealant 721a and the second sealant 721b. Since the driving circuit portions 802 and 803 do not require liquid crystal, only the pixel portion 801 holds the liquid crystal, and the second sealant 721b is provided to reinforce the entire panel.

  As described above, in this embodiment, the manufacturing process of the TFT can be shortened as compared with the prior art, and thus the manufacturing process of the liquid crystal display device can be shortened. The liquid crystal display device manufactured in this embodiment can also be used as a display portion of various electronic devices.

  In this embodiment, the TFT has a single gate structure. However, the present invention is not limited to this, and a multi-gate TFT having a plurality of channel formation regions, for example, a double gate TFT may be used.

  In the above, an example in which a liquid crystal display device is manufactured using the TFT shown in Example 1 is shown, but a liquid crystal display device can also be manufactured using TFTs formed in Examples 2 to 5. is there.

  For example, when a liquid crystal display device is manufactured using TFTs formed based on Example 2, a liquid crystal display device similar to that in FIG. 18 can be obtained.

  22 to 24 and 44 show examples of liquid crystal display devices manufactured based on Examples 3 to 5. FIG.

  FIG. 22 shows an example in which the TFT and CMOS circuit shown in FIG. 25 of Examples 3 to 4 are applied to the liquid crystal display device of this example. 18 and 25 are denoted by the same reference numerals.

  However, an interlayer insulating film 961 that also functions as a planarization film is formed over the TFTs 941 to 943. As the interlayer insulating film 961, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  Next, a conductive film is formed over the interlayer insulating film 961, and the pixel electrode 703 electrically connected to the wiring 955 is formed using the conductive film. The subsequent steps are the same as those described above.

  FIG. 23 shows an example in which the TFT and the CMOS circuit shown in FIG. 26 of Example 5 are applied to the liquid crystal display device of this example. 18 and 26 are denoted by the same reference numerals.

  However, a second interlayer insulating film 1143 that also functions as a planarization film is formed over the wirings 1134 and 1135 and the interlayer insulating film 1142. As the second interlayer insulating film 1143, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Note that siloxane is composed of a skeleton structure of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. is there. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  Next, a conductive film is formed over the interlayer insulating film 1143, and a pixel electrode 703 that is electrically connected to the wiring 1135 is formed using the conductive film. The subsequent steps are the same as those described above.

  FIG. 24 shows an example in which the TFT and the CMOS circuit shown in FIG. 27 of Example 5 are applied to the liquid crystal display device of this example. The same components as those in FIGS. 18 and 27 are denoted by the same reference numerals.

  However, a second interlayer insulating film 1242 that also functions as a planarization film is formed over the wirings 1234 and 1235 and the interlayer insulating film 1241. As the second interlayer insulating film 1242, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Siloxane is composed of a skeleton structure of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. . Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  Next, a conductive film is formed over the interlayer insulating film 1242, and the pixel electrode 703 electrically connected to the wiring 1235 is formed using the conductive film. The subsequent steps are the same as those described above.

  FIG. 44 shows an example in which the TFT and the CMOS circuit shown in FIG. 43 of Example 5 are applied to the liquid crystal display device of this example. 18 and 43 are denoted by the same reference numerals.

  However, an interlayer insulating film 1951 that also functions as a planarization film is formed over the TFTs 1941 to 1943. As the interlayer insulating film 1951, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. Alternatively, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  Next, a conductive film is formed over the interlayer insulating film 1951, and a pixel electrode 703 that is electrically connected to the electrode 1935 is formed using the conductive film. The subsequent steps are the same as those described above.

  In addition, this embodiment can be freely combined with any description in Embodiment Mode and Embodiments 1 to 5 if necessary.

  In this embodiment, an example in which a droplet discharge method is used for liquid crystal dropping is described. In this embodiment, an example of manufacturing four panels using a large-area substrate 1310 is shown in FIGS. 28 (A) to 28 (D), FIGS. 29 (A) to 29 (B), and FIG. FIG. 30B and FIG. 31A to FIG.

  FIG. 28A is a cross-sectional view in the middle of forming a liquid crystal layer by a dispenser (or ink jet). A liquid crystal material 1314 is applied to the droplet discharge device 1316 so as to cover a pixel portion 1311 surrounded by a sealant 1312. The nozzle 1318 is discharged, jetted, or dropped. The droplet discharge device 1316 is moved in the direction of the arrow in FIG. Although the example in which the nozzle 1318 is moved is shown here, the liquid crystal layer may be formed by fixing the nozzle and moving the substrate.

  FIG. 28B shows a perspective view. A state is shown in which the liquid crystal material 1314 is selectively ejected, jetted, or dropped only in a region surrounded by the sealing material 1312, and the dropping surface 1315 moves in accordance with the nozzle scanning direction 1313.

  FIGS. 28C and 28D are cross-sectional views in which a portion 1319 surrounded by a dotted line in FIG. 28A is enlarged. When the viscosity of the liquid crystal material is high, the liquid crystal material is continuously discharged and attached to the surface while being connected as shown in FIG. On the other hand, when the viscosity of the liquid crystal material is low, the liquid crystal material is discharged intermittently, and droplets are dropped one by one as shown in FIG.

  28C and 28D, reference numeral 1310 denotes a large area substrate, 1320 denotes a pixel TFT, and 1321 denotes a pixel electrode. The pixel portion 1311 includes pixel electrodes arranged in a matrix, switching elements connected to the pixel electrodes, here TFTs manufactured based on the descriptions in Embodiments 1 to 6, and a storage capacitor. It is configured.

  Here, the flow of panel manufacture will be described below with reference to FIGS. 29A to 29B and FIGS. 30A to 30B.

  First, a first substrate 1310 having a pixel portion 1311 formed on an insulating surface is prepared. The first substrate 1310 is previously subjected to formation of an alignment film, rubbing treatment, spherical spacer dispersion, columnar spacer formation, or color filter formation. Next, as illustrated in FIG. 29A, a sealant 1312 is formed on the first substrate 1310 in a predetermined position (a pattern surrounding the pixel portion 1311) on the first substrate 1310 in an inert gas atmosphere or under reduced pressure. . The translucent sealing material 1312 includes a filler (diameter 6 μm to 24 μm) and a viscosity of 40 to 400 Pa · s. It is preferable to select a sealing material that does not dissolve in the liquid crystal that comes into contact later. As the sealing material, an acrylic photo-curing resin or an acrylic thermosetting resin may be used. Further, since the sealing pattern is simple, the sealing material 1312 can be formed by a printing method.

  Next, a liquid crystal material 1314 is dropped in a region surrounded by the sealant 1312 by an inkjet method (FIG. 29B). As the liquid crystal material 1314, a known liquid crystal material having a viscosity that can be discharged by an inkjet method may be used. In addition, since the viscosity of the liquid crystal material can be set by adjusting the temperature, it is suitable for the ink jet method. A necessary amount of the liquid crystal material 1314 can be held in a region surrounded by the sealant 1312 without waste by an inkjet method.

  Next, the first substrate 1310 provided with the pixel portion 1311 and the second substrate 1331 provided with the counter electrode and the alignment film are bonded together under reduced pressure so that bubbles do not enter. Here, the sealing material 1312 is cured by performing ultraviolet irradiation and heat treatment at the same time as bonding. In addition to ultraviolet irradiation, heat treatment may be performed.

  FIGS. 31A to 31B show an example of a bonding apparatus capable of performing ultraviolet irradiation or heat treatment at the time of bonding or after bonding.

  31A to 31B, 1341 is a first substrate support, 1342 is a second substrate support, 1344 is a window, 1348 is a lower surface plate, and 1349 is a light source. 31 (A) to 31 (B), portions corresponding to those in FIGS. 28, 29 (A) to 29 (B), and FIGS. 30 (A) to 30 (B) have the same reference numerals. Used.

  The lower surface plate 1348 has a built-in heater and hardens the sealing material. In addition, a window 1344 is provided on the second substrate support base so that ultraviolet light or the like from the light source 1349 can pass therethrough. Although not shown here, the substrate is aligned through the window 1344. In addition, the second substrate 1331 to be the counter substrate is cut into a desired size in advance and fixed to the second substrate support base 1342 with a vacuum chuck or the like. FIG. 31A shows a state before bonding.

  At the time of bonding, after the first substrate support base 1341 and the second substrate support base 1342 are lowered, the first substrate 1310 and the second substrate 1331 are bonded together by applying pressure, and cured by irradiating ultraviolet light as it is. Let The state after pasting is shown in FIG.

  Next, the first substrate 1310 is cut using a cutting device such as a scriber device, a breaker device, or a roll cutter (FIG. 30B). Thus, four panels can be manufactured from one substrate. Then, the FPC is pasted using a known technique.

  Note that a glass substrate or a plastic substrate can be used as the first substrate 1310 and the second substrate 1331.

  Through the above process, a liquid crystal display device using a large-area substrate is manufactured.

  In addition, this embodiment can be freely combined with any description of the embodiment mode and Embodiments 1 to 6 if necessary.

  In this embodiment, an example of manufacturing a dual emission type EL (Electro-Luminescence) display device using the present invention will be described with reference to FIGS. 32 (A) to 32 (B) and FIG. 33 (A) to FIG. 33 (C), FIG. 34 (A) to FIG. 34 (B), FIG. 35 and FIG.

  First, based on Example 1, the process up to forming a semiconductor film into which an element selected from the group 15 shown in FIG. 7A is introduced (FIG. 32A) is performed. In addition, as for the manufacturing conditions, manufacturing steps, film forming materials, and the like of this example, those similar to those in Example 1 are used unless otherwise specified.

  However, the TFTs 1451 to 1453 may be formed based on the second to fifth embodiments. In that case, manufacturing conditions, manufacturing steps, film forming materials, and the like are the same as those described in each example.

  In FIG. 32A, 1401 is a substrate, 1402 to 1404 are gate electrodes, 1405 is a gate insulating film, 1406 is an amorphous semiconductor film, and 1407 is a semiconductor film into which an element selected from Group 15 is introduced.

Next, the semiconductor film 1407 is covered with a mask 1408 except for a region which will later become a P-channel TFT 1453, and an element selected from Group 13 is introduced (FIG. 32B). In this embodiment, boron (B) is used as an element selected from Group 13, and an ion implantation method is performed so that the concentration in the semiconductor film 1407 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²¹ cm ^−3. Alternatively, an ion doping method is used to form a P-type impurity region 1409 (FIG. 32C).

  Next, as illustrated in FIG. 32D, an island-shaped region 1421 including an island-shaped amorphous semiconductor film 1411 and an island-shaped semiconductor film 1412 is formed using the amorphous semiconductor film 1406 and the semiconductor film 1407, An island-shaped region 1422 including the crystalline semiconductor film 1413 and the island-shaped semiconductor film 1414, and an island-shaped region 1423 including the island-shaped amorphous semiconductor film 1415 and the island-shaped semiconductor film 1416 are formed.

  Next, a conductive film is formed so as to cover the island regions 1421 to 1423, and source and drain electrodes 1431 to 1436 connected to the source region and drain region of the TFT are formed using the conductive film (FIG. 33A )). As the conductive film, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material or a compound material containing the element as a main component is laminated. It may be used.

  Next, the island regions 1421 to 1423 are etched using the electrodes 1431 to 1436 as a mask. (FIG. 33B).

  As a result, all the regions of the island-like semiconductor films 1412, 1414, and 1416 that are not covered with the source or drain electrodes 1431 to 1436 are removed. In addition, the film thickness of the island-shaped amorphous semiconductor films 1411, 1413, and 1415 is reduced, and regions not covered with the source or drain electrodes 1431 to 1436 are exposed.

  Next, a catalytic element is introduced into a region exposed by etching and not covered with the electrodes 1431 to 1436 of the island-shaped amorphous semiconductor films 1411, 1413, and 1415 (FIG. 33B).

  Catalyst elements include nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). One selected element or a plurality of elements can be used.

  As a method for introducing the catalytic element, a method in which the catalytic element is dispersed in a solution and introduced by a spin coating method, or a method in which the catalytic element is introduced by plasma treatment using an electrode containing the catalytic element is used. Is possible.

  Then, by performing heat treatment at 550 to 600 ° C. for 4 to 8 hours in a nitrogen atmosphere, the island-shaped amorphous semiconductor films 1411, 1413, and 1415 are crystallized to form island-shaped crystalline semiconductor films 1437 to 1439. To do. By this heat treatment, the catalyst element moves from the added region simultaneously with crystallization and is gettered to the source or drain regions 1442, 1445, and 1448. Thus, crystalline semiconductor films 1437 to 1439 with reduced catalytic elements can be obtained.

  In addition, this heating step can activate an element selected from Group 15 or Group 13 included in the source or drain regions 1442, 1445, and 1448.

  From the above, inverted staggered N-channel TFTs 1451 and 1452 and a P-channel TFT 1453 are formed.

  The N-channel TFT 1451 has a channel formation region 1443, a source or drain region 1442, and an intrinsic region 1441. The N-channel TFT 1452 includes a channel formation region 1446, a source or drain region 1445, and an intrinsic region 1444. The P-channel TFT 1453 includes a channel formation region 1449 and a source or drain region 1448 intrinsic region 1447 (FIG. 33C).

  In this embodiment, the P-channel TFT 1453 is used as a pixel TFT of the dual emission EL display device. The N-channel TFTs 1451 and 1452 are used as TFTs of a driving circuit that drives the pixel TFT 1453. However, the pixel TFT is not necessarily a P-channel TFT, and an N-channel TFT may be used. In addition, the driving circuit does not need to be a circuit in which a plurality of N-channel TFTs are combined, but is a circuit in which an N-channel TFT and a P-channel TFT are complementarily combined, or a circuit in which a plurality of P-channel TFTs are combined. May be.

  Next, a first interlayer insulating film 1461 is formed so as to cover the TFTs 1451 to 1453.

  The first interlayer insulating film 1461 is formed using an insulating film containing silicon, for example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, or a stacked film thereof using plasma CVD or sputtering. Needless to say, the first interlayer insulating film 1461 is not limited to a silicon oxide film or a silicon nitride film containing nitrogen, or a laminated film thereof, and another insulating film containing silicon may be used as a single layer or a laminated structure. .

  Note that in the case where the first interlayer insulating film 1461 is formed using silicon nitride and silicon nitride containing oxygen, heat treatment is performed, and the island-shaped crystalline semiconductor films 1437 to 1439 are hydrogenated by hydrogen from the first interlayer insulating film 1461. It is also possible. In other words, dangling bonds existing in the island-like crystalline semiconductor films 1437 to 1439 can be terminated.

  Next, a second interlayer insulating film 1462 that functions as a planarization film is formed over the first interlayer insulating film 1461.

  As the second interlayer insulating film 1462, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, or benzocyclobutene), a resist, siloxane, and a stacked structure thereof can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used.

  Siloxane is composed of a skeleton structure formed by a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. is there. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  In this embodiment, siloxane is formed as the second interlayer insulating film 1462 by a spin coating method.

  Next, a third interlayer insulating film 1463 having a light-transmitting property is formed over the second interlayer insulating film 1462. The third interlayer insulating film 1463 is provided as an etching stopper film for protecting the planarization film that is the second interlayer insulating film 1462 when the pixel electrode 1464 is etched in a later step. However, when the pixel electrode 1464 is etched, the third interlayer insulating film 1463 is unnecessary if the second interlayer insulating film 1462 becomes an etching stopper film.

  Next, contact holes are formed in the first interlayer insulating film 1461, the second interlayer insulating film 1462, and the third interlayer insulating film 1463.

  Next, a pixel electrode (transparent electrode in this embodiment) 1464, that is, an anode of the organic light-emitting element is formed over the third interlayer insulating film 1463 in a thickness range of 10 nm to 800 nm (FIG. 34A). In addition to indium tin oxide (ITO), for example, indium zinc oxide (Indium Zinc Oxide) in which 2 to 20 atomic% zinc oxide (ZnO) is mixed with indium tin oxide or indium oxide is used as the pixel electrode. A transparent conductive material having a high work function (work function of 4.0 eV or more) can be used (FIG. 34A).

  Next, an insulator 1465 (referred to as a partition wall, a barrier, a bank, or the like) that covers the edge portion of the pixel electrode is formed using a new mask. As the insulator 1465, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, or benzocyclobutene) obtained by a coating method, a resist, or a SOG (Spin On Glass) film (for example, an alkyl) (SiOx film containing a group) is used in a thickness range of 0.8 μm to 1 μm.

  Next, layers 1471, 1472, 1473, 1474, and 1475 containing an organic compound are formed by an evaporation method or a coating method. Note that in order to improve the reliability of the light-emitting element, it is preferable to perform deaeration by performing vacuum heating before the formation of the layer 1471 containing an organic compound. For example, before vapor deposition of the organic compound material, it is desirable to perform a heat treatment at 200 ° C. to 300 ° C. in a reduced pressure atmosphere or an inert atmosphere in order to remove gas contained in the substrate. Note that in the case where the interlayer insulating film and the partition are formed using a silicon oxide film having high heat resistance, higher heat treatment (410 ° C.) can be applied.

  Then, using a vapor deposition mask, molybdenum oxide (MoOx) and 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (α-NPD) are selectively formed on the pixel electrode. And rubrene are co-evaporated to form a layer 1471 (hole injection layer) containing the first organic compound.

  In addition to MoOx, a material having a high hole injection property such as copper phthalocyanine (CuPc), vanadium oxide (VOx), ruthenium oxide (RuOx), or tungsten oxide (WOx) can be used. In addition, a hole injecting layer 1471 is formed by applying a high hole injecting polymer material such as poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) by a coating method. Also good.

  Next, α-NPD is selectively deposited using a deposition mask to form a layer (hole transport layer) 1472 containing a second organic compound on the layer 1471 containing the first organic compound. In addition to α-NPD, 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N , N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: A material having a high hole transporting property typified by an aromatic amine compound such as MTDATA) can be used.

  Next, a layer (light-emitting layer) 1473 including a third organic compound is selectively formed. In order to obtain a full-color display device, the vapor deposition mask is aligned for each of the emission colors (R, G, B) to selectively deposit each.

Next, Alq ₃ (tris (8-quinolinolato) aluminum) is selectively deposited using a deposition mask, and a layer (electron transport layer) 1474 including a fourth organic compound is formed over the light-emitting layer 1473. In addition to Alq ₃ , tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl) A material having a high electron transport property typified by a metal complex having a quinoline skeleton or a benzoquinoline skeleton such as -8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq) can be used. In addition, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (abbreviation: Zn ( Metal complexes having an oxazole or thiazole ligand such as BTZ) ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5 -(P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5 (4-Biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2 , 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can also be used as the electron-transport layer 1474 because of their high electron-transport properties.

Next, 4,4-bis (5-methylbenzoxazol-2-yl) stilbene (abbreviation: BzOs) and lithium (Li) are co-evaporated to cover the electron transport layer 1474 and the insulator 1465 and cover the entire surface. 5 (electron injection layer) 1475 containing 5 organic compounds is formed. By using the benzoxazole derivative (BzOS), damage due to the sputtering method at the time of forming the transparent electrode 1476 performed in a later process is suppressed. In addition to BzOs: Li, a material having a high electron-injection property such as an alkali metal or alkaline earth metal compound such as CaF ₂ , lithium fluoride (LiF), and cesium fluoride (CsF) can be used. . In addition, a mixture of Alq ₃ and magnesium (Mg) can also be used.

  Next, a transparent electrode 1476, that is, a cathode of an organic light emitting element is formed on the electron injection layer 1475 in a thickness range of 10 nm to 800 nm. As the transparent electrode 1476, in addition to indium tin oxide (ITO), for example, indium tin oxide containing Si element or IZO (Indium Zinc Oxide) in which 2 to 20 atomic% of zinc oxide (ZnO) is mixed with indium oxide. Can be used.

  As described above, a light emitting element is manufactured. The materials for the anode, the layer containing the first organic compound to the layer containing the fifth organic compound, and the cathode constituting the light-emitting element are appropriately selected, and the film thicknesses are also adjusted. It is desirable that the same material is used for the anode and the cathode, and the film thickness is approximately the same, preferably approximately 100 nm.

  Further, if necessary, a transparent protective layer 1477 which covers the light emitting element and prevents moisture from entering is formed. As the transparent protective layer 1477, a silicon nitride film, a silicon oxide film, a silicon nitride film containing oxygen (SiNO film (composition ratio N> O)) or a silicon oxide film containing nitrogen (SiON film) obtained by sputtering or CVD is used. (Composition ratio N <O)), a thin film mainly containing carbon (for example, a DLC film, a CN film), or the like can be used (FIG. 34B).

  Next, the second substrate 1481 and the substrate 1401 are attached to each other using a sealant containing a gap material for ensuring the substrate interval. The second substrate 1481 may also be a light-transmitting glass substrate or quartz substrate. In addition, a desiccant may be disposed as a gap (inert gas) between the pair of substrates, or a transparent sealing material (such as an ultraviolet curing or thermosetting epoxy resin) is filled between the pair of substrates. Also good.

  In the light emitting element, since the pixel electrodes 1464 and 1476 are formed of a light-transmitting material, light can be taken from one light emitting element in two directions, that is, from both sides.

  With the panel configuration described above, light emission from the upper surface and light emission from the lower surface can be made substantially the same.

  Finally, optical films (polarizing plate or circularly polarizing plate) 1482 and 1483 are provided to improve contrast (FIG. 35).

  FIG. 36 shows an example in which the pixel TFTs in the pixel portion are separately formed by RGB. In the pixel for red (R), a pixel TFT 1453R is connected to the pixel electrode 1464R, a layer containing a first organic compound (hole injection layer) 1471R, a layer containing a second organic compound (hole transport) Layer) 1472R, a layer containing a third organic compound (light emitting layer) 1473R, a layer containing a fourth organic compound (electron transport layer) 1474R, a layer containing a fifth organic compound (electron injection layer) 1475, a transparent electrode A (cathode) 1476 and a transparent protective layer 1477 are formed.

  In the green (G) pixel, a pixel TFT 1453G is connected to the pixel electrode 1464G, and a layer containing a first organic compound (hole injection layer) 1471G and a layer containing a second organic compound (holes) Transport layer) 1472G, layer containing third organic compound (light emitting layer) 1473G, layer containing fourth organic compound (electron transport layer) 1474G, layer containing fifth organic compound (electron injection layer) 1475, transparent An electrode (cathode) 1476 and a transparent protective layer 1477 are formed.

  Further, in the pixel for blue (B), a pixel TFT 1453B is connected to the pixel electrode 1464B, and a layer containing a first organic compound (hole injection layer) 1471B and a layer containing a second organic compound (holes) Transport layer) 1472B, layer containing a third organic compound (light emitting layer) 1473B, layer containing a fourth organic compound (electron transport layer) 1474B, layer containing a fifth organic compound (electron injection layer) 1475, transparent An electrode (cathode) 1476 and a transparent protective layer 1477 are formed.

Among these, for the light emitting layers 1473R, 1473G, and 1473B, a material such as Alq ₃ : DCM or Alq ₃ : rubrene: BisDCJTM is used as the light emitting layer 1473R that emits red light. For the light-emitting layer 1473G that emits green light, a material such as Alq ₃ : DMQD (N, N′-dimethylquinacridone) or Alq ₃ : coumarin 6 is used. For the light-emitting layer 1473B that emits blue light, a material such as α-NPD or tBu-DNA is used.

  In this embodiment, the TFT has a single gate structure. However, the present invention is not limited to this, and a multi-gate TFT having a plurality of channel formation regions, for example, a double gate TFT may be used.

  In addition, although the present Example demonstrated the double emission panel (dual emission panel), the structure of the top emission type panel (top emission panel) which is a single emission type panel, or a bottom emission type panel (bottom emission panel) is used. Of course.

  In order to produce a top emission panel, the anode of the organic light emitting element may be formed of a light shielding material instead of a transparent electrode. For example, when a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film is used, the resistance as a wiring is low, a good ohmic contact can be obtained, and the film can function as an anode. . In addition, the anode of the organic light emitting element may be a single layer such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, or a laminate of three or more layers may be used.

  The cathode of the top emission panel is preferably transparent or translucent, and can be formed using the same material as the pixel electrode.

  In order to manufacture a bottom emission panel, the anode of the organic light emitting element can be formed using the same material as the pixel electrode.

On the other hand, as the cathode of the bottom emission panel, a light-shielding material having a small work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used.

  Note that when the top emission panel or the bottom emission panel is manufactured, the layer containing the organic compound in the organic light emitting element may be appropriately changed according to the material of each anode or cathode.

  The light emitted from the light emitting element includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. One or both of them can be used in the examples.

  In addition, although it has already been described that the present embodiment is implemented using the steps of the first embodiment, it can be freely combined with any description of the embodiment and the second to fifth embodiments if necessary. Is possible.

  In this example, an example of manufacturing an ID chip using the present invention is shown in FIGS. 37A to 37B, 38A to 38B, and FIGS. B) and FIGS. 40 (A) to 40 (B).

  Note that in this embodiment, an isolated TFT is illustrated as a semiconductor element, but a semiconductor element used for an integrated circuit is not limited to this, and any circuit element can be used. For example, in addition to the TFT, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, and the like can be typically given.

  Here, the ID chip is an integrated circuit used for identifying an object, and information for identification is recorded in the ID chip itself. The ID chip can transmit and / or receive information to / from the management system and reader by radio waves or electromagnetic waves. By the information that the ID chip has, it becomes possible to know the place of production, the expiration date, the distribution route, etc. of the product to which the ID chip is attached. You can manage safety.

  First, as illustrated in FIG. 37A, a peeling layer 4001 is formed over a heat-resistant substrate (first substrate) 4000 by a sputtering method. As the first substrate 4000, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate including a stainless steel substrate or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. .

  As the separation layer 4001, a layer containing silicon as its main component, such as amorphous silicon, polycrystalline silicon, single crystal silicon, or microcrystalline silicon (including semi-amorphous silicon) can be used. The separation layer 4001 can be formed by a sputtering method, a low pressure thermal CVD method, a plasma CVD method, or the like. In this embodiment, amorphous silicon with a thickness of about 50 nm is formed by a low pressure thermal CVD method and used as the peeling layer 4001. Note that the separation layer 4001 is not limited to silicon and may be formed using a material that can be selectively removed by etching. The thickness of the release layer 4001 is preferably 50 to 60 nm. For semi-amorphous silicon, the thickness may be 30 to 50 nm.

  Next, a base film 4002 is formed over the peeling layer 4001. The base film 4002 is provided to prevent an alkali metal such as Na or an alkaline earth metal contained in the first substrate 4000 from diffusing into the semiconductor film and adversely affecting the characteristics of a semiconductor element such as a TFT. The base film 4002 also has a role of protecting the semiconductor element in a process of peeling the semiconductor element later. The base film 4002 may be a single layer or a stack of a plurality of insulating films. Therefore, the insulating film is formed using an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film.

In this embodiment, a silicon oxide film (SiON film) containing nitrogen having a thickness of 100 nm is used as the first layer base film (lower base film) 4002a, and oxygen having a thickness of 50 nm is used as the second layer base film (middle layer base film) 4002b. A silicon oxide film (SiON film) containing nitrogen having a thickness of 100 nm is sequentially stacked as a silicon nitride film (SiNO film) containing and a third layer base film (upper layer base film) 4002c to form the base film 4002. The material, film thickness, and number of layers are not limited to these. For example, the lower base film 4002a may be replaced with a SiON film, and a siloxane-based resin having a film thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiNx, Si ₃ N ₄ or the like) may be used instead of the SiNO film as the middle layer base film 4002b. In addition, a silicon oxide film may be used instead of the upper base film 4002c in place of the SiON film. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

  Alternatively, the lower base film 4002a of the base film 4002 closest to the peeling layer 4001 is formed using a SiON film or a silicon oxide film, the middle base film 4002b is formed using a siloxane-based resin, and the upper base film 4002c is formed using a silicon oxide film. You may do it.

Here, the silicon oxide film is formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD using a mixed gas such as SiH ₄ and O ₂ or TEOS (tetraethoxysilane) and O _2. Can do. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and NH ₃ . In addition, a silicon oxide film containing nitrogen (SiON: O> N) and a silicon nitride film containing oxygen (SiNO: N> O) typically use a mixed gas of SiH ₄ and N ₂ O, and plasma CVD is performed. Can be formed.

  After the base film 4002 is formed, the manufacturing process up to TFT formation of FIGS. 7A to 9C is performed by the same manufacturing process as that of the first embodiment. In addition, as for the manufacturing conditions, manufacturing steps, film forming materials, and the like of this example, the same manufacturing conditions, manufacturing steps, film forming materials, and the like as in Example 1 are used (FIG. 37A). .

  However, in this embodiment, n-channel TFTs 4011 and 4013 and a p-channel TFT 4012 are formed on a substrate 4000. The n-channel TFT 4011 has a gate electrode 4101, a gate insulating film 4104, an island-shaped crystalline semiconductor film 4111 including a channel formation region 4113, and a source or drain region 4112 in a base film 4002.

  The p-channel TFT 4012 has a gate electrode 4102, a gate insulating film 4104, an island-shaped crystalline semiconductor film 4114 including a channel formation region 4116, and a source or drain region 4115 in a base film 4002.

  The n-channel TFT 4013 includes a gate electrode 4103, a gate insulating film 4104, an island-shaped crystalline semiconductor film 4117 including a channel formation region 4119, and a source region or drain region 4118 in a base film 4002.

  Wirings 4300 and 4301 are in the source region or drain region 4112 of the n-channel TFT 4011, wirings 4301 and 4302 are in the source region or drain region 4115 of the p-channel TFT 4012, and wirings 4303 and 4304 are in the source region of the n-channel TFT 4013. Alternatively, they are respectively connected to the drain region 4118. Further, although not shown, the wiring 4304 is also connected to the gate electrode 4103 of the n-channel TFT 4013. The n-channel TFT 4013 can be used as a memory element of a random number ROM.

  Further, thereafter, a first interlayer insulating film 4200 for protecting the TFTs 4011 to 4013 and the wirings 4300 to 4304 is formed. As the first interlayer insulating film, it is preferable to use silicon nitride, silicon oxide containing nitrogen, aluminum nitride, aluminum oxide, silicon oxide, or the like which can prevent the entry of alkali metal or alkaline earth metal into the TFTs 4011 to 4013. . Specifically, for example, a SiON film having a thickness of about 600 nm can be used as the first interlayer insulating film 4200. In this case, the hydrogenation process may be performed after the formation of the SiON film. As described above, the three insulating films of SiON, SiNx, and SiON are formed on the TFTs 4011 to 4013, but the structure and material are not limited to these. By using the above structure, since the TFTs 4011 to 4013 are covered with the base film 4002 and the first interlayer insulating film 4200, an alkali metal such as Na or an alkaline earth metal is contained in the semiconductor film used for the semiconductor element. It is possible to further prevent diffusion and adversely affect the characteristics of the semiconductor element.

  Next, a second interlayer insulating film 4201 is formed on the first interlayer insulating film 4200. The second interlayer insulating film 4201 can be formed using a heat-resistant organic resin such as polyimide, acrylic, or polyamide. In addition to the organic resin, a low dielectric constant material (low-k material), a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material (hereinafter referred to as a siloxane-based resin), or the like is used. be able to. Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. Further, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Depending on the material, the second interlayer insulating film 4201 can be formed by spin coating, dip coating, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, A knife coater or the like can be employed. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the second interlayer insulating film 4201 may be formed by stacking these insulating films.

  Further, in this embodiment, a third interlayer insulating film 4202 is formed over the second interlayer insulating film 4201 (FIG. 37B). As the third interlayer insulating film 4202, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, benzocyclobutene, or resist, a siloxane resin, or the like may be used.

  Note that a filler may be mixed in the second interlayer insulating film 4201 or the third interlayer insulating film 4202 in order to prevent the second interlayer insulating film 4201 or the third interlayer insulating film 4202 from peeling or cracking. good.

  Next, contact holes are formed in the first interlayer insulating film 4200, the second interlayer insulating film 4201, and the third interlayer insulating film 4202. Further, a conductive material film is formed over the third interlayer insulating film 4202, and the antenna 4305 is formed using the conductive material film (FIG. 38A). The antenna 4305 is formed using a conductive material including one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn, Sn, and Ni, or a metal compound. be able to.

  The antenna 4305 is connected to the wiring 4300. Note that in FIG. 38A, the antenna 4305 is directly connected to the wiring 4300; however, the ID chip of the present invention is not limited to this structure. For example, the antenna 4305 and the wiring 4300 may be electrically connected using a wiring formed separately.

  The antenna 4305 can be formed by a printing method, a photolithography method, an evaporation method, a droplet discharge method, or the like. In this embodiment, the antenna 4305 is formed using a single-layer conductive film; however, it is also possible to form the antenna 4305 in which a plurality of conductive films are stacked. For example, the antenna 4305 may be formed by coating a wiring formed of Ni or the like with electroless plating.

  The droplet discharge method means a method of forming a predetermined pattern by discharging droplets containing a predetermined composition from the pores, and includes an ink jet method and the like in its category. The printing method includes a screen printing method and an offset printing method. By using a printing method or a droplet discharge method, the antenna 4305 can be formed without using an exposure mask. In addition, unlike the photolithography method, there is no waste of material that is removed by etching in the droplet discharge method and the printing method. In addition, since it is not necessary to use an expensive exposure mask, the cost for manufacturing the ID chip can be suppressed.

  In the case of using a droplet discharge method or various printing methods, for example, conductive particles in which Cu is coated with Ag can be used. Note that in the case where the antenna 4305 is formed by a droplet discharge method, it is preferable to perform treatment on the surface of the third interlayer insulating film 4202 so that the adhesion of the antenna 4305 is increased.

  Specifically, as a method for improving the adhesion, for example, a method of attaching a metal or a metal compound capable of improving the adhesion of the conductive film or the insulating film to the surface of the third interlayer insulating film 4202 by, for example, catalytic action, An organic insulating film having high adhesion to the formed conductive film or insulating film, a method of attaching a metal or a metal compound to the surface of the third interlayer insulating film 4202, a surface of the third interlayer insulating film 4202 under atmospheric pressure Alternatively, a method of performing surface modification by performing plasma treatment under reduced pressure may be used. Examples of the metal having high adhesion to the conductive film or insulating film include titanium, titanium oxide, 3d transition elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Zn. Is mentioned. Examples of the metal compound include the above-described metal oxides, nitrides, and oxynitrides. Examples of the organic insulating film include polyimide and siloxane resin.

  When the metal or metal compound attached to the third interlayer insulating film 4202 has conductivity, the sheet resistance is controlled so that the normal driving of the antenna is not hindered. Specifically, the average thickness of the conductive metal or metal compound is controlled to be, for example, 1 to 10 nm, or the metal or metal compound is partially or entirely insulated by oxidation. You can do it. Alternatively, the deposited metal or metal compound may be selectively removed by etching except for the region where the adhesion is desired to be improved. Alternatively, the metal or the metal compound may be selectively attached only to a specific region by using a droplet discharge method, a printing method, a sol-gel method, or the like, instead of attaching the metal or the metal compound to the entire surface of the substrate in advance. Note that the metal or metal compound does not have to be a completely continuous film on the surface of the third interlayer insulating film 4202, and may be dispersed to some extent.

  Then, as shown in FIG. 38B, after the antenna 4305 is formed, a protective layer 4400 is formed over the third interlayer insulating film 4202 so as to cover the antenna 4305. The protective layer 4400 is formed using a material that can protect the antenna 4305 when the peeling layer 4001 is later removed by etching. For example, the protective layer 4400 can be formed by applying an epoxy-based, acrylate-based, or silicon-based resin that is soluble in water or alcohols to the entire surface.

In this example, a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) is applied by spin coating so as to have a film thickness of 30 μm, and after exposure for 2 minutes for temporary curing, UV light is applied to the back surface. Exposure to 2.5 minutes and 10 minutes from the surface for a total of 12.5 minutes to perform main curing to form the protective layer 4400. In addition, when laminating | stacking several organic resin, there exists a possibility that it may melt | dissolve partially at the time of application | coating or baking with the solvent currently used between organic resins, or adhesiveness may become high too much. Therefore, in the case where an organic resin that is soluble in the same solvent is used for both the third interlayer insulating film 4202 and the protective layer 4400, the third interlayer insulating film 4202 is formed so that the protective layer 4400 can be removed smoothly in the subsequent process. It is preferable to form an inorganic insulating film (SiN _x film, SiN _x O _y film, AlN _x film, or AlN _x O _y film) so as to cover it.

  Next, as shown in FIG. 39A, a groove 4401 is formed in order to separate the ID chips. The groove 4401 may be formed so that the peeling layer 4001 is exposed. The groove 4401 can be formed by dicing, scribing, or the like. Note that the groove 4401 is not necessarily formed when the ID chip formed over the first substrate 4000 does not need to be separated.

Next, as shown in FIG. 39B, the peeling layer 4001 is removed by etching. In this embodiment, halogen fluoride is used as an etching gas, and the gas is introduced from the groove 4401. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used, and the temperature is 350 ° C., the flow rate is 300 sccm, the atmospheric pressure is 800 Pa, and the time is 3 hours. Alternatively, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogen fluoride such as ClF ₃ , the peeling layer 4001 is selectively etched, and the first substrate 4000 can be peeled from the TFTs 4011 to 4013. The halogen fluoride may be either a gas or a liquid.

  Next, as illustrated in FIG. 40A, the peeled TFTs 4011 to 4013 and the antenna 4305 are attached to the second substrate 4500 with an adhesive 4501. As the adhesive 4501, a material capable of bonding the second substrate 4500 and the base film 4002 is used. As the adhesive 4501, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the second substrate 4500, an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used for the second substrate 4500. As the plastic substrate, ARTON (manufactured by JSR) made of polynorbornene with a polar group can be used. Polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin and the like. The second substrate 4500 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Next, as shown in FIG. 40B, after the protective layer 4400 is removed, an adhesive 4503 is applied over the third interlayer insulating film 4202 so as to cover the antenna 4305, and a cover material 4502 is attached thereto. As in the case of the second substrate 4500, the cover material 4502 can be formed using a flexible organic material such as paper or plastic. The thickness of the adhesive 4503 may be, for example, 10 to 200 μm.

  The adhesive 4503 is formed using a material capable of bonding the cover material 4502 to the third interlayer insulating film 4202 and the antenna 4305. As the adhesive 4503, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

The ID chip is completed through the above-described steps. By the above manufacturing method, an extremely thin integrated circuit having a total film thickness of 0.3 μm to 3 μm, typically about 2 μm, can be formed between the second substrate 4500 and the cover material 4502. Note that the thickness of the integrated circuit includes not only the thickness of the semiconductor element itself but also the thicknesses of various insulating films and interlayer insulating films formed between the adhesive 4501 and the adhesive 4503. The area occupied by the integrated circuit included in the ID chip, 5 mm square (25 mm ²⁾ or less, and more preferably may be 0.3mm square (0.09 mm ²⁾ to 4 mm square (16 mm ²⁾ degree.

  Note that the mechanical strength of the ID chip can be increased by positioning the integrated circuit at a more central position between the second substrate 4500 and the cover material 4502. Specifically, when the distance between the second substrate 4500 and the cover material 4502 is d, the distance x between the second substrate 4500 and the center in the thickness direction of the integrated circuit is expressed by the following [Equation 1]. It is desirable to control the thicknesses of the adhesive 4501 and the adhesive 4503 so as to satisfy the above.

  Preferably, the thicknesses of the adhesive 4501 and the adhesive 4503 are controlled so as to satisfy the following [Equation 2].

  Note that FIG. 40B illustrates an example in which the cover material 4502 is used; however, the present invention is not limited to this structure. For example, the process may be ended up to the step shown in FIG.

  Note that in this embodiment, a method for peeling the substrate and the integrated circuit by providing a peeling layer between the first substrate 4000 having high heat resistance and the integrated circuit and removing the peeling layer by etching is shown. The manufacturing method of the ID chip of the present invention is not limited to this configuration. For example, a metal oxide film may be provided between a substrate having high heat resistance and the integrated circuit, and the integrated circuit may be peeled by weakening the metal oxide film by crystallization. Alternatively, a separation layer using an amorphous semiconductor film containing hydrogen is provided between a substrate with high heat resistance and an integrated circuit, and the separation layer is removed by laser light irradiation to separate the substrate and the integrated circuit. You may do it. Alternatively, the integrated circuit may be separated from the substrate by mechanically removing the highly heat-resistant substrate on which the integrated circuit is formed or removing the substrate by etching with a solution or gas.

  In order to ensure the flexibility of the ID chip, when an organic resin is used for the adhesive 4501 in contact with the base film 4002, a silicon nitride film or a silicon oxide film containing nitrogen is used as the base film 4002. Alkali metals such as Na and alkaline earth metals can be prevented from diffusing into the semiconductor film.

  Further, the surface of the object has a curved surface, whereby the second substrate 4500 of the ID chip bonded to the curved surface is bent so as to have a curved surface drawn by the movement of the generating line such as a conical surface or a column surface. In this case, it is desirable to align the direction of the bus and the direction in which the carriers of the TFTs 4011 to 4013 move. With the above structure, even when the second substrate 4500 is bent, it can be prevented that the characteristics of the TFTs 4011 to 4013 are affected. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, even when the second substrate 4500 is bent, the characteristics of the TFTs 4011 to 4013 are affected. It can be suppressed more.

  Note that although an example in which the antenna is formed over the same substrate as the integrated circuit has been described in this embodiment, the present invention is not limited to this structure. An antenna formed over another substrate and the integrated circuit may be bonded later to be electrically connected.

  In general, the frequency of radio waves used in an ID chip is 13.56 MHz and 2.45 GHz, and it is very important to increase the versatility to form an ID chip so that radio waves of that frequency can be detected. Is desirable.

In addition, the ID chip of this embodiment has an advantage that radio waves are less shielded than an ID chip formed using a semiconductor substrate, and the signal can be prevented from being attenuated by shielding the radio waves. Therefore, the cost of the ID chip can be significantly reduced when the glass substrate is used than when the semiconductor substrate is used. For example, a case where a silicon substrate having a diameter of 12 inches is used is compared with a case where a glass substrate of 730 × 920 mm ² is used. The area of the former silicon substrate is about 73000 mm ² , while the area of the latter glass substrate is about 672000 mm ² , and the glass substrate corresponds to about 9.2 times the silicon substrate. When the area of the latter glass substrate is about 672000 mm ² , ignoring the area consumed by dividing the substrate, it is calculated that about 672,000 1 mm square ID chips can be formed, and the number is about 9.2 times that of the silicon substrate. It is equivalent to the number of Capital investment for mass production of ID chips requires fewer steps when a 730 × 920 mm ² glass substrate is used than when a 12-inch diameter silicon substrate is used. It can be done in a third. Further, in the present invention, the glass substrate can be used again after the integrated circuit is peeled off. Therefore, cost can be significantly reduced as compared with the case of using a silicon substrate, even in view of the cost of filling a damaged glass substrate or cleaning the surface of the glass substrate. Even if the glass substrate is discarded without being reused, the cost of a 730 × 920 mm ² glass substrate is about half that of a silicon substrate having a diameter of 12 inches, thus greatly reducing the cost of the ID chip. You can see that

Therefore, it can be seen that when a glass substrate of 730 × 920 mm ² is used, the price of the ID chip can be reduced to about 1/30 compared to the case of using a 12-inch diameter silicon substrate. Since the ID chip is expected to be used on the premise that it is disposable, the ID chip of the present invention, which can significantly reduce the cost, is very useful for the above application.

  Note that in this example, the example in which the integrated circuit is separated and attached to a flexible substrate is described; however, the present invention is not limited to this structure. For example, in the case of using a substrate having a heat resistant temperature that can withstand heat treatment in a manufacturing process of an integrated circuit such as a glass substrate, the integrated circuit is not necessarily peeled off.

  In addition, this embodiment can be freely combined with any description of the embodiment mode and Embodiments 1 to 8 if necessary.

  As an electronic device to which the present invention is applied, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio component, etc.), a computer, a game device, a portable information terminal (mobile computer, cellular phone, portable type) A game machine or an electronic book), an image playback device provided with a recording medium (specifically, a device provided with a display capable of playing back a recording medium such as a Digital Versatile Disc (DVD) and displaying the image). It is done. Specific examples of these electronic devices are shown in FIGS. 41A to 41D and FIGS. 42A to 42D.

  FIG. 41A illustrates a light-emitting display device, such as a television receiver. A housing 5001, a display portion 5003, a speaker portion 5004, and the like are included. The present invention can be applied to the display portion 5003, a control circuit portion, and the like. In order to increase the contrast in the pixel portion, a polarizing plate or a circular polarizing plate may be provided. For example, a quarter λ plate, a ½ λ plate, and a polarizing plate are preferably provided in this order on the sealing substrate. Further, an antireflection film may be provided on the polarizing plate. By using the present invention, the light-emitting display device can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by attaching an ID chip manufactured by the method described in Example 9 to the light-emitting display device, a distribution route and the like can be clarified.

  FIG. 41B illustrates a liquid crystal display or an OLED display, which includes a housing 5101, a support base 5102, a display portion 5103, and the like. The present invention can be applied to the display portion 5103, a control circuit portion, and the like. By using the present invention, the display can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by attaching an ID chip manufactured by the method described in Example 9 to the display, the distribution route and the like can be clarified.

  FIG. 41C illustrates a mobile phone, which includes a main body 5201, a housing 5202, a display portion 5203, an audio input portion 5204, an audio output portion 5205, operation keys 5206, an antenna 5208, and the like. The present invention can be applied to the display portion 5203, a control circuit portion, and the like. By using the present invention, the mobile phone can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by attaching an ID chip manufactured by the method described in Embodiment 9 to the mobile phone, the distribution route and the like can be clarified.

FIG. 41D illustrates a computer, which includes a main body 5301, a housing 5302, a display portion 5303, a keyboard 5304, an external connection port 5305, a pointing mouse 5306, and the like. The present invention can be applied to the display portion 5303, a control circuit portion, and the like. By using the present invention, the computer can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed.
Further, by attaching an ID chip manufactured by the method described in Example 9 to the computer, a distribution route or the like can be clarified.

  FIG. 42A illustrates a portable computer, which includes a main body 6001, a display portion 6002, a switch 6003, operation keys 6004, an infrared port 6005, and the like. The present invention can be applied to the display portion 6002, the control circuit portion, and the like. By using the present invention, the computer can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by attaching an ID chip manufactured by the method described in Example 9 to the computer, a distribution route or the like can be clarified.

  FIG. 42B illustrates a portable game machine including a housing 6101, a display portion 6102, speaker portions 6103, operation keys 6104, a recording medium insertion portion 6105, and the like. The present invention can be applied to the display portion 6102, a control circuit portion, and the like. By using the present invention, the game machine can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by sticking the ID chip manufactured by the method described in Embodiment 9 to the game machine, the distribution route and the like can be clarified.

  FIG. 42C illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6201, a housing 6202, a display portion A 6203, a display portion B 6204, and a recording medium (such as a DVD). A reading unit 6205, operation keys 6206, a speaker unit 6207, and the like are included. A display portion A6203 mainly displays image information, and a display portion B6204 mainly displays character information. The present invention can be applied to the display portion A 6203, the display portion B 6204, a control circuit portion, and the like. Note that an image reproducing device provided with a recording medium includes a home game machine and the like. By using the present invention, the image reproducing device can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. Further, by attaching an ID chip manufactured by the method described in Example 9 to the image reproducing apparatus, the distribution route and the like can be clarified.

  FIG. 42D illustrates a TV that can carry only a display wirelessly. A housing 6302 includes a battery and a signal receiver, and the display portion 6303 and the speaker portion 6307 are driven by the battery. The battery can be repeatedly charged by the charger 6300. The charger 6300 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 6302 is controlled by operation keys 6306. The device illustrated in FIG. 42D can also be referred to as a video / audio two-way communication device because a signal can be sent from the housing 6302 to the charger 6300 by operating the operation key 6306. In addition, by operating the operation key 6306, a signal is transmitted from the housing 6302 to the charger 6300, and further, a signal that can be transmitted by the charger 6300 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device. The present invention can be applied to the display portion 6303, a control circuit portion, and the like. By using the present invention, the TV can be manufactured with fewer steps, and manufacturing time, manufacturing cost, and the like can be suppressed. In addition, by attaching an ID chip manufactured by the method described in Embodiment 9 to the TV, a distribution route and the like can be clarified.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be further reduced.

  It should be noted that the examples shown in this embodiment are just examples, and the present invention is not limited to these applications.

  In addition, this embodiment can be implemented by being freely combined with any description of the embodiment mode and Embodiments 1 to 9.

  According to the present invention, the heat treatment process for crystallization and gettering is performed only once, and the process is greatly shortened. By reducing the number of steps, cost increases and yield reduction can be suppressed.

10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B show a manufacturing process of a conventional semiconductor device. 10A and 10B show a manufacturing process of a conventional semiconductor device. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4 is a top view of a pixel of the liquid crystal display device of the present invention. FIG. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device using the liquid crystal dropping method of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device using the liquid crystal dropping method of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device using the liquid crystal dropping method of the present invention. The figure which shows bonding of the board | substrate in the liquid crystal display device of this invention. 4A and 4B illustrate a manufacturing process of an EL display device of the present invention. 4A and 4B illustrate a manufacturing process of an EL display device of the present invention. 4A and 4B illustrate a manufacturing process of an EL display device of the present invention. 4A and 4B illustrate a manufacturing process of an EL display device of the present invention. 4A and 4B illustrate a manufacturing process of an EL display device of the present invention. 4A and 4B show a manufacturing process of an ID chip of the present invention. 4A and 4B show a manufacturing process of an ID chip of the present invention. 4A and 4B show a manufacturing process of an ID chip of the present invention. The figure which shows the manufacturing process of ID chip of this invention FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention.

Explanation of symbols

100 substrate 101 gate electrode 102 gate insulating film 103 amorphous semiconductor film 104 semiconductor film 105 conductive film 106 drain electrode 107 drain region 108 channel formation region 109 crystalline semiconductor film 111 island-like amorphous semiconductor film 112 island-like semiconductor film 113 Island area 114 area

Claims (11)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first amorphous semiconductor film on the gate insulating film;
Forming a second semiconductor film containing an element selected from Group 15 on the first amorphous semiconductor film;
Using the second semiconductor film including the first amorphous semiconductor film and the element selected from the group 15, respectively form a first island-shaped amorphous semiconductor film and the second island-shaped semiconductor film And
Forming a source electrode and a drain electrode on the second island-shaped semiconductor film;
As a mask the source electrode and the drain electrode, and forming a source region and a drain region by removing part of the second island-shaped semiconductor film, reducing the thickness of the first island-shaped amorphous semiconductor film to expose the part by,
Introducing a catalytic element that promotes crystallization of the first island-shaped amorphous semiconductor film into the exposed region of the first island-shaped amorphous semiconductor film;
Heating the source region , the drain region, and the first island-shaped amorphous semiconductor film to crystallize the first island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film; A method for manufacturing a semiconductor device, characterized in that a catalytic element is gettered into the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first amorphous semiconductor film on the gate insulating film;
Forming a second semiconductor film containing an element selected from Group 15 on the first amorphous semiconductor film;
Using the second semiconductor film including the first amorphous semiconductor film and the element selected from the group 15, respectively form a first island-shaped amorphous semiconductor film and the second island-shaped semiconductor film And
Forming a source electrode and a drain electrode on the second island-shaped semiconductor film;
As a mask the source electrode and the drain electrode, and forming a source region and a drain region by removing part of the second island-shaped semiconductor film, reducing the thickness of the first island-shaped amorphous semiconductor film to expose the part by,
Forming a mask covering the exposed regions of the source electrode , the drain electrode, and the first island-shaped amorphous semiconductor film;
Wherein said mask exposed regions of the first island-shaped amorphous semiconductor film to form a window by etching, to expose the part of the first island-shaped amorphous semiconductor film,
The part of the first island-shaped amorphous semiconductor film the exposed, introducing a catalytic element which promotes crystallization of the first island-shaped amorphous semiconductor film,
Heating the source region , the drain region, and the first island-shaped amorphous semiconductor film to crystallize the first island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film; A method for manufacturing a semiconductor device, characterized in that a catalytic element is gettered into the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first amorphous semiconductor film on the gate insulating film;
Forming a second semiconductor film containing an element selected from Group 15 on the first amorphous semiconductor film;
Using the second semiconductor film including the first amorphous semiconductor film and the element selected from the group 15, respectively form a first island-shaped amorphous semiconductor film and the second island-shaped semiconductor film And
Forming a source electrode and a drain electrode on the second island-shaped semiconductor film;
As a mask the source electrode and the drain electrode, and forming a source region and a drain region by removing part of the second island-shaped semiconductor film, reducing the thickness of the first island-shaped amorphous semiconductor film to expose the part by,
Introducing a catalytic element that promotes crystallization of the first island-shaped amorphous semiconductor film into the exposed region of the first island-shaped amorphous semiconductor film;
The source region , the drain region, and the first island-shaped amorphous semiconductor film are heated to crystallize the first island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film, and the catalyst Gettering elements into the source and drain regions;
A manufacturing method of a semiconductor device, wherein a wiring electrically connected to the source electrode and the drain electrode is formed. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first amorphous semiconductor film on the gate insulating film;
Forming a second semiconductor film containing an element selected from Group 15 on the first amorphous semiconductor film;
Using the second semiconductor film including the first amorphous semiconductor film and the element selected from the group 15, respectively form a first island-shaped amorphous semiconductor film and the second island-shaped semiconductor film And
Forming a mask on the second island-shaped semiconductor film;
Using the mask to remove the part of the second island-shaped semiconductor film forming a source region and a drain region, a part to reduce the thickness of the first island-shaped amorphous semiconductor film To expose
Introducing a catalytic element that promotes crystallization of the first island-shaped amorphous semiconductor film into the exposed region of the first island-shaped amorphous semiconductor film;
Heating the source region , the drain region, and the first island-shaped amorphous semiconductor film to crystallize the first island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film; Gettering the catalytic element into the source and drain regions;
A manufacturing method of a semiconductor device, wherein a wiring electrically connected to the source region and the drain region is formed. In claim 3 or claim 4,
The method for manufacturing a semiconductor device, wherein the wiring is formed of a low melting point conductive material. In claim 5,
The method for manufacturing a semiconductor device, wherein the wiring is formed by a sputtering method, a droplet ejection method, or a CVD method. In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, wherein the element selected from the group 15 is activated by the heating. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first amorphous semiconductor film on the gate insulating film;
Forming a second semiconductor film containing an element selected from Group 15 on the first amorphous semiconductor film;
Introducing an element selected from Group 13 into the second semiconductor film containing an element selected from Group 15;
Using the second semiconductor film including the first amorphous semiconductor film and the Group 15 and an element selected from Group 13, first island-shaped amorphous semiconductor film and the second semiconductor island, respectively Forming a film,
Forming a source electrode and a drain electrode on the second island-shaped semiconductor film;
As a mask the source electrode and the drain electrode, to remove part of the second island-shaped semiconductor film forming a source region and a drain region, to reduce the thickness of the first island-shaped amorphous semiconductor film to expose the part Te,
Introducing a catalytic element that promotes crystallization of the first island-shaped amorphous semiconductor film into the exposed region of the first island-shaped amorphous semiconductor film;
Heating the source region , the drain region, and the first island-shaped amorphous semiconductor film to crystallize the first island-shaped amorphous semiconductor film to form an island-shaped crystalline semiconductor film; A method for manufacturing a semiconductor device, characterized in that a catalytic element is gettered into the source region and the drain region. In claim 8,
A method for manufacturing a semiconductor device, wherein the element selected from the group 15 and group 13 is activated by the heating. In any one of Claims 1 thru | or 9,
The catalyst elements are nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au). A method for manufacturing a semiconductor device, which is one selected element or a plurality of elements. In any one of Claims 1 to 10,
The source electrode and the drain electrode include one element selected from tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum (Mo), or an alloy material or a compound material containing the element as a main component. A method for manufacturing a semiconductor device.

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